135 lines
3.8 KiB
C
135 lines
3.8 KiB
C
/*
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* Copyright (c) 2008, Google Inc.
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* All rights reserved.
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* Copyright (c) 2009-2011, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <reg.h>
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#include <stdint.h>
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#include <debug.h>
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#include <gsbi.h>
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#include <platform/iomap.h>
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#include <platform/clock.h>
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/* Set rate and enable the clock */
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void clock_config(uint32_t ns, uint32_t md, uint32_t ns_addr, uint32_t md_addr)
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{
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unsigned int val = 0;
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/* Activate the reset for the M/N Counter */
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val = 1 << 7;
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writel(val, ns_addr);
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/* Write the MD value into the MD register */
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if (md_addr != 0x0)
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writel(md, md_addr);
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/* Write the ns value, and active reset for M/N Counter, again */
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val = 1 << 7;
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val |= ns;
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writel(val, ns_addr);
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/* De-activate the reset for M/N Counter */
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val = 1 << 7;
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val = ~val;
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val = val & readl(ns_addr);
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writel(val, ns_addr);
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/* Enable the Clock Root */
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val = 1 << 11;
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val = val | readl(ns_addr);
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writel(val, ns_addr);
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/* Enable the Clock Branch */
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val = 1 << 9;
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val = val | readl(ns_addr);
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writel(val, ns_addr);
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/* Enable the M/N Counter */
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val = 1 << 8;
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val = val | readl(ns_addr);
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writel(val, ns_addr);
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}
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void pll8_enable(void)
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{
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unsigned int curr_value = 0;
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/* Vote for PLL8 to be enabled */
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curr_value = readl(MSM_BOOT_PLL_ENABLE_SC0);
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curr_value |= (1 << 8);
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writel(curr_value, MSM_BOOT_PLL_ENABLE_SC0);
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/* Proceed only after PLL is enabled */
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while (!(readl(MSM_BOOT_PLL8_STATUS) & (1<<16)));
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}
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void acpu_clock_init(void)
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{
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/* ADM3: enable cc_adm0_clk */
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writel( (1 << SC0_U_BRANCH_ENA_VOTE_ADM0) |
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(1 << SC0_U_BRANCH_ENA_VOTE_ADM0_PBUS), SC0_U_BRANCH_ENA_VOTE);
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}
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void hsusb_clock_init(void)
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{
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uint32_t reg;
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pll8_enable();
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/* Setup USB HS1 System clock - 60 Mhz */
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//TODO: Remove this when verify that this is already configured
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if (!(readl(USB_HS1_SYSTEM_CLK_NS))){
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clock_config(USB_XCVR_CLK_NS,
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USB_XCVR_CLK_MD,
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USB_HS1_SYSTEM_CLK_NS,
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USB_HS1_SYSTEM_CLK_MD);
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}
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/* Setup USB HS1 XCVR clock - 60 Mhz */
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clock_config(USB_XCVR_CLK_NS,
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USB_XCVR_CLK_MD,
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USB_HS1_XCVR_FS_CLK_NS,
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USB_HS1_XCVR_FS_CLK_MD);
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/* HS-USB: enable cc_usb_hs1_hs_clk */
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reg = readl(USB_HS1_HCLK_CTL);
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reg |= 0x1 << 4;
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writel( reg, USB_HS1_HCLK_CTL);
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}
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/* Configure UART clock - based on the gsbi id */
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void clock_config_uart_dm(uint8_t id)
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{
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/* Enable gsbi_uart_clk */
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clock_config(UART_DM_CLK_NS_115200,
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UART_DM_CLK_MD_115200,
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GSBIn_UART_APPS_NS(id),
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GSBIn_UART_APPS_MD(id));
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/* Enable gsbi_pclk */
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writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id));
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}
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