151 lines
4.6 KiB
C
Executable File
151 lines
4.6 KiB
C
Executable File
/*++
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Copyright (c) Realtek Semiconductor Corp. All rights reserved.
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Module Name:
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Hal88XXPwrSeqCmd.c
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Abstract:
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Implement HW Power sequence configuration CMD handling routine for Realtek devices.
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Major Change History:
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When Who What
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---------- --------------- -------------------------------
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2012-04-03 Filen Create.
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--*/
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#include "../HalPrecomp.h"
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//
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// Description:
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// This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC.
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//
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// Assumption:
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// We should follow specific format which was released from HW SD.
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//
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// 2011.07.07, added by Roger.
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//
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BOOLEAN
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HalPwrSeqCmdParsing88XX(
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IN HAL_PADAPTER Adapter,
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IN u1Byte CutVersion,
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IN u1Byte FabVersion,
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IN u1Byte InterfaceType,
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IN WLAN_PWR_CFG PwrSeqCmd[]
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)
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{
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WLAN_PWR_CFG PwrCfgCmd = {0};
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u32 bPollingBit = _FALSE;
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u32 AryIdx=0;
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u8 value = 0;
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u32 offset = 0;
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u32 pollingCount = 0; // polling autoload done.
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u32 maxPollingCnt = 5000;
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do {
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PwrCfgCmd=PwrSeqCmd[AryIdx];
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RT_TRACE(COMP_INIT, DBG_LOUD, ("%s %d, ENTRY, offset:0x%x, cut_msk:0x%x, fab_msk:0x%x, if_msk:0x%x, base:0x%x, cmd:0x%x, msk:0x%x, value:0x%x\n",
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__FUNCTION__, __LINE__, GET_PWR_CFG_OFFSET(PwrCfgCmd), GET_PWR_CFG_CUT_MASK(PwrCfgCmd),
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GET_PWR_CFG_FAB_MASK(PwrCfgCmd), GET_PWR_CFG_INTF_MASK(PwrCfgCmd), GET_PWR_CFG_BASE(PwrCfgCmd),
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GET_PWR_CFG_CMD(PwrCfgCmd), GET_PWR_CFG_MASK(PwrCfgCmd), GET_PWR_CFG_VALUE(PwrCfgCmd)) );
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HAL_delay_us(600);
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//2 Only Handle the command whose FAB, CUT, and Interface are matched
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if((GET_PWR_CFG_FAB_MASK(PwrCfgCmd)&FabVersion)&&
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(GET_PWR_CFG_CUT_MASK(PwrCfgCmd)&CutVersion)&&
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(GET_PWR_CFG_INTF_MASK(PwrCfgCmd)&InterfaceType)) {
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switch(GET_PWR_CFG_CMD(PwrCfgCmd))
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{
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case PWR_CMD_READ:
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RT_TRACE(COMP_INIT, DBG_LOUD, ("%s %d, PWR_CMD_READ\n", __FUNCTION__, __LINE__));
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break;
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case PWR_CMD_WRITE:
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RT_TRACE(COMP_INIT, DBG_LOUD, ("%s %d, PWR_CMD_WRITE\n", __FUNCTION__, __LINE__));
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offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
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#ifdef CONFIG_SDIO_HCI
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//
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// <Roger_Notes> We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface
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// 2011.07.07.
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//
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if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
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{
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// Read Back SDIO Local value
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value = SdioLocalCmd52Read1Byte(Adapter, offset);
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value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd));
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value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd));
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// Write Back SDIO Local value
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SdioLocalCmd52Write1Byte(Adapter, offset, value);
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}
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else
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#endif
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{
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//Read the value from system register
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value = HAL_RTL_R8(offset);
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value = value&(~(GET_PWR_CFG_MASK(PwrCfgCmd)));
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value = value|(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd));
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//Write the value back to sytem register
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HAL_RTL_W8(offset, value);
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}
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break;
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case PWR_CMD_POLLING:
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RT_TRACE(COMP_INIT, DBG_LOUD, ("%s %d, PWR_CMD_POLLING\n", __FUNCTION__, __LINE__));
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bPollingBit = _FALSE;
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offset = GET_PWR_CFG_OFFSET(PwrCfgCmd);
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do {
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#ifdef CONFIG_SDIO_HCI
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if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO)
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value = SdioLocalCmd52Read1Byte(Adapter, offset);
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else
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#endif
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value = HAL_RTL_R8(offset);
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value = value & GET_PWR_CFG_MASK(PwrCfgCmd);
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if(value==(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd)))
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bPollingBit = _TRUE;
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else
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HAL_delay_us(20);
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if(pollingCount++ > maxPollingCnt){
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RT_TRACE(COMP_INIT, DBG_WARNING, ("%s %d, PWR_CMD_POLLING, Fail to polling Offset[0x%x]\n", __FUNCTION__, __LINE__, offset));
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return _FALSE;
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}
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}while(!bPollingBit);
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break;
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case PWR_CMD_DELAY:
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RT_TRACE(COMP_INIT, DBG_LOUD, ("%s %d, PWR_CMD_DELAY\n", __FUNCTION__, __LINE__));
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if(GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US)
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HAL_delay_us(GET_PWR_CFG_OFFSET(PwrCfgCmd));
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else
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HAL_delay_us(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000);
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break;
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case PWR_CMD_END:
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// When this command is parsed, end the process
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RT_TRACE(COMP_INIT, DBG_LOUD, ("%s %d, PWR_CMD_END\n", __FUNCTION__, __LINE__));
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return _TRUE;
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break;
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default:
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RT_TRACE(COMP_INIT, DBG_SERIOUS, ("%s %d, Unknown CMD!!\n", __FUNCTION__, __LINE__));
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break;
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}
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}
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AryIdx++;//Add Array Index
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}while(1);
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return _TRUE;
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}
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