57 lines
2.2 KiB
Plaintext
57 lines
2.2 KiB
Plaintext
Test: ldrex_test.sh
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Usage: ldrex_test.sh [-n | --nominal] [-s | --stress] [-a | --adversarial]
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[-r | --repeatability] [-c | --case] <case_num>
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Only one option each time. They are not supposed to be used in conjunction with each other.
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When use -n, -s, -a, -r, all the cases will be run one by one. The specified test case will
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be tested if option is -c.
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case_num: different case num with different test case
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Note:
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This testcase is only meant for 32-bit ARM and not for 64-bit yet. Another kernel test change
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of loading and storing exclusive register for 64-bit instruction(ldxr and stxr) will be
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submited later.
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Description:
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The LDREX and STREX instructions split the operation of atomically updating
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memory into two separate steps. Together, they provide atomic updates in
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conjunction with exclusive monitors that track exclusive memory accesses.
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An exclusive monitor is a simple state machine, with the possible states open and
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exclusive. To support synchronization between processors, a system must implement
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two sets of monitors, local and global. A Load-Exclusive operation updates the
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monitors to exclusive state. A Store-Exclusive operation accesses the monitor(s) to
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determine whether it can complete successfully. A Store-Exclusive can succeed only if
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all accessed exclusive monitors are in the exclusive state.
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case_num :
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0 --- Test Stop
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1 --- cacheable: 4 LDREX on same memory location - same cpu
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2 --- cacheable: NR_CPUS LDREX on different memory location - same cpu
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3 --- Uncacheable: 4 LDREX on same memory location - same cpu
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4 --- Uncacheable: 1 LDREX on different memory location - same cpu
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5 --- cacheable: 4 LDREX on same memory location for all present cores
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6 --- cacheable: 1 LDREX on different memory location for all present cores
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7 --- Uncacheable: 2 LDREX on same memory location for all present cores
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8 --- Uncacheable: 1 LDREX on different memory location for all present cores
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9 --- Uncacheable: 1 LDREX on same memory location for all present cores
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except waiting thread for cpu (NR_CPUS -1)
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10 --- cacheable: 1 LDREX on different memory location for all present cores
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except waiting thread for cpu (NR_CPUS -1)
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11 --- cacheable: LDREX and STREX for all present cores with multiple threads
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