320 lines
7.5 KiB
C
320 lines
7.5 KiB
C
/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef MSM8X16_WCD_H
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#define MSM8X16_WCD_H
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#include <sound/soc.h>
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#include <sound/jack.h>
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#include <sound/q6afe-v2.h>
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#include "wcd-mbhc-v2.h"
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#include "wcdcal-hwdep.h"
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#define MICBIAS_EXT_BYP_CAP 0x00
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#define MICBIAS_NO_EXT_BYP_CAP 0x01
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#define MSM8X16_WCD_NUM_REGISTERS 0x6FF
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#define MSM8X16_WCD_MAX_REGISTER (MSM8X16_WCD_NUM_REGISTERS-1)
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#define MSM8X16_WCD_CACHE_SIZE MSM8X16_WCD_NUM_REGISTERS
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#define MSM8X16_WCD_NUM_IRQ_REGS 2
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#define MAX_REGULATOR 7
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#define MSM8X16_WCD_REG_VAL(reg, val) {reg, 0, val}
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#define MSM8X16_TOMBAK_LPASS_AUDIO_CORE_DIG_CODEC_CLK_SEL 0xFE03B004
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#define MSM8X16_TOMBAK_LPASS_DIGCODEC_CMD_RCGR 0x0181C09C
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#define MSM8X16_TOMBAK_LPASS_DIGCODEC_CFG_RCGR 0x0181C0A0
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#define MSM8X16_TOMBAK_LPASS_DIGCODEC_M 0x0181C0A4
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#define MSM8X16_TOMBAK_LPASS_DIGCODEC_N 0x0181C0A8
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#define MSM8X16_TOMBAK_LPASS_DIGCODEC_D 0x0181C0AC
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#define MSM8X16_TOMBAK_LPASS_DIGCODEC_CBCR 0x0181C0B0
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#define MSM8X16_TOMBAK_LPASS_DIGCODEC_AHB_CBCR 0x0181C0B4
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#define MSM8X16_CODEC_NAME "msm8x16_wcd_codec"
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#define MSM8X16_WCD_IS_DIGITAL_REG(reg) \
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(((reg >= 0x200) && (reg <= 0x4FF)) ? 1 : 0)
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#define MSM8X16_WCD_IS_TOMBAK_REG(reg) \
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(((reg >= 0x000) && (reg <= 0x1FF)) ? 1 : 0)
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/*
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* MCLK activity indicators during suspend and resume call
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*/
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#define MCLK_SUS_DIS 1
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#define MCLK_SUS_RSC 2
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#define MCLK_SUS_NO_ACT 3
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#define NUM_DECIMATORS 4
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#define MSM89XX_VDD_SPKDRV_NAME "cdc-vdd-spkdrv"
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#define DEFAULT_MULTIPLIER 800
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#define DEFAULT_GAIN 9
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#define DEFAULT_OFFSET 100
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extern const u8 msm8x16_wcd_reg_readable[MSM8X16_WCD_CACHE_SIZE];
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extern const u8 msm8x16_wcd_reg_readonly[MSM8X16_WCD_CACHE_SIZE];
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extern const u8 msm8x16_wcd_reset_reg_defaults[MSM8X16_WCD_CACHE_SIZE];
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extern const u8 cajon_digital_reg[MSM8X16_WCD_CACHE_SIZE];
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enum codec_versions {
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TOMBAK_1_0,
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TOMBAK_2_0,
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CONGA,
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CAJON,
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CAJON_2_0,
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DIANGU,
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UNSUPPORTED,
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};
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enum wcd_curr_ref {
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I_h4_UA = 0,
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I_pt5_UA,
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I_14_UA,
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I_l4_UA,
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I_1_UA,
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};
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enum wcd_mbhc_imp_det_pin {
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WCD_MBHC_DET_NONE = 0,
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WCD_MBHC_DET_HPHL,
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WCD_MBHC_DET_HPHR,
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WCD_MBHC_DET_BOTH,
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};
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/* Each micbias can be assigned to one of three cfilters
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* Vbatt_min >= .15V + ldoh_v
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* ldoh_v >= .15v + cfiltx_mv
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* If ldoh_v = 1.95 160 mv < cfiltx_mv < 1800 mv
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* If ldoh_v = 2.35 200 mv < cfiltx_mv < 2200 mv
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* If ldoh_v = 2.75 240 mv < cfiltx_mv < 2600 mv
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* If ldoh_v = 2.85 250 mv < cfiltx_mv < 2700 mv
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*/
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struct wcd9xxx_micbias_setting {
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u8 ldoh_v;
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u32 cfilt1_mv; /* in mv */
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u32 cfilt2_mv; /* in mv */
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u32 cfilt3_mv; /* in mv */
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/* Different WCD9xxx series codecs may not
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* have 4 mic biases. If a codec has fewer
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* mic biases, some of these properties will
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* not be used.
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*/
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u8 bias1_cfilt_sel;
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u8 bias2_cfilt_sel;
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u8 bias3_cfilt_sel;
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u8 bias4_cfilt_sel;
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u8 bias1_cap_mode;
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u8 bias2_cap_mode;
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u8 bias3_cap_mode;
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u8 bias4_cap_mode;
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bool bias2_is_headset_only;
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};
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enum msm8x16_wcd_pid_current {
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MSM8X16_WCD_PID_MIC_2P5_UA,
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MSM8X16_WCD_PID_MIC_5_UA,
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MSM8X16_WCD_PID_MIC_10_UA,
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MSM8X16_WCD_PID_MIC_20_UA,
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};
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struct msm8x16_wcd_reg_mask_val {
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u16 reg;
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u8 mask;
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u8 val;
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};
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enum msm8x16_wcd_mbhc_analog_pwr_cfg {
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MSM8X16_WCD_ANALOG_PWR_COLLAPSED = 0,
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MSM8X16_WCD_ANALOG_PWR_ON,
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MSM8X16_WCD_NUM_ANALOG_PWR_CONFIGS,
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};
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/* Number of input and output I2S port */
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enum {
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MSM8X16_WCD_RX1 = 0,
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MSM8X16_WCD_RX2,
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MSM8X16_WCD_RX3,
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MSM8X16_WCD_RX_MAX,
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};
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enum {
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MSM8X16_WCD_TX1 = 0,
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MSM8X16_WCD_TX2,
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MSM8X16_WCD_TX3,
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MSM8X16_WCD_TX4,
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MSM8X16_WCD_TX_MAX,
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};
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enum {
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/* INTR_REG 0 - Digital Periph */
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MSM8X16_WCD_IRQ_SPKR_CNP = 0,
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MSM8X16_WCD_IRQ_SPKR_CLIP,
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MSM8X16_WCD_IRQ_SPKR_OCP,
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MSM8X16_WCD_IRQ_MBHC_INSREM_DET1,
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MSM8X16_WCD_IRQ_MBHC_RELEASE,
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MSM8X16_WCD_IRQ_MBHC_PRESS,
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MSM8X16_WCD_IRQ_MBHC_INSREM_DET,
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MSM8X16_WCD_IRQ_MBHC_HS_DET,
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/* INTR_REG 1 - Analog Periph */
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MSM8X16_WCD_IRQ_EAR_OCP,
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MSM8X16_WCD_IRQ_HPHR_OCP,
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MSM8X16_WCD_IRQ_HPHL_OCP,
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MSM8X16_WCD_IRQ_EAR_CNP,
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MSM8X16_WCD_IRQ_HPHR_CNP,
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MSM8X16_WCD_IRQ_HPHL_CNP,
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MSM8X16_WCD_NUM_IRQS,
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};
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enum {
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ON_DEMAND_MICBIAS = 0,
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ON_DEMAND_SPKDRV,
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ON_DEMAND_SUPPLIES_MAX,
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};
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/*
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* The delay list is per codec HW specification.
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* Please add delay in the list in the future instead
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* of magic number
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*/
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enum {
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CODEC_DELAY_1_MS = 1000,
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CODEC_DELAY_1_1_MS = 1100,
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};
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struct msm8x16_wcd_regulator {
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const char *name;
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int min_uv;
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int max_uv;
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int optimum_ua;
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bool ondemand;
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struct regulator *regulator;
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};
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struct on_demand_supply {
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struct regulator *supply;
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atomic_t ref;
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};
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struct wcd_imped_i_ref {
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enum wcd_curr_ref curr_ref;
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int min_val;
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int multiplier;
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int gain_adj;
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int offset;
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};
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struct msm8916_asoc_mach_data {
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int codec_type;
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int ext_pa;
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int us_euro_gpio;
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int spk_ext_pa_gpio;
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int mclk_freq;
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int lb_mode;
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u8 micbias1_cap_mode;
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u8 micbias2_cap_mode;
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atomic_t mclk_rsc_ref;
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atomic_t mclk_enabled;
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atomic_t wsa_mclk_rsc_ref;
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struct mutex cdc_mclk_mutex;
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struct mutex wsa_mclk_mutex;
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struct delayed_work disable_mclk_work;
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struct afe_digital_clk_cfg digital_cdc_clk;
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struct afe_clk_set digital_cdc_core_clk;
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struct afe_clk_set digital_cdc_mclk;
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void __iomem *vaddr_gpio_mux_spkr_ctl;
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void __iomem *vaddr_gpio_mux_mic_ctl;
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void __iomem *vaddr_gpio_mux_quin_ctl;
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void __iomem *vaddr_gpio_mux_pcm_ctl;
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struct on_demand_supply wsa_switch_supply;
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};
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struct msm8x16_wcd_pdata {
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int irq;
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int irq_base;
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int num_irqs;
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int reset_gpio;
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void *msm8x16_wcd_ahb_base_vaddr;
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struct wcd9xxx_micbias_setting micbias;
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struct msm8x16_wcd_regulator regulator[MAX_REGULATOR];
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u32 mclk_rate;
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u32 is_lpass;
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u32 dig_cdc_addr;
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};
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enum msm8x16_wcd_micbias_num {
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MSM8X16_WCD_MICBIAS1 = 0,
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};
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struct msm8x16_wcd {
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struct device *dev;
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struct mutex io_lock;
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u8 version;
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int reset_gpio;
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int (*read_dev)(struct snd_soc_codec *codec,
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unsigned short reg);
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int (*write_dev)(struct snd_soc_codec *codec,
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unsigned short reg, u8 val);
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u32 num_of_supplies;
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struct regulator_bulk_data *supplies;
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u8 idbyte[4];
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int num_irqs;
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u32 mclk_rate;
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char __iomem *dig_base;
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};
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struct msm8x16_wcd_priv {
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struct snd_soc_codec *codec;
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u16 pmic_rev;
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u16 codec_version;
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u32 boost_voltage;
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u32 adc_count;
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u32 rx_bias_count;
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s32 dmic_1_2_clk_cnt;
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u32 mute_mask;
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bool mclk_enabled;
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bool clock_active;
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bool config_mode_active;
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u16 boost_option;
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bool spk_boost_set;
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bool ear_pa_boost_set;
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bool ext_spk_boost_set;
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bool dec_active[NUM_DECIMATORS];
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struct on_demand_supply on_demand_list[ON_DEMAND_SUPPLIES_MAX];
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struct regulator *spkdrv_reg;
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/* mbhc module */
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struct wcd_mbhc mbhc;
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/* cal info for codec */
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struct fw_info *fw_data;
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struct blocking_notifier_head notifier;
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int (*codec_spk_ext_pa_cb)(struct snd_soc_codec *codec, int enable);
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unsigned long status_mask;
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struct wcd_imped_i_ref imped_i_ref;
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enum wcd_mbhc_imp_det_pin imped_det_pin;
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};
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extern int msm8x16_wcd_mclk_enable(struct snd_soc_codec *codec, int mclk_enable,
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bool dapm);
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extern int msm8x16_wcd_hs_detect(struct snd_soc_codec *codec,
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struct wcd_mbhc_config *mbhc_cfg);
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extern void msm8x16_wcd_hs_detect_exit(struct snd_soc_codec *codec);
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extern void msm8x16_wcd_spk_ext_pa_cb(
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int (*codec_spk_ext_pa)(struct snd_soc_codec *codec,
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int enable), struct snd_soc_codec *codec);
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#endif
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