864 lines
24 KiB
C
864 lines
24 KiB
C
/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef MDSS_DSI_H
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#define MDSS_DSI_H
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#include <linux/list.h>
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#include <linux/mdss_io_util.h>
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#include <linux/irqreturn.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/gpio.h>
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#include "mdss_panel.h"
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#include "mdss_dsi_cmd.h"
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#include "mdss_dsi_clk.h"
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#define MMSS_SERDES_BASE_PHY 0x04f01000 /* mmss (De)Serializer CFG */
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#define MIPI_OUTP(addr, data) writel_relaxed((data), (addr))
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#define MIPI_INP(addr) readl_relaxed(addr)
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#define MIPI_OUTP_SECURE(addr, data) writel_relaxed((data), (addr))
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#define MIPI_INP_SECURE(addr) readl_relaxed(addr)
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#define MIPI_DSI_PRIM 1
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#define MIPI_DSI_SECD 2
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#define MIPI_DSI_PANEL_VGA 0
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#define MIPI_DSI_PANEL_WVGA 1
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#define MIPI_DSI_PANEL_WVGA_PT 2
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#define MIPI_DSI_PANEL_FWVGA_PT 3
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#define MIPI_DSI_PANEL_WSVGA_PT 4
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#define MIPI_DSI_PANEL_QHD_PT 5
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#define MIPI_DSI_PANEL_WXGA 6
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#define MIPI_DSI_PANEL_WUXGA 7
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#define MIPI_DSI_PANEL_720P_PT 8
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#define DSI_PANEL_MAX 8
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#define MDSS_DSI_HW_REV_100 0x10000000 /* 8974 */
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#define MDSS_DSI_HW_REV_100_1 0x10000001 /* 8x26 */
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#define MDSS_DSI_HW_REV_100_2 0x10000002 /* 8x26v2 */
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#define MDSS_DSI_HW_REV_101 0x10010000 /* 8974v2 */
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#define MDSS_DSI_HW_REV_101_1 0x10010001 /* 8974Pro */
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#define MDSS_DSI_HW_REV_102 0x10020000 /* 8084 */
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#define MDSS_DSI_HW_REV_103 0x10030000 /* 8994 */
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#define MDSS_DSI_HW_REV_103_1 0x10030001 /* 8916/8936 */
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#define MDSS_DSI_HW_REV_104 0x10040000 /* 8996 */
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#define MDSS_DSI_HW_REV_104_1 0x10040001 /* 8996 */
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#define MDSS_DSI_HW_REV_104_2 0x10040002 /* 8937 */
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#define MDSS_DSI_HW_REV_STEP_0 0x0
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#define MDSS_DSI_HW_REV_STEP_1 0x1
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#define MDSS_DSI_HW_REV_STEP_2 0x2
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#define NONE_PANEL "none"
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enum { /* mipi dsi panel */
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DSI_VIDEO_MODE,
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DSI_CMD_MODE,
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};
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enum {
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ST_DSI_CLK_OFF,
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ST_DSI_SUSPEND,
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ST_DSI_RESUME,
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ST_DSI_PLAYING,
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ST_DSI_NUM
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};
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enum {
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EV_DSI_UPDATE,
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EV_DSI_DONE,
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EV_DSI_TOUT,
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EV_DSI_NUM
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};
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enum {
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LANDSCAPE = 1,
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PORTRAIT = 2,
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};
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enum dsi_trigger_type {
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DSI_CMD_MODE_DMA,
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DSI_CMD_MODE_MDP,
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};
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enum dsi_panel_bl_ctrl {
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BL_PWM,
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BL_WLED,
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BL_DCS_CMD,
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UNKNOWN_CTRL,
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};
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enum dsi_panel_status_mode {
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ESD_NONE = 0,
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ESD_BTA,
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ESD_REG,
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ESD_REG_NT35596,
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ESD_TE,
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ESD_MAX,
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};
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enum dsi_ctrl_op_mode {
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DSI_LP_MODE,
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DSI_HS_MODE,
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};
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enum dsi_lane_map_type {
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DSI_LANE_MAP_0123,
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DSI_LANE_MAP_3012,
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DSI_LANE_MAP_2301,
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DSI_LANE_MAP_1230,
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DSI_LANE_MAP_0321,
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DSI_LANE_MAP_1032,
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DSI_LANE_MAP_2103,
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DSI_LANE_MAP_3210,
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};
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enum dsi_pm_type {
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/* PANEL_PM not used as part of power_data in dsi_shared_data */
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DSI_PANEL_PM,
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DSI_CORE_PM,
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DSI_CTRL_PM,
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DSI_PHY_PM,
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DSI_MAX_PM
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};
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/*
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* DSI controller states.
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* CTRL_STATE_UNKNOWN - Unknown state of DSI controller.
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* CTRL_STATE_PANEL_INIT - State specifies that the panel is initialized.
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* CTRL_STATE_MDP_ACTIVE - State specifies that MDP is ready to send
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* data to DSI.
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* CTRL_STATE_DSI_ACTIVE - State specifies that DSI controller/PHY is
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* initialized.
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*/
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#define CTRL_STATE_UNKNOWN 0x00
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#define CTRL_STATE_PANEL_INIT BIT(0)
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#define CTRL_STATE_MDP_ACTIVE BIT(1)
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#define CTRL_STATE_DSI_ACTIVE BIT(2)
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#define DSI_NON_BURST_SYNCH_PULSE 0
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#define DSI_NON_BURST_SYNCH_EVENT 1
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#define DSI_BURST_MODE 2
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#define DSI_RGB_SWAP_RGB 0
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#define DSI_RGB_SWAP_RBG 1
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#define DSI_RGB_SWAP_BGR 2
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#define DSI_RGB_SWAP_BRG 3
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#define DSI_RGB_SWAP_GRB 4
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#define DSI_RGB_SWAP_GBR 5
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#define DSI_VIDEO_DST_FORMAT_RGB565 0
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#define DSI_VIDEO_DST_FORMAT_RGB666 1
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#define DSI_VIDEO_DST_FORMAT_RGB666_LOOSE 2
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#define DSI_VIDEO_DST_FORMAT_RGB888 3
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#define DSI_CMD_DST_FORMAT_RGB111 0
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#define DSI_CMD_DST_FORMAT_RGB332 3
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#define DSI_CMD_DST_FORMAT_RGB444 4
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#define DSI_CMD_DST_FORMAT_RGB565 6
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#define DSI_CMD_DST_FORMAT_RGB666 7
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#define DSI_CMD_DST_FORMAT_RGB888 8
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#define DSI_INTR_DESJEW_MASK BIT(31)
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#define DSI_INTR_DYNAMIC_REFRESH_MASK BIT(29)
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#define DSI_INTR_DYNAMIC_REFRESH_DONE BIT(28)
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#define DSI_INTR_ERROR_MASK BIT(25)
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#define DSI_INTR_ERROR BIT(24)
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#define DSI_INTR_BTA_DONE_MASK BIT(21)
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#define DSI_INTR_BTA_DONE BIT(20)
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#define DSI_INTR_VIDEO_DONE_MASK BIT(17)
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#define DSI_INTR_VIDEO_DONE BIT(16)
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#define DSI_INTR_CMD_MDP_DONE_MASK BIT(9)
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#define DSI_INTR_CMD_MDP_DONE BIT(8)
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#define DSI_INTR_CMD_DMA_DONE_MASK BIT(1)
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#define DSI_INTR_CMD_DMA_DONE BIT(0)
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/* Update this if more interrupt masks are added in future chipsets */
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#define DSI_INTR_TOTAL_MASK 0x2222AA02
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#define DSI_INTR_MASK_ALL \
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(DSI_INTR_DESJEW_MASK | \
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DSI_INTR_DYNAMIC_REFRESH_MASK | \
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DSI_INTR_ERROR_MASK | \
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DSI_INTR_BTA_DONE_MASK | \
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DSI_INTR_VIDEO_DONE_MASK | \
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DSI_INTR_CMD_MDP_DONE_MASK | \
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DSI_INTR_CMD_DMA_DONE_MASK)
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#define DSI_CMD_TRIGGER_NONE 0x0 /* mdp trigger */
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#define DSI_CMD_TRIGGER_TE 0x02
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#define DSI_CMD_TRIGGER_SW 0x04
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#define DSI_CMD_TRIGGER_SW_SEOF 0x05 /* cmd dma only */
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#define DSI_CMD_TRIGGER_SW_TE 0x06
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#define DSI_VIDEO_TERM BIT(16)
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#define DSI_MDP_TERM BIT(8)
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#define DSI_DYNAMIC_TERM BIT(4)
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#define DSI_BTA_TERM BIT(1)
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#define DSI_CMD_TERM BIT(0)
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#define DSI_DATA_LANES_STOP_STATE 0xF
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#define DSI_CLK_LANE_STOP_STATE BIT(4)
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#define DSI_DATA_LANES_ENABLED 0xF0
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/* offsets for dynamic refresh */
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#define DSI_DYNAMIC_REFRESH_CTRL 0x200
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#define DSI_DYNAMIC_REFRESH_PIPE_DELAY 0x204
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#define DSI_DYNAMIC_REFRESH_PIPE_DELAY2 0x208
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#define DSI_DYNAMIC_REFRESH_PLL_DELAY 0x20C
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#define MAX_ERR_INDEX 10
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extern struct device dsi_dev;
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extern u32 dsi_irq;
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extern struct mdss_dsi_ctrl_pdata *ctrl_list[];
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enum {
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DSI_CTRL_0,
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DSI_CTRL_1,
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DSI_CTRL_MAX,
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};
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/*
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* Common DSI properties for each controller. The DSI root probe will create the
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* shared_data struct which should be accessible to each controller. The goal is
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* to only access ctrl_pdata and ctrl_pdata->shared_data during the lifetime of
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* each controller i.e. mdss_dsi_res should not be used directly.
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*/
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struct dsi_shared_data {
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u32 hw_config; /* DSI setup configuration i.e. single/dual/split */
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u32 pll_src_config; /* PLL source selection for DSI link clocks */
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u32 hw_rev; /* DSI h/w revision */
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u32 phy_rev; /* DSI PHY revision*/
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/* DSI ULPS clamp register offsets */
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u32 ulps_clamp_ctrl_off;
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u32 ulps_phyrst_ctrl_off;
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bool cmd_clk_ln_recovery_en;
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bool dsi0_active;
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bool dsi1_active;
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/* DSI bus clocks */
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struct clk *mdp_core_clk;
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struct clk *ahb_clk;
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struct clk *axi_clk;
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struct clk *mmss_misc_ahb_clk;
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/* Other shared clocks */
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struct clk *ext_byte0_clk;
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struct clk *ext_pixel0_clk;
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struct clk *ext_byte1_clk;
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struct clk *ext_pixel1_clk;
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/* Clock sources for branch clocks */
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struct clk *byte0_parent;
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struct clk *pixel0_parent;
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struct clk *byte1_parent;
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struct clk *pixel1_parent;
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/* DSI core regulators */
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struct dss_module_power power_data[DSI_MAX_PM];
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/* Shared mutex for DSI PHY regulator */
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struct mutex phy_reg_lock;
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/* Data bus(AXI) scale settings */
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struct msm_bus_scale_pdata *bus_scale_table;
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u32 bus_handle;
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u32 bus_refcount;
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};
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struct mdss_dsi_data {
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bool res_init;
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struct platform_device *pdev;
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/* List of controller specific struct data */
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struct mdss_dsi_ctrl_pdata *ctrl_pdata[DSI_CTRL_MAX];
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/*
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* This structure should hold common data structures like
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* mutex, clocks, regulator information, setup information
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*/
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struct dsi_shared_data *shared_data;
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};
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/*
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* enum mdss_dsi_hw_config - Supported DSI h/w configurations
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*
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* @SINGLE_DSI: Single DSI panel driven by either DSI0 or DSI1.
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* @DUAL_DSI: Two DSI panels driven independently by DSI0 & DSI1.
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* @SPLIT_DSI: A split DSI panel driven by both the DSI controllers
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* with the DSI link clocks sourced by a single DSI PLL.
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*/
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enum mdss_dsi_hw_config {
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SINGLE_DSI,
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DUAL_DSI,
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SPLIT_DSI,
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};
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/*
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* enum mdss_dsi_pll_src_config - The PLL source for DSI link clocks
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*
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* @PLL_SRC_0: The link clocks are sourced out of PLL0.
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* @PLL_SRC_1: The link clocks are sourced out of PLL1.
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*/
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enum mdss_dsi_pll_src_config {
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PLL_SRC_DEFAULT,
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PLL_SRC_0,
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PLL_SRC_1,
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};
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struct dsi_panel_cmds {
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char *buf;
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int blen;
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struct dsi_cmd_desc *cmds;
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int cmd_cnt;
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int link_state;
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};
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struct dsi_panel_timing {
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struct mdss_panel_timing timing;
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uint32_t phy_timing[12];
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uint32_t phy_timing_8996[40];
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/* DSI_CLKOUT_TIMING_CTRL */
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char t_clk_post;
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char t_clk_pre;
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struct dsi_panel_cmds on_cmds;
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struct dsi_panel_cmds post_panel_on_cmds;
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struct dsi_panel_cmds switch_cmds;
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};
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struct dsi_kickoff_action {
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struct list_head act_entry;
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void (*action) (void *);
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void *data;
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};
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struct dsi_pinctrl_res {
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struct pinctrl *pinctrl;
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struct pinctrl_state *gpio_state_active;
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struct pinctrl_state *gpio_state_suspend;
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};
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struct panel_horizontal_idle {
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int min;
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int max;
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int idle;
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};
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struct dsi_err_container {
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u32 fifo_err_cnt;
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u32 phy_err_cnt;
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u32 err_cnt;
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u32 err_time_delta;
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u32 max_err_index;
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u32 index;
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s64 err_time[MAX_ERR_INDEX];
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};
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#define DSI_CTRL_LEFT DSI_CTRL_0
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#define DSI_CTRL_RIGHT DSI_CTRL_1
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#define DSI_CTRL_CLK_SLAVE DSI_CTRL_RIGHT
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#define DSI_CTRL_CLK_MASTER DSI_CTRL_LEFT
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#define DSI_EV_PLL_UNLOCKED 0x0001
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#define DSI_EV_MDP_FIFO_UNDERFLOW 0x0002
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#define DSI_EV_DSI_FIFO_EMPTY 0x0004
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#define DSI_EV_DLNx_FIFO_OVERFLOW 0x0008
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#define DSI_EV_LP_RX_TIMEOUT 0x0010
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#define DSI_EV_STOP_HS_CLK_LANE 0x40000000
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#define DSI_EV_MDP_BUSY_RELEASE 0x80000000
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#define MDSS_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x02a0
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#define MDSS_DSI_VIDEO_COMPRESSION_MODE_CTRL2 0x02a4
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#define MDSS_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x02a8
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#define MDSS_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x02ac
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#define MDSS_DSI_COMMAND_COMPRESSION_MODE_CTRL3 0x02b0
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struct mdss_dsi_ctrl_pdata {
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int ndx; /* panel_num */
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int (*on) (struct mdss_panel_data *pdata);
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int (*post_panel_on)(struct mdss_panel_data *pdata);
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int (*off) (struct mdss_panel_data *pdata);
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int (*low_power_config) (struct mdss_panel_data *pdata, int enable);
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int (*set_col_page_addr)(struct mdss_panel_data *pdata, bool force);
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int (*check_status) (struct mdss_dsi_ctrl_pdata *pdata);
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int (*check_read_status) (struct mdss_dsi_ctrl_pdata *pdata);
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int (*cmdlist_commit)(struct mdss_dsi_ctrl_pdata *ctrl, int from_mdp);
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void (*switch_mode) (struct mdss_panel_data *pdata, int mode);
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struct mdss_panel_data panel_data;
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unsigned char *ctrl_base;
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struct dss_io_data ctrl_io;
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struct dss_io_data mmss_misc_io;
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struct dss_io_data phy_io;
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struct dss_io_data phy_regulator_io;
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int reg_size;
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u32 flags;
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struct clk *byte_clk;
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struct clk *esc_clk;
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struct clk *pixel_clk;
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struct clk *mux_byte_clk;
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struct clk *mux_pixel_clk;
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struct clk *pll_byte_clk;
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struct clk *pll_pixel_clk;
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struct clk *shadow_byte_clk;
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struct clk *shadow_pixel_clk;
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struct clk *byte_clk_rcg;
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struct clk *pixel_clk_rcg;
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struct clk *vco_dummy_clk;
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u8 ctrl_state;
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int panel_mode;
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int irq_cnt;
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int disp_te_gpio;
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int rst_gpio;
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int disp_en_gpio;
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int bklt_en_gpio;
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int mode_gpio;
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int bklt_ctrl; /* backlight ctrl */
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bool pwm_pmi;
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int pwm_period;
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int pwm_pmic_gpio;
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int pwm_lpg_chan;
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int bklt_max;
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int new_fps;
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int pwm_enabled;
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int clk_lane_cnt;
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bool dmap_iommu_map;
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bool dsi_irq_line;
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bool dcs_cmd_insert;
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atomic_t te_irq_ready;
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bool cmd_sync_wait_broadcast;
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bool cmd_sync_wait_trigger;
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struct mdss_rect roi;
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struct pwm_device *pwm_bl;
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u32 pclk_rate;
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u32 byte_clk_rate;
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u32 pclk_rate_bkp;
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u32 byte_clk_rate_bkp;
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bool refresh_clk_rate; /* flag to recalculate clk_rate */
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struct dss_module_power panel_power_data;
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struct dss_module_power power_data[DSI_MAX_PM]; /* for 8x10 */
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u32 dsi_irq_mask;
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struct mdss_hw *dsi_hw;
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struct mdss_intf_recovery *recovery;
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struct dsi_panel_cmds on_cmds;
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struct dsi_panel_cmds post_dms_on_cmds;
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struct dsi_panel_cmds post_panel_on_cmds;
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struct dsi_panel_cmds off_cmds;
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struct dsi_panel_cmds status_cmds;
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|
u32 status_cmds_rlen;
|
|
u32 *status_value;
|
|
u32 status_error_count;
|
|
u32 max_status_error_count;
|
|
|
|
struct dsi_panel_cmds video2cmd;
|
|
struct dsi_panel_cmds cmd2video;
|
|
|
|
char pps_buf[DSC_PPS_LEN]; /* dsc pps */
|
|
|
|
struct dcs_cmd_list cmdlist;
|
|
struct completion dma_comp;
|
|
struct completion mdp_comp;
|
|
struct completion video_comp;
|
|
struct completion dynamic_comp;
|
|
struct completion bta_comp;
|
|
spinlock_t irq_lock;
|
|
spinlock_t mdp_lock;
|
|
int mdp_busy;
|
|
struct mutex mutex;
|
|
struct mutex cmd_mutex;
|
|
struct mutex cmdlist_mutex;
|
|
struct regulator *lab; /* vreg handle */
|
|
struct regulator *ibb; /* vreg handle */
|
|
struct mutex clk_lane_mutex;
|
|
|
|
bool null_insert_enabled;
|
|
bool ulps;
|
|
bool core_power;
|
|
bool mmss_clamp;
|
|
char dlane_swap; /* data lane swap */
|
|
bool is_phyreg_enabled;
|
|
bool burst_mode_enabled;
|
|
|
|
struct dsi_buf tx_buf;
|
|
struct dsi_buf rx_buf;
|
|
struct dsi_buf status_buf;
|
|
int status_mode;
|
|
int rx_len;
|
|
int cur_max_pkt_size;
|
|
|
|
struct dsi_pinctrl_res pin_res;
|
|
|
|
unsigned long dma_size;
|
|
dma_addr_t dma_addr;
|
|
bool cmd_cfg_restore;
|
|
bool do_unicast;
|
|
|
|
int horizontal_idle_cnt;
|
|
struct panel_horizontal_idle *line_idle;
|
|
struct mdss_util_intf *mdss_util;
|
|
struct dsi_shared_data *shared_data;
|
|
|
|
void *clk_mngr;
|
|
void *dsi_clk_handle;
|
|
void *mdp_clk_handle;
|
|
int m_vote_cnt;
|
|
/* debugfs structure */
|
|
struct mdss_dsi_debugfs_info *debugfs_info;
|
|
|
|
struct dsi_err_container err_cont;
|
|
|
|
|
|
bool ds_registered;
|
|
|
|
struct kobject *kobj;
|
|
int fb_node;
|
|
|
|
struct workqueue_struct *workq;
|
|
struct delayed_work dba_work;
|
|
bool timing_db_mode;
|
|
};
|
|
|
|
struct dsi_status_data {
|
|
struct notifier_block fb_notifier;
|
|
struct delayed_work check_status;
|
|
struct msm_fb_data_type *mfd;
|
|
};
|
|
|
|
void mdss_dsi_read_hw_revision(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
int dsi_panel_device_register(struct platform_device *ctrl_pdev,
|
|
struct device_node *pan_node, struct mdss_dsi_ctrl_pdata *ctrl_pdata);
|
|
|
|
int mdss_dsi_cmds_tx(struct mdss_dsi_ctrl_pdata *ctrl,
|
|
struct dsi_cmd_desc *cmds, int cnt, int use_dma_tpg);
|
|
|
|
int mdss_dsi_cmds_rx(struct mdss_dsi_ctrl_pdata *ctrl,
|
|
struct dsi_cmd_desc *cmds, int rlen, int use_dma_tpg);
|
|
|
|
void mdss_dsi_host_init(struct mdss_panel_data *pdata);
|
|
void mdss_dsi_op_mode_config(int mode,
|
|
struct mdss_panel_data *pdata);
|
|
void mdss_dsi_restore_intr_mask(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
void mdss_dsi_cmd_mode_ctrl(int enable);
|
|
void mdp4_dsi_cmd_trigger(void);
|
|
void mdss_dsi_cmd_mdp_start(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
void mdss_dsi_cmd_bta_sw_trigger(struct mdss_panel_data *pdata);
|
|
void mdss_dsi_ack_err_status(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
int mdss_dsi_clk_ctrl(struct mdss_dsi_ctrl_pdata *ctrl, void *clk_handle,
|
|
enum mdss_dsi_clk_type clk_type, enum mdss_dsi_clk_state clk_state);
|
|
void mdss_dsi_clk_req(struct mdss_dsi_ctrl_pdata *ctrl,
|
|
struct dsi_panel_clk_ctrl *clk_ctrl);
|
|
void mdss_dsi_controller_cfg(int enable,
|
|
struct mdss_panel_data *pdata);
|
|
void mdss_dsi_sw_reset(struct mdss_dsi_ctrl_pdata *ctrl_pdata, bool restore);
|
|
|
|
irqreturn_t mdss_dsi_isr(int irq, void *ptr);
|
|
irqreturn_t hw_vsync_handler(int irq, void *data);
|
|
void mdss_dsi_irq_handler_config(struct mdss_dsi_ctrl_pdata *ctrl_pdata);
|
|
|
|
void mdss_dsi_set_tx_power_mode(int mode, struct mdss_panel_data *pdata);
|
|
int mdss_dsi_clk_div_config(struct mdss_panel_info *panel_info,
|
|
int frame_rate);
|
|
int mdss_dsi_clk_refresh(struct mdss_panel_data *pdata);
|
|
int mdss_dsi_link_clk_init(struct platform_device *pdev,
|
|
struct mdss_dsi_ctrl_pdata *ctrl_pdata);
|
|
void mdss_dsi_link_clk_deinit(struct device *dev,
|
|
struct mdss_dsi_ctrl_pdata *ctrl_pdata);
|
|
int mdss_dsi_core_clk_init(struct platform_device *pdev,
|
|
struct dsi_shared_data *sdata);
|
|
void mdss_dsi_core_clk_deinit(struct device *dev,
|
|
struct dsi_shared_data *sdata);
|
|
int mdss_dsi_shadow_clk_init(struct platform_device *pdev,
|
|
struct mdss_dsi_ctrl_pdata *ctrl_pdata);
|
|
void mdss_dsi_shadow_clk_deinit(struct device *dev,
|
|
struct mdss_dsi_ctrl_pdata *ctrl_pdata);
|
|
int mdss_dsi_pre_clkoff_cb(void *priv,
|
|
enum mdss_dsi_clk_type clk_type,
|
|
enum mdss_dsi_clk_state new_state);
|
|
int mdss_dsi_post_clkoff_cb(void *priv,
|
|
enum mdss_dsi_clk_type clk_type,
|
|
enum mdss_dsi_clk_state curr_state);
|
|
int mdss_dsi_post_clkon_cb(void *priv,
|
|
enum mdss_dsi_clk_type clk_type,
|
|
enum mdss_dsi_clk_state curr_state);
|
|
int mdss_dsi_pre_clkon_cb(void *priv,
|
|
enum mdss_dsi_clk_type clk_type,
|
|
enum mdss_dsi_clk_state new_state);
|
|
int mdss_dsi_panel_reset(struct mdss_panel_data *pdata, int enable);
|
|
void mdss_dsi_phy_disable(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
void mdss_dsi_cmd_test_pattern(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
void mdss_dsi_video_test_pattern(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
void mdss_dsi_panel_pwm_cfg(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
bool mdss_dsi_panel_pwm_enable(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
void mdss_dsi_ctrl_phy_restore(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
void mdss_dsi_phy_sw_reset(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
void mdss_dsi_phy_init(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
void mdss_dsi_ctrl_init(struct device *ctrl_dev,
|
|
struct mdss_dsi_ctrl_pdata *ctrl);
|
|
void mdss_dsi_cmd_mdp_busy(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
void mdss_dsi_wait4video_done(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
int mdss_dsi_en_wait4dynamic_done(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
int mdss_dsi_cmdlist_commit(struct mdss_dsi_ctrl_pdata *ctrl, int from_mdp);
|
|
void mdss_dsi_cmdlist_kickoff(int intf);
|
|
int mdss_dsi_bta_status_check(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
int mdss_dsi_reg_status_check(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
bool __mdss_dsi_clk_enabled(struct mdss_dsi_ctrl_pdata *ctrl, u8 clk_type);
|
|
void mdss_dsi_ctrl_setup(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
void mdss_dsi_dln0_phy_err(struct mdss_dsi_ctrl_pdata *ctrl, bool print_en);
|
|
void mdss_dsi_lp_cd_rx(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
void mdss_dsi_get_hw_revision(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
void mdss_dsi_read_phy_revision(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
u32 mdss_dsi_panel_cmd_read(struct mdss_dsi_ctrl_pdata *ctrl, char cmd0,
|
|
char cmd1, void (*fxn)(int), char *rbuf, int len);
|
|
int mdss_dsi_panel_init(struct device_node *node,
|
|
struct mdss_dsi_ctrl_pdata *ctrl_pdata,
|
|
int ndx);
|
|
int mdss_dsi_panel_timing_switch(struct mdss_dsi_ctrl_pdata *ctrl_pdata,
|
|
struct mdss_panel_timing *timing);
|
|
|
|
int mdss_panel_parse_bl_settings(struct device_node *np,
|
|
struct mdss_dsi_ctrl_pdata *ctrl_pdata);
|
|
int mdss_panel_get_dst_fmt(u32 bpp, char mipi_mode, u32 pixel_packing,
|
|
char *dst_format);
|
|
|
|
int mdss_dsi_register_recovery_handler(struct mdss_dsi_ctrl_pdata *ctrl,
|
|
struct mdss_intf_recovery *recovery);
|
|
void mdss_dsi_unregister_bl_settings(struct mdss_dsi_ctrl_pdata *ctrl_pdata);
|
|
void mdss_dsi_panel_dsc_pps_send(struct mdss_dsi_ctrl_pdata *ctrl,
|
|
struct mdss_panel_info *pinfo);
|
|
void mdss_dsi_dsc_config(struct mdss_dsi_ctrl_pdata *ctrl,
|
|
struct dsc_desc *dsc);
|
|
void mdss_dsi_dfps_config_8996(struct mdss_dsi_ctrl_pdata *ctrl);
|
|
|
|
static inline const char *__mdss_dsi_pm_name(enum dsi_pm_type module)
|
|
{
|
|
switch (module) {
|
|
case DSI_CORE_PM: return "DSI_CORE_PM";
|
|
case DSI_CTRL_PM: return "DSI_CTRL_PM";
|
|
case DSI_PHY_PM: return "DSI_PHY_PM";
|
|
case DSI_PANEL_PM: return "PANEL_PM";
|
|
default: return "???";
|
|
}
|
|
}
|
|
|
|
static inline const char *__mdss_dsi_pm_supply_node_name(
|
|
enum dsi_pm_type module)
|
|
{
|
|
switch (module) {
|
|
case DSI_CORE_PM: return "qcom,core-supply-entries";
|
|
case DSI_CTRL_PM: return "qcom,ctrl-supply-entries";
|
|
case DSI_PHY_PM: return "qcom,phy-supply-entries";
|
|
case DSI_PANEL_PM: return "qcom,panel-supply-entries";
|
|
default: return "???";
|
|
}
|
|
}
|
|
|
|
static inline u32 mdss_dsi_get_hw_config(struct dsi_shared_data *sdata)
|
|
{
|
|
return sdata->hw_config;
|
|
}
|
|
|
|
static inline bool mdss_dsi_is_hw_config_single(struct dsi_shared_data *sdata)
|
|
{
|
|
return mdss_dsi_get_hw_config(sdata) == SINGLE_DSI;
|
|
}
|
|
|
|
static inline bool mdss_dsi_is_hw_config_split(struct dsi_shared_data *sdata)
|
|
{
|
|
return mdss_dsi_get_hw_config(sdata) == SPLIT_DSI;
|
|
}
|
|
|
|
static inline bool mdss_dsi_is_hw_config_dual(struct dsi_shared_data *sdata)
|
|
{
|
|
return mdss_dsi_get_hw_config(sdata) == DUAL_DSI;
|
|
}
|
|
|
|
static inline bool mdss_dsi_get_pll_src_config(struct dsi_shared_data *sdata)
|
|
{
|
|
return sdata->pll_src_config;
|
|
}
|
|
|
|
/*
|
|
* mdss_dsi_is_pll_src_default: Check if the DSI device uses default PLL src
|
|
* For single-dsi and dual-dsi configuration, PLL source need not be
|
|
* explicitly specified. In this case, the default PLL source configuration
|
|
* is assumed.
|
|
*
|
|
* @sdata: pointer to DSI shared data structure
|
|
*/
|
|
static inline bool mdss_dsi_is_pll_src_default(struct dsi_shared_data *sdata)
|
|
{
|
|
return sdata->pll_src_config == PLL_SRC_DEFAULT;
|
|
}
|
|
|
|
/*
|
|
* mdss_dsi_is_pll_src_pll0: Check if the PLL source for a DSI device is PLL0
|
|
* The function is only valid if the DSI configuration is single/split DSI.
|
|
* Not valid for dual DSI configuration.
|
|
*
|
|
* @sdata: pointer to DSI shared data structure
|
|
*/
|
|
static inline bool mdss_dsi_is_pll_src_pll0(struct dsi_shared_data *sdata)
|
|
{
|
|
return sdata->pll_src_config == PLL_SRC_0;
|
|
}
|
|
|
|
/*
|
|
* mdss_dsi_is_pll_src_pll1: Check if the PLL source for a DSI device is PLL1
|
|
* The function is only valid if the DSI configuration is single/split DSI.
|
|
* Not valid for dual DSI configuration.
|
|
*
|
|
* @sdata: pointer to DSI shared data structure
|
|
*/
|
|
static inline bool mdss_dsi_is_pll_src_pll1(struct dsi_shared_data *sdata)
|
|
{
|
|
return sdata->pll_src_config == PLL_SRC_1;
|
|
}
|
|
|
|
static inline bool mdss_dsi_is_dsi0_active(struct dsi_shared_data *sdata)
|
|
{
|
|
return sdata->dsi0_active;
|
|
}
|
|
|
|
static inline bool mdss_dsi_is_dsi1_active(struct dsi_shared_data *sdata)
|
|
{
|
|
return sdata->dsi1_active;
|
|
}
|
|
|
|
static inline u32 mdss_dsi_get_phy_revision(struct mdss_dsi_ctrl_pdata *ctrl)
|
|
{
|
|
return ctrl->shared_data->phy_rev;
|
|
}
|
|
|
|
static inline const char *mdss_dsi_get_fb_name(struct mdss_dsi_ctrl_pdata *ctrl)
|
|
{
|
|
struct mdss_panel_info *pinfo = &(ctrl->panel_data.panel_info);
|
|
|
|
if (mdss_dsi_is_hw_config_dual(ctrl->shared_data)) {
|
|
if (pinfo->is_prim_panel)
|
|
return "qcom,mdss-fb-map-prim";
|
|
else
|
|
return "qcom,mdss-fb-map-sec";
|
|
} else {
|
|
return "qcom,mdss-fb-map-prim";
|
|
}
|
|
}
|
|
|
|
static inline bool mdss_dsi_sync_wait_enable(struct mdss_dsi_ctrl_pdata *ctrl)
|
|
{
|
|
return ctrl->cmd_sync_wait_broadcast;
|
|
}
|
|
|
|
static inline bool mdss_dsi_sync_wait_trigger(struct mdss_dsi_ctrl_pdata *ctrl)
|
|
{
|
|
return ctrl->cmd_sync_wait_broadcast &&
|
|
ctrl->cmd_sync_wait_trigger;
|
|
}
|
|
|
|
static inline bool mdss_dsi_is_left_ctrl(struct mdss_dsi_ctrl_pdata *ctrl)
|
|
{
|
|
return ctrl->ndx == DSI_CTRL_LEFT;
|
|
}
|
|
|
|
static inline bool mdss_dsi_is_right_ctrl(struct mdss_dsi_ctrl_pdata *ctrl)
|
|
{
|
|
return ctrl->ndx == DSI_CTRL_RIGHT;
|
|
}
|
|
|
|
static inline struct mdss_dsi_ctrl_pdata *mdss_dsi_get_other_ctrl(
|
|
struct mdss_dsi_ctrl_pdata *ctrl)
|
|
{
|
|
if (ctrl->ndx == DSI_CTRL_RIGHT)
|
|
return ctrl_list[DSI_CTRL_LEFT];
|
|
|
|
return ctrl_list[DSI_CTRL_RIGHT];
|
|
}
|
|
|
|
static inline struct mdss_dsi_ctrl_pdata *mdss_dsi_get_ctrl_by_index(int ndx)
|
|
{
|
|
if (ndx >= DSI_CTRL_MAX)
|
|
return NULL;
|
|
|
|
return ctrl_list[ndx];
|
|
}
|
|
|
|
static inline bool mdss_dsi_is_ctrl_clk_master(struct mdss_dsi_ctrl_pdata *ctrl)
|
|
{
|
|
return mdss_dsi_is_hw_config_split(ctrl->shared_data) &&
|
|
(ctrl->ndx == DSI_CTRL_CLK_MASTER);
|
|
}
|
|
|
|
static inline bool mdss_dsi_is_ctrl_clk_slave(struct mdss_dsi_ctrl_pdata *ctrl)
|
|
{
|
|
return mdss_dsi_is_hw_config_split(ctrl->shared_data) &&
|
|
(ctrl->ndx == DSI_CTRL_CLK_SLAVE);
|
|
}
|
|
|
|
static inline bool mdss_dsi_is_te_based_esd(struct mdss_dsi_ctrl_pdata *ctrl)
|
|
{
|
|
return (ctrl->status_mode == ESD_TE) &&
|
|
gpio_is_valid(ctrl->disp_te_gpio) &&
|
|
mdss_dsi_is_left_ctrl(ctrl);
|
|
}
|
|
|
|
static inline struct mdss_dsi_ctrl_pdata *mdss_dsi_get_ctrl_clk_master(void)
|
|
{
|
|
return ctrl_list[DSI_CTRL_CLK_MASTER];
|
|
}
|
|
|
|
static inline struct mdss_dsi_ctrl_pdata *mdss_dsi_get_ctrl_clk_slave(void)
|
|
{
|
|
return ctrl_list[DSI_CTRL_CLK_SLAVE];
|
|
}
|
|
|
|
static inline bool mdss_dsi_is_panel_off(struct mdss_panel_data *pdata)
|
|
{
|
|
return mdss_panel_is_power_off(pdata->panel_info.panel_power_state);
|
|
}
|
|
|
|
static inline bool mdss_dsi_is_panel_on(struct mdss_panel_data *pdata)
|
|
{
|
|
return mdss_panel_is_power_on(pdata->panel_info.panel_power_state);
|
|
}
|
|
|
|
static inline bool mdss_dsi_is_panel_on_interactive(
|
|
struct mdss_panel_data *pdata)
|
|
{
|
|
return mdss_panel_is_power_on_interactive(
|
|
pdata->panel_info.panel_power_state);
|
|
}
|
|
|
|
static inline bool mdss_dsi_is_panel_on_lp(struct mdss_panel_data *pdata)
|
|
{
|
|
return mdss_panel_is_power_on_lp(pdata->panel_info.panel_power_state);
|
|
}
|
|
|
|
static inline bool mdss_dsi_ulps_feature_enabled(
|
|
struct mdss_panel_data *pdata)
|
|
{
|
|
return pdata->panel_info.ulps_feature_enabled;
|
|
}
|
|
|
|
static inline bool mdss_dsi_cmp_panel_reg(struct dsi_buf status_buf,
|
|
u32 *status_val, int i)
|
|
{
|
|
return status_buf.data[i] == status_val[i];
|
|
}
|
|
|
|
#endif /* MDSS_DSI_H */
|