269 lines
6.5 KiB
C
269 lines
6.5 KiB
C
/************************************************************
|
|
* Copyright (C), 2015, TP-LINK TECHNOLOGIES CO., LTD.
|
|
*
|
|
* File name: s90319fb.h
|
|
* Version: 1.0
|
|
* Description: Framebuffer driver for LCD s90319.
|
|
*
|
|
* Author: Wang Dongyang
|
|
* Create Date: 2015-07
|
|
************************************************************/
|
|
|
|
#ifndef __S90319FB_H__
|
|
#define __S90319FB_H__
|
|
|
|
struct s90319fb_info {
|
|
struct device *dev;
|
|
};
|
|
|
|
struct s90319fb_mach_info {
|
|
struct s90319fb_display *displays; /* attached diplays info */
|
|
u8 num_displays; /* number of defined displays */
|
|
u8 default_display;
|
|
};
|
|
|
|
/* LCD description */
|
|
struct s90319fb_display {
|
|
/* Screen size */
|
|
u16 width;
|
|
u16 height;
|
|
|
|
/* Screen info */
|
|
u16 xres;
|
|
u16 yres;
|
|
u16 bpp;
|
|
|
|
u32 pixclock; /* pixclock in picoseconds */
|
|
u16 left_margin; /* value in pixels (TFT) or HCLKs (STN) */
|
|
u16 right_margin; /* value in pixels (TFT) or HCLKs (STN) */
|
|
u16 hsync_len; /* value in pixels (TFT) or HCLKs (STN) */
|
|
u16 upper_margin; /* value in lines (TFT) or 0 (STN) */
|
|
u16 lower_margin; /* value in lines (TFT) or 0 (STN) */
|
|
u16 vsync_len; /* value in lines (TFT) or 0 (STN) */
|
|
};
|
|
|
|
#define ROW_NUM 128
|
|
#define PAGE_NUM 128
|
|
#define COLUMN_NUM 128
|
|
|
|
#define X_OFFSET 2
|
|
#define Y_OFFSET 3
|
|
#define Y_OFFSET_GC9106 1
|
|
|
|
uint8_t oled_s90319_set_col_addr[] = {
|
|
0x00, 0x00, 0x00, 0x00
|
|
};
|
|
|
|
uint8_t oled_s90319_set_row_addr[] = {
|
|
0x00, 0x00, 0x00, 0x00
|
|
};
|
|
|
|
#define OLED_SET_COL_CMD 0x2A
|
|
#define OLED_SET_ROW_CMD 0x2B
|
|
#define OLED_WRITE_DATA_CMD 0x2C
|
|
|
|
/* set col command */
|
|
uint8_t oled_set_col_cmd[] = {
|
|
OLED_SET_COL_CMD,
|
|
};
|
|
|
|
/* set row command */
|
|
uint8_t oled_set_row_cmd[] = {
|
|
OLED_SET_ROW_CMD,
|
|
};
|
|
|
|
/* write data command */
|
|
uint8_t oled_write_data_cmd[] = {
|
|
OLED_WRITE_DATA_CMD,
|
|
};
|
|
|
|
#define CMD_DISPLAY_OFF_ON(bit) (0xAE|(bit)) /* v: 0|1 */
|
|
#define CMD_DOUBLE_SET_CHARGE_PUMP 0x8D /* Enable: 0x14, Disable: 0x10*/
|
|
|
|
|
|
/* set backlight command */
|
|
uint8_t oled_s90319_backlight_cmd[] = {
|
|
CMD_DISPLAY_OFF_ON(0)
|
|
};
|
|
|
|
/* panel on/off command */
|
|
uint8_t oled_s90319_panel_off_cmd[] = {
|
|
CMD_DISPLAY_OFF_ON(0), /* manual display on */
|
|
CMD_DOUBLE_SET_CHARGE_PUMP, 0x10 /* set charge pump enable*/
|
|
};
|
|
|
|
/* GPIO */
|
|
//#define LCD_BL 3
|
|
//#define LCD_RST 4
|
|
//#define LCD_CS 23
|
|
//#define LCD_RS 22
|
|
//#define LCD_WR 21
|
|
//#define LCD_RD 20
|
|
|
|
//#define SETX_REG 0x2A /* register to set the point of x */
|
|
//#define SETY_REG 0x2B /* register to set the point of y */
|
|
//#define MEMWR_REG 0x2C /* register of memrory write */
|
|
|
|
//#define CTRL_GPIO 20 /* ctrl start from 20 */
|
|
//#define DATA_GPIO 12 /* data start from 12 */
|
|
|
|
/*GPIO 20-23 control */
|
|
//#define CTRL_START 0x1 /* (0001) prepare to transfer cmd */
|
|
//#define CTRL_END 0xb /* (1011) cmd over */
|
|
//#define DATA_START 0x5 /* (0101) prepare to transfer data */
|
|
//#define DATA_END 0xf /* (1111) data over */
|
|
|
|
//#define CTRL_RESET 0xff0fffff /* GPIO ctrl 20 - 23 */
|
|
//#define DATA_RESET 0xfff00fff /* GPIO data 12 - 19 */
|
|
//#define CRTL_DATA_RESET 0xff000fff /* GPIO ctrl & data 12 - 23 */
|
|
//#define OUTENABLE 0xff000fe7 /* set GPIO 3,4, 12 - 23 output enable */
|
|
|
|
#define BACKLIGHT_LEVEL_MAX 32 /* backlight max level */
|
|
#define BACKLIGHT_LEVEL_MIN 0 /* backlight shut down */
|
|
#define BACKLIGHT_INIT_MIN 32 /* the least time to init ( > 30 us) */
|
|
#define BACKLIGHT_LSD 3020 /* the least time to close ( > 3ms) */
|
|
#define BACKLIGHT_LTD 100 /* last time for low ( 0.5 - 500 us) */
|
|
#define BACKLIGHT_HTD 1 /* last time for high ( > 0.5 us) */
|
|
|
|
/* command to init LCD */
|
|
u8 MDDIC[] = {
|
|
1, /* the number of parameters */
|
|
0xE0, /* the address of register */
|
|
0x01 /* the parameter of the register */
|
|
};
|
|
|
|
u8 SLEEPOUT[] = {
|
|
0, 0x11
|
|
};
|
|
|
|
/* VCOM Control Register */
|
|
u8 VCMCTL[] = {
|
|
5, 0xF4, 0x59, 0x59, 0x57, 0x57, 0x11
|
|
};
|
|
|
|
/* Source Output Control Register */
|
|
u8 SRCCTL[] = {
|
|
6, 0xF5, 0x12, 0x00, 0x0B, 0xF0, 0x00, 0x1F
|
|
};
|
|
|
|
/* PWRCTL : Power Control Register */
|
|
u8 PWRCTL[] = {
|
|
8, 0xF3, 0xFF, 0x2A, 0x2A, 0x07, 0x22, 0x57, 0x57, 0x20
|
|
};
|
|
|
|
/* Display Control Register */
|
|
u8 DISCTRL[] = {
|
|
11, 0xF2, 0x0E, 0x14, 0x00, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x1A, 0x1A
|
|
};
|
|
|
|
/* Positive Gamma Control Register for Red */
|
|
u8 POSRED[] = {
|
|
15, 0xF7, 0x1A, 0x03, 0x00, 0x00, 0x00, 0x12, 0x26,0x35, 0x05, 0x00,\
|
|
0x12, 0x0E, 0x00, 0x88, 0x22
|
|
};
|
|
|
|
/* Negative Gamma Control Register for Red */
|
|
u8 NEGRED[] = {
|
|
15, 0xF8, 0x03, 0x1A, 0x00, 0x00, 0x00, 0x12, 0x26, 0x35,0x05, 0x00,\
|
|
0x12, 0x0E, 0x00, 0x88, 0x22
|
|
};
|
|
|
|
/* Positive Gamma Control Register for Green */
|
|
u8 POSGREEN[] = {
|
|
15, 0xF9, 0x1D, 0x03, 0x00, 0x00, 0x00, 0x19, 0x2A, 0x33,0x08, 0x00,\
|
|
0x10, 0x0E, 0x04, 0x88, 0x22
|
|
};
|
|
|
|
/* Negative Gamma Control Register for Green */
|
|
u8 NEGGREEN[] = {
|
|
15, 0xFA, 0x03, 0x1D, 0x00, 0x00, 0x00, 0x19, 0x2A, 0x33, 0x08, 0x00,\
|
|
0x10, 0x0E, 0x04, 0x88, 0x42
|
|
};
|
|
|
|
/* Positive Gamma Control Register for Blue */
|
|
u8 POSBLUE[] = {
|
|
15, 0xFB, 0x06, 0x03, 0x03, 0x05, 0x05, 0x14, 0x23, 0x2D, 0x0E, 0x0E,\
|
|
0x1D, 0x19, 0x09, 0x88, 0x22
|
|
};
|
|
|
|
/* Negative Gamma Control Register for Blue */
|
|
u8 NEGBLUE[] = {
|
|
15, 0xFC, 0x03, 0x06, 0x03, 0x05, 0x05, 0x14, 0x23, 0x2D, 0x0E, 0x0E,\
|
|
0x1D, 0x19, 0x09, 0x88, 0x12
|
|
};
|
|
|
|
/* Turn on the Tearing Effect output signal */
|
|
u8 TEARLINE[] = {
|
|
1, 0x35, 0x00
|
|
};
|
|
|
|
/* Memrory write */
|
|
u8 MEMWR[] = {
|
|
0, 0x2C
|
|
};
|
|
|
|
/* Display on */
|
|
u8 DISON[] = {
|
|
0, 0x29
|
|
};
|
|
|
|
/* Interface Control Register */
|
|
u8 INTERFACE[] = {
|
|
4,
|
|
0xF6,
|
|
0x00, /* IPM---MDT[1,0]=01 */
|
|
0x08,
|
|
0x10,
|
|
0x00
|
|
};
|
|
|
|
/* COLMOD : Interface Pixel Format */
|
|
u8 COLMOD[] = {
|
|
1,
|
|
0x3A,
|
|
0x55 /* 565----16-bits/pixel */
|
|
};
|
|
|
|
/* Display the RAM */
|
|
u8 DISPLAY[] = {
|
|
1,
|
|
0x36,
|
|
0x28 /* X-Y exchange PAL_BGR: RRGGBB */
|
|
};
|
|
|
|
/* Gate Control Register */
|
|
u8 GATECON[] = {
|
|
2,
|
|
0xFD,
|
|
0x02,
|
|
0x01 /* 240 * 400 */
|
|
};
|
|
|
|
/* Set the point of y */
|
|
u8 SETY[] = {
|
|
4,
|
|
0x2B,
|
|
0x00,
|
|
0x00, /* start 0 */
|
|
0x00,
|
|
0xEF /* end 239 */
|
|
};
|
|
|
|
/* Set the point of x */
|
|
u8 SETX[] = {
|
|
4,
|
|
0x2A,
|
|
0x00,
|
|
0x00, /* start 0*/
|
|
0x01,
|
|
0x8F /* end 319 */
|
|
};
|
|
|
|
u8 *init_cmd[] = {
|
|
MDDIC, SLEEPOUT, VCMCTL, SRCCTL, PWRCTL, COLMOD, DISCTRL, INTERFACE,\
|
|
POSRED, NEGRED, POSGREEN, NEGGREEN, POSBLUE, NEGBLUE, TEARLINE,\
|
|
DISPLAY, GATECON, SETX, SETY, MEMWR, DISON, NULL
|
|
};
|
|
|
|
#endif /* __S90319FB_H__ */
|