265 lines
7.1 KiB
C
265 lines
7.1 KiB
C
/*
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* Copyright (c) 2005-2011 Atheros Communications Inc.
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* Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _PCI_H_
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#define _PCI_H_
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#include <linux/interrupt.h>
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#include "hw.h"
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#include "ce.h"
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/*
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* maximum number of bytes that can be handled atomically by DiagRead/DiagWrite
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*/
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#define DIAG_TRANSFER_LIMIT 2048
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/*
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* maximum number of bytes that can be
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* handled atomically by DiagRead/DiagWrite
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*/
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#define DIAG_TRANSFER_LIMIT 2048
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struct bmi_xfer {
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bool tx_done;
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bool rx_done;
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bool wait_for_resp;
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u32 resp_len;
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};
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/*
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* PCI-specific Target state
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*
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* NOTE: Structure is shared between Host software and Target firmware!
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*
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* Much of this may be of interest to the Host so
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* HOST_INTEREST->hi_interconnect_state points here
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* (and all members are 32-bit quantities in order to
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* facilitate Host access). In particular, Host software is
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* required to initialize pipe_cfg_addr and svc_to_pipe_map.
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*/
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struct pcie_state {
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/* Pipe configuration Target address */
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/* NB: ce_pipe_config[CE_COUNT] */
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u32 pipe_cfg_addr;
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/* Service to pipe map Target address */
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/* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
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u32 svc_to_pipe_map;
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/* number of MSI interrupts requested */
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u32 msi_requested;
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/* number of MSI interrupts granted */
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u32 msi_granted;
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/* Message Signalled Interrupt address */
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u32 msi_addr;
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/* Base data */
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u32 msi_data;
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/*
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* Data for firmware interrupt;
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* MSI data for other interrupts are
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* in various SoC registers
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*/
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u32 msi_fw_intr_data;
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/* PCIE_PWR_METHOD_* */
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u32 power_mgmt_method;
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/* PCIE_CONFIG_FLAG_* */
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u32 config_flags;
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};
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/* PCIE_CONFIG_FLAG definitions */
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#define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
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/* Host software's Copy Engine configuration. */
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#define CE_ATTR_FLAGS 0
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/*
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* Configuration information for a Copy Engine pipe.
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* Passed from Host to Target during startup (one per CE).
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*
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* NOTE: Structure is shared between Host software and Target firmware!
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*/
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struct ce_pipe_config {
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__le32 pipenum;
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__le32 pipedir;
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__le32 nentries;
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__le32 nbytes_max;
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__le32 flags;
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__le32 reserved;
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};
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/*
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* Directions for interconnect pipe configuration.
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* These definitions may be used during configuration and are shared
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* between Host and Target.
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*
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* Pipe Directions are relative to the Host, so PIPEDIR_IN means
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* "coming IN over air through Target to Host" as with a WiFi Rx operation.
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* Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
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* as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
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* Target since things that are "PIPEDIR_OUT" are coming IN to the Target
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* over the interconnect.
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*/
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#define PIPEDIR_NONE 0
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#define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
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#define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
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#define PIPEDIR_INOUT 3 /* bidirectional */
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/* Establish a mapping between a service/direction and a pipe. */
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struct service_to_pipe {
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__le32 service_id;
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__le32 pipedir;
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__le32 pipenum;
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};
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/* Per-pipe state. */
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struct ath10k_pci_pipe {
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/* Handle of underlying Copy Engine */
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struct ath10k_ce_pipe *ce_hdl;
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/* Our pipe number; facilitiates use of pipe_info ptrs. */
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u8 pipe_num;
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/* Convenience back pointer to hif_ce_state. */
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struct ath10k *hif_ce_state;
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size_t buf_sz;
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/* protects compl_free and num_send_allowed */
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spinlock_t pipe_lock;
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struct ath10k_pci *ar_pci;
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struct tasklet_struct intr;
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};
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struct ath10k_pci {
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struct pci_dev *pdev;
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struct device *dev;
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struct ath10k *ar;
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void __iomem *mem;
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/*
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* Number of MSI interrupts granted, 0 --> using legacy PCI line
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* interrupts.
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*/
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int num_msi_intrs;
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struct tasklet_struct intr_tq;
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struct tasklet_struct msi_fw_err;
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struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
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struct ath10k_hif_cb msg_callbacks_current;
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/* Copy Engine used for Diagnostic Accesses */
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struct ath10k_ce_pipe *ce_diag;
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/* FIXME: document what this really protects */
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spinlock_t ce_lock;
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/* Map CE id to ce_state */
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struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
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struct timer_list rx_post_retry;
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};
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static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
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{
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return (struct ath10k_pci *)ar->drv_priv;
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}
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#define ATH10K_PCI_RX_POST_RETRY_MS 50
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#define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
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#define PCIE_WAKE_TIMEOUT 5000 /* 5ms */
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#define BAR_NUM 0
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#define CDC_WAR_MAGIC_STR 0xceef0000
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#define CDC_WAR_DATA_CE 4
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/*
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* TODO: Should be a function call specific to each Target-type.
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* This convoluted macro converts from Target CPU Virtual Address Space to CE
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* Address Space. As part of this process, we conservatively fetch the current
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* PCIE_BAR. MOST of the time, this should match the upper bits of PCI space
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* for this device; but that's not guaranteed.
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*/
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#define TARG_CPU_SPACE_TO_CE_SPACE(ar, pci_addr, addr) \
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(((ioread32((pci_addr)+(SOC_CORE_BASE_ADDRESS| \
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CORE_CTRL_ADDRESS)) & 0x7ff) << 21) | \
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0x100000 | ((addr) & 0xfffff))
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/* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
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#define DIAG_ACCESS_CE_TIMEOUT_MS 10
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/* Target exposes its registers for direct access. However before host can
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* access them it needs to make sure the target is awake (ath10k_pci_wake,
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* ath10k_pci_wake_wait, ath10k_pci_is_awake). Once target is awake it won't go
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* to sleep unless host tells it to (ath10k_pci_sleep).
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*
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* If host tries to access target registers without waking it up it can
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* scribble over host memory.
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*
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* If target is asleep waking it up may take up to even 2ms.
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*/
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static inline void ath10k_pci_write32(struct ath10k *ar, u32 offset,
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u32 value)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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iowrite32(value, ar_pci->mem + offset);
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}
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static inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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return ioread32(ar_pci->mem + offset);
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}
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static inline u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
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{
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return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
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}
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static inline void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
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{
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ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
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}
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static inline u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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return ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
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}
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static inline void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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iowrite32(val, ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
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}
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#endif /* _PCI_H_ */
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