151 lines
3.9 KiB
C
151 lines
3.9 KiB
C
/*
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* Synopsys DW APB ICTL irqchip driver.
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*
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* based on GPL'ed 2.6 kernel sources
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* (c) Marvell International Ltd.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include "irqchip.h"
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#define APB_INT_ENABLE_L 0x00
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#define APB_INT_ENABLE_H 0x04
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#define APB_INT_MASK_L 0x08
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#define APB_INT_MASK_H 0x0c
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#define APB_INT_FINALSTATUS_L 0x30
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#define APB_INT_FINALSTATUS_H 0x34
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static void dw_apb_ictl_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_get_chip(irq);
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struct irq_chip_generic *gc = irq_get_handler_data(irq);
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struct irq_domain *d = gc->private;
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u32 stat;
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int n;
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chained_irq_enter(chip, desc);
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for (n = 0; n < gc->num_ct; n++) {
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stat = readl_relaxed(gc->reg_base +
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APB_INT_FINALSTATUS_L + 4 * n);
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while (stat) {
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u32 hwirq = ffs(stat) - 1;
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generic_handle_irq(irq_find_mapping(d,
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gc->irq_base + hwirq + 32 * n));
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stat &= ~(1 << hwirq);
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}
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}
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chained_irq_exit(chip, desc);
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}
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static int __init dw_apb_ictl_init(struct device_node *np,
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struct device_node *parent)
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{
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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struct resource r;
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struct irq_domain *domain;
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struct irq_chip_generic *gc;
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void __iomem *iobase;
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int ret, nrirqs, irq;
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u32 reg;
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/* Map the parent interrupt for the chained handler */
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irq = irq_of_parse_and_map(np, 0);
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if (irq <= 0) {
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pr_err("%s: unable to parse irq\n", np->full_name);
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return -EINVAL;
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}
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ret = of_address_to_resource(np, 0, &r);
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if (ret) {
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pr_err("%s: unable to get resource\n", np->full_name);
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return ret;
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}
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if (!request_mem_region(r.start, resource_size(&r), np->full_name)) {
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pr_err("%s: unable to request mem region\n", np->full_name);
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return -ENOMEM;
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}
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iobase = ioremap(r.start, resource_size(&r));
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if (!iobase) {
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pr_err("%s: unable to map resource\n", np->full_name);
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ret = -ENOMEM;
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goto err_release;
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}
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/*
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* DW IP can be configured to allow 2-64 irqs. We can determine
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* the number of irqs supported by writing into enable register
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* and look for bits not set, as corresponding flip-flops will
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* have been removed by sythesis tool.
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*/
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/* mask and enable all interrupts */
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writel(~0, iobase + APB_INT_MASK_L);
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writel(~0, iobase + APB_INT_MASK_H);
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writel(~0, iobase + APB_INT_ENABLE_L);
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writel(~0, iobase + APB_INT_ENABLE_H);
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reg = readl(iobase + APB_INT_ENABLE_H);
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if (reg)
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nrirqs = 32 + fls(reg);
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else
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nrirqs = fls(readl(iobase + APB_INT_ENABLE_L));
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domain = irq_domain_add_linear(np, nrirqs,
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&irq_generic_chip_ops, NULL);
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if (!domain) {
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pr_err("%s: unable to add irq domain\n", np->full_name);
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ret = -ENOMEM;
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goto err_unmap;
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}
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ret = irq_alloc_domain_generic_chips(domain, 32, (nrirqs > 32) ? 2 : 1,
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np->name, handle_level_irq, clr, 0,
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IRQ_GC_INIT_MASK_CACHE);
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if (ret) {
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pr_err("%s: unable to alloc irq domain gc\n", np->full_name);
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goto err_unmap;
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}
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gc = irq_get_domain_generic_chip(domain, 0);
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gc->private = domain;
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gc->reg_base = iobase;
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gc->chip_types[0].regs.mask = APB_INT_MASK_L;
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
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gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
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if (nrirqs > 32) {
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gc->chip_types[1].regs.mask = APB_INT_MASK_H;
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gc->chip_types[1].chip.irq_mask = irq_gc_mask_set_bit;
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gc->chip_types[1].chip.irq_unmask = irq_gc_mask_clr_bit;
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}
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irq_set_handler_data(irq, gc);
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irq_set_chained_handler(irq, dw_apb_ictl_handler);
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return 0;
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err_unmap:
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iounmap(iobase);
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err_release:
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release_mem_region(r.start, resource_size(&r));
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return ret;
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}
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IRQCHIP_DECLARE(dw_apb_ictl,
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"snps,dw-apb-ictl", dw_apb_ictl_init);
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