311 lines
6.7 KiB
C
311 lines
6.7 KiB
C
/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <linux/export.h>
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#include <linux/iommu.h>
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#include <linux/qcom_iommu.h>
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#include <asm/sections.h>
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static DEFINE_MUTEX(iommu_list_lock);
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static LIST_HEAD(iommu_list);
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#define MRC(reg, processor, op1, crn, crm, op2) \
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__asm__ __volatile__ ( \
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" mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \
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: "=r" (reg))
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#define RCP15_PRRR(reg) MRC(reg, p15, 0, c10, c2, 0)
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#define RCP15_NMRR(reg) MRC(reg, p15, 0, c10, c2, 1)
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#define RCP15_MAIR0(reg) MRC(reg, p15, 0, c10, c2, 0)
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#define RCP15_MAIR1(reg) MRC(reg, p15, 0, c10, c2, 1)
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/* These values come from proc-v7-2level.S */
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#define PRRR_VALUE 0xff0a81a8
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#define NMRR_VALUE 0x40e040e0
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/* These values come from proc-v7-3level.S */
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#define MAIR0_VALUE 0xeeaa4400
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#define MAIR1_VALUE 0xff000004
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static struct iommu_access_ops *iommu_access_ops;
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struct bus_type msm_iommu_sec_bus_type = {
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.name = "msm_iommu_sec_bus",
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};
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struct bus_type iommu_non_sec_bus_type = {
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.name = "msm_iommu_non_sec_bus",
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};
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struct bus_type *msm_iommu_non_sec_bus_type;
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#ifndef CONFIG_ARM_SMMU
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int msm_iommu_bus_register(void)
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{
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msm_iommu_non_sec_bus_type = &platform_bus_type;
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return 0;
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}
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#else
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int msm_iommu_bus_register(void)
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{
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msm_iommu_non_sec_bus_type = &iommu_non_sec_bus_type;
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return bus_register(msm_iommu_non_sec_bus_type);
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}
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#endif
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void msm_access_control(void)
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{
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int ret;
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struct device *cb_dev;
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struct iommu_domain *domain;
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unsigned long start, kernel_start, kernel_end, end;
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start = 0;
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kernel_start = rounddown(__pa(_stext), PAGE_SIZE);
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kernel_end = ALIGN(__pa(_etext), PAGE_SIZE);
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end = 0xFFFFFFFF;
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/*
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* If a target doesn't have the access control feature
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* it won't have CB and that's okay
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*/
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cb_dev = msm_iommu_get_ctx("access_control");
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domain = iommu_domain_alloc(msm_iommu_non_sec_bus_type);
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if (!domain) {
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pr_err("Couldn't get domain for access control\n");
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goto err;
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}
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/*
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* Map the region from start to kernel_start
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*/
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if (start < kernel_start) {
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ret = iommu_map(domain, start, start, kernel_start - start,
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IOMMU_READ | IOMMU_WRITE | IOMMU_DEVICE);
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if (ret) {
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pr_err("Mapping failed for region lower than kernel\n");
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goto free_dom;
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}
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}
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/*
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* Map the region from kernel_end to end of DDR
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*/
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ret = iommu_map(domain, kernel_end, kernel_end, end - kernel_end + 1,
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IOMMU_READ | IOMMU_WRITE);
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if (ret) {
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pr_err("Mapping failed for region above kernel\n");
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goto free_dom;
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}
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ret = iommu_attach_device(domain, cb_dev);
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if (ret) {
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pr_err("Attach of access_control CB failed\n");
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goto free_dom;
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}
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return;
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free_dom:
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iommu_domain_free(domain);
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err:
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BUG();
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}
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/**
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* Pass the context bank device here. Based on the context bank
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* device, the bus is chosen and hence the respective IOMMU ops.
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*/
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struct bus_type *msm_iommu_get_bus(struct device *dev)
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{
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if (!dev)
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return NULL;
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if (of_device_is_compatible(dev->of_node, "qcom,msm-smmu-v2-ctx")) {
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if (of_property_read_bool(dev->of_node, "qcom,secure-context"))
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return &msm_iommu_sec_bus_type;
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else
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return msm_iommu_non_sec_bus_type;
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} else
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return &platform_bus_type;
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}
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EXPORT_SYMBOL(msm_iommu_get_bus);
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void msm_set_iommu_access_ops(struct iommu_access_ops *ops)
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{
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iommu_access_ops = ops;
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}
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struct iommu_access_ops *msm_get_iommu_access_ops()
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{
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BUG_ON(iommu_access_ops == NULL);
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return iommu_access_ops;
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}
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EXPORT_SYMBOL(msm_get_iommu_access_ops);
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void msm_iommu_add_drv(struct msm_iommu_drvdata *drv)
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{
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mutex_lock(&iommu_list_lock);
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list_add(&drv->list, &iommu_list);
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mutex_unlock(&iommu_list_lock);
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}
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void msm_iommu_remove_drv(struct msm_iommu_drvdata *drv)
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{
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mutex_lock(&iommu_list_lock);
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list_del(&drv->list);
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mutex_unlock(&iommu_list_lock);
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}
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static int find_iommu_ctx(struct device *dev, void *data)
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{
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struct msm_iommu_ctx_drvdata *c;
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c = dev_get_drvdata(dev);
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if (!c || !c->name)
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return 0;
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return !strcmp(data, c->name);
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}
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static struct device *find_context(struct device *dev, const char *name)
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{
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return device_find_child(dev, (void *)name, find_iommu_ctx);
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}
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struct device *msm_iommu_get_ctx(const char *ctx_name)
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{
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struct msm_iommu_drvdata *drv;
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struct device *dev = NULL;
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mutex_lock(&iommu_list_lock);
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list_for_each_entry(drv, &iommu_list, list) {
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dev = find_context(drv->dev, ctx_name);
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if (dev)
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break;
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}
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mutex_unlock(&iommu_list_lock);
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put_device(dev);
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if (!dev || !dev_get_drvdata(dev)) {
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pr_debug("Could not find context <%s>\n", ctx_name);
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dev = ERR_PTR(-EPROBE_DEFER);
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}
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return dev;
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}
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EXPORT_SYMBOL(msm_iommu_get_ctx);
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/*
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* Selecting NMRR, PRRR, MAIR0 and MAIR1 for SMMU has a dependency on
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* the SMMU page table formate and a CPU mode. To simplify that, refer
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* the table below.
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*
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* +-----------+-------------+------+
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* | ARM | ARM_LPAE | ARM64|
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* +------------+-----------+-------------+------+
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* | SMMUv7S | RCP15_PRRR| PRRR | PRRR |
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* | | RCP15_NMRR| NMRR | NMRR |
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* +------------+-----------+-------------+------+
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* | SMMUv7L | MAIR0 | RCP15_MAIR0 | MAIR0|
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* | | MAIR1 | RCP15_MAIR1 | MAIR1|
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* +------------+-----------+-------------+------+
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* | SMMUv8L | MAIR0 | RCP15_MAIR0 | MAIR0|
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* | | MAIR1 | RCP15_MAIR1 | MAIR1|
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* +------------+-----------+-------------+------+
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*/
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#ifdef CONFIG_ARM64
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u32 msm_iommu_get_mair0(void)
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{
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return MAIR0_VALUE;
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}
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u32 msm_iommu_get_mair1(void)
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{
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return MAIR1_VALUE;
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}
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u32 msm_iommu_get_prrr(void)
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{
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return PRRR_VALUE;
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}
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u32 msm_iommu_get_nmrr(void)
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{
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return NMRR_VALUE;
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}
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#elif defined(CONFIG_ARM_LPAE)
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u32 msm_iommu_get_mair0(void)
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{
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unsigned int mair0;
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RCP15_MAIR0(mair0);
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return mair0;
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}
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u32 msm_iommu_get_mair1(void)
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{
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unsigned int mair1;
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RCP15_MAIR1(mair1);
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return mair1;
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}
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u32 msm_iommu_get_prrr(void)
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{
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return PRRR_VALUE;
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}
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u32 msm_iommu_get_nmrr(void)
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{
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return NMRR_VALUE;
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}
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#else
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u32 msm_iommu_get_mair0(void)
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{
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return MAIR0_VALUE;
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}
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u32 msm_iommu_get_mair1(void)
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{
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return MAIR1_VALUE;
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}
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u32 msm_iommu_get_prrr(void)
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{
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u32 prrr;
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RCP15_PRRR(prrr);
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return prrr;
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}
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u32 msm_iommu_get_nmrr(void)
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{
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u32 nmrr;
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RCP15_NMRR(nmrr);
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return nmrr;
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}
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#endif
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