248 lines
7.5 KiB
C
248 lines
7.5 KiB
C
/*
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* Copyright (C) 2012 Invensense, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/i2c.h>
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#include <linux/kfifo.h>
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#include <linux/spinlock.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/sysfs.h>
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#include <linux/iio/kfifo_buf.h>
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#include <linux/iio/trigger.h>
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#include <linux/iio/triggered_buffer.h>
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#include <linux/iio/trigger_consumer.h>
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#include <linux/platform_data/invensense_mpu6050.h>
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/**
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* struct inv_mpu6050_reg_map - Notable registers.
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* @sample_rate_div: Divider applied to gyro output rate.
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* @lpf: Configures internal low pass filter.
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* @user_ctrl: Enables/resets the FIFO.
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* @fifo_en: Determines which data will appear in FIFO.
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* @gyro_config: gyro config register.
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* @accl_config: accel config register
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* @fifo_count_h: Upper byte of FIFO count.
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* @fifo_r_w: FIFO register.
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* @raw_gyro: Address of first gyro register.
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* @raw_accl: Address of first accel register.
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* @temperature: temperature register
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* @int_enable: Interrupt enable register.
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* @pwr_mgmt_1: Controls chip's power state and clock source.
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* @pwr_mgmt_2: Controls power state of individual sensors.
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*/
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struct inv_mpu6050_reg_map {
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u8 sample_rate_div;
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u8 lpf;
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u8 user_ctrl;
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u8 fifo_en;
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u8 gyro_config;
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u8 accl_config;
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u8 fifo_count_h;
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u8 fifo_r_w;
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u8 raw_gyro;
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u8 raw_accl;
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u8 temperature;
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u8 int_enable;
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u8 pwr_mgmt_1;
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u8 pwr_mgmt_2;
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};
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/*device enum */
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enum inv_devices {
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INV_MPU6050,
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INV_MPU6500,
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INV_NUM_PARTS
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};
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/**
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* struct inv_mpu6050_chip_config - Cached chip configuration data.
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* @fsr: Full scale range.
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* @lpf: Digital low pass filter frequency.
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* @accl_fs: accel full scale range.
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* @enable: master enable state.
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* @accl_fifo_enable: enable accel data output
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* @gyro_fifo_enable: enable gyro data output
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* @fifo_rate: FIFO update rate.
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*/
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struct inv_mpu6050_chip_config {
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unsigned int fsr:2;
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unsigned int lpf:3;
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unsigned int accl_fs:2;
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unsigned int enable:1;
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unsigned int accl_fifo_enable:1;
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unsigned int gyro_fifo_enable:1;
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u16 fifo_rate;
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};
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/**
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* struct inv_mpu6050_hw - Other important hardware information.
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* @num_reg: Number of registers on device.
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* @name: name of the chip.
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* @reg: register map of the chip.
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* @config: configuration of the chip.
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*/
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struct inv_mpu6050_hw {
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u8 num_reg;
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u8 *name;
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const struct inv_mpu6050_reg_map *reg;
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const struct inv_mpu6050_chip_config *config;
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};
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/*
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* struct inv_mpu6050_state - Driver state variables.
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* @TIMESTAMP_FIFO_SIZE: fifo size for timestamp.
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* @trig: IIO trigger.
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* @chip_config: Cached attribute information.
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* @reg: Map of important registers.
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* @hw: Other hardware-specific information.
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* @chip_type: chip type.
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* @time_stamp_lock: spin lock to time stamp.
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* @client: i2c client handle.
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* @plat_data: platform data.
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* @timestamps: kfifo queue to store time stamp.
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*/
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struct inv_mpu6050_state {
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#define TIMESTAMP_FIFO_SIZE 16
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struct iio_trigger *trig;
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struct inv_mpu6050_chip_config chip_config;
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const struct inv_mpu6050_reg_map *reg;
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const struct inv_mpu6050_hw *hw;
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enum inv_devices chip_type;
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spinlock_t time_stamp_lock;
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struct i2c_client *client;
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struct inv_mpu6050_platform_data plat_data;
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DECLARE_KFIFO(timestamps, long long, TIMESTAMP_FIFO_SIZE);
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};
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/*register and associated bit definition*/
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#define INV_MPU6050_REG_SAMPLE_RATE_DIV 0x19
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#define INV_MPU6050_REG_CONFIG 0x1A
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#define INV_MPU6050_REG_GYRO_CONFIG 0x1B
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#define INV_MPU6050_REG_ACCEL_CONFIG 0x1C
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#define INV_MPU6050_REG_FIFO_EN 0x23
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#define INV_MPU6050_BIT_ACCEL_OUT 0x08
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#define INV_MPU6050_BITS_GYRO_OUT 0x70
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#define INV_MPU6050_REG_INT_ENABLE 0x38
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#define INV_MPU6050_BIT_DATA_RDY_EN 0x01
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#define INV_MPU6050_BIT_DMP_INT_EN 0x02
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#define INV_MPU6050_REG_RAW_ACCEL 0x3B
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#define INV_MPU6050_REG_TEMPERATURE 0x41
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#define INV_MPU6050_REG_RAW_GYRO 0x43
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#define INV_MPU6050_REG_USER_CTRL 0x6A
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#define INV_MPU6050_BIT_FIFO_RST 0x04
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#define INV_MPU6050_BIT_DMP_RST 0x08
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#define INV_MPU6050_BIT_I2C_MST_EN 0x20
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#define INV_MPU6050_BIT_FIFO_EN 0x40
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#define INV_MPU6050_BIT_DMP_EN 0x80
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#define INV_MPU6050_REG_PWR_MGMT_1 0x6B
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#define INV_MPU6050_BIT_H_RESET 0x80
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#define INV_MPU6050_BIT_SLEEP 0x40
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#define INV_MPU6050_BIT_CLK_MASK 0x7
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#define INV_MPU6050_REG_PWR_MGMT_2 0x6C
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#define INV_MPU6050_BIT_PWR_ACCL_STBY 0x38
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#define INV_MPU6050_BIT_PWR_GYRO_STBY 0x07
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#define INV_MPU6050_REG_FIFO_COUNT_H 0x72
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#define INV_MPU6050_REG_FIFO_R_W 0x74
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#define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6
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#define INV_MPU6050_FIFO_COUNT_BYTE 2
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#define INV_MPU6050_FIFO_THRESHOLD 500
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#define INV_MPU6050_POWER_UP_TIME 100
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#define INV_MPU6050_TEMP_UP_TIME 100
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#define INV_MPU6050_SENSOR_UP_TIME 30
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#define INV_MPU6050_REG_UP_TIME 5
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#define INV_MPU6050_TEMP_OFFSET 12421
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#define INV_MPU6050_TEMP_SCALE 2941
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#define INV_MPU6050_MAX_GYRO_FS_PARAM 3
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#define INV_MPU6050_MAX_ACCL_FS_PARAM 3
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#define INV_MPU6050_THREE_AXIS 3
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#define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT 3
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#define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT 3
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/* 6 + 6 round up and plus 8 */
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#define INV_MPU6050_OUTPUT_DATA_SIZE 24
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/* init parameters */
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#define INV_MPU6050_INIT_FIFO_RATE 50
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#define INV_MPU6050_TIME_STAMP_TOR 5
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#define INV_MPU6050_MAX_FIFO_RATE 1000
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#define INV_MPU6050_MIN_FIFO_RATE 4
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#define INV_MPU6050_ONE_K_HZ 1000
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/* scan element definition */
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enum inv_mpu6050_scan {
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INV_MPU6050_SCAN_ACCL_X,
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INV_MPU6050_SCAN_ACCL_Y,
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INV_MPU6050_SCAN_ACCL_Z,
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INV_MPU6050_SCAN_GYRO_X,
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INV_MPU6050_SCAN_GYRO_Y,
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INV_MPU6050_SCAN_GYRO_Z,
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INV_MPU6050_SCAN_TIMESTAMP,
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};
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enum inv_mpu6050_filter_e {
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INV_MPU6050_FILTER_256HZ_NOLPF2 = 0,
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INV_MPU6050_FILTER_188HZ,
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INV_MPU6050_FILTER_98HZ,
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INV_MPU6050_FILTER_42HZ,
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INV_MPU6050_FILTER_20HZ,
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INV_MPU6050_FILTER_10HZ,
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INV_MPU6050_FILTER_5HZ,
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INV_MPU6050_FILTER_2100HZ_NOLPF,
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NUM_MPU6050_FILTER
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};
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/* IIO attribute address */
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enum INV_MPU6050_IIO_ATTR_ADDR {
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ATTR_GYRO_MATRIX,
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ATTR_ACCL_MATRIX,
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};
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enum inv_mpu6050_accl_fs_e {
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INV_MPU6050_FS_02G = 0,
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INV_MPU6050_FS_04G,
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INV_MPU6050_FS_08G,
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INV_MPU6050_FS_16G,
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NUM_ACCL_FSR
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};
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enum inv_mpu6050_fsr_e {
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INV_MPU6050_FSR_250DPS = 0,
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INV_MPU6050_FSR_500DPS,
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INV_MPU6050_FSR_1000DPS,
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INV_MPU6050_FSR_2000DPS,
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NUM_MPU6050_FSR
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};
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enum inv_mpu6050_clock_sel_e {
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INV_CLK_INTERNAL = 0,
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INV_CLK_PLL,
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NUM_CLK
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};
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irqreturn_t inv_mpu6050_irq_handler(int irq, void *p);
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irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
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int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev);
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void inv_mpu6050_remove_trigger(struct inv_mpu6050_state *st);
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int inv_reset_fifo(struct iio_dev *indio_dev);
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int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask);
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int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val);
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int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on);
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