492 lines
12 KiB
C
492 lines
12 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "msm_drv.h"
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#include "msm_mmu.h"
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#include "mdp5_kms.h"
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static const char *iommu_ports[] = {
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"mdp_0",
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};
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static struct mdp5_platform_config *mdp5_get_config(struct platform_device *dev);
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const struct mdp5_config *mdp5_cfg;
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static const struct mdp5_config msm8x74_config = {
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.name = "msm8x74",
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.ctl = {
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.count = 5,
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.base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
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},
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.pipe_vig = {
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.count = 3,
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.base = { 0x01200, 0x01600, 0x01a00 },
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},
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.pipe_rgb = {
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.count = 3,
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.base = { 0x01e00, 0x02200, 0x02600 },
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},
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.pipe_dma = {
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.count = 2,
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.base = { 0x02a00, 0x02e00 },
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},
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.lm = {
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.count = 5,
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.base = { 0x03200, 0x03600, 0x03a00, 0x03e00, 0x04200 },
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},
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.dspp = {
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.count = 3,
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.base = { 0x04600, 0x04a00, 0x04e00 },
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},
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.ad = {
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.count = 2,
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.base = { 0x13100, 0x13300 }, /* NOTE: no ad in v1.0 */
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},
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.intf = {
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.count = 4,
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.base = { 0x12500, 0x12700, 0x12900, 0x12b00 },
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},
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};
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static const struct mdp5_config apq8084_config = {
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.name = "apq8084",
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.ctl = {
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.count = 5,
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.base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },
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},
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.pipe_vig = {
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.count = 4,
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.base = { 0x01200, 0x01600, 0x01a00, 0x01e00 },
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},
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.pipe_rgb = {
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.count = 4,
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.base = { 0x02200, 0x02600, 0x02a00, 0x02e00 },
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},
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.pipe_dma = {
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.count = 2,
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.base = { 0x03200, 0x03600 },
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},
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.lm = {
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.count = 6,
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.base = { 0x03a00, 0x03e00, 0x04200, 0x04600, 0x04a00, 0x04e00 },
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},
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.dspp = {
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.count = 4,
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.base = { 0x05200, 0x05600, 0x05a00, 0x05e00 },
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},
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.ad = {
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.count = 3,
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.base = { 0x13500, 0x13700, 0x13900 },
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},
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.intf = {
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.count = 5,
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.base = { 0x12500, 0x12700, 0x12900, 0x12b00, 0x12d00 },
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},
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};
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struct mdp5_config_entry {
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int revision;
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const struct mdp5_config *config;
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};
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static const struct mdp5_config_entry mdp5_configs[] = {
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{ .revision = 0, .config = &msm8x74_config },
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{ .revision = 2, .config = &msm8x74_config },
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{ .revision = 3, .config = &apq8084_config },
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};
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static int mdp5_select_hw_cfg(struct msm_kms *kms)
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{
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
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struct drm_device *dev = mdp5_kms->dev;
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uint32_t version, major, minor;
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int i, ret = 0;
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mdp5_enable(mdp5_kms);
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version = mdp5_read(mdp5_kms, REG_MDP5_MDP_VERSION);
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mdp5_disable(mdp5_kms);
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major = FIELD(version, MDP5_MDP_VERSION_MAJOR);
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minor = FIELD(version, MDP5_MDP_VERSION_MINOR);
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DBG("found MDP5 version v%d.%d", major, minor);
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if (major != 1) {
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dev_err(dev->dev, "unexpected MDP major version: v%d.%d\n",
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major, minor);
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ret = -ENXIO;
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goto out;
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}
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mdp5_kms->rev = minor;
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/* only after mdp5_cfg global pointer's init can we access the hw */
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for (i = 0; i < ARRAY_SIZE(mdp5_configs); i++) {
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if (mdp5_configs[i].revision != minor)
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continue;
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mdp5_kms->hw_cfg = mdp5_cfg = mdp5_configs[i].config;
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break;
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}
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if (unlikely(!mdp5_kms->hw_cfg)) {
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dev_err(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
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major, minor);
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ret = -ENXIO;
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goto out;
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}
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DBG("MDP5: %s config selected", mdp5_kms->hw_cfg->name);
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return 0;
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out:
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return ret;
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}
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static int mdp5_hw_init(struct msm_kms *kms)
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{
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
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struct drm_device *dev = mdp5_kms->dev;
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int i;
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pm_runtime_get_sync(dev->dev);
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/* Magic unknown register writes:
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*
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* W VBIF:0x004 00000001 (mdss_mdp.c:839)
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* W MDP5:0x2e0 0xe9 (mdss_mdp.c:839)
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* W MDP5:0x2e4 0x55 (mdss_mdp.c:839)
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* W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839)
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* W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839)
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* W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839)
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* W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839)
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* W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839)
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* W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839)
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*
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* Downstream fbdev driver gets these register offsets/values
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* from DT.. not really sure what these registers are or if
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* different values for different boards/SoC's, etc. I guess
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* they are the golden registers.
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*
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* Not setting these does not seem to cause any problem. But
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* we may be getting lucky with the bootloader initializing
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* them for us. OTOH, if we can always count on the bootloader
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* setting the golden registers, then perhaps we don't need to
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* care.
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*/
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mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);
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for (i = 0; i < mdp5_kms->hw_cfg->ctl.count; i++)
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mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(i), 0);
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pm_runtime_put_sync(dev->dev);
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return 0;
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}
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static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
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struct drm_encoder *encoder)
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{
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return rate;
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}
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static void mdp5_preclose(struct msm_kms *kms, struct drm_file *file)
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{
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
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struct msm_drm_private *priv = mdp5_kms->dev->dev_private;
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unsigned i;
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for (i = 0; i < priv->num_crtcs; i++)
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mdp5_crtc_cancel_pending_flip(priv->crtcs[i], file);
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}
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static void mdp5_destroy(struct msm_kms *kms)
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{
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struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
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struct msm_mmu *mmu = mdp5_kms->mmu;
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if (mmu) {
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mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports));
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mmu->funcs->destroy(mmu);
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}
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kfree(mdp5_kms);
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}
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static const struct mdp_kms_funcs kms_funcs = {
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.base = {
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.hw_init = mdp5_hw_init,
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.irq_preinstall = mdp5_irq_preinstall,
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.irq_postinstall = mdp5_irq_postinstall,
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.irq_uninstall = mdp5_irq_uninstall,
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.irq = mdp5_irq,
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.enable_vblank = mdp5_enable_vblank,
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.disable_vblank = mdp5_disable_vblank,
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.get_format = mdp_get_format,
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.round_pixclk = mdp5_round_pixclk,
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.preclose = mdp5_preclose,
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.destroy = mdp5_destroy,
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},
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.set_irqmask = mdp5_set_irqmask,
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};
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int mdp5_disable(struct mdp5_kms *mdp5_kms)
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{
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DBG("");
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clk_disable_unprepare(mdp5_kms->ahb_clk);
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clk_disable_unprepare(mdp5_kms->axi_clk);
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clk_disable_unprepare(mdp5_kms->core_clk);
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clk_disable_unprepare(mdp5_kms->lut_clk);
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return 0;
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}
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int mdp5_enable(struct mdp5_kms *mdp5_kms)
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{
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DBG("");
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clk_prepare_enable(mdp5_kms->ahb_clk);
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clk_prepare_enable(mdp5_kms->axi_clk);
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clk_prepare_enable(mdp5_kms->core_clk);
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clk_prepare_enable(mdp5_kms->lut_clk);
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return 0;
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}
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static int modeset_init(struct mdp5_kms *mdp5_kms)
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{
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static const enum mdp5_pipe crtcs[] = {
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SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
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};
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struct drm_device *dev = mdp5_kms->dev;
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struct msm_drm_private *priv = dev->dev_private;
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struct drm_encoder *encoder;
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int i, ret;
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/* construct CRTCs: */
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for (i = 0; i < mdp5_kms->hw_cfg->pipe_rgb.count; i++) {
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struct drm_plane *plane;
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struct drm_crtc *crtc;
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plane = mdp5_plane_init(dev, crtcs[i], true);
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if (IS_ERR(plane)) {
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ret = PTR_ERR(plane);
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dev_err(dev->dev, "failed to construct plane for %s (%d)\n",
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pipe2name(crtcs[i]), ret);
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goto fail;
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}
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crtc = mdp5_crtc_init(dev, plane, i);
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if (IS_ERR(crtc)) {
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ret = PTR_ERR(crtc);
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dev_err(dev->dev, "failed to construct crtc for %s (%d)\n",
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pipe2name(crtcs[i]), ret);
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goto fail;
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}
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priv->crtcs[priv->num_crtcs++] = crtc;
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}
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/* Construct encoder for HDMI: */
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encoder = mdp5_encoder_init(dev, 3, INTF_HDMI);
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if (IS_ERR(encoder)) {
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dev_err(dev->dev, "failed to construct encoder\n");
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ret = PTR_ERR(encoder);
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goto fail;
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}
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/* NOTE: the vsync and error irq's are actually associated with
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* the INTF/encoder.. the easiest way to deal with this (ie. what
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* we do now) is assume a fixed relationship between crtc's and
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* encoders. I'm not sure if there is ever a need to more freely
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* assign crtcs to encoders, but if there is then we need to take
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* care of error and vblank irq's that the crtc has registered,
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* and also update user-requested vblank_mask.
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*/
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encoder->possible_crtcs = BIT(0);
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mdp5_crtc_set_intf(priv->crtcs[0], 3, INTF_HDMI);
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priv->encoders[priv->num_encoders++] = encoder;
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/* Construct bridge/connector for HDMI: */
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mdp5_kms->hdmi = hdmi_init(dev, encoder);
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if (IS_ERR(mdp5_kms->hdmi)) {
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ret = PTR_ERR(mdp5_kms->hdmi);
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dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret);
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goto fail;
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}
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return 0;
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fail:
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return ret;
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}
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static int get_clk(struct platform_device *pdev, struct clk **clkp,
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const char *name)
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{
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struct device *dev = &pdev->dev;
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struct clk *clk = devm_clk_get(dev, name);
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if (IS_ERR(clk)) {
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dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
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return PTR_ERR(clk);
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}
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*clkp = clk;
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return 0;
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}
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struct msm_kms *mdp5_kms_init(struct drm_device *dev)
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{
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struct platform_device *pdev = dev->platformdev;
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struct mdp5_platform_config *config = mdp5_get_config(pdev);
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struct mdp5_kms *mdp5_kms;
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struct msm_kms *kms = NULL;
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struct msm_mmu *mmu;
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int i, ret;
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mdp5_kms = kzalloc(sizeof(*mdp5_kms), GFP_KERNEL);
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if (!mdp5_kms) {
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dev_err(dev->dev, "failed to allocate kms\n");
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ret = -ENOMEM;
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goto fail;
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}
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mdp_kms_init(&mdp5_kms->base, &kms_funcs);
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kms = &mdp5_kms->base.base;
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mdp5_kms->dev = dev;
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mdp5_kms->smp_blk_cnt = config->smp_blk_cnt;
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mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
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if (IS_ERR(mdp5_kms->mmio)) {
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ret = PTR_ERR(mdp5_kms->mmio);
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goto fail;
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}
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mdp5_kms->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF");
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if (IS_ERR(mdp5_kms->vbif)) {
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ret = PTR_ERR(mdp5_kms->vbif);
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goto fail;
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}
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mdp5_kms->vdd = devm_regulator_get(&pdev->dev, "vdd");
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if (IS_ERR(mdp5_kms->vdd)) {
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ret = PTR_ERR(mdp5_kms->vdd);
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goto fail;
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}
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ret = regulator_enable(mdp5_kms->vdd);
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if (ret) {
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dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
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goto fail;
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}
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ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk");
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if (ret)
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goto fail;
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ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk");
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if (ret)
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goto fail;
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ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src");
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if (ret)
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goto fail;
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ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk");
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if (ret)
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goto fail;
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ret = get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk");
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if (ret)
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goto fail;
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ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk");
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if (ret)
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goto fail;
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ret = clk_set_rate(mdp5_kms->src_clk, config->max_clk);
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ret = mdp5_select_hw_cfg(kms);
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if (ret)
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goto fail;
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/* make sure things are off before attaching iommu (bootloader could
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* have left things on, in which case we'll start getting faults if
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* we don't disable):
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*/
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mdp5_enable(mdp5_kms);
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for (i = 0; i < mdp5_kms->hw_cfg->intf.count; i++)
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mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
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mdp5_disable(mdp5_kms);
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mdelay(16);
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if (config->iommu) {
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mmu = msm_iommu_new(&pdev->dev, config->iommu);
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if (IS_ERR(mmu)) {
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ret = PTR_ERR(mmu);
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dev_err(dev->dev, "failed to init iommu: %d\n", ret);
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goto fail;
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}
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ret = mmu->funcs->attach(mmu, iommu_ports,
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ARRAY_SIZE(iommu_ports));
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if (ret) {
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dev_err(dev->dev, "failed to attach iommu: %d\n", ret);
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mmu->funcs->destroy(mmu);
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goto fail;
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}
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} else {
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dev_info(dev->dev, "no iommu, fallback to phys "
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"contig buffers for scanout\n");
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mmu = NULL;
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}
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mdp5_kms->mmu = mmu;
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mdp5_kms->id = msm_register_mmu(dev, mmu);
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if (mdp5_kms->id < 0) {
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ret = mdp5_kms->id;
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dev_err(dev->dev, "failed to register mdp5 iommu: %d\n", ret);
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goto fail;
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}
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ret = modeset_init(mdp5_kms);
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if (ret) {
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dev_err(dev->dev, "modeset_init failed: %d\n", ret);
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goto fail;
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|
}
|
|
|
|
return kms;
|
|
|
|
fail:
|
|
if (kms)
|
|
mdp5_destroy(kms);
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
static struct mdp5_platform_config *mdp5_get_config(struct platform_device *dev)
|
|
{
|
|
static struct mdp5_platform_config config = {};
|
|
#ifdef CONFIG_OF
|
|
/* TODO */
|
|
#endif
|
|
config.iommu = iommu_domain_alloc(msm_iommu_get_bus(&dev->dev));
|
|
/* TODO hard-coded in downstream mdss, but should it be? */
|
|
config.max_clk = 200000000;
|
|
/* TODO get from DT: */
|
|
config.smp_blk_cnt = 22;
|
|
|
|
return &config;
|
|
}
|