429 lines
13 KiB
Plaintext
429 lines
13 KiB
Plaintext
#
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# EDAC Kconfig
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# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
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# Licensed and distributed under the GPL
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#
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config EDAC_SUPPORT
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bool
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menuconfig EDAC
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bool "EDAC (Error Detection And Correction) reporting"
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depends on HAS_IOMEM
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depends on X86 || PPC || TILE || ARM || EDAC_SUPPORT
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help
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EDAC is designed to report errors in the core system.
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These are low-level errors that are reported in the CPU or
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supporting chipset or other subsystems:
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memory errors, cache errors, PCI errors, thermal throttling, etc..
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If unsure, select 'Y'.
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If this code is reporting problems on your system, please
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see the EDAC project web pages for more information at:
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<http://bluesmoke.sourceforge.net/>
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and:
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<http://buttersideup.com/edacwiki>
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There is also a mailing list for the EDAC project, which can
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be found via the sourceforge page.
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if EDAC
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config EDAC_LEGACY_SYSFS
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bool "EDAC legacy sysfs"
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default y
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help
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Enable the compatibility sysfs nodes.
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Use 'Y' if your edac utilities aren't ported to work with the newer
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structures.
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config EDAC_DEBUG
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bool "Debugging"
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help
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This turns on debugging information for the entire EDAC subsystem.
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You do so by inserting edac_module with "edac_debug_level=x." Valid
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levels are 0-4 (from low to high) and by default it is set to 2.
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Usually you should select 'N' here.
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config EDAC_DECODE_MCE
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tristate "Decode MCEs in human-readable form (only on AMD for now)"
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depends on CPU_SUP_AMD && X86_MCE_AMD
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default y
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---help---
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Enable this option if you want to decode Machine Check Exceptions
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occurring on your machine in human-readable form.
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You should definitely say Y here in case you want to decode MCEs
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which occur really early upon boot, before the module infrastructure
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has been initialized.
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config EDAC_MCE_INJ
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tristate "Simple MCE injection interface over /sysfs"
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depends on EDAC_DECODE_MCE
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default n
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help
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This is a simple interface to inject MCEs over /sysfs and test
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the MCE decoding code in EDAC.
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This is currently AMD-only.
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config EDAC_MM_EDAC
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tristate "Main Memory EDAC (Error Detection And Correction) reporting"
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select RAS
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help
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Some systems are able to detect and correct errors in main
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memory. EDAC can report statistics on memory error
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detection and correction (EDAC - or commonly referred to ECC
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errors). EDAC will also try to decode where these errors
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occurred so that a particular failing memory module can be
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replaced. If unsure, select 'Y'.
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config EDAC_GHES
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bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
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depends on ACPI_APEI_GHES && (EDAC_MM_EDAC=y)
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default y
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help
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Not all machines support hardware-driven error report. Some of those
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provide a BIOS-driven error report mechanism via ACPI, using the
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APEI/GHES driver. By enabling this option, the error reports provided
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by GHES are sent to userspace via the EDAC API.
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When this option is enabled, it will disable the hardware-driven
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mechanisms, if a GHES BIOS is detected, entering into the
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"Firmware First" mode.
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It should be noticed that keeping both GHES and a hardware-driven
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error mechanism won't work well, as BIOS will race with OS, while
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reading the error registers. So, if you want to not use "Firmware
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first" GHES error mechanism, you should disable GHES either at
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compilation time or by passing "ghes.disable=1" Kernel parameter
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at boot time.
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In doubt, say 'Y'.
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config EDAC_AMD64
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tristate "AMD64 (Opteron, Athlon64) K8, F10h"
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depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
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help
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Support for error detection and correction of DRAM ECC errors on
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the AMD64 families of memory controllers (K8 and F10h)
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config EDAC_AMD64_ERROR_INJECTION
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bool "Sysfs HW Error injection facilities"
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depends on EDAC_AMD64
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help
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Recent Opterons (Family 10h and later) provide for Memory Error
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Injection into the ECC detection circuits. The amd64_edac module
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allows the operator/user to inject Uncorrectable and Correctable
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errors into DRAM.
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When enabled, in each of the respective memory controller directories
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(/sys/devices/system/edac/mc/mcX), there are 3 input files:
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- inject_section (0..3, 16-byte section of 64-byte cacheline),
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- inject_word (0..8, 16-bit word of 16-byte section),
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- inject_ecc_vector (hex ecc vector: select bits of inject word)
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In addition, there are two control files, inject_read and inject_write,
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which trigger the DRAM ECC Read and Write respectively.
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config EDAC_AMD76X
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tristate "AMD 76x (760, 762, 768)"
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depends on EDAC_MM_EDAC && PCI && X86_32
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help
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Support for error detection and correction on the AMD 76x
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series of chipsets used with the Athlon processor.
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config EDAC_E7XXX
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tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
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depends on EDAC_MM_EDAC && PCI && X86_32
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help
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Support for error detection and correction on the Intel
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E7205, E7500, E7501 and E7505 server chipsets.
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config EDAC_E752X
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tristate "Intel e752x (e7520, e7525, e7320) and 3100"
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depends on EDAC_MM_EDAC && PCI && X86
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help
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Support for error detection and correction on the Intel
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E7520, E7525, E7320 server chipsets.
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config EDAC_I82443BXGX
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tristate "Intel 82443BX/GX (440BX/GX)"
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depends on EDAC_MM_EDAC && PCI && X86_32
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depends on BROKEN
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help
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Support for error detection and correction on the Intel
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82443BX/GX memory controllers (440BX/GX chipsets).
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config EDAC_I82875P
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tristate "Intel 82875p (D82875P, E7210)"
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depends on EDAC_MM_EDAC && PCI && X86_32
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help
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Support for error detection and correction on the Intel
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DP82785P and E7210 server chipsets.
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config EDAC_I82975X
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tristate "Intel 82975x (D82975x)"
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depends on EDAC_MM_EDAC && PCI && X86
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help
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Support for error detection and correction on the Intel
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DP82975x server chipsets.
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config EDAC_I3000
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tristate "Intel 3000/3010"
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depends on EDAC_MM_EDAC && PCI && X86
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help
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Support for error detection and correction on the Intel
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3000 and 3010 server chipsets.
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config EDAC_I3200
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tristate "Intel 3200"
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depends on EDAC_MM_EDAC && PCI && X86
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help
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Support for error detection and correction on the Intel
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3200 and 3210 server chipsets.
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config EDAC_IE31200
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tristate "Intel e312xx"
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depends on EDAC_MM_EDAC && PCI && X86
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help
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Support for error detection and correction on the Intel
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E3-1200 based DRAM controllers.
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config EDAC_X38
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tristate "Intel X38"
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depends on EDAC_MM_EDAC && PCI && X86
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help
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Support for error detection and correction on the Intel
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X38 server chipsets.
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config EDAC_I5400
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tristate "Intel 5400 (Seaburg) chipsets"
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depends on EDAC_MM_EDAC && PCI && X86
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help
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Support for error detection and correction the Intel
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i5400 MCH chipset (Seaburg).
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config EDAC_I7CORE
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tristate "Intel i7 Core (Nehalem) processors"
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depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
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help
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Support for error detection and correction the Intel
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i7 Core (Nehalem) Integrated Memory Controller that exists on
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newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
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and Xeon 55xx processors.
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config EDAC_I82860
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tristate "Intel 82860"
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depends on EDAC_MM_EDAC && PCI && X86_32
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help
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Support for error detection and correction on the Intel
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82860 chipset.
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config EDAC_R82600
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tristate "Radisys 82600 embedded chipset"
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depends on EDAC_MM_EDAC && PCI && X86_32
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help
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Support for error detection and correction on the Radisys
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82600 embedded chipset.
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config EDAC_I5000
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tristate "Intel Greencreek/Blackford chipset"
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depends on EDAC_MM_EDAC && X86 && PCI
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help
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Support for error detection and correction the Intel
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Greekcreek/Blackford chipsets.
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config EDAC_I5100
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tristate "Intel San Clemente MCH"
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depends on EDAC_MM_EDAC && X86 && PCI
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help
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Support for error detection and correction the Intel
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San Clemente MCH.
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config EDAC_I7300
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tristate "Intel Clarksboro MCH"
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depends on EDAC_MM_EDAC && X86 && PCI
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help
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Support for error detection and correction the Intel
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Clarksboro MCH (Intel 7300 chipset).
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config EDAC_SBRIDGE
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tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
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depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
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depends on PCI_MMCONFIG
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help
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Support for error detection and correction the Intel
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Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
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config EDAC_MPC85XX
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tristate "Freescale MPC83xx / MPC85xx"
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depends on EDAC_MM_EDAC && FSL_SOC && (PPC_83xx || PPC_85xx)
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help
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Support for error detection and correction on the Freescale
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MPC8349, MPC8560, MPC8540, MPC8548
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config EDAC_MV64X60
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tristate "Marvell MV64x60"
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depends on EDAC_MM_EDAC && MV64X60
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help
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Support for error detection and correction on the Marvell
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MV64360 and MV64460 chipsets.
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config EDAC_PASEMI
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tristate "PA Semi PWRficient"
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depends on EDAC_MM_EDAC && PCI
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depends on PPC_PASEMI
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help
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Support for error detection and correction on PA Semi
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PWRficient.
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config EDAC_CELL
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tristate "Cell Broadband Engine memory controller"
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depends on EDAC_MM_EDAC && PPC_CELL_COMMON
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help
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Support for error detection and correction on the
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Cell Broadband Engine internal memory controller
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on platform without a hypervisor
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config EDAC_PPC4XX
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tristate "PPC4xx IBM DDR2 Memory Controller"
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depends on EDAC_MM_EDAC && 4xx
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help
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This enables support for EDAC on the ECC memory used
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with the IBM DDR2 memory controller found in various
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PowerPC 4xx embedded processors such as the 405EX[r],
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440SP, 440SPe, 460EX, 460GT and 460SX.
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config EDAC_AMD8131
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tristate "AMD8131 HyperTransport PCI-X Tunnel"
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depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
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help
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Support for error detection and correction on the
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AMD8131 HyperTransport PCI-X Tunnel chip.
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Note, add more Kconfig dependency if it's adopted
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on some machine other than Maple.
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config EDAC_AMD8111
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tristate "AMD8111 HyperTransport I/O Hub"
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depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
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help
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Support for error detection and correction on the
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AMD8111 HyperTransport I/O Hub chip.
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Note, add more Kconfig dependency if it's adopted
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on some machine other than Maple.
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config EDAC_CPC925
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tristate "IBM CPC925 Memory Controller (PPC970FX)"
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depends on EDAC_MM_EDAC && PPC64
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help
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Support for error detection and correction on the
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IBM CPC925 Bridge and Memory Controller, which is
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a companion chip to the PowerPC 970 family of
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processors.
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config EDAC_TILE
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tristate "Tilera Memory Controller"
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depends on EDAC_MM_EDAC && TILE
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default y
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help
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Support for error detection and correction on the
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Tilera memory controller.
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config EDAC_HIGHBANK_MC
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tristate "Highbank Memory Controller"
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depends on EDAC_MM_EDAC && ARCH_HIGHBANK
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help
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Support for error detection and correction on the
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Calxeda Highbank memory controller.
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config EDAC_HIGHBANK_L2
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tristate "Highbank L2 Cache"
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depends on EDAC_MM_EDAC && ARCH_HIGHBANK
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help
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Support for error detection and correction on the
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Calxeda Highbank memory controller.
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config EDAC_OCTEON_PC
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tristate "Cavium Octeon Primary Caches"
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depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
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help
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Support for error detection and correction on the primary caches of
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the cnMIPS cores of Cavium Octeon family SOCs.
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config EDAC_OCTEON_L2C
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tristate "Cavium Octeon Secondary Caches (L2C)"
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depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
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help
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Support for error detection and correction on the
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Cavium Octeon family of SOCs.
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config EDAC_OCTEON_LMC
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tristate "Cavium Octeon DRAM Memory Controller (LMC)"
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depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
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help
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Support for error detection and correction on the
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Cavium Octeon family of SOCs.
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config EDAC_OCTEON_PCI
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tristate "Cavium Octeon PCI Controller"
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depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC
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help
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Support for error detection and correction on the
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Cavium Octeon family of SOCs.
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config EDAC_ALTERA_MC
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tristate "Altera SDRAM Memory Controller EDAC"
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depends on EDAC_MM_EDAC && ARCH_SOCFPGA
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help
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Support for error detection and correction on the
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Altera SDRAM memory controller. Note that the
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preloader must initialize the SDRAM before loading
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the kernel.
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config EDAC_CORTEX_ARM64
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depends on EDAC_MM_EDAC && ARM64
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bool "ARM Cortex A53/A57 L1/L2 Caches"
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help
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Support for error detection and correction on the
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ARM Cortex A53 and A57 CPUs. For debugging issues having to do with
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stability and overall system health, you should probably say 'Y'
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here.
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config EDAC_CORTEX_ARM64_PANIC_ON_CE
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depends on EDAC_CORTEX_ARM64
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bool "Panic on correctable errors"
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help
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Forcibly cause a kernel panic if an correctable error (CE) is
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detected, even though the error is (by definition) correctable and
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would otherwise result in no adverse system effects. This can reduce
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debugging times on hardware which may be operating at voltages or
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frequencies outside normal specification.
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For production builds, you should definitely say 'N' here.
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config EDAC_CORTEX_ARM64_DBE_IRQ_ONLY
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depends on EDAC_CORTEX_ARM64
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bool "Only check for parity errors when an irq is generated"
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help
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In ARM64, parity errors will cause an interrupt
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to be triggered but may also cause a data abort to
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occur. Only check for EDAC errors for the interrupt.
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If unsure, say no.
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config EDAC_CORTEX_ARM64_PANIC_ON_UE
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depends on EDAC_CORTEX_ARM64
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bool "Panic on uncorrectable errors"
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help
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Forcibly cause a kernel panic if an uncorrectable error (UE) is
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detected. This can reduce debugging times on hardware which may be
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operating at voltages or frequencies outside normal specification.
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For production builds, you should probably say 'N' here.
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endif # EDAC
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