250 lines
6.8 KiB
C
250 lines
6.8 KiB
C
/*
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* OMAP gate clock support
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* Tero Kristo <t-kristo@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/clk/ti.h>
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#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
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#undef pr_fmt
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#define pr_fmt(fmt) "%s: " fmt, __func__
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static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
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static const struct clk_ops omap_gate_clkdm_clk_ops = {
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.init = &omap2_init_clk_clkdm,
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.enable = &omap2_clkops_enable_clkdm,
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.disable = &omap2_clkops_disable_clkdm,
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};
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static const struct clk_ops omap_gate_clk_ops = {
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.init = &omap2_init_clk_clkdm,
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.enable = &omap2_dflt_clk_enable,
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.disable = &omap2_dflt_clk_disable,
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.is_enabled = &omap2_dflt_clk_is_enabled,
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};
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static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
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.init = &omap2_init_clk_clkdm,
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.enable = &omap36xx_gate_clk_enable_with_hsdiv_restore,
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.disable = &omap2_dflt_clk_disable,
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.is_enabled = &omap2_dflt_clk_is_enabled,
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};
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/**
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* omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
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* from HSDivider PWRDN problem Implements Errata ID: i556.
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* @clk: DPLL output struct clk
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*
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* 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
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* dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
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* valueafter their respective PWRDN bits are set. Any dummy write
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* (Any other value different from the Read value) to the
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* corresponding CM_CLKSEL register will refresh the dividers.
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*/
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static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
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{
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struct clk_divider *parent;
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struct clk_hw *parent_hw;
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u32 dummy_v, orig_v;
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int ret;
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/* Clear PWRDN bit of HSDIVIDER */
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ret = omap2_dflt_clk_enable(clk);
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/* Parent is the x2 node, get parent of parent for the m2 div */
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parent_hw = __clk_get_hw(__clk_get_parent(__clk_get_parent(clk->clk)));
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parent = to_clk_divider(parent_hw);
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/* Restore the dividers */
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if (!ret) {
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orig_v = ti_clk_ll_ops->clk_readl(parent->reg);
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dummy_v = orig_v;
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/* Write any other value different from the Read value */
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dummy_v ^= (1 << parent->shift);
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ti_clk_ll_ops->clk_writel(dummy_v, parent->reg);
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/* Write the original divider */
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ti_clk_ll_ops->clk_writel(orig_v, parent->reg);
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}
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return ret;
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}
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static void __init _of_ti_gate_clk_setup(struct device_node *node,
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const struct clk_ops *ops,
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const struct clk_hw_omap_ops *hw_ops)
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{
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struct clk *clk;
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struct clk_init_data init = { NULL };
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struct clk_hw_omap *clk_hw;
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const char *clk_name = node->name;
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const char *parent_name;
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u32 val;
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clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
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if (!clk_hw)
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return;
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clk_hw->hw.init = &init;
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init.name = clk_name;
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init.ops = ops;
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if (ops != &omap_gate_clkdm_clk_ops) {
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clk_hw->enable_reg = ti_clk_get_reg_addr(node, 0);
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if (!clk_hw->enable_reg)
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goto cleanup;
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if (!of_property_read_u32(node, "ti,bit-shift", &val))
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clk_hw->enable_bit = val;
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}
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clk_hw->ops = hw_ops;
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clk_hw->flags = MEMMAP_ADDRESSING;
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if (of_clk_get_parent_count(node) != 1) {
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pr_err("%s must have 1 parent\n", clk_name);
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goto cleanup;
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}
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parent_name = of_clk_get_parent_name(node, 0);
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init.parent_names = &parent_name;
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init.num_parents = 1;
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if (of_property_read_bool(node, "ti,set-rate-parent"))
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init.flags |= CLK_SET_RATE_PARENT;
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if (of_property_read_bool(node, "ti,set-bit-to-disable"))
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clk_hw->flags |= INVERT_ENABLE;
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clk = clk_register(NULL, &clk_hw->hw);
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if (!IS_ERR(clk)) {
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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return;
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}
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cleanup:
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kfree(clk_hw);
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}
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static void __init
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_of_ti_composite_gate_clk_setup(struct device_node *node,
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const struct clk_hw_omap_ops *hw_ops)
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{
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struct clk_hw_omap *gate;
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u32 val = 0;
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return;
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gate->enable_reg = ti_clk_get_reg_addr(node, 0);
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if (!gate->enable_reg)
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goto cleanup;
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of_property_read_u32(node, "ti,bit-shift", &val);
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gate->enable_bit = val;
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gate->ops = hw_ops;
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gate->flags = MEMMAP_ADDRESSING;
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if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE))
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return;
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cleanup:
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kfree(gate);
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}
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static void __init
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of_ti_composite_no_wait_gate_clk_setup(struct device_node *node)
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{
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_of_ti_composite_gate_clk_setup(node, NULL);
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}
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CLK_OF_DECLARE(ti_composite_no_wait_gate_clk, "ti,composite-no-wait-gate-clock",
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of_ti_composite_no_wait_gate_clk_setup);
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#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
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static void __init of_ti_composite_interface_clk_setup(struct device_node *node)
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{
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_of_ti_composite_gate_clk_setup(node, &clkhwops_iclk_wait);
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}
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CLK_OF_DECLARE(ti_composite_interface_clk, "ti,composite-interface-clock",
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of_ti_composite_interface_clk_setup);
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#endif
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static void __init of_ti_composite_gate_clk_setup(struct device_node *node)
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{
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_of_ti_composite_gate_clk_setup(node, &clkhwops_wait);
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}
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CLK_OF_DECLARE(ti_composite_gate_clk, "ti,composite-gate-clock",
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of_ti_composite_gate_clk_setup);
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static void __init of_ti_clkdm_gate_clk_setup(struct device_node *node)
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{
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_of_ti_gate_clk_setup(node, &omap_gate_clkdm_clk_ops, NULL);
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}
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CLK_OF_DECLARE(ti_clkdm_gate_clk, "ti,clkdm-gate-clock",
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of_ti_clkdm_gate_clk_setup);
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static void __init of_ti_hsdiv_gate_clk_setup(struct device_node *node)
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{
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_of_ti_gate_clk_setup(node, &omap_gate_clk_hsdiv_restore_ops,
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&clkhwops_wait);
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}
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CLK_OF_DECLARE(ti_hsdiv_gate_clk, "ti,hsdiv-gate-clock",
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of_ti_hsdiv_gate_clk_setup);
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static void __init of_ti_gate_clk_setup(struct device_node *node)
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{
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_of_ti_gate_clk_setup(node, &omap_gate_clk_ops, NULL);
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}
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CLK_OF_DECLARE(ti_gate_clk, "ti,gate-clock", of_ti_gate_clk_setup);
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static void __init of_ti_wait_gate_clk_setup(struct device_node *node)
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{
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_of_ti_gate_clk_setup(node, &omap_gate_clk_ops, &clkhwops_wait);
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}
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CLK_OF_DECLARE(ti_wait_gate_clk, "ti,wait-gate-clock",
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of_ti_wait_gate_clk_setup);
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#ifdef CONFIG_ARCH_OMAP3
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static void __init of_ti_am35xx_gate_clk_setup(struct device_node *node)
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{
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_of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
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&clkhwops_am35xx_ipss_module_wait);
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}
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CLK_OF_DECLARE(ti_am35xx_gate_clk, "ti,am35xx-gate-clock",
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of_ti_am35xx_gate_clk_setup);
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static void __init of_ti_dss_gate_clk_setup(struct device_node *node)
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{
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_of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
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&clkhwops_omap3430es2_dss_usbhost_wait);
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}
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CLK_OF_DECLARE(ti_dss_gate_clk, "ti,dss-gate-clock",
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of_ti_dss_gate_clk_setup);
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#endif
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