414 lines
9.1 KiB
C
414 lines
9.1 KiB
C
/*
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* This is the configuration for SSV Dil/NetPC DNP/5370 board.
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*
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* DIL module: http://www.dilnetpc.com/dnp0086.htm
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* SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm
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*
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* Copyright 2010 3ality Digital Systems
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* Copyright 2005 National ICT Australia (NICTA)
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* Copyright 2004-2006 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/device.h>
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/plat-ram.h>
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#include <linux/mtd/physmap.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/i2c.h>
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#include <linux/spi/mmc_spi.h>
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#include <linux/phy.h>
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#include <asm/dma.h>
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#include <asm/bfin5xx_spi.h>
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#include <asm/reboot.h>
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#include <asm/portmux.h>
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#include <asm/dpmc.h>
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/*
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* Name the Board for the /proc/cpuinfo
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*/
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const char bfin_board_name[] = "DNP/5370";
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#define FLASH_MAC 0x202f0000
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#define CONFIG_MTD_PHYSMAP_LEN 0x300000
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#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
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static struct platform_device rtc_device = {
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.name = "rtc-bfin",
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.id = -1,
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};
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#endif
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#if IS_ENABLED(CONFIG_BFIN_MAC)
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#include <linux/bfin_mac.h>
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static const unsigned short bfin_mac_peripherals[] = P_RMII0;
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static struct bfin_phydev_platform_data bfin_phydev_data[] = {
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{
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.addr = 1,
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.irq = PHY_POLL, /* IRQ_MAC_PHYINT */
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},
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};
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static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
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.phydev_number = 1,
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.phydev_data = bfin_phydev_data,
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.phy_mode = PHY_INTERFACE_MODE_RMII,
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.mac_peripherals = bfin_mac_peripherals,
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};
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static struct platform_device bfin_mii_bus = {
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.name = "bfin_mii_bus",
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.dev = {
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.platform_data = &bfin_mii_bus_data,
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}
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};
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static struct platform_device bfin_mac_device = {
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.name = "bfin_mac",
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.dev = {
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.platform_data = &bfin_mii_bus,
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}
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};
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#endif
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#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
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static struct mtd_partition asmb_flash_partitions[] = {
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{
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.name = "bootloader(nor)",
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.size = 0x30000,
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.offset = 0,
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}, {
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.name = "linux kernel and rootfs(nor)",
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.size = 0x300000 - 0x30000 - 0x10000,
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.offset = MTDPART_OFS_APPEND,
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}, {
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.name = "MAC address(nor)",
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.size = 0x10000,
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.offset = MTDPART_OFS_APPEND,
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.mask_flags = MTD_WRITEABLE,
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}
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};
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static struct physmap_flash_data asmb_flash_data = {
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.width = 1,
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.parts = asmb_flash_partitions,
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.nr_parts = ARRAY_SIZE(asmb_flash_partitions),
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};
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static struct resource asmb_flash_resource = {
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.start = 0x20000000,
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.end = 0x202fffff,
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.flags = IORESOURCE_MEM,
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};
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/* 4 MB NOR flash attached to async memory banks 0-2,
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* therefore only 3 MB visible.
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*/
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static struct platform_device asmb_flash_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &asmb_flash_data,
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},
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.num_resources = 1,
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.resource = &asmb_flash_resource,
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};
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#endif
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#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
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#if IS_ENABLED(CONFIG_MMC_SPI)
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static struct bfin5xx_spi_chip mmc_spi_chip_info = {
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.enable_dma = 0, /* use no dma transfer with this chip*/
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};
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#endif
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#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
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/* This mapping is for at45db642 it has 1056 page size,
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* partition size and offset should be page aligned
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*/
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static struct mtd_partition bfin_spi_dataflash_partitions[] = {
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{
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.name = "JFFS2 dataflash(nor)",
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#ifdef CONFIG_MTD_PAGESIZE_1024
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.offset = 0x40000,
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.size = 0x7C0000,
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#else
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.offset = 0x0,
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.size = 0x840000,
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#endif
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}
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};
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static struct flash_platform_data bfin_spi_dataflash_data = {
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.name = "mtd_dataflash",
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.parts = bfin_spi_dataflash_partitions,
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.nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
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.type = "mtd_dataflash",
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};
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static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
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.enable_dma = 0, /* use no dma transfer with this chip*/
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};
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#endif
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static struct spi_board_info bfin_spi_board_info[] __initdata = {
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/* SD/MMC card reader at SPI bus */
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#if IS_ENABLED(CONFIG_MMC_SPI)
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{
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.modalias = "mmc_spi",
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.max_speed_hz = 20000000,
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.bus_num = 0,
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.chip_select = 1,
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.controller_data = &mmc_spi_chip_info,
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.mode = SPI_MODE_3,
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},
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#endif
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/* 8 Megabyte Atmel NOR flash chip at SPI bus */
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#if IS_ENABLED(CONFIG_MTD_DATAFLASH)
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{
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.modalias = "mtd_dataflash",
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.max_speed_hz = 16700000,
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.bus_num = 0,
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.chip_select = 2,
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.platform_data = &bfin_spi_dataflash_data,
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.controller_data = &spi_dataflash_chip_info,
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.mode = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */
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},
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#endif
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};
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/* SPI controller data */
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/* SPI (0) */
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static struct resource bfin_spi0_resource[] = {
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[0] = {
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.start = SPI0_REGBASE,
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.end = SPI0_REGBASE + 0xFF,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = CH_SPI,
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.end = CH_SPI,
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.flags = IORESOURCE_DMA,
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},
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[2] = {
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.start = IRQ_SPI,
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.end = IRQ_SPI,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct bfin5xx_spi_master spi_bfin_master_info = {
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.num_chipselect = 8,
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.enable_dma = 1, /* master has the ability to do dma transfer */
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.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
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};
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static struct platform_device spi_bfin_master_device = {
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.name = "bfin-spi",
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.id = 0, /* Bus number */
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.num_resources = ARRAY_SIZE(bfin_spi0_resource),
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.resource = bfin_spi0_resource,
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.dev = {
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.platform_data = &spi_bfin_master_info, /* Passed to driver */
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},
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};
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#endif
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#if IS_ENABLED(CONFIG_SERIAL_BFIN)
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#ifdef CONFIG_SERIAL_BFIN_UART0
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static struct resource bfin_uart0_resources[] = {
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{
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.start = UART0_THR,
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.end = UART0_GCTL+2,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = IRQ_UART0_TX,
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.end = IRQ_UART0_TX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = IRQ_UART0_RX,
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.end = IRQ_UART0_RX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = IRQ_UART0_ERROR,
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.end = IRQ_UART0_ERROR,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = CH_UART0_TX,
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.end = CH_UART0_TX,
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.flags = IORESOURCE_DMA,
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},
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{
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.start = CH_UART0_RX,
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.end = CH_UART0_RX,
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.flags = IORESOURCE_DMA,
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},
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};
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static unsigned short bfin_uart0_peripherals[] = {
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P_UART0_TX, P_UART0_RX, 0
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};
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static struct platform_device bfin_uart0_device = {
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.name = "bfin-uart",
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.id = 0,
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.num_resources = ARRAY_SIZE(bfin_uart0_resources),
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.resource = bfin_uart0_resources,
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.dev = {
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.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
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},
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};
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#endif
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#ifdef CONFIG_SERIAL_BFIN_UART1
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static struct resource bfin_uart1_resources[] = {
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{
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.start = UART1_THR,
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.end = UART1_GCTL+2,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = IRQ_UART1_TX,
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.end = IRQ_UART1_TX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = IRQ_UART1_RX,
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.end = IRQ_UART1_RX,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = IRQ_UART1_ERROR,
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.end = IRQ_UART1_ERROR,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = CH_UART1_TX,
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.end = CH_UART1_TX,
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.flags = IORESOURCE_DMA,
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},
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{
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.start = CH_UART1_RX,
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.end = CH_UART1_RX,
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.flags = IORESOURCE_DMA,
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},
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};
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static unsigned short bfin_uart1_peripherals[] = {
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P_UART1_TX, P_UART1_RX, 0
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};
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static struct platform_device bfin_uart1_device = {
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.name = "bfin-uart",
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.id = 1,
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.num_resources = ARRAY_SIZE(bfin_uart1_resources),
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.resource = bfin_uart1_resources,
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.dev = {
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.platform_data = &bfin_uart1_peripherals, /* Passed to driver */
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},
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};
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#endif
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#endif
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#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
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static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
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static struct resource bfin_twi0_resource[] = {
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[0] = {
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.start = TWI0_REGBASE,
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.end = TWI0_REGBASE + 0xff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_TWI,
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.end = IRQ_TWI,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device i2c_bfin_twi_device = {
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.name = "i2c-bfin-twi",
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.id = 0,
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.num_resources = ARRAY_SIZE(bfin_twi0_resource),
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.resource = bfin_twi0_resource,
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.dev = {
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.platform_data = &bfin_twi0_pins,
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},
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};
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#endif
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static struct platform_device *dnp5370_devices[] __initdata = {
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#if IS_ENABLED(CONFIG_SERIAL_BFIN)
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#ifdef CONFIG_SERIAL_BFIN_UART0
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&bfin_uart0_device,
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#endif
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#ifdef CONFIG_SERIAL_BFIN_UART1
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&bfin_uart1_device,
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#endif
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#endif
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#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
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&asmb_flash_device,
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#endif
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#if IS_ENABLED(CONFIG_BFIN_MAC)
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&bfin_mii_bus,
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&bfin_mac_device,
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#endif
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#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
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&spi_bfin_master_device,
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#endif
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#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
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&i2c_bfin_twi_device,
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#endif
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#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
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&rtc_device,
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#endif
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};
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static int __init dnp5370_init(void)
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{
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printk(KERN_INFO "DNP/5370: registering device resources\n");
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platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices));
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printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n",
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ARRAY_SIZE(bfin_spi_board_info));
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spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
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printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC);
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return 0;
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}
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arch_initcall(dnp5370_init);
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/*
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* Currently the MAC address is saved in Flash by U-Boot
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*/
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int bfin_get_ether_addr(char *addr)
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{
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*(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
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*(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
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return 0;
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}
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EXPORT_SYMBOL(bfin_get_ether_addr);
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