256 lines
6.2 KiB
C
256 lines
6.2 KiB
C
/*
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* Cavium Networks CNS3420 Validation Board
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*
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* Copyright 2000 Deep Blue Solutions Ltd
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* Copyright 2008 ARM Limited
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* Copyright 2008 Cavium Networks
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* Scott Shu
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* Copyright 2010 MontaVista Software, LLC.
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* Anton Vorontsov <avorontsov@mvista.com>
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/compiler.h>
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#include <linux/serial_core.h>
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#include <linux/serial_8250.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mtd/partitions.h>
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#include <linux/usb/ehci_pdriver.h>
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#include <linux/usb/ohci_pdriver.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include "cns3xxx.h"
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#include "pm.h"
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#include "core.h"
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#include "devices.h"
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/*
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* NOR Flash
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*/
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static struct mtd_partition cns3420_nor_partitions[] = {
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{
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.name = "uboot",
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.size = 0x00040000,
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.offset = 0,
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.mask_flags = MTD_WRITEABLE,
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}, {
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.name = "kernel",
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.size = 0x004C0000,
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.offset = MTDPART_OFS_APPEND,
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}, {
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.name = "filesystem",
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.size = 0x7000000,
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.offset = MTDPART_OFS_APPEND,
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}, {
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.name = "filesystem2",
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.size = 0x0AE0000,
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.offset = MTDPART_OFS_APPEND,
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}, {
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.name = "ubootenv",
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.size = MTDPART_SIZ_FULL,
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.offset = MTDPART_OFS_APPEND,
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},
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};
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static struct physmap_flash_data cns3420_nor_pdata = {
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.width = 2,
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.parts = cns3420_nor_partitions,
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.nr_parts = ARRAY_SIZE(cns3420_nor_partitions),
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};
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static struct resource cns3420_nor_res = {
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.start = CNS3XXX_FLASH_BASE,
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.end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
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};
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static struct platform_device cns3420_nor_pdev = {
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.name = "physmap-flash",
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.id = 0,
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.resource = &cns3420_nor_res,
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.num_resources = 1,
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.dev = {
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.platform_data = &cns3420_nor_pdata,
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},
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};
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/*
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* UART
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*/
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static void __init cns3420_early_serial_setup(void)
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{
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#ifdef CONFIG_SERIAL_8250_CONSOLE
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static struct uart_port cns3420_serial_port = {
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.membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
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.mapbase = CNS3XXX_UART0_BASE,
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.irq = IRQ_CNS3XXX_UART0,
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.iotype = UPIO_MEM,
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.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
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.regshift = 2,
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.uartclk = 24000000,
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.line = 0,
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.type = PORT_16550A,
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.fifosize = 16,
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};
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early_serial_setup(&cns3420_serial_port);
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#endif
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}
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/*
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* USB
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*/
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static struct resource cns3xxx_usb_ehci_resources[] = {
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[0] = {
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.start = CNS3XXX_USB_BASE,
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.end = CNS3XXX_USB_BASE + SZ_16M - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_CNS3XXX_USB_EHCI,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
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static int csn3xxx_usb_power_on(struct platform_device *pdev)
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{
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/*
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* EHCI and OHCI share the same clock and power,
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* resetting twice would cause the 1st controller been reset.
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* Therefore only do power up at the first up device, and
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* power down at the last down device.
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*
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* Set USB AHB INCR length to 16
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*/
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if (atomic_inc_return(&usb_pwr_ref) == 1) {
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cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
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cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
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cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST);
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__raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)),
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MISC_CHIP_CONFIG_REG);
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}
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return 0;
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}
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static void csn3xxx_usb_power_off(struct platform_device *pdev)
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{
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/*
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* EHCI and OHCI share the same clock and power,
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* resetting twice would cause the 1st controller been reset.
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* Therefore only do power up at the first up device, and
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* power down at the last down device.
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*/
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if (atomic_dec_return(&usb_pwr_ref) == 0)
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cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST);
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}
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static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = {
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.power_on = csn3xxx_usb_power_on,
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.power_off = csn3xxx_usb_power_off,
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};
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static struct platform_device cns3xxx_usb_ehci_device = {
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.name = "ehci-platform",
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.num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
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.resource = cns3xxx_usb_ehci_resources,
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.dev = {
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.dma_mask = &cns3xxx_usb_ehci_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = &cns3xxx_usb_ehci_pdata,
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},
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};
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static struct resource cns3xxx_usb_ohci_resources[] = {
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[0] = {
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.start = CNS3XXX_USB_OHCI_BASE,
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.end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_CNS3XXX_USB_OHCI,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
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static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
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.num_ports = 1,
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.power_on = csn3xxx_usb_power_on,
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.power_off = csn3xxx_usb_power_off,
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};
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static struct platform_device cns3xxx_usb_ohci_device = {
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.name = "ohci-platform",
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.num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
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.resource = cns3xxx_usb_ohci_resources,
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.dev = {
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.dma_mask = &cns3xxx_usb_ohci_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = &cns3xxx_usb_ohci_pdata,
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},
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};
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/*
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* Initialization
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*/
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static struct platform_device *cns3420_pdevs[] __initdata = {
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&cns3420_nor_pdev,
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&cns3xxx_usb_ehci_device,
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&cns3xxx_usb_ohci_device,
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};
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static void __init cns3420_init(void)
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{
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cns3xxx_l2x0_init();
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platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
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cns3xxx_ahci_init();
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cns3xxx_sdhci_init();
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pm_power_off = cns3xxx_power_off;
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}
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static struct map_desc cns3420_io_desc[] __initdata = {
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{
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.virtual = CNS3XXX_UART0_BASE_VIRT,
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.pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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static void __init cns3420_map_io(void)
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{
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cns3xxx_map_io();
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iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
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cns3420_early_serial_setup();
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}
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MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
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.atag_offset = 0x100,
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.map_io = cns3420_map_io,
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.init_irq = cns3xxx_init_irq,
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.init_time = cns3xxx_timer_init,
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.init_machine = cns3420_init,
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.init_late = cns3xxx_pcie_init_late,
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.restart = cns3xxx_restart,
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MACHINE_END
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