133 lines
4.0 KiB
C
133 lines
4.0 KiB
C
/*
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* linux/arch/arm/include/asm/pmu.h
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*
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* Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __ARM_PMU_H__
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#define __ARM_PMU_H__
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#include <linux/interrupt.h>
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#include <linux/perf_event.h>
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/*
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* struct arm_pmu_platdata - ARM PMU platform data
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*
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* @handle_irq: an optional handler which will be called from the
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* interrupt and passed the address of the low level handler,
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* and can be used to implement any platform specific handling
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* before or after calling it.
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* @runtime_resume: an optional handler which will be called by the
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* runtime PM framework following a call to pm_runtime_get().
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* Note that if pm_runtime_get() is called more than once in
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* succession this handler will only be called once.
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* @runtime_suspend: an optional handler which will be called by the
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* runtime PM framework following a call to pm_runtime_put().
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* Note that if pm_runtime_get() is called more than once in
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* succession this handler will only be called following the
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* final call to pm_runtime_put() that actually disables the
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* hardware.
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*/
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struct arm_pmu_platdata {
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irqreturn_t (*handle_irq)(int irq, void *dev,
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irq_handler_t pmu_handler);
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int (*runtime_resume)(struct device *dev);
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int (*runtime_suspend)(struct device *dev);
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};
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#ifdef CONFIG_HW_PERF_EVENTS
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/*
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* The ARMv7 CPU PMU supports up to 32 event counters.
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*/
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#define ARMPMU_MAX_HWEVENTS 32
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#define HW_OP_UNSUPPORTED 0xFFFF
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#define C(_x) PERF_COUNT_HW_CACHE_##_x
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#define CACHE_OP_UNSUPPORTED 0xFFFF
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#define PERF_MAP_ALL_UNSUPPORTED \
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[0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
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#define PERF_CACHE_MAP_ALL_UNSUPPORTED \
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[0 ... C(MAX) - 1] = { \
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[0 ... C(OP_MAX) - 1] = { \
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[0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \
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}, \
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}
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/* The events for a given PMU register set. */
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struct pmu_hw_events {
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/*
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* The events that are active on the PMU for the given index.
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*/
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struct perf_event **events;
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/*
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* A 1 bit for an index indicates that the counter is being used for
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* an event. A 0 means that the counter can be used.
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*/
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unsigned long *used_mask;
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/*
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* Hardware lock to serialize accesses to PMU registers. Needed for the
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* read/modify/write sequences.
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*/
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raw_spinlock_t pmu_lock;
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};
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struct arm_pmu {
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struct pmu pmu;
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cpumask_t active_irqs;
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char *name;
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irqreturn_t (*handle_irq)(int irq_num, void *dev);
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void (*enable)(struct perf_event *event);
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void (*disable)(struct perf_event *event);
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int (*get_event_idx)(struct pmu_hw_events *hw_events,
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struct perf_event *event);
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void (*clear_event_idx)(struct pmu_hw_events *hw_events,
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struct perf_event *event);
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int (*set_event_filter)(struct hw_perf_event *evt,
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struct perf_event_attr *attr);
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u32 (*read_counter)(struct perf_event *event);
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void (*write_counter)(struct perf_event *event, u32 val);
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void (*start)(struct arm_pmu *);
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void (*stop)(struct arm_pmu *);
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void (*reset)(void *);
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int (*request_irq)(struct arm_pmu *, irq_handler_t handler);
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void (*free_irq)(struct arm_pmu *);
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int (*map_event)(struct perf_event *event);
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int num_events;
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atomic_t active_events;
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struct mutex reserve_mutex;
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u64 max_period;
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struct platform_device *plat_device;
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struct pmu_hw_events *(*get_hw_events)(void);
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};
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#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
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extern const struct dev_pm_ops armpmu_dev_pm_ops;
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int armpmu_register(struct arm_pmu *armpmu, int type);
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u64 armpmu_event_update(struct perf_event *event);
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int armpmu_event_set_period(struct perf_event *event);
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int armpmu_map_event(struct perf_event *event,
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const unsigned (*event_map)[PERF_COUNT_HW_MAX],
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const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX],
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u32 raw_event_mask);
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#endif /* CONFIG_HW_PERF_EVENTS */
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#endif /* __ARM_PMU_H__ */
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