368 lines
11 KiB
Plaintext
368 lines
11 KiB
Plaintext
MSM TLMM pinmux controller
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Qualcomm MSM integrates a GPIO and Pin mux/config hardware, (TOP Level Mode
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Multiplexer in short TLMM). It controls the input/output settings on the
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available pads/pins and also provides ability to multiplex and configure the
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output of various on-chip controllers onto these pads. The pins are also of
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different types, encapsulating different functions and having differing register
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semantics.
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Required Properties:
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- compatible: identifies TLMM hardware version. should be one of the following
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"qcom,msm-tlmm-8916"
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"qcom,msm-tlmm-8226"
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"qcom,msm-tlmm-8974"
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"qcom,msm-tlmm-mdm9640"
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"qcom,msm-tlmm-vpipa"
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- reg: Base address of the pin controller hardware module and length of
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the address space it occupies.
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- Pin types as child nodes: Pin types supported by a particular controller
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instance are represented as child nodes of the
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controller node. This is optional.
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Each pin type nodes' name must be unique and one of followings. Also each pin
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type nodes can be present only when the specific pin type is supported by
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SoC's TLMM :
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- gp : General purpose pins
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- sdc : SDC pins
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- qdsc : QDSC pins
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Each pin type node must contain following properties:
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Required Properties
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- #qcom,pin-cells: number of cells in the pin type specifier.
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- qcom,num-pins: number of pins of given type present on the MSM.
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Optional: A pintype may support gpio operations. In that case, a pintype
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node can have an additional child node representing a gpio controller.
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Additionally the pintype may also support using pins as interrupt triggers.
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In this case we augment the gpio controller node with interrupt controller
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attributes. The interrupt controller node, if present, needs to specify the
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number of pins that can be used as interrupts as well as the id of the
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processor core to which they need to be routed. Generally the apps id is
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fixed for a given TLMM block in all SOCs that use that TLMM block.
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However in some SOCs, the processor id can change. Override the default
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value in that case.
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- gpio-controller: Can be used as a gpio controller
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- #gpio-cells: Should be two. The first cell is the pin number and the
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second cell is used to specify optional parameters
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- interrupt-controller: Can be used as an interrupt controller
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- compatible: identifies the interrupt controller.
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- This should be "qcom,msm-tlmm-gp".
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- num_irqs: number of pins that can be used as an interrupt source.
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- apps_id: if present, override the default core id for given TLMM block.
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- #interrupt-cells: Should be two. The first cell is the pin number used as
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irq and the second cell is used to specify optional
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flags
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- Pin groups as child nodes: The pin mux (selecting pin function
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mode) and pin config (pull up/down, driver strength, direction) settings are
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represented as child nodes of the pin-controller node. There is no limit on
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the count of these child nodes.
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Required Properties
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-qcom,pins: phandle specifying pin type and a pin number.
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-qcom,num-grp-pins: number of pins in the group.
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-label: name to identify the pin group to be used by a client.
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Optional Properties
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-qcom,pin-func: function setting for the pin group.
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The child node should contain a list of pin(s) on which a particular pin
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function selection or pin configuration (or both) have to applied. This
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list of pins is specified using the property name "qcom,pins". There
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should be atleast one pin specified for this property and there is no upper
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limit on the count of pins that can be specified. The pins are specified
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using the pintype phandle and the pin number within that pintype.
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The pin function selection that should be applied on the pins listed in the
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child node is specified using the "qcom,pin-func" property. The value
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of this property that should be applied to each of the pins listed in the
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"qcom,pins" property, should be picked from the hardware manual of the SoC.
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This property is optional in the child node if no specific function
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selection is desired for the pins listed in the child node or if the pin is
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to be used for bit banging.
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The pin group node must additionally have a pin configuration node as its own
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child node. There can be more then one such configuration node for a pin group
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node. There can be one or more configurations within the configuration
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node. These configurations are applied to all pins mentioned above using the
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"qcom,pins" property. These configurations are specific to the pintype of the
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pins.
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For the pin configuration properties supported by both pin types lookup
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Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
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The values specified by these config properties should be derived from the
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hardware manual and these values are programmed as-is into the pin config
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register of the pin-controller.
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NOTE: A pin group node should be formed for all pins that are going to have
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the same function and configuration settings. If a subset of pins to be used
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by a client require different function or configuration settings or both
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then they should be modelled as a separate pin group node to be used by
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the client.
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The client nodes that require a particular pin function selection and/or
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pin configuration should use the bindings listed in the "pinctrl-bindings txt"
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file.
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In case of SDC pintype, we model it as containing 6 pins. 3 each for SDC1 and
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SDC2. Pins 0-2 corresponds to clock, data and command lines of
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SDC1 and Pins 3-5 correspond to clock, data and command lines of SDC2.
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Example 1: A pin-controller node with pin types
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pinctrl@fd5110000 {
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compatible = "qcom,msm-tlmm-8974";
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reg = <0xfd5110000 0x4000>;
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/* General purpose pin type */
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gp: gp {
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qcom,num-pins = <117>;
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#qcom,pin-cells = <1>;
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/* Supports Gpio controller */
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msm_gpio: msm_gpio {
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "qcom,msm-tlmm-gp";
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interrupt-controller;
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#interrupt-cells <2>;
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num_irqs = <117>;
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apps_id = <4>;
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};
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};
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/* Sdc pin type */
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sdc: sdc {
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qcom,num-pins = <6>;
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#qcom,pin-cells = <1>;
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};
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};
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Example 2: Spi pin entries within the pincontroller node
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pinctrl@fd511000 {
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....
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..
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pmx-spi-bus {
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/*
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* MOSI, MISO and CLK lines
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* all sharing same function and config
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* settings for each configuration node.
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*/
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qcom,pins = <&gp 0>, <&gp 1>, <&gp 3>;
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qcom,num-grp-pins = <3>;
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qcom,pin-func = <1>;
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label = "spi-bus";
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/* Active configuration of bus pins */
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spi-bus-active: spi-bus-active {
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/*
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* Property names as specified in
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* pinctrl-bindings.txt
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*/
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drive-strength = <8>; /* 8 MA */
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bias-disable; /* No PULL */
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};
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/* Sleep configuration of bus pins */
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spi-bus-sleep: spi-bus-sleep {
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/*
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* Property values as specified in HW
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* manual.
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*/
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drive-strength = <2>; /* 2 MA */
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bias-disable;
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};
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};
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pmx-spi-cs {
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/*
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* Chip select for SPI
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* different config
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* settings as compared to bus pins.
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*/
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qcom,pins = <&gp 2>;
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qcom,num-grp-pins = <1>;
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qcom,pin-func = <1>;
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label = "spi-cs"
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/* Active configuration of cs pin */
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spi-cs-active: spi-cs-active {
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/*
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* Property names as specified in
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* pinctrl-bindings.txt
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*/
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drive-strength = <4>; /* 4 MA */
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bias-disable; /* No PULL */
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};
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/* Sleep configuration of cs pin */
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spi-cs-sleep: spi-cs-sleep {
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/*
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* Property values as specified in HW
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* manual.
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*/
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drive-strength = <2>; /* 2 MA */
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bias-disable = <0>; /* No PULL */
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};
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};
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};
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Example 3: Same pin group with different pin function settings modelled as
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separate nodes
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pinctrl@fd511000 {
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...
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..
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pmx-wcnss-5wire-active {
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qcom,pins = <&gp 40>, <&gp 41>, <&gp 42>, <&gp 43>.
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<&gp 44>;
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qcom,pin-func = <1>;
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qcom,num-grp-pins = <5>;
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label = "wcnss-5wire-active";
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wcnss-5wire-active: wcnss-active {
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drive-strength = <6>; / * 6MA */
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bias-pull-up;
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};
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};
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pmx-wcnss-5wire-suspend {
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qcom,pins = <&gp 40>, <&gp 41>, <&gp 42>, <&gp 43>.
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<&gp 44>;
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qcom,pin-func = <0>;
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qcom,num-grp-pins = <5>;
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label = "wcnss-5wire-suspend";
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wcnss-5wire-sleep: wcnss-sleep {
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drive-strength = <6>; / * 6MA */
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bias-pull-down;
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};
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};
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};
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Example 4: SDC pins
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pinctrl@0xfd511000 {
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...
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..
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pmx-sdc1_clk {
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qcom,pins = <&sdc 0>;
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qcom,num-grp-pins = <1>;
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label = "sdc1-clk";
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sdc1_clk_on: clk_on {
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bias-disable; /* NO pull */
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drive-strength = <12>; /* 12 MA */
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};
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sdc1_clk_off: clk_off {
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bias-disable; /* NO pull */
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drive-strength = <2>; /* 2 MA */
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};
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};
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pmx-sdc1_cmd {
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qcom,pins = <&sdc 1>;
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qcom,num-grp-pins = <1>;
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label = "sdc1-cmd";
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sdc1_cmd_on: clk_on {
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bias-disable; /* NO pull */
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drive-strength = <12>; /* 12 MA */
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};
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sdc1_cmd_off: cmd_off {
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bias-pull-up = <0x3>; /* pull up */
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drive-strength = <2>; /* 2 MA */
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};
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};
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pmx-sdc1_data {
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qcom,pins = <&sdc 2>;
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qcom,num-grp-pins = <1>;
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label = "sdc1-data";
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sdc1_data_on: data_on {
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bias-pull-up; /* NO pull */
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drive-strength = <12>; /* 12 MA */
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};
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sdc1_data_off: data_off {
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bias-pull-up; /* pull up */
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drive-strength = <0>; /* 2 MA */
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};
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};
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pmx-sdc2_clk {
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qcom,pins = <&sdc 3>;
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qcom,num-grp-pins = <1>;
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label = "sdc2-clk";
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sdc2_clk_on: clk_on {
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bias-disable; /* NO pull */
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drive-strength = <12>; /* 12 MA */
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};
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sdc2_clk_off: clk_off {
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bias-disable; /* NO pull */
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drive-strength = <2>; /* 2 MA */
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};
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};
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pmx-sdc2_cmd {
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qcom,pins = <&sdc 4>;
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qcom,num-grp-pins = <1>;
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label = "sdc2-cmd";
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sdc2_cmd_on: cmd_on {
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bias-disable; /* NO pull */
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drive-strength = <12>; /* 12 MA */
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};
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sdc2_cmd_off: cmd_off {
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bias-pull-up; /* pull up */
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drive-strength = <2>; /* 2 MA */
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};
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};
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pmx-sdc2_data {
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qcom,pins = <&sdc 5>;
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qcom,num-grp-pins = <1>;
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label = "sdc2-data";
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sdc2_data_on: data_on {
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bias-pull-up; /* NO pull */
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drive-strength = <12>; /* 12 MA */
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};
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sdc2_data_off: data_off {
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bias-pull-up; /* pull up */
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drive-strength = <2>; /* 2 MA */
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};
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};
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Example 5: A SPI client node that supports 'active' and 'sleep' states.
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spi_0: spi@f9923000 { /* BLSP1 QUP1 */
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.....
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...
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/* pins used by spi controllers */
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&spi-bus-active &spi-cs-active>;
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pinctrl-1 = <&spi-bus-sleep &spi-cs-sleep>;
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...
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..
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};
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Example 6: A wcnss node with active and sleep states
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qcom,wcnss-wlan@fb000000 {
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....
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..
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/* pins used by wlan controllers */
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&wcnss-5wire-active>;
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pinctrl-1 = <&wcnss-5wire-sleep>;
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...
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};
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Example 7: SDC1 and SDC2 nodes with on and off states.
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&sdhc_1 {
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....
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..
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/* pins used by SDCC1 */
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pinctrl-names = "on", "off";
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pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
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pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
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...
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..
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};
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&sdhc_2 {
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....
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..
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pinctrl-names = "on", "off";
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pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
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pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
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};
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