502 lines
17 KiB
C
502 lines
17 KiB
C
/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _USB30_DWC_H
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#define _USB30_DWC_H
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#include <bits.h>
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/********************* START: h/w defined values ******************************/
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/* device command ids */
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typedef enum
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{
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DWC_DEV_CMD_TX_SET_LINK_FN_LMP_VAL = 0x01,
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DWC_DEV_CMD_SET_PERIODIC_PARAMS_VAL = 0x02,
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DWC_DEV_CMD_TX_FN_WAKE_DEV_NOTIFY_VAL = 0x03,
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DWC_DEV_CMD_SET_SCRATCHPAD_BUF_LO_VAL = 0x04,
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DWC_DEV_CMD_SET_SCRATCHPAD_BUF_HI_VAL = 0x05,
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DWC_DEV_CMD_TX_FN_HOST_REQ_NOTIFY_VAL = 0x06,
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DWC_DEV_CMD_TX_DEVICE_NOTIFY_VAL = 0x07,
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DWC_DEV_CMD_SELECTED_FIFO_FLUSH_VAL = 0x09,
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DWC_DEV_CMD_ALL_FIFO_FLUSH_VAL = 0x0A,
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DWC_DEV_CMD_SET_EP_NRDY_VAL = 0x0C,
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DWC_DEV_CMD_RUN_SOC_LOOPBACK_TEST_VAL = 0x10,
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} dwc_dev_cmd_t;
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/* ep command ids */
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typedef enum
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{
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DEPCMD_CMD_SET_EP_CONF = 0x1,
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DEPCMD_CMD_SET_TR_CONF = 0x2,
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DEPCMD_CMD_GET_EP_STATE = 0x3,
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DEPCMD_CMD_SET_STALL = 0x4,
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DEPCMD_CMD_CLEAR_STALL = 0x5,
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DEPCMD_CMD_START_TRANSFER = 0x6,
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DEPCMD_CMD_UPDATE_TRANSFER = 0x7,
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DEPCMD_CMD_END_TRANSFER = 0x8,
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DEPCMD_CMD_START_NEW_CONF = 0x9,
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} dwc_dep_cmd_id_t;
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/* ep type */
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typedef enum {
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EP_TYPE_CONTROL = 0x0,
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EP_TYPE_ISOCHRONOUS = 0x1,
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EP_TYPE_BULK = 0x2,
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EP_TYPE_INTERRUPT = 0x3,
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} dwc_ep_type_t;
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/* ep direction */
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typedef enum
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{
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DWC_EP_DIRECTION_OUT = 0x0,
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DWC_EP_DIRECTION_IN = 0x1
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} dwc_ep_direction_t;
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/* macros to parse event information */
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#define DWC_EVENT_IS_DEVICE_EVENT(_event) BIT_SHIFT(_event, 0)
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/* parse device events */
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#define DWC_EVENT_DEVICE_EVENT_ID(_event) BITS_SHIFT(_event, 11, 8)
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#define DWC_EVENT_DEVICE_EVENT_INFO(_event) BITS_SHIFT(_event, 24, 16)
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#define DWC_EVENT_DEVICE_EVENT_INFO_SS_EVENT(_event_info) BIT_SHIFT(_event_info, 4)
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#define DWC_EVENT_DEVICE_EVENT_INFO_LINK_STATE(_event_info) BITS_SHIFT(_event_info, 3, 0)
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/* parse ep events */
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#define DWC_EVENT_EP_EVENT_PARAM(_event) BITS_SHIFT(_event, 31, 16)
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#define DWC_EVENT_EP_EVENT_CMD_TYPE(_event) BITS_SHIFT(_event, 27, 24)
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#define DWC_EVENT_EP_EVENT_XFER_RES_IDX(_event) BITS_SHIFT(_event, 22, 16)
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#define DWC_EVENT_EP_EVENT_STATUS(_event) BITS_SHIFT(_event, 15, 12)
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#define DWC_EVENT_EP_EVENT_CTRL_STAGE(_event) BITS_SHIFT(_event, 13, 12)
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#define DWC_EVENT_EP_EVENT_ID(_event) BITS_SHIFT(_event, 9, 6)
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#define DWC_EVENT_EP_EVENT_EP_NUM(_event) BITS_SHIFT(_event, 5, 1)
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/* device event ids */
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typedef enum
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{
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DWC_EVENT_DEVICE_EVENT_ID_VENDOR_DEVICE_TEST_LMP = 12,
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DWC_EVENT_DEVICE_EVENT_ID_BUFFER_OVERFLOW = 11,
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DWC_EVENT_DEVICE_EVENT_ID_GENERIC_CMD_COMPLETE = 10,
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DWC_EVENT_DEVICE_EVENT_ID_ERRATIC_ERROR = 9,
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DWC_EVENT_DEVICE_EVENT_ID_SOF = 7,
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DWC_EVENT_DEVICE_EVENT_ID_SUSPEND_ENTRY = 6,
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DWC_EVENT_DEVICE_EVENT_ID_HIBER = 5,
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DWC_EVENT_DEVICE_EVENT_ID_WAKEUP = 4,
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DWC_EVENT_DEVICE_EVENT_ID_USB_LINK_STATUS_CHANGE = 3,
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DWC_EVENT_DEVICE_EVENT_ID_CONNECT_DONE = 2,
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DWC_EVENT_DEVICE_EVENT_ID_USB_RESET = 1,
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DWC_EVENT_DEVICE_EVENT_ID_DISCONNECT = 0,
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DWC_EVENT_DEVICE_EVENTS_ALL = BITS(0xFFFFFFFF, 12, 0)
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} dwc_event_device_event_id_t;
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/* ep event ids */
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typedef enum
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{
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DWC_EVENT_EP_CMD_COMPLETE = 7,
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DWC_EVENT_EP_XFER_NOT_READY = 3,
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DWC_EVENT_EP_XFER_IN_PROGRESS = 2,
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DWC_EVENT_EP_XFER_COMPLETE = 1,
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} dwc_event_ep_event_id_t;
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/* values for control stage in ep events */
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#define CONTROL_DATA_REQUEST 1
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#define CONTROL_STATUS_REQUEST 2
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/* values for event status field for transfer complete event */
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#define DWC_XFER_COMPLETE_EVT_STATUS_SHORT_PKT 0x2
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#define DWC_XFER_COMPLETE_EVT_STATUS_IOC 0x4
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#define DWC_XFER_COMPLETE_EVT_STATUS_LST 0x8
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/* master bus data width (DWC_USB3_MDWIDTH in snps data book) */
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#define DWC_MASTER_BUS_WIDTH 8
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/* super speed link states */
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typedef enum
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{
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U0 = 0x0,
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U1,
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U2,
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U3,
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SS_DIS,
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RX_DET,
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SS_INACT,
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POLL,
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RECOV,
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HRESET,
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CMPLY,
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LPBK,
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RESUME_RESET = 0xF,
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} dwc_event_device_ss_link_state_t;
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/* high speed link states */
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typedef enum
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{
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ON = 0x0,
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L1 = 0x2,
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L2 = 0x3,
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DISCONNECTED = 0x4,
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EARLY_SUSPEND = 0x5,
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RESET = 0xE,
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RESUME = 0xF,
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} dwc_event_device_hs_link_state_t;
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/* action for set config*/
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enum
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{
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SET_CONFIG_ACTION_INIT = 0x0,
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SET_CONFIG_ACTION_RESTORE = 0x1,
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SET_CONFIG_ACTION_MODIFY = 0x2,
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};
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/* EP Cmd Param bits */
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#define DEPCMDPAR1_USB_EP_NUM_BIT 26
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#define DEPCMDPAR1_USB_EP_DIR_BIT 25
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#define DEPCMDPAR0_ACTION_BIT 30
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#define DEPCMDPAR0_BURST_SIZE_BIT 22
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#define DEPCMDPAR0_FIFO_NUM_BIT 17
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#define DEPCMDPAR0_MAX_PKT_SIZE_BIT 3
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#define DEPCMDPAR0_EP_TYPE_BIT 1
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#define DEPCMDPAR2_XFER_N_RDY_BIT 10
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#define DEPCMDPAR2_XFER_IN_PROG_BIT 9
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#define DEPCMDPAR2_XFER_COMPLETE_BIT 8
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enum
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{
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DSTS_CONNECTSPD_HS = 0,
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DSTS_CONNECTSPD_FS1 = 1, /* phy clk @ 30 or 60 MHz */
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DSTS_CONNECTSPD_LS = 2,
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DSTS_CONNECTSPD_FS2 = 3, /* phy clk @ 48 MHz */
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DSTS_CONNECTSPD_SS = 4,
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};
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/**************************** TRB (Transfer Request Block)*********************/
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#define DWC_TRB_F1_PTR_LOW_BMSK 0xFFFFFFFF
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#define DWC_TRB_F1_PTR_LOW_SHFT 0
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#define DWC_TRB_F2_PTR_HIGH_BMSK 0xFFFFFFFF
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#define DWC_TRB_F2_PTR_HIGH_SHFT 0
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#define DWC_TRB_F3_BUFSIZ_BMSK 0x00FFFFFF
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#define DWC_TRB_F3_BUFSIZ_SHFT 0
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#define DWC_TRB_F3_PCM1_BMSK 0x03000000
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#define DWC_TRB_F3_PCM1_SHFT 24
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#define DWC_TRB_F3_TRBSTS_BMSK 0xF0000000
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#define DWC_TRB_F3_TRBSTS_SHFT 28
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#define DWC_TRB_F4_IOC_BMSK 0x800
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#define DWC_TRB_F4_IOC_SHFT 11
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#define DWC_TRB_F4_ISP_BMSK 0x400
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#define DWC_TRB_F4_ISP_SHFT 10
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#define DWC_TRB_F4_TRBCTL_BMSK 0x3F0
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#define DWC_TRB_F4_TRBCTL_SHFT 4
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#define DWC_TRB_F4_CSP_BMSK 0x8
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#define DWC_TRB_F4_CSP_SHFT 3
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#define DWC_TRB_F4_CHN_BMSK 0x4
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#define DWC_TRB_F4_CHN_SHFT 2
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#define DWC_TRB_F4_LST_BMSK 0x2
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#define DWC_TRB_F4_LST_SHFT 1
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#define DWC_TRB_F4_HWO_BMSK 0x1
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#define DWC_TRB_F4_HWO_SHFT 0
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/**************************** END - TRB ***************************************/
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#define DWC_MAX_BYTES_PER_TRB 0x00FFFFFF
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/********************* END: h/w defined values ********************************/
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/******************** START: local data not needed by external APIs ***********/
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/* event buffer: used to manage various controller events */
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typedef struct {
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uint32_t *buf; /* ptr to event buffer. */
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uint16_t buf_size; /* size of buf. */
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uint16_t max_index; /* max index value. initialized once. used to track rollover. */
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uint16_t index; /* index into the buf for reading next event */
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} dwc_event_buf_t;
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/* device command */
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typedef struct {
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uint32_t cmd;
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uint32_t param;
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} dwc_device_cmd_t;
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/* ep command */
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typedef struct {
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uint32_t cmd;
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uint8_t xfer_resource_index;
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uint32_t param2;
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uint32_t param1;
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uint32_t param0;
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} dwc_ep_cmd_t;
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/* state of data transfer on an ep */
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typedef enum
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{
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EP_STATE_INIT = 0x0, /* initial state. cannot start transfer. */
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EP_STATE_INACTIVE = 0x1, /* start xfer has not been issued. transfer is NOT in progress. start transfer can be issued ONLY in this state. */
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EP_STATE_START_TRANSFER = 0x2, /* start xfer is issued but cmd is not completed yet. */
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EP_STATE_XFER_IN_PROG = 0x3, /* start xfer is issued and xfer is in progress. */
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} dwc_ep_state_t;
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/* control fsm states: states to manage control transfers */
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typedef enum
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{
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EP_FSM_INIT = 0,
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EP_FSM_SETUP = 1,
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EP_FSM_CTRL_DATA = 2,
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EP_FSM_WAIT_FOR_HOST_2 = 3, /* 2-stage transfer wait-for-host stage */
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EP_FSM_WAIT_FOR_HOST_3 = 4, /* 3-stage transfer wait-for-host stage */
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EP_FSM_STATUS_2 = 5,
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EP_FSM_STATUS_3 = 6,
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EP_FSM_STALL = 7,
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} dwc_ctrl_fsm_t;
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/* TRB type */
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typedef enum
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{
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TRBCTL_NORMAL = 1,
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TRBCTL_CONTROL_SETUP = 2,
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TRBCTL_CONTROL_STATUS_2 = 3,
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TRBCTL_CONTROL_STATUS_3 = 4,
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TRBCTL_CONTROL_DATA = 5,
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TRBCTL_LINK_TRB = 8,
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} dwc_trb_trbctl_t;
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/* data transfer request */
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typedef struct
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{
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uint8_t *data;
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uint32_t len;
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dwc_trb_trbctl_t trbctl;
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void *context;
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void (*callback)(void *context, uint32_t actual, int status);
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} dwc_request_t;
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/******************** END: local data not needed by external APIs *************/
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/******************** START: data needed by external APIs *********************/
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/* TRB fields */
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typedef struct
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{
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uint32_t f1;
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uint32_t f2;
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uint32_t f3;
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uint32_t f4;
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} dwc_trb_t;
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/* index into the ep array of the dwc device */
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#define DWC_EP_INDEX(_usb_ep, _direction) (((_usb_ep) << 1) | (_direction))
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/* phyical ep number: same as ep index. */
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#define DWC_EP_PHY_NUM(_usb_ep, _direction) (((_usb_ep) << 1) | (_direction))
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/* since we assume non-flexible mapping, phy_num is same as index. */
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#define DWC_EP_PHY_TO_INDEX(_ep_phy_num) (_ep_phy_num)
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typedef void (*dwc_transfer_callback_t)(void *context, uint32_t actual, int status);
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/* length of zero-length-packet */
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/* TODO: shouldn't this be same a max pkt size for the EP
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* which is specified by udc? fastboot doesn't need this.
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* So this is not verified.
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*/
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#define DWC_ZLP_BUF_SIZE 512
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/* Structure to keep all information about an endpoint */
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typedef struct
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{
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uint8_t number; /* usb ep number */
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dwc_ep_direction_t dir; /* usb ep direction */
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dwc_ep_type_t type; /* ctrl/blk etc. */
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uint16_t max_pkt_size; /* max packet size */
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uint8_t zlp; /* uses zero length pkt to terminate xfer */
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uint32_t burst_size; /* max packets to transfer before waiting for ack */
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uint8_t phy_num; /* physical EP to which this usb ep is mapped */
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uint8_t tx_fifo_num; /* which TX FIFO to use. only applies to IN endpoints */
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uint8_t zlp_buf[DWC_ZLP_BUF_SIZE]; /* buffer needed to pad when OUT requests are not exact multiple of max_pkt_size and for zlp */
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uint8_t resource_idx; /* assigned by h/w on each start xfer cmd. Needed to stop/update xfers. */
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dwc_trb_t *trb; /* ptr to the first TRB in the chain. */
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uint32_t trb_count; /* size of TRB chain. */
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uint32_t trb_queued; /* number of TRBs queued in the current request. */
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uint32_t bytes_queued; /* number of bytes queued in the current request. */
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dwc_request_t req; /* transfer request that is currently queued on this ep. */
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dwc_ep_state_t state; /* data transfer state of the ep. */
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} dwc_ep_t;
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/* dwc device events */
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typedef enum
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{
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DWC_NOTIFY_EVENT_OFFLINE,
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DWC_NOTIFY_EVENT_CONNECTED_LS,
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DWC_NOTIFY_EVENT_CONNECTED_FS,
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DWC_NOTIFY_EVENT_CONNECTED_HS,
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DWC_NOTIFY_EVENT_CONNECTED_SS,
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DWC_NOTIFY_EVENT_DISCONNECTED,
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} dwc_notify_event_t;
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/* maximum number of endpoints supported. */
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#define DWC_MAX_NUM_OF_EP 8
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/* length of setup packet */
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#define DWC_SETUP_PKT_LEN 8
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enum
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{
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DWC_SETUP_ERROR = -1,
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DWC_SETUP_2_STAGE = 2,
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DWC_SETUP_3_STAGE = 3,
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};
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/* Structure to keep all DWC device information. */
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typedef struct
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{
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void *base; /* base address for snps core registers */
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uint32_t core_id; /* snps core version. read from h/w during init */
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dwc_ep_t ep[DWC_MAX_NUM_OF_EP]; /* array of endpoint data */
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dwc_event_buf_t event_buf; /* event buffer management */
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dwc_ctrl_fsm_t ctrl_state; /* states to manage control transfers : setup/data/wait/status */
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uint8_t *setup_pkt; /* Buffer for the received setup packet */
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/* callback into client to notify device events: online/offline/connect speed */
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void *notify_context;
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void (*notify)(void *context, dwc_notify_event_t event);
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/* callback into client to process the setup msgs. */
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void *setup_context;
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int (*setup_handler)(void* context, uint8_t* data);
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bool is_test_mode;
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uint16_t test_mode;
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} dwc_dev_t;
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/* config data to initialize dwc layer */
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typedef struct
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{
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void *base; /* dwc base address */
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uint32_t *event_buf; /* buffer to be used for h/w events */
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uint16_t event_buf_size; /* buffer size */
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/* callback for dwc events */
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void *notify_context;
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void (*notify)(void *context, dwc_notify_event_t event);
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/* callback for handling setup packets */
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void *setup_context;
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int (*setup_handler)(void *context, uint8_t *data);
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} dwc_config_t;
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/********************************* dwc global apis ****************************/
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/* generic apis */
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dwc_dev_t* dwc_init(dwc_config_t *config);
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void dwc_reset(dwc_dev_t *dev, uint8_t reset);
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/* phy specific apis */
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void dwc_phy_digital_reset(dwc_dev_t *dev);
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void dwc_usb2_phy_soft_reset(dwc_dev_t *dev);
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void dwc_ss_phy_workaround_12(dwc_dev_t *dev);
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/* device specific apis */
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void dwc_device_init(dwc_dev_t *dev);
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void dwc_device_reset(dwc_dev_t *dev);
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void dwc_device_run(dwc_dev_t *dev, uint8_t run);
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void dwc_device_set_addr(dwc_dev_t *dev, uint16_t addr);
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void dwc_device_set_configuration(dwc_dev_t *dev);
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void dwc_device_set_periodic_param(dwc_dev_t *dev, uint32_t val);
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void dwc_device_add_ep(dwc_dev_t *dev, dwc_ep_t *new_ep);
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/* data transfer apis */
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int dwc_transfer_request(dwc_dev_t *dwc,
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uint8_t usb_ep,
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dwc_ep_direction_t dir,
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void *buf,
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uint32_t len,
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dwc_transfer_callback_t callback,
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void *callback_context);
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/******************** END: data needed by external APIs *********************/
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/* static apis */
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/* command complete event handler */
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static void dwc_event_handle_cmd_complete(dwc_dev_t *dev, uint32_t *event);
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/* device event handler */
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static void dwc_event_handler_device(dwc_dev_t *dev, uint32_t *event);
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static void dwc_event_device_link_status_change(dwc_dev_t *dev, uint32_t *event);
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static void dwc_event_device_reset(dwc_dev_t *dev);
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static void dwc_event_device_connect_done(dwc_dev_t *dev);
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static void dwc_event_device_disconnect(dwc_dev_t *dev);
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/* bulk ep event handling functions */
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static void dwc_event_handler_ep_bulk(dwc_dev_t *dev, uint32_t *event);
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static void dwc_event_handler_ep_bulk_state_inactive(dwc_dev_t *dev, uint32_t *event);
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static void dwc_event_handler_ep_bulk_state_xfer_in_prog(dwc_dev_t *dev, uint32_t *event);
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static void dwc_ep_bulk_state_inactive_enter(dwc_dev_t *dev, uint8_t ep_phy_num);
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/* control ep event handling functions */
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static void dwc_event_handler_ep_ctrl(dwc_dev_t *dev, uint32_t *event);
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static void dwc_ep_ctrl_state_setup_enter(dwc_dev_t *dev);
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static void dwc_event_handler_ep_ctrl_state_setup(dwc_dev_t *dev, uint32_t *event);
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static void dwc_event_handler_ep_ctrl_state_data(dwc_dev_t *dev, uint32_t *event);
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static void dwc_event_handler_ep_ctrl_state_wait_for_host_2(dwc_dev_t *dev, uint32_t *event);
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static void dwc_event_handler_ep_ctrl_state_wait_for_host_3(dwc_dev_t *dev, uint32_t *event);
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static void dwc_event_handler_ep_ctrl_state_status_2(dwc_dev_t *dev, uint32_t *event);
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static void dwc_event_handler_ep_ctrl_state_status_3(dwc_dev_t *dev, uint32_t *event);
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static void dwc_event_handler_ep_ctrl_state_stall(dwc_dev_t *dev, uint32_t *event);
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static enum handler_return dwc_irq_handler_ee1(void* arg);
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static void dwc_ep_config_init_enable(dwc_dev_t *dev, uint8_t index);
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void dwc_ep_cmd_clear_stall(dwc_dev_t *dev, uint8_t ep_phy_num);
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static int dwc_request_queue(dwc_dev_t *dev, uint8_t ep_phy_num, dwc_request_t *req);
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#endif
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