258 lines
7.1 KiB
C
258 lines
7.1 KiB
C
/*
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* * Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <debug.h>
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#include <pm_pwm.h>
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#include <pm8x41_hw.h>
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#define NSEC_PER_USEC 1000L
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#define USEC_PER_SEC 1000000L
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#define NSEC_PER_SEC 1000000000L
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#define NUM_REF_CLOCKS 3
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#define NSEC_1024HZ (NSEC_PER_SEC / 1024)
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#define NSEC_32768HZ (NSEC_PER_SEC / 32768)
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#define NSEC_19P2MHZ (NSEC_PER_SEC / 19200000)
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#define NUM_PRE_DIVIDE 4
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#define PRE_DIVIDE_1 1
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#define PRE_DIVIDE_3 3
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#define PRE_DIVIDE_5 5
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#define PRE_DIVIDE_6 6
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static unsigned int pt_t[NUM_PRE_DIVIDE][NUM_REF_CLOCKS] = {
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{ PRE_DIVIDE_1 * NSEC_1024HZ,
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PRE_DIVIDE_1 * NSEC_32768HZ,
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PRE_DIVIDE_1 * NSEC_19P2MHZ,
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},
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{ PRE_DIVIDE_3 * NSEC_1024HZ,
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PRE_DIVIDE_3 * NSEC_32768HZ,
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PRE_DIVIDE_3 * NSEC_19P2MHZ,
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},
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{ PRE_DIVIDE_5 * NSEC_1024HZ,
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PRE_DIVIDE_5 * NSEC_32768HZ,
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PRE_DIVIDE_5 * NSEC_19P2MHZ,
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},
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{ PRE_DIVIDE_6 * NSEC_1024HZ,
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PRE_DIVIDE_6 * NSEC_32768HZ,
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PRE_DIVIDE_6 * NSEC_19P2MHZ,
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},
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};
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enum pwm_ctl_reg {
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SIZE_CLK,
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FREQ_PREDIV_CLK,
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TYPE_CONFIG,
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VALUE_LSB,
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VALUE_MSB,
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};
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#define NUM_PWM_CTL_REGS 5
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struct pm_pwm_config {
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int pwm_size; /* round up to 6 or 9 for 6/9-bit PWM SIZE */
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int clk;
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int pre_div;
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int pre_div_exp;
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int pwm_value;
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uint8_t pwm_ctl[NUM_PWM_CTL_REGS];
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};
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static void pm_pwm_reg_write(uint8_t off, uint8_t val)
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{
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REG_WRITE(PM_PWM_BASE(off), val);
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}
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/*
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* PWM Frequency = Clock Frequency / (N * T)
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* or
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* PWM Period = Clock Period * (N * T)
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* where
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* N = 2^9 or 2^6 for 9-bit or 6-bit PWM size
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* T = Pre-divide * 2^m, where m = 0..7 (exponent)
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*
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* This is the formula to figure out m for the best pre-divide and clock:
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* (PWM Period / N) = (Pre-divide * Clock Period) * 2^m
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*/
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#define PRE_DIVIDE_MAX 6
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#define CLK_PERIOD_MAX NSEC_1024HZ
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#define PM_PWM_M_MAX 7
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#define MAX_MPT ((PRE_DIVIDE_MAX * CLK_PERIOD_MAX) << PM_PWM_M_MAX)
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static void pm_pwm_calc_period(unsigned int period_us,
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struct pm_pwm_config *pwm_config)
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{
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int n, m, clk, div;
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int best_m, best_div, best_clk;
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unsigned int last_err, cur_err, min_err;
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unsigned int tmp_p, period_n;
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n = 6;
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if (period_us < ((unsigned)(-1) / NSEC_PER_USEC))
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period_n = (period_us * NSEC_PER_USEC) >> n;
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else
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period_n = (period_us >> n) * NSEC_PER_USEC;
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if (period_n >= MAX_MPT) {
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n = 9;
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period_n >>= 3;
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}
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min_err = last_err = (unsigned)(-1);
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best_m = 0;
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best_clk = 0;
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best_div = 0;
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for (clk = 0; clk < NUM_REF_CLOCKS; clk++) {
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for (div = 0; div < NUM_PRE_DIVIDE; div++) {
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/* period_n = (PWM Period / N) */
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/* tmp_p = (Pre-divide * Clock Period) * 2^m */
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tmp_p = pt_t[div][clk];
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for (m = 0; m <= PM_PWM_M_MAX; m++) {
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if (period_n > tmp_p)
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cur_err = period_n - tmp_p;
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else
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cur_err = tmp_p - period_n;
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if (cur_err < min_err) {
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min_err = cur_err;
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best_m = m;
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best_clk = clk;
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best_div = div;
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}
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if (m && cur_err > last_err)
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/* Break for bigger cur_err */
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break;
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last_err = cur_err;
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tmp_p <<= 1;
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}
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}
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}
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pwm_config->pwm_size = n;
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pwm_config->clk = best_clk;
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pwm_config->pre_div = best_div;
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pwm_config->pre_div_exp = best_m;
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}
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static void pm_pwm_calc_pwm_value(struct pm_pwm_config *pwm_config,
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unsigned int period_us,
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unsigned int duty_us)
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{
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int max_pwm_value;
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unsigned int tmp;
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/* Figure out pwm_value with overflow handling */
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tmp = 1 << (sizeof(tmp) * 8 - pwm_config->pwm_size);
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if (duty_us < tmp) {
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tmp = duty_us << pwm_config->pwm_size;
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pwm_config->pwm_value = tmp / period_us;
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} else {
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tmp = period_us >> pwm_config->pwm_size;
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pwm_config->pwm_value = duty_us / tmp;
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}
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max_pwm_value = (1 << pwm_config->pwm_size) - 1;
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if (pwm_config->pwm_value > max_pwm_value)
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pwm_config->pwm_value = max_pwm_value;
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}
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#define PM_PWM_SIZE_9_BIT 1
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#define PM_PWM_SIZE_6_BIT 0
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static void pm_pwm_config_regs(struct pm_pwm_config *pwm_config)
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{
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int i;
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uint8_t reg;
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reg = ((pwm_config->pwm_size > 6 ? PM_PWM_SIZE_9_BIT : PM_PWM_SIZE_6_BIT)
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<< PM_PWM_SIZE_SEL_SHIFT)
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& PM_PWM_SIZE_SEL_MASK;
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reg |= (pwm_config->clk + 1) & PM_PWM_CLK_SEL_MASK;
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pwm_config->pwm_ctl[SIZE_CLK] = reg;
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reg = (pwm_config->pre_div << PM_PWM_PREDIVIDE_SHIFT)
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& PM_PWM_PREDIVIDE_MASK;
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reg |= pwm_config->pre_div_exp & PM_PWM_M_MASK;
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pwm_config->pwm_ctl[FREQ_PREDIV_CLK] = reg;
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/* Enable glitch removal by default */
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reg = 1 << PM_PWM_EN_GLITCH_REMOVAL_SHIFT
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& PM_PWM_EN_GLITCH_REMOVAL_MASK;
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pwm_config->pwm_ctl[TYPE_CONFIG] = reg;
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if (pwm_config->pwm_size > 6) {
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pwm_config->pwm_ctl[VALUE_LSB] = pwm_config->pwm_value
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& PM_PWM_VALUE_BIT7_0;
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pwm_config->pwm_ctl[VALUE_MSB] = (pwm_config->pwm_value >> 8)
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& PM_PWM_VALUE_BIT8;
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} else
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pwm_config->pwm_ctl[VALUE_LSB] = pwm_config->pwm_value
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& PM_PWM_VALUE_BIT5_0;
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for (i = 0; i < NUM_PWM_CTL_REGS; i++)
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pm_pwm_reg_write(PM_PWM_CTL_REG_OFFSET + i, pwm_config->pwm_ctl[i]);
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reg = 1 & PM_PWM_SYNC_MASK;
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pm_pwm_reg_write(PM_PWM_SYNC_REG_OFFSET, reg);
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}
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/* usec: 19.2M, n=6, m=0, pre=2 */
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#define PM_PWM_PERIOD_MIN 7
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/* 1K, n=9, m=7, pre=6 */
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#define PM_PWM_PERIOD_MAX (384 * USEC_PER_SEC)
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int pm_pwm_config(unsigned int duty_us, unsigned int period_us)
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{
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struct pm_pwm_config pwm_config;
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if ((duty_us > period_us) || (period_us > PM_PWM_PERIOD_MAX) ||
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(period_us < PM_PWM_PERIOD_MIN)) {
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dprintf(CRITICAL, "Error in duty cycle and period\n");
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return -1;
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}
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pm_pwm_calc_period(period_us, &pwm_config);
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pm_pwm_calc_pwm_value(&pwm_config, period_us, duty_us);
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dprintf(SPEW, "duty/period=%u/%u usec: pwm_value=%d (of %d)\n",
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duty_us, period_us, pwm_config.pwm_value, 1 << pwm_config.pwm_size);
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pm_pwm_config_regs(&pwm_config);
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return 0;
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}
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void pm_pwm_enable(bool enable)
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{
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uint8_t reg;
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reg = enable << PM_PWM_ENABLE_CTL_SHIFT
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& PM_PWM_ENABLE_CTL_MASK;
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pm_pwm_reg_write(PM_PWM_ENABLE_CTL_REG_OFFSET, reg);
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}
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