754 lines
18 KiB
C
754 lines
18 KiB
C
/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation, nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <bits.h>
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#include <debug.h>
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#include <reg.h>
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#include <spmi.h>
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#include <string.h>
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#include <pm8x41_hw.h>
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#include <pm8x41.h>
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#include <rpm-ipc.h>
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#include <regulator.h>
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#include <platform/timer.h>
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/* Enable LN BB CLK */
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static uint32_t ln_bb_clk[][8] = {
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{
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RPM_CLK_BUFFER_A_REQ, LNBB_CLK_ID,
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KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
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RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY, 4, RPM_CLK_BUFFER_PIN_CONTROL_ENABLE_NONE,
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},
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{
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RPM_CLK_BUFFER_A_REQ, LNBB_CLK_ID,
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KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
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RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY, 4, RPM_CLK_BUFFER_PIN_CONTROL_ENABLE_NONE,
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},
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};
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static uint8_t mpp_slave_id;
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void pmi8994_config_mpp_slave_id(uint8_t slave_id)
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{
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mpp_slave_id = slave_id;
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}
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/* SPMI helper functions */
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uint8_t pm8x41_reg_read(uint32_t addr)
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{
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uint8_t val = 0;
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struct pmic_arb_cmd cmd;
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struct pmic_arb_param param;
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cmd.address = PERIPH_ID(addr);
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cmd.offset = REG_OFFSET(addr);
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cmd.slave_id = SLAVE_ID(addr);
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cmd.priority = 0;
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param.buffer = &val;
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param.size = 1;
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pmic_arb_read_cmd(&cmd, ¶m);
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return val;
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}
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uint32_t spmi_reg_read(uint32_t slave_id, uint16_t addr, uint8_t *data, uint8_t priority)
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{
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struct pmic_arb_cmd cmd;
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struct pmic_arb_param param;
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cmd.address = PERIPH_ID(addr);
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cmd.offset = REG_OFFSET(addr);
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cmd.slave_id = slave_id;
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cmd.priority = priority;
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param.buffer = data;
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param.size = 1;
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return pmic_arb_read_cmd(&cmd, ¶m);
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}
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uint32_t spmi_reg_write(uint32_t slave_id, uint16_t addr, uint8_t *data, uint8_t priority)
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{
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struct pmic_arb_cmd cmd;
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struct pmic_arb_param param;
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cmd.address = PERIPH_ID(addr);
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cmd.offset = REG_OFFSET(addr);
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cmd.slave_id = slave_id;
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cmd.priority = priority;
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param.buffer = data;
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param.size = 1;
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return pmic_arb_write_cmd(&cmd, ¶m);
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}
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/* SPMI helper function which takes slave id as the i/p */
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void pm8xxx_reg_write(uint8_t slave_id, uint32_t addr, uint8_t val)
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{
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struct pmic_arb_cmd cmd;
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struct pmic_arb_param param;
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cmd.address = PERIPH_ID(addr);
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cmd.offset = REG_OFFSET(addr);
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cmd.slave_id = slave_id;
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cmd.priority = 0;
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param.buffer = &val;
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param.size = 1;
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pmic_arb_write_cmd(&cmd, ¶m);
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}
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void pm8x41_reg_write(uint32_t addr, uint8_t val)
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{
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struct pmic_arb_cmd cmd;
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struct pmic_arb_param param;
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cmd.address = PERIPH_ID(addr);
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cmd.offset = REG_OFFSET(addr);
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cmd.slave_id = SLAVE_ID(addr);
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cmd.priority = 0;
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param.buffer = &val;
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param.size = 1;
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pmic_arb_write_cmd(&cmd, ¶m);
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}
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/* Exported functions */
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/* Set the boot done flag */
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void pm8x41_set_boot_done()
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{
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uint8_t val;
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val = REG_READ(SMBB_MISC_BOOT_DONE);
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val |= BIT(BOOT_DONE_BIT);
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REG_WRITE(SMBB_MISC_BOOT_DONE, val);
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}
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/* Configure GPIO */
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int pm8x41_gpio_config(uint8_t gpio, struct pm8x41_gpio *config)
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{
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uint8_t val;
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uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio);
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/* Disable the GPIO */
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val = REG_READ(gpio_base + GPIO_EN_CTL);
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val &= ~BIT(PERPH_EN_BIT);
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REG_WRITE(gpio_base + GPIO_EN_CTL, val);
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/* Select the mode */
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val = config->function | (config->direction << 4);
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REG_WRITE(gpio_base + GPIO_MODE_CTL, val);
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/* Set the right pull */
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val = config->pull;
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REG_WRITE(gpio_base + GPIO_DIG_PULL_CTL, val);
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/* Select the VIN */
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val = config->vin_sel;
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REG_WRITE(gpio_base + GPIO_DIG_VIN_CTL, val);
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if (config->direction == PM_GPIO_DIR_OUT) {
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/* Set the right dig out control */
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val = config->out_strength | (config->output_buffer << 4);
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REG_WRITE(gpio_base + GPIO_DIG_OUT_CTL, val);
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}
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/* Enable the GPIO */
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val = REG_READ(gpio_base + GPIO_EN_CTL);
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val |= BIT(PERPH_EN_BIT);
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REG_WRITE(gpio_base + GPIO_EN_CTL, val);
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return 0;
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}
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/* Reads the status of requested gpio */
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int pm8x41_gpio_get(uint8_t gpio, uint8_t *status)
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{
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uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio);
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*status = REG_READ(gpio_base + GPIO_STATUS);
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/* Return the value of the GPIO pin */
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*status &= BIT(GPIO_STATUS_VAL_BIT);
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dprintf(SPEW, "GPIO %d status is %d\n", gpio, *status);
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return 0;
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}
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/* Write the output value of the requested gpio */
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int pm8x41_gpio_set(uint8_t gpio, uint8_t value)
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{
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uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio);
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uint8_t val;
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/* Set the output value of the gpio */
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val = REG_READ(gpio_base + GPIO_MODE_CTL);
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val = (val & ~PM_GPIO_OUTPUT_MASK) | value;
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REG_WRITE(gpio_base + GPIO_MODE_CTL, val);
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return 0;
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}
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/* Configure PM and PMI GPIO with slave id */
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int pm8x41_gpio_config_sid(uint8_t sid, uint8_t gpio, struct pm8x41_gpio *config)
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{
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uint8_t val;
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uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio);
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gpio_base &= 0x0ffff; /* clear sid */
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gpio_base |= (sid << 16); /* add sid */
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dprintf(SPEW, "%s: gpio=%d base=%x\n", __func__, gpio, gpio_base);
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/* Disable the GPIO */
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val = REG_READ(gpio_base + GPIO_EN_CTL);
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val &= ~BIT(PERPH_EN_BIT);
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REG_WRITE(gpio_base + GPIO_EN_CTL, val);
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/* Select the mode */
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val = config->function | (config->direction << 4);
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REG_WRITE(gpio_base + GPIO_MODE_CTL, val);
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/* Set the right pull */
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val = config->pull;
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REG_WRITE(gpio_base + GPIO_DIG_PULL_CTL, val);
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/* Select the VIN */
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val = config->vin_sel;
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REG_WRITE(gpio_base + GPIO_DIG_VIN_CTL, val);
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if (config->direction == PM_GPIO_DIR_OUT) {
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/* Set the right dig out control */
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val = config->out_strength | (config->output_buffer << 4);
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REG_WRITE(gpio_base + GPIO_DIG_OUT_CTL, val);
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}
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/* Enable the GPIO */
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val = REG_READ(gpio_base + GPIO_EN_CTL);
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val |= BIT(PERPH_EN_BIT);
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REG_WRITE(gpio_base + GPIO_EN_CTL, val);
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return 0;
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}
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/* Reads the status of requested gpio */
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int pm8x41_gpio_get_sid(uint8_t sid, uint8_t gpio, uint8_t *status)
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{
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uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio);
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gpio_base &= 0x0ffff; /* clear sid */
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gpio_base |= (sid << 16); /* add sid */
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*status = REG_READ(gpio_base + GPIO_STATUS);
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/* Return the value of the GPIO pin */
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*status &= BIT(GPIO_STATUS_VAL_BIT);
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dprintf(SPEW, "GPIO %d status is %d\n", gpio, *status);
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return 0;
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}
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/* Write the output value of the requested gpio */
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int pm8x41_gpio_set_sid(uint8_t sid, uint8_t gpio, uint8_t value)
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{
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uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio);
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uint8_t val;
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gpio_base &= 0x0ffff; /* clear sid */
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gpio_base |= (sid << 16); /* add sid */
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dprintf(SPEW, "%s: gpio=%d base=%x\n", __func__, gpio, gpio_base);
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/* Set the output value of the gpio */
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val = REG_READ(gpio_base + GPIO_MODE_CTL);
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val = (val & ~PM_GPIO_OUTPUT_MASK) | value;
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REG_WRITE(gpio_base + GPIO_MODE_CTL, val);
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return 0;
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}
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/* Prepare PON RESIN S2 reset (bite) */
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void pm8x41_resin_s2_reset_enable()
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{
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uint8_t val;
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/* disable s2 reset */
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REG_WRITE(PON_RESIN_N_RESET_S2_CTL, 0x0);
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/* Delay needed for disable to kick in. */
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udelay(300);
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/* configure s1 timer to 0 */
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REG_WRITE(PON_RESIN_N_RESET_S1_TIMER, 0x0);
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/* configure s2 timer to 2s */
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REG_WRITE(PON_RESIN_N_RESET_S2_TIMER, PON_RESIN_N_RESET_S2_TIMER_MAX_VALUE);
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/* configure reset type */
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REG_WRITE(PON_RESIN_N_RESET_S2_CTL, S2_RESET_TYPE_WARM);
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val = REG_READ(PON_RESIN_N_RESET_S2_CTL);
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/* enable s2 reset */
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val |= BIT(S2_RESET_EN_BIT);
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REG_WRITE(PON_RESIN_N_RESET_S2_CTL, val);
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}
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/* Disable PON RESIN S2 reset. (bite)*/
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void pm8x41_resin_s2_reset_disable()
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{
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/* disable s2 reset */
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REG_WRITE(PON_RESIN_N_RESET_S2_CTL, 0x0);
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/* Delay needed for disable to kick in. */
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udelay(300);
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}
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/* Resin irq status for faulty pmic*/
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uint32_t pm8x41_v2_resin_status()
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{
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uint8_t rt_sts = 0;
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/* Enable S2 reset so we can detect the volume down key press */
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pm8x41_resin_s2_reset_enable();
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/* Delay before interrupt triggering.
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* See PON_DEBOUNCE_CTL reg.
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*/
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mdelay(100);
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rt_sts = REG_READ(PON_INT_RT_STS);
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/* Must disable S2 reset otherwise PMIC will reset if key
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* is held longer than S2 timer.
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*/
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pm8x41_resin_s2_reset_disable();
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return (rt_sts & BIT(RESIN_BARK_INT_BIT));
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}
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/* Resin pin status */
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uint32_t pm8x41_resin_status()
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{
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uint8_t rt_sts = 0;
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rt_sts = REG_READ(PON_INT_RT_STS);
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return (rt_sts & BIT(RESIN_ON_INT_BIT));
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}
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/* Return 1 if power key is pressed */
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uint32_t pm8x41_get_pwrkey_is_pressed()
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{
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uint8_t pwr_sts = 0;
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pwr_sts = REG_READ(PON_INT_RT_STS);
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if (pwr_sts & BIT(KPDPWR_ON_INT_BIT))
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return 1;
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else
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return 0;
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}
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void pm8994_reset_configure(uint8_t reset_type)
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{
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/* Slave ID of pm8994 and pmi8994 */
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uint8_t slave_id[] = {0, 2};
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uint8_t i;
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/* Reset sequence
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1. Disable the ps hold for pm8994
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2. set reset type for both pm8994 & pmi8994
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3. Enable ps hold for pm8994 to trigger the reset
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*/
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/* disable PS_HOLD_RESET */
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pm8xxx_reg_write(slave_id[0], PON_PS_HOLD_RESET_CTL2, 0x0);
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pm8xxx_reg_write(slave_id[1], PON_PS_HOLD_RESET_CTL2, 0x0);
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/* Delay needed for disable to kick in. */
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udelay(300);
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/* configure reset type */
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for (i = 0; i < ARRAY_SIZE(slave_id); i++)
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pm8xxx_reg_write(slave_id[i], PON_PS_HOLD_RESET_CTL, reset_type);
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/* enable PS_HOLD_RESET */
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for (i = 0; i < ARRAY_SIZE(slave_id); i++)
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pm8xxx_reg_write(slave_id[i], PON_PS_HOLD_RESET_CTL2, BIT(S2_RESET_EN_BIT));
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}
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void pm8x41_v2_reset_configure(uint8_t reset_type)
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{
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uint8_t val;
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/* disable PS_HOLD_RESET */
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REG_WRITE(PON_PS_HOLD_RESET_CTL, 0x0);
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/* Delay needed for disable to kick in. */
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udelay(300);
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/* configure reset type */
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REG_WRITE(PON_PS_HOLD_RESET_CTL, reset_type);
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val = REG_READ(PON_PS_HOLD_RESET_CTL);
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/* enable PS_HOLD_RESET */
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val |= BIT(S2_RESET_EN_BIT);
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REG_WRITE(PON_PS_HOLD_RESET_CTL, val);
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}
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void pm8x41_reset_configure(uint8_t reset_type)
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{
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/* disable PS_HOLD_RESET */
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REG_WRITE(PON_PS_HOLD_RESET_CTL2, 0x0);
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/* Delay needed for disable to kick in. */
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udelay(300);
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/* configure reset type */
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REG_WRITE(PON_PS_HOLD_RESET_CTL, reset_type);
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/* enable PS_HOLD_RESET */
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REG_WRITE(PON_PS_HOLD_RESET_CTL2, BIT(S2_RESET_EN_BIT));
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}
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/*
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* LDO set voltage, takes ldo name & voltage in UV as input
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*/
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int pm8x41_ldo_set_voltage(struct pm8x41_ldo *ldo, uint32_t voltage)
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{
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uint32_t range = 0;
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uint32_t step = 0;
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uint32_t mult = 0;
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uint32_t val = 0;
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uint32_t vmin = 0;
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if (!ldo)
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{
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dprintf(CRITICAL, "LDO pointer is invalid: %p\n", ldo);
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return 1;
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}
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/* Program Normal power mode */
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val = 0x0;
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val = (1 << LDO_NORMAL_PWR_BIT);
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REG_WRITE((ldo->base + LDO_POWER_MODE), val);
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/*
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* Select range, step & vmin based on input voltage & type of LDO
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* LDO can operate in low, mid, high power mode
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*/
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if (ldo->type == PLDO_TYPE)
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{
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if (voltage < PLDO_UV_MIN)
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{
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range = 2;
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step = PLDO_UV_STEP_LOW;
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vmin = PLDO_UV_VMIN_LOW;
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}
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else if (voltage < PDLO_UV_MID)
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{
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range = 3;
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step = PLDO_UV_STEP_MID;
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vmin = PLDO_UV_VMIN_MID;
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}
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else
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{
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range = 4;
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step = PLDO_UV_STEP_HIGH;
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vmin = PLDO_UV_VMIN_HIGH;
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}
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}
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else
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{
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range = 2;
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step = NLDO_UV_STEP;
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vmin = NLDO_UV_VMIN_LOW;
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}
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mult = (voltage - vmin) / step;
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/* Set Range in voltage ctrl register */
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val = 0x0;
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val = range << LDO_RANGE_SEL_BIT;
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REG_WRITE((ldo->base + LDO_RANGE_CTRL), val);
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/* Set multiplier in voltage ctrl register */
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val = 0x0;
|
|
val = mult << LDO_VSET_SEL_BIT;
|
|
REG_WRITE((ldo->base + LDO_STEP_CTRL), val);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Enable or Disable LDO
|
|
*/
|
|
int pm8x41_ldo_control(struct pm8x41_ldo *ldo, uint8_t enable)
|
|
{
|
|
uint32_t val = 0;
|
|
|
|
if (!ldo)
|
|
{
|
|
dprintf(CRITICAL, "LDO pointer is invalid: %p\n", ldo);
|
|
return 1;
|
|
}
|
|
|
|
/* Enable LDO */
|
|
if (enable)
|
|
val = (1 << LDO_VREG_ENABLE_BIT);
|
|
else
|
|
val = (0 << LDO_VREG_ENABLE_BIT);
|
|
|
|
REG_WRITE((ldo->base + LDO_EN_CTL_REG), val);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* lpg channel register write:
|
|
*/
|
|
void pm8x41_lpg_write(uint8_t chan, uint8_t off, uint8_t val)
|
|
{
|
|
uint32_t lpg_base = LPG_N_PERIPHERAL_BASE(chan);
|
|
|
|
REG_WRITE(lpg_base + off, val);
|
|
}
|
|
|
|
/*
|
|
* pmi lpg channel register write with slave_id:
|
|
*/
|
|
void pm8x41_lpg_write_sid(uint8_t sid, uint8_t chan, uint8_t off, uint8_t val)
|
|
{
|
|
uint32_t lpg_base = LPG_N_PERIPHERAL_BASE(chan);
|
|
|
|
lpg_base &= 0x0ffff; /* clear sid */
|
|
lpg_base |= (sid << 16); /* add sid */
|
|
|
|
dprintf(SPEW, "%s: lpg=%d base=%x\n", __func__, chan, lpg_base);
|
|
|
|
REG_WRITE(lpg_base + off, val);
|
|
}
|
|
|
|
uint8_t pm8x41_get_pmic_rev()
|
|
{
|
|
return REG_READ(REVID_REVISION4);
|
|
}
|
|
|
|
uint8_t pm8x41_get_pon_reason()
|
|
{
|
|
return REG_READ(PON_PON_REASON1);
|
|
}
|
|
|
|
uint8_t pm8950_get_pon_reason()
|
|
{
|
|
uint8_t pon_reason = 0;
|
|
|
|
pon_reason = REG_READ(SMBCHGL_USB_ICL_STS_2|PMI8950_SLAVE_ID);
|
|
/* check usbin/dcin status on pmi and set the corresponding bits for pon */
|
|
pon_reason = (pon_reason & (USBIN_ACTIVE_PWR_SRC|DCIN_ACTIVE_PWR_SRC)) << 3 ;
|
|
pon_reason |= REG_READ(PON_PON_REASON1);
|
|
|
|
return pon_reason;
|
|
}
|
|
|
|
uint8_t pm8x41_get_pon_poff_reason1()
|
|
{
|
|
return REG_READ(PON_POFF_REASON1);
|
|
}
|
|
|
|
uint8_t pm8x41_get_pon_poff_reason2()
|
|
{
|
|
return REG_READ(PON_POFF_REASON2);
|
|
}
|
|
|
|
void pm8x41_enable_mvs(struct pm8x41_mvs *mvs, enum mvs_en_ctl enable)
|
|
{
|
|
ASSERT(mvs);
|
|
|
|
REG_WRITE(mvs->base + MVS_EN_CTL, enable << MVS_EN_CTL_ENABLE_SHIFT);
|
|
}
|
|
|
|
void pm8x41_enable_mpp(struct pm8x41_mpp *mpp, enum mpp_en_ctl enable)
|
|
{
|
|
ASSERT(mpp);
|
|
|
|
REG_WRITE(((mpp->base + MPP_EN_CTL) + (mpp_slave_id << 16)), enable << MPP_EN_CTL_ENABLE_SHIFT);
|
|
}
|
|
|
|
void pm8x41_config_output_mpp(struct pm8x41_mpp *mpp)
|
|
{
|
|
ASSERT(mpp);
|
|
|
|
REG_WRITE(((mpp->base + MPP_DIG_VIN_CTL) + (mpp_slave_id << 16)), mpp->vin);
|
|
|
|
REG_WRITE(((mpp->base + MPP_MODE_CTL) + (mpp_slave_id << 16)), mpp->mode | (MPP_DIGITAL_OUTPUT << MPP_MODE_CTL_MODE_SHIFT));
|
|
}
|
|
|
|
uint8_t pm8x41_get_is_cold_boot()
|
|
{
|
|
if (REG_READ(PON_WARMBOOT_STATUS1) || REG_READ(PON_WARMBOOT_STATUS2)) {
|
|
dprintf(INFO,"%s: Warm boot\n", __func__);
|
|
return 0;
|
|
}
|
|
dprintf(INFO,"%s: cold boot\n", __func__);
|
|
return 1;
|
|
}
|
|
|
|
/* api to control lnbb clock */
|
|
void pm8x41_lnbb_clock_ctrl(uint8_t enable)
|
|
{
|
|
if (enable)
|
|
{
|
|
rpm_clk_enable(&ln_bb_clk[GENERIC_ENABLE][0], 24);
|
|
}
|
|
else
|
|
{
|
|
rpm_clk_enable(&ln_bb_clk[GENERIC_DISABLE][0], 24);
|
|
}
|
|
}
|
|
|
|
/* api to control diff clock */
|
|
void pm8x41_diff_clock_ctrl(uint8_t enable)
|
|
{
|
|
uint8_t reg;
|
|
|
|
reg = REG_READ(DIFF_CLK1_EN_CTL);
|
|
|
|
if (enable)
|
|
{
|
|
reg |= BIT(DIFF_CLK1_EN_BIT);
|
|
}
|
|
else
|
|
{
|
|
reg &= ~BIT(DIFF_CLK1_EN_BIT);
|
|
}
|
|
|
|
REG_WRITE(DIFF_CLK1_EN_CTL, reg);
|
|
}
|
|
|
|
void pm8x41_clear_pmic_watchdog(void)
|
|
{
|
|
pm8x41_reg_write(PMIC_WD_RESET_S2_CTL2, 0x0);
|
|
}
|
|
|
|
/* API to check for borken battery */
|
|
int pm8xxx_is_battery_broken()
|
|
{
|
|
uint8_t trkl_default = 0;
|
|
uint8_t vbat_det_default = 0;
|
|
int batt_is_broken = 0;
|
|
|
|
/* Store original trickle charging current setting */
|
|
trkl_default = pm8x41_reg_read(PM8XXX_IBAT_ATC_A);
|
|
/* Store original VBAT_DET_LO setting */
|
|
vbat_det_default = pm8x41_reg_read(PM8XXX_VBAT_DET);
|
|
|
|
/*Set trickle charge current to 50mA (IBAT_ATC_A = 0x00) */
|
|
pm8x41_reg_write(PM8XXX_IBAT_ATC_A, 0x00);
|
|
/* Set VBAT_DET_LO to 4.3V so that VBAT_DET_HI = 4.52V (VBAT_DET_LO = 0x35) */
|
|
pm8x41_reg_write(PM8XXX_VBAT_DET, VBAT_DET_LO_4_30V);
|
|
/* Unlock SMBBP Secured Register */
|
|
pm8x41_reg_write(PM8XXX_SEC_ACCESS, SEC_ACCESS);
|
|
/* Disable VTRKL_FAULT comp (SMBBP_CHGR_COMP_OVR0 = 0x08) */
|
|
pm8x41_reg_write(PM8XXX_COMP_OVR0, OVR0_DIS_VTRKL_FAULT);
|
|
/* Disable VCP (SMBB_BAT_IF_VCP = 0x00) */
|
|
pm8x41_reg_write(PM8XXX_VCP, 0x00);
|
|
/* Unlock SMBBP Secured Register */
|
|
pm8x41_reg_write(PM8XXX_SEC_ACCESS, SEC_ACCESS);
|
|
/* Force trickle charging (SMBB_CHGR_TRKL_CHG_TEST = 0x01) */
|
|
pm8x41_reg_write(PM8XXX_TRKL_CHG_TEST, CHG_TRICKLE_FORCED_ON);
|
|
/* Wait for vbat to rise */
|
|
mdelay(12);
|
|
|
|
/* Check Above VBAT_DET_HIGH status */
|
|
if (pm8x41_reg_read(PM8XXX_VBAT_IN_TSTS) & VBAT_DET_HI_RT_STS)
|
|
batt_is_broken = 1;
|
|
else
|
|
batt_is_broken = 0;
|
|
|
|
/* Unlock SMBBP Secured Register */
|
|
pm8x41_reg_write(PM8XXX_SEC_ACCESS, SEC_ACCESS);
|
|
|
|
/* Disable force trickle charging */
|
|
pm8x41_reg_write(PM8XXX_TRKL_CHG_TEST, 0x00);
|
|
/* re-enable VCP */
|
|
pm8x41_reg_write(PM8XXX_VCP, VCP_ENABLE);
|
|
/* restore trickle charging default current */
|
|
pm8x41_reg_write(PM8XXX_IBAT_ATC_A, trkl_default);
|
|
/* restore VBAT_DET_LO setting to original value */
|
|
pm8x41_reg_write(PM8XXX_VBAT_DET, vbat_det_default);
|
|
|
|
return batt_is_broken;
|
|
}
|
|
|
|
/* Detect broken battery for pmi 8994*/
|
|
bool pmi8994_is_battery_broken()
|
|
{
|
|
bool batt_is_broken;
|
|
uint8_t fast_charge = 0;
|
|
|
|
/* Disable the input missing ppoller */
|
|
REG_WRITE(PMI8994_CHGR_TRIM_OPTIONS_7_0, REG_READ(PMI8994_CHGR_TRIM_OPTIONS_7_0) & ~INPUT_MISSING_POLLER_EN);
|
|
/* Disable current termination */
|
|
REG_WRITE(PMI8994_CHGR_CFG2, REG_READ(PMI8994_CHGR_CFG2) & ~CURRENT_TERM_EN);
|
|
/* Fast-charge current to 300 mA */
|
|
fast_charge = REG_READ(PMI8994_FCC_CFG);
|
|
REG_WRITE(PMI8994_FCC_CFG, 0x0);
|
|
/* Change the float voltage to 4.50V */
|
|
REG_WRITE(PMI8994_FV_CFG, 0x3F);
|
|
|
|
mdelay(5);
|
|
|
|
if (REG_READ(PMI8994_INT_RT_STS) & BAT_TAPER_MODE_CHARGING_RT_STS)
|
|
batt_is_broken = true;
|
|
else
|
|
batt_is_broken = false;
|
|
|
|
/* Set float voltage back to 4.35V */
|
|
REG_WRITE(PMI8994_FV_CFG, 0x2B);
|
|
/* Enable current termination */
|
|
REG_WRITE(PMI8994_CHGR_CFG2, REG_READ(PMI8994_CHGR_CFG2) | CURRENT_TERM_EN);
|
|
/* Fast-charge current back to default mA */
|
|
REG_WRITE(PMI8994_FCC_CFG, fast_charge);
|
|
/* Re-enable the input missing poller */
|
|
REG_WRITE(PMI8994_CHGR_TRIM_OPTIONS_7_0, REG_READ(PMI8994_CHGR_TRIM_OPTIONS_7_0) | INPUT_MISSING_POLLER_EN);
|
|
|
|
return batt_is_broken;
|
|
}
|