64 lines
2.4 KiB
C
64 lines
2.4 KiB
C
/*
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* * Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PMIC_PWM_H
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#define __PMIC_PWM_H
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#define PM_PWM_SIZE_SEL_MASK 0x04
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#define PM_PWM_SIZE_SEL_SHIFT 2
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#define PM_PWM_CLK_SEL_MASK 0x03
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#define PM_PWM_PREDIVIDE_MASK 0x60
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#define PM_PWM_PREDIVIDE_SHIFT 5
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#define PM_PWM_M_MASK 0x07
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#define PM_PWM_SYNC_MASK 0x01
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#define PM_PWM_ENABLE_CTL_MASK 0x80
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#define PM_PWM_ENABLE_CTL_SHIFT 7
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#define PM_PWM_EN_GLITCH_REMOVAL_MASK 0x20
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#define PM_PWM_EN_GLITCH_REMOVAL_SHIFT 5
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#define PM_PWM_VALUE_BIT7_0 0xFF
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#define PM_PWM_VALUE_BIT8 0x01
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#define PM_PWM_VALUE_BIT5_0 0x3F
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#define PM_PWM_BASE(x) (0x1BC00 + (x))
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#define PM_PWM_CTL_REG_OFFSET 0x41
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#define PM_PWM_SYNC_REG_OFFSET 0x47
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#define PM_PWM_ENABLE_CTL_REG_OFFSET 0x46
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int pm_pwm_config(unsigned int duty_us, unsigned int period_us);
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void pm_pwm_enable(bool enable);
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#endif
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