173 lines
6.9 KiB
C
173 lines
6.9 KiB
C
/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation, nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _PM8x41_HW_H_
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#define _PM8x41_HW_H_
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#include <stdint.h>
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#include <sys/types.h>
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/* SMBB Registers */
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#define SMBB_MISC_BOOT_DONE 0x1642
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/* SMBB bit values */
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#define BOOT_DONE_BIT 7
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#define REVID_REVISION4 0x103
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/* LPG Registers */
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#define LPG_SLAVE_ID 0x10000 /* slave_id == 1 */
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#define LPG_PERIPHERAL_BASE (0x0B100 | LPG_SLAVE_ID)
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/* Peripheral base address for LPG channel */
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#define LPG_N_PERIPHERAL_BASE(x) (LPG_PERIPHERAL_BASE + ((x) - 1) * 0x100)
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/* GPIO Registers */
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#define GPIO_PERIPHERAL_BASE 0xC000
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/* Peripheral base address for GPIO_X */
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#define GPIO_N_PERIPHERAL_BASE(x) (GPIO_PERIPHERAL_BASE + ((x) - 1) * 0x100)
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/* Register offsets within GPIO */
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#define GPIO_STATUS 0x08
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#define GPIO_MODE_CTL 0x40
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#define GPIO_DIG_VIN_CTL 0x41
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#define GPIO_DIG_PULL_CTL 0x42
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#define GPIO_DIG_OUT_CTL 0x45
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#define GPIO_EN_CTL 0x46
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/* GPIO bit values */
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#define PERPH_EN_BIT 7
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#define GPIO_STATUS_VAL_BIT 0
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/* PON Peripheral registers */
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#define PON_PON_REASON1 0x808
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#define PON_WARMBOOT_STATUS1 0x80A
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#define PON_WARMBOOT_STATUS2 0x80B
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#define PON_POFF_REASON1 0x80C
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#define PON_POFF_REASON2 0x80D
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#define PON_INT_RT_STS 0x810
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#define PON_INT_SET_TYPE 0x811
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#define PON_INT_POLARITY_HIGH 0x812
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#define PON_INT_POLARITY_LOW 0x813
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#define PON_INT_LATCHED_CLR 0x814
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#define PON_INT_EN_SET 0x815
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#define PON_INT_LATCHED_STS 0x818
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#define PON_INT_PENDING_STS 0x819
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#define PON_RESIN_N_RESET_S1_TIMER 0x844 /* bits 0:3 : S1_TIMER */
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#define PON_RESIN_N_RESET_S2_TIMER 0x845 /* bits 0:2 : S2_TIMER */
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#define PON_RESIN_N_RESET_S2_CTL 0x846 /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE */
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#define PON_PS_HOLD_RESET_CTL 0x85A /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE */
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#define PON_PS_HOLD_RESET_CTL2 0x85B
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#define PMIC_WD_RESET_S2_CTL2 0x857
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/* PON Peripheral register bit values */
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#define RESIN_ON_INT_BIT 1
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#define KPDPWR_ON_INT_BIT 0
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#define RESIN_BARK_INT_BIT 4
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#define S2_RESET_EN_BIT 7
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#define S2_RESET_TYPE_WARM 0x1
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#define PON_RESIN_N_RESET_S2_TIMER_MAX_VALUE 0x7
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/* USB Peripheral registers */
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#define SMBCHGL_USB_ICL_STS_2 0x1309
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/* PMI8950 slave id */
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#define PMI8950_SLAVE_ID 0x20000
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/* USB Peripheral register bits */
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#define USBIN_ACTIVE_PWR_SRC BIT(0)
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#define DCIN_ACTIVE_PWR_SRC BIT(1)
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/* MPP registers */
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#define MPP_DIG_VIN_CTL 0x41
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#define MPP_MODE_CTL 0x40
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#define MPP_EN_CTL 0x46
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#define MPP_MODE_CTL_MODE_SHIFT 4
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#define MPP_EN_CTL_ENABLE_SHIFT 7
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/* MVS registers */
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#define MVS_EN_CTL 0x46
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#define MVS_EN_CTL_ENABLE_SHIFT 7
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void pm8x41_reg_write(uint32_t addr, uint8_t val);
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uint8_t pm8x41_reg_read(uint32_t addr);
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/* SPMI Macros */
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#define REG_READ(_a) pm8x41_reg_read(_a)
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#define REG_WRITE(_a, _v) pm8x41_reg_write(_a, _v)
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#define REG_OFFSET(_addr) ((_addr) & 0xFF)
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#define PERIPH_ID(_addr) (((_addr) & 0xFF00) >> 8)
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#define SLAVE_ID(_addr) ((_addr) >> 16)
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#define LDO_RANGE_CTRL 0x40
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#define LDO_STEP_CTRL 0x41
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#define LDO_POWER_MODE 0x45
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#define LDO_EN_CTL_REG 0x46
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/* USB3 phy clock */
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#define DIFF_CLK1_EN_CTL 0x5746
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#define DIFF_CLK1_EN_BIT 7
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#define LNBB_CLK_EN_CTL 0x5246
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#define LNBB_CLK_EN_BIT 7
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/* SMBB registers */
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#define PM8XXX_IBAT_ATC_A 0x1054
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#define PM8XXX_VBAT_DET 0x105D
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#define PM8XXX_SEC_ACCESS 0x10D0
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#define PM8XXX_COMP_OVR0 0x10ED
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#define PM8XXX_VCP 0x1247
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#define PM8XXX_TRKL_CHG_TEST 0x10E2
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#define PM8XXX_VBAT_IN_TSTS 0x1010
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/* Macros for broken battery */
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#define VBAT_DET_LO_4_30V 0x35
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#define SEC_ACCESS 0xa5
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#define OVR0_DIS_VTRKL_FAULT 0x08
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#define CHG_TRICKLE_FORCED_ON 0x01
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#define VBAT_DET_HI_RT_STS 0x02
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#define VCP_ENABLE 0x01
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#define PMI8994_CHGR_CFG2 0x210FC
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#define CURRENT_TERM_EN BIT(3)
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#define PMI8994_FCC_CFG 0x210F2
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#define PMI8994_FV_CFG 0x210F4
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#define PMI8994_INT_RT_STS 0x21010
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#define BAT_TAPER_MODE_CHARGING_RT_STS BIT(6)
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#define PMI8994_CHGR_TRIM_OPTIONS_7_0 0x216F6
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#define INPUT_MISSING_POLLER_EN BIT(3)
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int pm8xxx_is_battery_broken(void);
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bool pmi8994_battery_broken(void);
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#endif
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