245 lines
7.4 KiB
C
245 lines
7.4 KiB
C
/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation, nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _PM8x41_H_
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#define _PM8x41_H_
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#include <sys/types.h>
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#define PM_GPIO_DIR_OUT 0x01
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#define PM_GPIO_DIR_IN 0x00
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#define PM_GPIO_DIR_BOTH 0x02
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#define PM_GPIO_PULL_UP_30 0
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#define PM_GPIO_PULL_UP_1_5 1
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#define PM_GPIO_PULL_UP_31_5 2
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/* 1.5uA + 30uA boost */
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#define PM_GPIO_PULL_UP_1_5_30 3
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#define PM_GPIO_PULLDOWN_10 4
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#define PM_GPIO_PULL_RESV_2 5
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#define PM_GPIO_OUT_CMOS 0x00
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#define PM_GPIO_OUT_DRAIN_NMOS 0x01
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#define PM_GPIO_OUT_DRAIN_PMOS 0x02
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#define PM_GPIO_OUT_DRIVE_LOW 0x01
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#define PM_GPIO_OUT_DRIVE_MED 0x02
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#define PM_GPIO_OUT_DRIVE_HIGH 0x03
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#define PM_GPIO_FUNC_LOW 0x00
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#define PM_GPIO_FUNC_HIGH 0x01
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#define PM_GPIO_FUNC_2 0x06
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#define PM_GPIO_FUNC_1 0x04
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#define PM_GPIO_MODE_MASK 0x70
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#define PM_GPIO_OUTPUT_MASK 0x0F
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#define PON_PSHOLD_WARM_RESET 0x1
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#define PON_PSHOLD_SHUTDOWN 0x4
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#define PON_PSHOLD_HARD_RESET 0x7
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enum PM8X41_VERSIONS
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{
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PM8X41_VERSION_V1 = 0,
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PM8X41_VERSION_V2 = 1,
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};
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/*Target power on reasons*/
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#define HARD_RST 1
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#define DC_CHG 8
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#define USB_CHG 16
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#define PON1 32
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#define CBLPWR_N 64
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#define KPDPWR_N 128
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/*Target power off reasons*/
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#define KPDPWR_AND_RESIN 32
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#define STAGE3 128
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struct pm8x41_gpio {
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int direction;
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int output_buffer;
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int output_value;
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int pull;
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int vin_sel;
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int out_strength;
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int function;
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int inv_int_pol;
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int disable_pin;
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};
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struct pm8x41_ldo {
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uint8_t type;
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uint32_t base;
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};
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/* LDO base addresses. */
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#define PM8x41_LDO2 0x14100
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#define PM8x41_LDO4 0x14300
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#define PM8x41_LDO8 0x14700
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#define PM8x41_LDO12 0x14B00
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#define PM8x41_LDO14 0x14D00
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#define PM8x41_LDO15 0x14E00
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#define PM8x41_LDO19 0x15200
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#define PM8x41_LDO22 0x15500
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/* LDO voltage ranges */
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#define NLDO_UV_MIN 375000
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#define NLDO_UV_MAX 1537500
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#define NLDO_UV_STEP 12500
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#define NLDO_UV_VMIN_LOW 750000
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#define PLDO_UV_VMIN_LOW 750000
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#define PLDO_UV_VMIN_MID 1500000
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#define PLDO_UV_VMIN_HIGH 1750000
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#define PLDO_UV_MIN 1537500
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#define PDLO_UV_MID 3075000
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#define PLDO_UV_MAX 4900000
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#define PLDO_UV_STEP_LOW 12500
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#define PLDO_UV_STEP_MID 25000
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#define PLDO_UV_STEP_HIGH 50000
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#define LDO_RANGE_SEL_BIT 0
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#define LDO_VSET_SEL_BIT 0
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#define LDO_VREG_ENABLE_BIT 7
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#define LDO_NORMAL_PWR_BIT 7
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#define PLDO_TYPE 0
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#define NLDO_TYPE 1
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#define LDO(_base, _type) \
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{ \
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.type = _type, \
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.base = _base, \
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}
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enum mpp_vin_select
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{
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MPP_VIN0,
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MPP_VIN1,
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MPP_VIN2,
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MPP_VIN3,
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};
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enum mpp_mode_en_source_select
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{
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MPP_LOW,
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MPP_HIGH,
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MPP_PAIRED_MPP,
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MPP_NOT_PAIRED_MPP,
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MPP_DTEST1 = 8,
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MPP_NOT_DTEST1,
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MPP_DTEST2,
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MPP_NOT_DTEST2,
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MPP_DTEST3,
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MPP_NOT_DTEST3,
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MPP_DTEST4,
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MPP_NOT_DTEST4,
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};
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enum mpp_en_ctl
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{
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MPP_DISABLE,
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MPP_ENABLE,
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};
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enum mvs_en_ctl
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{
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MVS_DISABLE,
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MVS_ENABLE,
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};
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enum mpp_mode
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{
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MPP_DIGITAL_INPUT,
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MPP_DIGITAL_OUTPUT,
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MPP_DIGITAL_IN_AND_OUT,
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MPP_BIDIRECTIONAL,
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MPP_ANALOG_INPUT,
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MPP_ANALOG_OUTPUT,
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MPP_CURRENT_SINK,
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MPP_RESERVED,
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};
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struct pm8x41_mpp
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{
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uint32_t base;
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enum mpp_vin_select vin;
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enum mpp_mode_en_source_select mode;
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};
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struct pm8x41_mvs
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{
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uint32_t base;
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};
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#define PM8x41_MMP1_BASE 0xA000
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#define PM8x41_MMP2_BASE 0xA100
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#define PM8x41_MMP3_BASE 0xA200
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#define PM8x41_MMP4_BASE 0xA300
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#define PM8x41_MVS1_BASE 0x18400
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void pm8x41_lpg_write(uint8_t chan, uint8_t off, uint8_t val);
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void pm8x41_lpg_write_sid(uint8_t sid, uint8_t chan, uint8_t off, uint8_t val);
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int pm8x41_gpio_get(uint8_t gpio, uint8_t *status);
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int pm8x41_gpio_get_sid(uint8_t sid, uint8_t gpio, uint8_t *status);
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int pm8x41_gpio_set(uint8_t gpio, uint8_t value);
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int pm8x41_gpio_set_sid(uint8_t sid, uint8_t gpio, uint8_t value);
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int pm8x41_gpio_config(uint8_t gpio, struct pm8x41_gpio *config);
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int pm8x41_gpio_config_sid(uint8_t sid, uint8_t gpio, struct pm8x41_gpio *config);
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void pm8x41_set_boot_done();
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uint32_t pm8x41_v2_resin_status();
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uint32_t pm8x41_resin_status();
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void pm8x41_reset_configure(uint8_t);
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void pm8994_reset_configure(uint8_t);
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void pm8x41_v2_reset_configure(uint8_t);
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int pm8x41_ldo_set_voltage(struct pm8x41_ldo *ldo, uint32_t voltage);
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int pm8x41_ldo_control(struct pm8x41_ldo *ldo, uint8_t enable);
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uint8_t pm8x41_get_pmic_rev();
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uint8_t pm8x41_get_pon_reason();
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uint8_t pm8950_get_pon_reason();
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uint8_t pm8x41_get_pon_poff_reason1();
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uint8_t pm8x41_get_pon_poff_reason2();
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uint32_t pm8x41_get_pwrkey_is_pressed();
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void pm8x41_config_output_mpp(struct pm8x41_mpp *mpp);
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void pm8x41_enable_mpp(struct pm8x41_mpp *mpp, enum mpp_en_ctl enable);
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void pm8x41_enable_mvs(struct pm8x41_mvs *mvs, enum mvs_en_ctl enable);
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uint8_t pm8x41_get_is_cold_boot();
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void pm8x41_diff_clock_ctrl(uint8_t enable);
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void pm8x41_clear_pmic_watchdog(void);
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void pm8x41_lnbb_clock_ctrl(uint8_t enable);
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void pmi8994_config_mpp_slave_id(uint8_t slave_id);
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void pm_pwm_enable(bool enable);
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int pm_pwm_config(unsigned int duty_us, unsigned int period_us);
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uint32_t spmi_reg_read(uint32_t slave_id, uint16_t addr, uint8_t *data, uint8_t priority);
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uint32_t spmi_reg_write(uint32_t slave_id, uint16_t addr, uint8_t *data, uint8_t priority);
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#endif
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