* Qualcomm MSM JPEG

Required properties:
- cell-index: jpeg hardware core index
- compatible :
    - "qcom,jpeg"
    - "qcom,jpeg_dma"
- reg : offset and length of the register set of jpeg device and vbif device
    for the jpeg operating in compatible mode.
- reg-names : should specify relevant names to each reg property defined.
- interrupts : should contain the jpeg interrupt.
- interrupt-names : should specify relevant names to each interrupts
  property defined.
- clock-names : names of clocks required for the device.
- clocks : clocks required for the device.
- qcom, clock-rates: rates of the required clocks.
- vdd-supply: phandle to GDSC regulator controlling JPEG core.
- mmagic-vdd-supply: phandle to GDSC regulator controlling mmagic.
- camss-vdd-supply: phandle to GDSC regulator controlling camss.

Optional properties:
- qcom,vbif-reg-settings: relative address offsets and value pairs for VBIF registers.
- qcom,qos-reg-settings: relative address offsets and value pairs for QoS registers.
- qcom,prefetch-reg-settings: relative address offsets and value pairs for
  MMU prefetch registers.

Example:

	qcom,jpeg@a1c000 {
		cell-index = <0>;
		compatible = "qcom,jpeg";
		reg = <0xa1c000 0x4000>,
			<0xa60000 0x3000>;
		reg-names = "jpeg";
		interrupts = <0 316 0>;
		interrupt-names = "jpeg";
                mmagic-vdd-supply = <&gdsc_mmagic_camss>;
                camss-vdd-supply = <&gdsc_camss_top>;
                vdd-supply = <&gdsc_jpeg>;
                qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd";
		clock-names =  "core_clk", "iface_clk", "bus_clk0",
			       "camss_top_ahb_clk", "camss_ahb_clk", "smmu_jpeg_axi_clk",
                               "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk",
                               "mmagic_camss_axi_clk";
		clocks = <&clock_mmss clk_camss_jpeg0_clk>,
			<&clock_mmss clk_camss_jpeg_ahb_clk>,
			<&clock_mmss clk_camss_jpeg_axi_clk>,
			<&clock_mmss clk_camss_top_ahb_clk>,
			<&clock_mmss clk_camss_ahb_clk>,
			<&clock_mmss clk_smmu_jpeg_axi_clk>,
                        <&clock_mmss clk_mmss_mmagic_ahb_clk>,
                        <&clock_gcc  clk_mmssnoc_axi_clk>,
                        <&clock_mmss clk_mmagic_camss_axi_clk>;
		qcom,clock-rates = <320000000 0 0 0 0 0 0 0 0>;
		qcom,vbif-reg-settings = <0x4 0x1>,
			<0xb0 0x00100010>,
			<0xc0 0x10001000>;
		qcom,qos-reg-settings = <0x28 0x00000008>;
		qcom,prefetch-reg-settings = <0x30c 0x1111>,
			<0x318 0x31>,
			<0x324 0x31>,
			<0x330 0x31>,
			<0x33c 0x0>;
		status = "ok";
	};

	qcom,jpeg@a24000 {
		cell-index = <2>;
		compatible = "qcom,jpeg";
		reg = <0xa24000 0x4000>,
			<0xa60000 0x3000>;
		reg-names = "jpeg";
		interrupts = <0 318 0>;
		interrupt-names = "jpeg";
                mmagic-vdd-supply = <&gdsc_mmagic_camss>;
                camss-vdd-supply = <&gdsc_camss_top>;
                vdd-supply = <&gdsc_jpeg>;
                qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd";
		clock-names =  "core_clk", "iface_clk", "bus_clk0",
                               "camss_top_ahb_clk", "camss_ahb_clk", "smmu_jpeg_axi_clk",
                               "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk",
                               "mmagic_camss_axi_clk";
		clocks = <&clock_mmss clk_camss_jpeg2_clk>,
		       <&clock_mmss clk_camss_jpeg_ahb_clk>,
		       <&clock_mmss clk_camss_jpeg_axi_clk>,
		       <&clock_mmss clk_camss_top_ahb_clk>,
		       <&clock_mmss clk_camss_ahb_clk>,
		       <&clock_mmss clk_smmu_jpeg_axi_clk>,
                       <&clock_mmss clk_mmss_mmagic_ahb_clk>,
                       <&clock_gcc  clk_mmssnoc_axi_clk>,
                       <&clock_mmss clk_mmagic_camss_axi_clk>;
		qcom,clock-rates = <266670000 0 0 0 0 0 0 0 0>;
		qcom,vbif-reg-settings = <0x4 0x1>,
			<0xb0 0x00100010>,
			<0xc0 0x10001000>;
		qcom,qos-reg-settings = <0x28 0x00000008>;
		qcom,prefetch-reg-settings = <0x30c 0x1111>,
			<0x318 0x0>,
			<0x324 0x31>,
			<0x330 0x31>,
			<0x33c 0x31>;
		status = "ok";
	};

	qcom,jpeg@aa0000 {
		cell-index = <3>;
		compatible = "qcom,jpeg_dma";
		reg = <0xaa0000 0x4000>,
			<0xa60000 0x3000>;
		reg-names = "jpeg";
		interrupts = <0 304 0>;
		interrupt-names = "jpeg";
                mmagic-vdd-supply = <&gdsc_mmagic_camss>;
                camss-vdd-supply = <&gdsc_camss_top>;
                vdd-supply = <&gdsc_jpeg>;
                qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd";
		clock-names =  "core_clk", "iface_clk", "bus_clk0",
                               "camss_top_ahb_clk", "camss_ahb_clk", "smmu_jpeg_axi_clk",
                               "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk",
                               "mmagic_camss_axi_clk";
		clocks = <&clock_mmss clk_camss_jpeg_dma_clk>,
			<&clock_mmss clk_camss_jpeg_ahb_clk>,
			<&clock_mmss clk_camss_jpeg_axi_clk>,
			<&clock_mmss clk_camss_top_ahb_clk>,
			<&clock_mmss clk_camss_ahb_clk>,
			<&clock_mmss clk_smmu_jpeg_axi_clk>,
                        <&clock_mmss clk_mmss_mmagic_ahb_clk>,
                        <&clock_gcc  clk_mmssnoc_axi_clk>,
                        <&clock_mmss clk_mmagic_camss_axi_clk>;
		qcom,clock-rates = <266670000 0 0 0 0 0 0 0 0>;
		qcom,vbif-reg-settings = <0x4 0x1>,
			<0xb0 0x00100010>,
			<0xc0 0x10001000>;
		qcom,qos-reg-settings = <0x28 0x00000008>;
		qcom,prefetch-reg-settings = <0x18c 0x11>,
			<0x1a0 0x31>,
			<0x1b0 0x31>;
		status = "ok";
	};