* Qualcomm MSM CPP

Required properties:
- cell-index: cpp hardware core index
- compatible :
    - "qcom,cpp"
- reg : offset and length of the register set for the device
    for the cpp operating in compatible mode.
- reg-names : should specify relevant names to each reg property defined.
  - cpp - has CPP MICRO register set.
  - cpp_vbif - has VBIF core register set used by CPP.
  - cpp_hw - has CPP hardware register set.
- interrupts : should contain the cpp interrupt.
- interrupt-names : should specify relevant names to each interrupts
  property defined.
- vdd-supply: phandle to GDSC regulator controlling VFE & CPP core.
- clocks: list of phandles to the clock controller device and coresponding
  clock names.
- clock-names: name of the clocks required for the device used by the consumer.
- qcom,clock-rates: clock rate in Hz.
- qcom,min-clock-rate: minimum clock rate in Hz, to be set to CPP hardware in
  case dynamic clock scaling based on prevalent streams need lower clock rate.
- qcom,cpp-fw-payload-info: Child node for cpp node having infomration on
  cpp firmware payload offsets. This is mandatory node.

Required properties of the child node:
- qcom,stripe-base = Base offset of stripes in cpp payload.
- qcom,plane-base = Base offset of planes in cpp payload.
- qcom,stripe-size = size of each stripe in payload.
- qcom,plane-size = size of each plane in payload.
- qcom,fe-ptr-off = offset from stripe base to fetch engine address
  location in payload.
- qcom,we-ptr-off = offset from stripe base to write engine address
  location in payload.

Optional properties of the child node:
- qcom,ref-fe-ptr-off =  offset from stripe base to reference fetch engine
  address location in payload.
- qcom,ref-we-ptr-off = offset from stripe base to reference write engine
  address location in payload.
- qcom,we-meta-ptr-off = offset from stripe base to metadata address
  location in payload.
- qcom,fe-mmu-pf-ptr-off = offset from plane base to fetch engine mmu prefetch
  address min location in payload.
- qcom,ref-fe-mmu-pf-ptr-off = offset from plane base to reference fetch engine
  mmu prefetch address min location in payload.
- qcom,we-mmu-pf-ptr-off = offset from plane base to write engine mmu prefetch
  address min location in payload.
- qcom,dup-we-mmu-pf-ptr-off = offset from plane base to duplicate write engine
   mmu prefetch address min location in payload.
- qcom,ref-we-mmu-pf-ptr-off =  offset from plane base to reference write engine
   mmu prefetch address min location in payload.
- qcom,set-group-buffer-len = length/size of set group buffer command used for
  hfr.
- qcom,dup-frame-indicator-off =  offset for duplicate frame indicator in a
  batch for frames

Optional properties:
- mmagic-vdd-supply: phandle to GDSC regulator controlling mmagic.
- camss-vdd-supply: phandle to GDSC regulator controlling camss.
- qcom,bus-master: Flag for presence of CPP bus master. It has to be set only for
  platforms that support such feature.
- qcom,vbif-setting: The offset and value for vbif core qos registers.
  The first entry is register offset and second entry is register value.

Example:

	qcom,cpp@fda04000 {
		cell-index = <0>;
		compatible = "qcom,cpp";
		reg = <0xfda04000 0x100>,
			<0xfda80000 0x200>,
			<0xfda18000 0x008>,
			<0xfd8c36D4 0x4>;
		reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp";
		interrupts = <0 49 0>;
		interrupt-names = "cpp";
		mmagic-vdd-supply = <&gdsc_mmagic_camss>;
		camss-vdd-supply = <&gdsc_camss_top>;
		vdd-supply = <&gdsc_cpp>;
		clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
			<&clock_gcc  clk_mmssnoc_axi_clk>,
			<&clock_mmss clk_mmagic_camss_axi_clk>,
			<&clock_mmss clk_camss_top_ahb_clk>,
			<&clock_mmss clk_cpp_clk_src>,
			<&clock_mmss clk_camss_cpp_ahb_clk>,
			<&clock_mmss clk_camss_cpp_axi_clk>,
			<&clock_mmss clk_camss_cpp_clk>,
			<&clock_mmss clk_camss_micro_ahb_clk>,
			<&clock_mmss clk_camss_ahb_clk>;
			<&clock_mmss clk_smmu_cpp_axi_clk>,
			<&clock_mmss clk_camss_cpp_vbif_ahb_clk>,
		clock-names = "mmss_mmagic_ahb_clk", "mmssnoc_axi_clk",
			"mmagic_camss_axi_clk", "camss_top_ahb_clk",
			"cpp_core_clk",	"camss_cpp_ahb_clk",
			"camss_cpp_axi_clk", "camss_cpp_clk",
			"micro_iface_clk", "camss_ahb_clk";
			"smmu_cpp_axi_clk", "cpp_vbif_ahb_clk";
		qcom,clock-rates = <0 0 0 0 465000000 0 0 465000000 0 0 0 0>;
		qcom,min-clock-rate = <320000000>;
		qcom,bus-master = <1>;
		qcom,vbif-qos-setting = <0x20 0x10000000>,
			<0x24 0x10000000>,
			<0x28 0x10000000>,
			<0x2C 0x10000000>;
		qcom,cpp-fw-payload-info {
			qcom,stripe-base = <553>;
			qcom,plane-base = <481>;
			qcom,stripe-size = <61>;
			qcom,plane-size = <24>;
			qcom,fe-ptr-off = <11>;
			qcom,we-ptr-off = <23>;
			qcom,ref-fe-ptr-off = <17>;
			qcom,ref-we-ptr-off = <36>;
			qcom,we-meta-ptr-off = <42>;
			qcom,fe-mmu-pf-ptr-off = <6>;
			qcom,ref-fe-mmu-pf-ptr-off = <9>;
			qcom,we-mmu-pf-ptr-off = <12>;
			qcom,dup-we-mmu-pf-ptr-off = <17>;
			qcom,ref-we-mmu-pf-ptr-off = <22>;
			qcom,set-group-buffer-len = <135>;
			qcom,dup-frame-indicator-off = <70>;

		};
	};