/*
 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

&soc {
	qcom,msm-cam@8c0000 {
		compatible = "qcom,msm-cam";
		reg = <0x8c0000 0x40000>;
		reg-names = "msm-cam";
		status = "ok";
		bus-vectors = "suspend", "svs", "nominal", "turbo";
		qcom,bus-votes = <0 300000000 640000000 640000000>;
	};

	qcom,csiphy@a34000 {
		cell-index = <0>;
		compatible = "qcom,csiphy-v3.5", "qcom,csiphy";
		reg = <0xa34000 0x1000>, <0xA00030 0x4>;
		reg-names = "csiphy", "csiphy_clk_mux";
		interrupts = <0 78 0>;
		interrupt-names = "csiphy";
		clocks = <&clock_mmss clk_camss_top_ahb_clk>,
			<&clock_mmss clk_camss_ispif_ahb_clk>,
			<&clock_mmss clk_csi0phytimer_clk_src>,
			<&clock_mmss clk_camss_csi0phytimer_clk>,
			<&clock_mmss clk_camss_ahb_clk>,
			<&clock_mmss clk_csiphy0_3p_clk_src>,
			<&clock_mmss clk_camss_csiphy0_3p_clk>;
		clock-names = "camss_top_ahb_clk",
			"ispif_ahb_clk", "csiphy_timer_src_clk",
			"csiphy_timer_clk", "camss_ahb_clk",
			"csiphy_3p_clk_src", "csi_phy_3p_clk";
		qcom,clock-rates = <0 0 200000000 0 0 100000000 0>;
	};

	qcom,csiphy@a35000 {
		cell-index = <1>;
		compatible = "qcom,csiphy-v3.5", "qcom,csiphy";
		reg = <0xa35000 0x1000>, <0xA00038 0x4>;
		reg-names = "csiphy", "csiphy_clk_mux";
		interrupts = <0 79 0>;
		interrupt-names = "csiphy";
		clocks = <&clock_mmss clk_camss_top_ahb_clk>,
			<&clock_mmss clk_camss_ispif_ahb_clk>,
			<&clock_mmss clk_csi1phytimer_clk_src>,
			<&clock_mmss clk_camss_csi1phytimer_clk>,
			<&clock_mmss clk_camss_ahb_clk>,
			<&clock_mmss clk_csiphy1_3p_clk_src>,
			<&clock_mmss clk_camss_csiphy1_3p_clk>;
		clock-names = "camss_top_ahb_clk",
			"ispif_ahb_clk", "csiphy_timer_src_clk",
			"csiphy_timer_clk", "camss_ahb_clk",
			"csiphy_3p_clk_src", "csi_phy_3p_clk";
		qcom,clock-rates = <0 0 200000000 0 0 100000000 0>;
	};

	qcom,csiphy@a36000 {
		cell-index = <2>;
		compatible = "qcom,csiphy-v3.5", "qcom,csiphy";
		reg = <0xa36000 0x1000>, <0xA00040 0x4>;
		reg-names = "csiphy", "csiphy_clk_mux";
		interrupts = <0 80 0>;
		interrupt-names = "csiphy";
		clocks = <&clock_mmss clk_camss_top_ahb_clk>,
			<&clock_mmss clk_camss_ispif_ahb_clk>,
			<&clock_mmss clk_csi2phytimer_clk_src>,
			<&clock_mmss clk_camss_csi2phytimer_clk>,
			<&clock_mmss clk_camss_ahb_clk>,
			<&clock_mmss clk_csiphy2_3p_clk_src>,
			<&clock_mmss clk_camss_csiphy2_3p_clk>;
		clock-names = "camss_top_ahb_clk",
			"ispif_ahb_clk", "csiphy_timer_src_clk",
			"csiphy_timer_clk", "camss_ahb_clk",
			"csiphy_3p_clk_src", "csi_phy_3p_clk";
		qcom,clock-rates = <0 0 200000000 0 0 100000000 0>;
	};

	qcom,csid@a30000  {
		cell-index = <0>;
		compatible = "qcom,csid-v3.5", "qcom,csid";
		reg = <0xa30000 0x400>;
		reg-names = "csid";
		interrupts = <0 296 0>;
		interrupt-names = "csid";
		qcom,csi-vdd-voltage = <1250000>;
		qcom,mipi-csi-vdd-supply = <&pm8994_l2>;
		mmagic-supply = <&gdsc_mmagic_camss>;
		gdscr-supply = <&gdsc_camss_top>;
		qcom,cam-vreg-name = "mmagic", "gdscr";
		clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
			<&clock_mmss clk_camss_top_ahb_clk>,
			<&clock_mmss clk_camss_ispif_ahb_clk>,
			<&clock_mmss clk_csi0_clk_src>,
			<&clock_mmss clk_camss_csi0_clk>,
			<&clock_mmss clk_camss_csi0phy_clk>,
			<&clock_mmss clk_camss_csi0_ahb_clk>,
			<&clock_mmss clk_camss_csi0rdi_clk>,
			<&clock_mmss clk_camss_csi0pix_clk>,
			<&clock_mmss clk_camss_ahb_clk>;
		clock-names = "mmagic_camss_ahb_clk", "camss_top_ahb_clk",
			"ispif_ahb_clk", "csi_src_clk", "csi_clk",
			"csi_phy_clk", "csi_ahb_clk", "csi_rdi_clk",
			"csi_pix_clk", "camss_ahb_clk";
		qcom,clock-rates = <0 0 0 200000000 0 0 0 0 0 0>;
		status = "ok";
	};

	qcom,csid@a30400 {
		cell-index = <1>;
		compatible = "qcom,csid-v3.5", "qcom,csid";
		reg = <0xa30400 0x400>;
		reg-names = "csid";
		interrupts = <0 297 0>;
		interrupt-names = "csid";
		qcom,csi-vdd-voltage = <1250000>;
		qcom,mipi-csi-vdd-supply = <&pm8994_l2>;
		mmagic-supply = <&gdsc_mmagic_camss>;
		gdscr-supply = <&gdsc_camss_top>;
		qcom,cam-vreg-name = "mmagic", "gdscr";
		clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
			<&clock_mmss clk_camss_top_ahb_clk>,
			<&clock_mmss clk_camss_ispif_ahb_clk>,
			<&clock_mmss clk_csi1_clk_src>,
			<&clock_mmss clk_camss_csi1_clk>,
			<&clock_mmss clk_camss_csi1phy_clk>,
			<&clock_mmss clk_camss_csi1_ahb_clk>,
			<&clock_mmss clk_camss_csi1rdi_clk>,
			<&clock_mmss clk_camss_csi1pix_clk>,
			<&clock_mmss clk_camss_ahb_clk>;
		clock-names = "mmagic_camss_ahb_clk", "camss_top_ahb_clk",
			"ispif_ahb_clk", "csi_src_clk", "csi_clk",
			"csi_phy_clk", "csi_ahb_clk", "csi_rdi_clk",
			"csi_pix_clk", "camss_ahb_clk";
		qcom,clock-rates = <0 0 0 200000000 0 0 0 0 0 0>;
	};

	qcom,csid@a30800 {
		cell-index = <2>;
		compatible = "qcom,csid-v3.5", "qcom,csid";
		reg = <0xa30800 0x400>;
		reg-names = "csid";
		interrupts = <0 298 0>;
		interrupt-names = "csid";
		qcom,csi-vdd-voltage = <1250000>;
		qcom,mipi-csi-vdd-supply = <&pm8994_l2>;
		mmagic-supply = <&gdsc_mmagic_camss>;
		gdscr-supply = <&gdsc_camss_top>;
		qcom,cam-vreg-name = "mmagic", "gdscr";
		clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
			<&clock_mmss clk_camss_top_ahb_clk>,
			<&clock_mmss clk_camss_ispif_ahb_clk>,
			<&clock_mmss clk_csi2_clk_src>,
			<&clock_mmss clk_camss_csi2_clk>,
			<&clock_mmss clk_camss_csi2phy_clk>,
			<&clock_mmss clk_camss_csi2_ahb_clk>,
			<&clock_mmss clk_camss_csi2rdi_clk>,
			<&clock_mmss clk_camss_csi2pix_clk>,
			<&clock_mmss clk_camss_ahb_clk>;
		clock-names = "mmagic_camss_ahb_clk", "camss_top_ahb_clk",
			"ispif_ahb_clk", "csi_src_clk", "csi_clk",
			"csi_phy_clk", "csi_ahb_clk", "csi_rdi_clk",
			"csi_pix_clk", "camss_ahb_clk";
		qcom,clock-rates = <0 0 0 200000000 0 0 0 0 0 0>;
	};

	qcom,csid@a30c00 {
		cell-index = <3>;
		compatible = "qcom,csid-v3.5", "qcom,csid";
		reg = <0xa30c00 0x400>;
		reg-names = "csid";
		interrupts = <0 299 0>;
		interrupt-names = "csid";
		qcom,csi-vdd-voltage = <1250000>;
		qcom,mipi-csi-vdd-supply = <&pm8994_l2>;
		mmagic-supply = <&gdsc_mmagic_camss>;
		gdscr-supply = <&gdsc_camss_top>;
		qcom,cam-vreg-name = "mmagic", "gdscr";
		clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
			<&clock_mmss clk_camss_top_ahb_clk>,
			<&clock_mmss clk_camss_ispif_ahb_clk>,
			<&clock_mmss clk_csi3_clk_src>,
			<&clock_mmss clk_camss_csi3_clk>,
			<&clock_mmss clk_camss_csi3phy_clk>,
			<&clock_mmss clk_camss_csi3_ahb_clk>,
			<&clock_mmss clk_camss_csi3rdi_clk>,
			<&clock_mmss clk_camss_csi3pix_clk>,
			<&clock_mmss clk_camss_ahb_clk>;
		clock-names = "mmagic_camss_ahb_clk", "camss_top_ahb_clk",
			"ispif_ahb_clk", "csi_src_clk", "csi_clk",
			"csi_phy_clk", "csi_ahb_clk", "csi_rdi_clk",
			"csi_pix_clk", "camss_ahb_clk";
		qcom,clock-rates = <0 0 0 200000000 0 0 0 0 0 0>;
	};

	qcom,ispif@a31000 {
		cell-index = <0>;
		compatible = "qcom,ispif-v3.0", "qcom,ispif";
		reg = <0xa31000 0xc00>,
			<0xa00020 0x4>;
		reg-names = "ispif", "csi_clk_mux";
		interrupts = <0 309 0>;
		interrupt-names = "ispif";
		qcom,num-isps = <0x2>;
		camss-vdd-supply = <&gdsc_camss_top>;
		mmagic-vdd-supply = <&gdsc_mmagic_camss>;
		vfe0-vdd-supply = <&gdsc_vfe0>;
		vfe1-vdd-supply = <&gdsc_vfe1>;
		qcom,vdd-names = "camss-vdd", "mmagic-vdd", "vfe0-vdd",
				"vfe1-vdd";
		clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
			<&clock_mmss clk_camss_top_ahb_clk>,
			<&clock_mmss clk_camss_ahb_clk>,
			<&clock_mmss clk_camss_ispif_ahb_clk>,
			<&clock_mmss clk_csi0_clk_src>,
			<&clock_mmss clk_camss_csi0_clk>,
			<&clock_mmss clk_camss_csi0rdi_clk>,
			<&clock_mmss clk_camss_csi0pix_clk>,
			<&clock_mmss clk_csi1_clk_src>,
			<&clock_mmss clk_camss_csi1_clk>,
			<&clock_mmss clk_camss_csi1rdi_clk>,
			<&clock_mmss clk_camss_csi1pix_clk>,
			<&clock_mmss clk_csi2_clk_src>,
			<&clock_mmss clk_camss_csi2_clk>,
			<&clock_mmss clk_camss_csi2rdi_clk>,
			<&clock_mmss clk_camss_csi2pix_clk>,
			<&clock_mmss clk_csi3_clk_src>,
			<&clock_mmss clk_camss_csi3_clk>,
			<&clock_mmss clk_camss_csi3rdi_clk>,
			<&clock_mmss clk_camss_csi3pix_clk>,
			<&clock_mmss clk_vfe0_clk_src>,
			<&clock_mmss clk_camss_vfe0_clk>,
			<&clock_mmss clk_camss_csi_vfe0_clk>,
			<&clock_mmss clk_vfe1_clk_src>,
			<&clock_mmss clk_camss_vfe1_clk>,
			<&clock_mmss clk_camss_csi_vfe1_clk>;
		clock-names = "mmagic_camss_ahb_clk",
			"camss_top_ahb_clk",
			"camss_ahb_clk", "ispif_ahb_clk",
			"csi0_src_clk", "csi0_clk",
			"csi0_pix_clk", "csi0_rdi_clk",
			"csi1_src_clk", "csi1_clk",
			"csi1_pix_clk", "csi1_rdi_clk",
			"csi2_src_clk", "csi2_clk",
			"csi2_pix_clk", "csi2_rdi_clk",
			"csi3_src_clk", "csi3_clk",
			"csi3_pix_clk", "csi3_rdi_clk",
			"vfe0_clk_src", "camss_vfe_vfe0_clk", "camss_csi_vfe0_clk",
			"vfe1_clk_src", "camss_vfe_vfe1_clk", "camss_csi_vfe1_clk";
		qcom,clock-rates = <0 0 0 0
			200000000 0 0 0
			200000000 0 0 0
			200000000 0 0 0
			200000000 0 0 0
			0 0 0
			0 0 0>;
		qcom,clock-control = "NO_SET_RATE", "NO_SET_RATE",
			"NO_SET_RATE", "NO_SET_RATE",
			"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
			"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
			"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
			"SET_RATE", "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
			"INIT_RATE", "NO_SET_RATE", "NO_SET_RATE",
			"INIT_RATE", "NO_SET_RATE", "NO_SET_RATE";
		status = "ok";
	};

	vfe0: qcom,vfe0@a10000 {
		cell-index = <0>;
		compatible = "qcom,vfe47";
		reg = <0xa10000 0x4000>,
			<0xa40000 0x3000>;
		reg-names = "vfe", "vfe_vbif";
		interrupts = <0 314 0>;
		interrupt-names = "vfe";
		vdd-supply = <&gdsc_vfe0>;
		mmagic-vdd-supply = <&gdsc_mmagic_camss>;
		camss-vdd-supply = <&gdsc_camss_top>;
		clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
			<&clock_mmss clk_mmagic_camss_axi_clk>,
			<&clock_mmss clk_camss_top_ahb_clk>,
			<&clock_mmss clk_camss_ahb_clk>,
			<&clock_mmss clk_vfe0_clk_src>,
			<&clock_mmss clk_camss_vfe0_clk>,
			<&clock_mmss clk_camss_csi_vfe0_clk>,
			<&clock_mmss clk_camss_vfe_ahb_clk>,
			<&clock_mmss clk_camss_vfe0_ahb_clk>,
			<&clock_mmss clk_camss_vfe_axi_clk>,
			<&clock_mmss clk_camss_vfe0_stream_clk>,
			<&clock_mmss clk_smmu_vfe_axi_clk>;
		clock-names = "mmagic_ahb_clk",
			"camss_axi_clk",
			"camss_top_ahb_clk" , "camss_ahb_clk",
			"vfe_clk_src", "camss_vfe_clk",
			"camss_csi_vfe_clk",
			"vfe_vbif_ahb_clk", "vfe_ahb_clk",
			"bus_clk", "vfe_stream_clk", "smmu_vfe_axi_clk";
		qcom,clock-rates = <0 0 0 0 320000000 0 0 0 0 0 0 0>;
		status = "ok";
		qos-entries = <8>;
		qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418
			0x41c 0x420>;
		qos-settings = <0xaaa9aaa9
			0xaaa9aaa9
			0xaaa9aaa9
			0xaaa9aaa9
			0xaaa9aaa9
			0xaaa9aaa9
			0xaaa9aaa9
			0x0001aaa9>;
		vbif-entries = <1>;
		vbif-regs = <0x124>;
		vbif-settings = <0x3>;
		ds-entries = <17>;
		ds-regs = <0x424 0x428 0x42c 0x430 0x434
			0x438 0x43c 0x440 0x444 0x448 0x44c
			0x450 0x454 0x458 0x45c 0x460 0x464>;
		ds-settings = <0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0x40000103>;
		max-clk-svs = <300000000>;
		max-clk-nominal = <465000000>;
		max-clk-turbo = <600000000>;
	};

	vfe1: qcom,vfe1@a14000 {
		cell-index = <1>;
		compatible = "qcom,vfe47";
		reg = <0xa14000 0x4000>,
			<0xa40000 0x3000>;
		reg-names = "vfe", "vfe_vbif";
		interrupts = <0 315 0>;
		interrupt-names = "vfe";
		vdd-supply = <&gdsc_vfe1>;
		mmagic-vdd-supply = <&gdsc_mmagic_camss>;
		camss-vdd-supply = <&gdsc_camss_top>;
		clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
			<&clock_mmss clk_mmagic_camss_axi_clk>,
			<&clock_mmss clk_camss_top_ahb_clk>,
			<&clock_mmss clk_camss_ahb_clk>,
			<&clock_mmss clk_vfe1_clk_src>,
			<&clock_mmss clk_camss_vfe1_clk>,
			<&clock_mmss clk_camss_csi_vfe1_clk>,
			<&clock_mmss clk_camss_vfe_ahb_clk>,
			<&clock_mmss clk_camss_vfe1_ahb_clk>,
			<&clock_mmss clk_camss_vfe_axi_clk>,
			<&clock_mmss clk_camss_vfe1_stream_clk>,
			<&clock_mmss clk_smmu_vfe_axi_clk>;
		clock-names = "mmagic_ahb_clk",
			"camss_axi_clk",
			"camss_top_ahb_clk" , "camss_ahb_clk",
			"vfe_clk_src", "camss_vfe_clk",
			"camss_csi_vfe_clk",
			"vfe_vbif_ahb_clk", "vfe_ahb_clk",
			"bus_clk", "vfe_stream_clk", "smmu_vfe_axi_clk";
		qcom,clock-rates = <0 0 0 0 320000000 0 0 0 0 0 0 0>;
		status = "ok";
		qos-entries = <8>;
		qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418
			0x41c 0x420>;
		qos-settings = <0xaaa9aaa9
			0xaaa9aaa9
			0xaaa9aaa9
			0xaaa9aaa9
			0xaaa9aaa9
			0xaaa9aaa9
			0xaaa9aaa9
			0x0001aaa9>;
		vbif-entries = <1>;
		vbif-regs = <0x124>;
		vbif-settings = <0x3>;
		ds-entries = <17>;
		ds-regs = <0x424 0x428 0x42c 0x430 0x434
			0x438 0x43c 0x440 0x444 0x448 0x44c
			0x450 0x454 0x458 0x45c 0x460 0x464>;
		ds-settings = <0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0xcccc0011
			0x40000103>;
		max-clk-svs = <300000000>;
		max-clk-nominal = <465000000>;
		max-clk-turbo = <600000000>;
	};

	qcom,vfe {
		compatible = "qcom,vfe";
		num_child = <2>;
	};

	qcom,cam_smmu {
		compatible = "qcom,msm-cam-smmu";

		msm_cam_smmu_cb1 {
			compatible = "qcom,msm-cam-smmu-cb";
			iommus = <&vfe_smmu 0>,
					<&vfe_smmu 1>,
					<&vfe_smmu 2>,
					<&vfe_smmu 3>;
			label = "vfe";
			qcom,scratch-buf-support;
		};

		msm_cam_smmu_cb3 {
			compatible = "qcom,msm-cam-smmu-cb";
			iommus = <&cpp_fd_smmu 0>;
			label = "cpp";
		};

		msm_cam_smmu_cb4 {
			compatible = "qcom,msm-cam-smmu-cb";
			iommus = <&cpp_fd_smmu 1>;
			label = "camera_fd";
		};

		msm_cam_smmu_cb5 {
			compatible = "qcom,msm-cam-smmu-cb";
			iommus = <&jpeg_smmu 0>;
			label = "jpeg_enc0";
		};

		msm_cam_smmu_cb6 {
			compatible = "qcom,msm-cam-smmu-cb";
			iommus = <&jpeg_smmu 1>;
			label = "jpeg_dma";
		};

		msm_cam_smmu_cb7 {
			compatible = "qcom,msm-cam-smmu-cb";
			iommus = <&jpeg_smmu 2>;
			label = "jpeg_dec";
		};
	};

	qcom,jpeg@a1c000 {
		cell-index = <0>;
		compatible = "qcom,jpeg";
		reg = <0xa1c000 0x4000>,
			<0xa60000 0x3000>;
		reg-names = "jpeg";
		interrupts = <0 316 0>;
		interrupt-names = "jpeg";
		mmagic-vdd-supply = <&gdsc_mmagic_camss>;
		camss-vdd-supply = <&gdsc_camss_top>;
		vdd-supply = <&gdsc_jpeg>;
		qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd";
		clock-names = "mmss_mmagic_ahb_clk",
			      "core_clk", "iface_clk", "bus_clk0",
			      "camss_top_ahb_clk", "camss_ahb_clk",
			      "smmu_jpeg_axi_clk", "mmagic_camss_axi_clk";
		clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
			<&clock_mmss clk_camss_jpeg0_clk>,
			<&clock_mmss clk_camss_jpeg_ahb_clk>,
			<&clock_mmss clk_camss_jpeg_axi_clk>,
			<&clock_mmss clk_camss_top_ahb_clk>,
			<&clock_mmss clk_camss_ahb_clk>,
			<&clock_mmss clk_smmu_jpeg_axi_clk>,
			<&clock_mmss clk_mmagic_camss_axi_clk>;
		qcom,clock-rates = <0 320000000 0 0 0 0 0 0>;
		qcom,vbif-reg-settings = <0x4 0x1>;
		qcom,prefetch-reg-settings = <0x30c 0x1111>,
			<0x318 0x31>,
			<0x324 0x31>,
			<0x330 0x31>,
			<0x33c 0x0>;
		status = "ok";
	};

	qcom,jpeg@a24000 {
		cell-index = <2>;
		compatible = "qcom,jpeg";
		reg = <0xa24000 0x4000>,
			<0xa60000 0x3000>;
		reg-names = "jpeg";
		interrupts = <0 318 0>;
		interrupt-names = "jpeg";
		mmagic-vdd-supply = <&gdsc_mmagic_camss>;
		camss-vdd-supply = <&gdsc_camss_top>;
		vdd-supply = <&gdsc_jpeg>;
		qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd";
		clock-names =  "mmss_mmagic_ahb_clk",
				"core_clk", "iface_clk", "bus_clk0",
				"camss_top_ahb_clk", "camss_ahb_clk",
				"smmu_jpeg_axi_clk", "mmagic_camss_axi_clk";
		clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
			<&clock_mmss clk_camss_jpeg2_clk>,
			<&clock_mmss clk_camss_jpeg_ahb_clk>,
			<&clock_mmss clk_camss_jpeg_axi_clk>,
			<&clock_mmss clk_camss_top_ahb_clk>,
			<&clock_mmss clk_camss_ahb_clk>,
			<&clock_mmss clk_smmu_jpeg_axi_clk>,
			<&clock_mmss clk_mmagic_camss_axi_clk>;
		qcom,clock-rates = <0 266670000 0 0 0 0 0 0>;
		qcom,vbif-reg-settings = <0x4 0x1>;
		qcom,prefetch-reg-settings = <0x30c 0x1111>,
			<0x318 0x0>,
			<0x324 0x31>,
			<0x330 0x31>,
			<0x33c 0x31>;
		status = "ok";
	};

	qcom,jpeg@aa0000 {
		cell-index = <3>;
		compatible = "qcom,jpeg_dma";
		reg = <0xaa0000 0x4000>,
			<0xa60000 0x3000>;
		reg-names = "jpeg";
		interrupts = <0 304 0>;
		interrupt-names = "jpeg";
		mmagic-vdd-supply = <&gdsc_mmagic_camss>;
		camss-vdd-supply = <&gdsc_camss_top>;
		vdd-supply = <&gdsc_jpeg>;
		qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd";
		clock-names =  "mmss_mmagic_ahb_clk",
				"core_clk", "iface_clk", "bus_clk0",
				"camss_top_ahb_clk", "camss_ahb_clk",
				"smmu_jpeg_axi_clk", "mmagic_camss_axi_clk";
		clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
			<&clock_mmss clk_camss_jpeg_dma_clk>,
			<&clock_mmss clk_camss_jpeg_ahb_clk>,
			<&clock_mmss clk_camss_jpeg_axi_clk>,
			<&clock_mmss clk_camss_top_ahb_clk>,
			<&clock_mmss clk_camss_ahb_clk>,
			<&clock_mmss clk_smmu_jpeg_axi_clk>,
			<&clock_mmss clk_mmagic_camss_axi_clk>;
		qcom,clock-rates = <0 266670000 0 0 0 0 0 0>;
		qcom,vbif-reg-settings = <0x4 0x1>;
		qcom,prefetch-reg-settings = <0x18c 0x11>,
			<0x1a0 0x31>,
			<0x1b0 0x31>;
		status = "ok";
	};

	qcom,irqrouter@a00000 {
		cell-index = <0>;
		compatible = "qcom,irqrouter";
		reg = <0xa00000 0x4000>;
		reg-names = "irqrouter";
	};

	cpp: qcom,cpp@a04000 {
		cell-index = <0>;
		compatible = "qcom,cpp";
		reg = <0xa04000 0x100>,
			<0xa80000 0x3000>,
			<0xa18000 0x3000>,
			<0x8c36D4 0x4>;
		reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp";
		interrupts = <0 294 0>;
		interrupt-names = "cpp";
		mmagic-vdd-supply = <&gdsc_mmagic_camss>;
		camss-vdd-supply = <&gdsc_camss_top>;
		vdd-supply = <&gdsc_cpp>;
		qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd";
		clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
			<&clock_mmss clk_mmagic_camss_axi_clk>,
			<&clock_mmss clk_camss_top_ahb_clk>,
			<&clock_mmss clk_cpp_clk_src>,
			<&clock_mmss clk_camss_cpp_ahb_clk>,
			<&clock_mmss clk_camss_cpp_axi_clk>,
			<&clock_mmss clk_camss_cpp_clk>,
			<&clock_mmss clk_camss_micro_ahb_clk>,
			<&clock_mmss clk_camss_ahb_clk>,
			<&clock_mmss clk_smmu_cpp_axi_clk>,
			<&clock_mmss clk_camss_cpp_vbif_ahb_clk>;
		clock-names = "mmss_mmagic_ahb_clk",
			"mmagic_camss_axi_clk", "camss_top_ahb_clk",
			"cpp_core_clk",	"camss_cpp_ahb_clk",
			"camss_cpp_axi_clk", "camss_cpp_clk",
			"micro_iface_clk", "camss_ahb_clk",
			"smmu_cpp_axi_clk", "cpp_vbif_ahb_clk";
		qcom,clock-rates = <0 0 0 465000000 0 0 465000000 0 0 0 0>;
		qcom,min-clock-rate = <200000000>;
		qcom,bus-master = <1>;
		qcom,vbif-qos-setting = <0x20 0x10000000>,
			<0x24 0x10000000>,
			<0x28 0x10000000>,
			<0x2C 0x10000000>;
		status = "ok";
		qcom,msm-bus,name = "msm_camera_cpp";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<106 512 0 0>,
			<106 512 0 0>;
		qcom,msm-bus-vector-dyn-vote;
		qcom,cpp-fw-payload-info {
			qcom,stripe-base = <553>;
			qcom,plane-base = <481>;
			qcom,stripe-size = <61>;
			qcom,plane-size = <24>;
			qcom,fe-ptr-off = <11>;
			qcom,we-ptr-off = <23>;
			qcom,ref-fe-ptr-off = <17>;
			qcom,ref-we-ptr-off = <36>;
			qcom,we-meta-ptr-off = <42>;
			qcom,fe-mmu-pf-ptr-off = <6>;
			qcom,ref-fe-mmu-pf-ptr-off = <9>;
			qcom,we-mmu-pf-ptr-off = <12>;
			qcom,dup-we-mmu-pf-ptr-off = <17>;
			qcom,ref-we-mmu-pf-ptr-off = <22>;
			qcom,set-group-buffer-len = <135>;
			qcom,dup-frame-indicator-off = <70>;
		};
	};

	qcom,fd@aa4000 {
		cell-index = <0>;
		compatible = "qcom,face-detection";
		reg = <0xaa4000 0x800>,
			<0xaa5000 0x400>,
			<0xa80000 0x3000>;
		reg-names = "fd_core", "fd_misc", "fd_vbif";
		interrupts = <0 293 0>;
		interrupt-names = "fd";
		mmagic-vdd-supply = <&gdsc_mmagic_camss>;
		camss-vdd-supply = <&gdsc_camss_top>;
		vdd-supply = <&gdsc_fd>;
		qcom,vdd-names = "mmagic-vdd", "camss-vdd", "vdd";
		clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
			<&clock_mmss clk_mmagic_camss_axi_clk>,
			<&clock_mmss clk_camss_top_ahb_clk>,
			<&clock_mmss clk_fd_core_clk_src>,
			<&clock_mmss clk_fd_core_clk>,
			<&clock_mmss clk_fd_core_uar_clk>,
			<&clock_mmss clk_fd_ahb_clk>,
			<&clock_mmss clk_smmu_cpp_axi_clk>,
			<&clock_mmss clk_camss_ahb_clk>,
			<&clock_mmss clk_camss_cpp_axi_clk>,
			<&clock_mmss clk_camss_cpp_vbif_ahb_clk>,
			<&clock_mmss clk_smmu_cpp_ahb_clk>;
		clock-names = "mmss_mmagic_ahb_clk",
			"mmagic_camss_axi_clk", "camss_top_ahb_clk",
			"fd_core_clk_src", "fd_core_clk",
			"fd_core_uar_clk", "fd_ahb_clk",
			"smmu_cpp_axi_clk", "camss_ahb_clk",
			"camss_cpp_axi_clk", "cpp_vbif_ahb_clk",
			"smmu_cpp_ahb_clk";
		clock-rates = <0 0 0 400000000 400000000>,
			<400000000 80000000 0 0 0 0 0>;
		qcom,bus-bandwidth-vectors = <13000000 13000000>,
			<45000000 45000000>,
			<90000000 90000000>;
		qcom,fd-vbif-reg-settings = <0x20 0x10000000 0x30000000>,
			<0x24 0x10000000 0x30000000>,
			<0x28 0x10000000 0x30000000>,
			<0x2c 0x10000000 0x30000000>;
		qcom,fd-misc-reg-settings = <0x20 0x2 0x3>,
			<0x24 0x2 0x3>;
		status = "ok";
	};

	cci: qcom,cci@a0c000 {
		cell-index = <0>;
		compatible = "qcom,cci";
		reg = <0xa0c000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "cci";
		interrupts = <0 295 0>;
		interrupt-names = "cci";
		status = "ok";
		mmagic-supply = <&gdsc_mmagic_camss>;
		gdscr-supply = <&gdsc_camss_top>;
		qcom,cam-vreg-name = "mmagic", "gdscr";
		clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
			<&clock_mmss clk_camss_top_ahb_clk>,
			<&clock_mmss clk_cci_clk_src>,
			<&clock_mmss clk_camss_cci_ahb_clk>,
			<&clock_mmss clk_camss_cci_clk>,
			<&clock_mmss clk_camss_ahb_clk>;
		clock-names = "mmagic_camss_ahb_clk", "camss_top_ahb_clk",
                        "cci_src_clk", "cci_ahb_clk", "camss_cci_clk",
			"camss_ahb_clk";
		qcom,clock-rates = <0 0 19200000 0 0 0>,
			<0 0 37500000 0 0 0>;
		pinctrl-names = "cci_default", "cci_suspend";
			pinctrl-0 = <&cci0_active &cci1_active>;
			pinctrl-1 = <&cci0_suspend &cci1_suspend>;
		gpios = <&tlmm 17 0>,
			<&tlmm 18 0>,
			<&tlmm 19 0>,
			<&tlmm 20 0>;
		qcom,gpio-tbl-num = <0 1 2 3>;
		qcom,gpio-tbl-flags = <1 1 1 1>;
		qcom,gpio-tbl-label = "CCI_I2C_DATA0",
				      "CCI_I2C_CLK0",
				      "CCI_I2C_DATA1",
				      "CCI_I2C_CLK1";
		i2c_freq_100Khz: qcom,i2c_standard_mode {
			status = "disabled";
		};
		i2c_freq_400Khz: qcom,i2c_fast_mode {
			status = "disabled";
		};
		i2c_freq_custom: qcom,i2c_custom_mode {
			status = "disabled";
		};
		i2c_freq_1Mhz: qcom,i2c_fast_plus_mode {
			status = "disabled";
		};
	};
};

&i2c_freq_100Khz {
	qcom,hw-thigh = <78>;
	qcom,hw-tlow = <114>;
	qcom,hw-tsu-sto = <28>;
	qcom,hw-tsu-sta = <28>;
	qcom,hw-thd-dat = <10>;
	qcom,hw-thd-sta = <77>;
	qcom,hw-tbuf = <118>;
	qcom,hw-scl-stretch-en = <0>;
	qcom,hw-trdhld = <6>;
	qcom,hw-tsp = <1>;
	status = "ok";
};

&i2c_freq_400Khz {
	qcom,hw-thigh = <20>;
	qcom,hw-tlow = <28>;
	qcom,hw-tsu-sto = <21>;
	qcom,hw-tsu-sta = <21>;
	qcom,hw-thd-dat = <13>;
	qcom,hw-thd-sta = <18>;
	qcom,hw-tbuf = <32>;
	qcom,hw-scl-stretch-en = <0>;
	qcom,hw-trdhld = <6>;
	qcom,hw-tsp = <3>;
	status = "ok";
};

&i2c_freq_custom {
	qcom,hw-thigh = <15>;
	qcom,hw-tlow = <28>;
	qcom,hw-tsu-sto = <21>;
	qcom,hw-tsu-sta = <21>;
	qcom,hw-thd-dat = <13>;
	qcom,hw-thd-sta = <18>;
	qcom,hw-tbuf = <25>;
	qcom,hw-scl-stretch-en = <1>;
	qcom,hw-trdhld = <6>;
	qcom,hw-tsp = <3>;
	status = "ok";
};

&i2c_freq_1Mhz {
	qcom,hw-thigh = <16>;
	qcom,hw-tlow = <22>;
	qcom,hw-tsu-sto = <17>;
	qcom,hw-tsu-sta = <18>;
	qcom,hw-thd-dat = <16>;
	qcom,hw-thd-sta = <15>;
	qcom,hw-tbuf = <19>;
	qcom,hw-scl-stretch-en = <1>;
	qcom,hw-trdhld = <3>;
	qcom,hw-tsp = <3>;
	qcom,cci-clk-src = <37500000>;
	status = "ok";
};