/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
 *
 * This program is Mree software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/msm/msm-bus-ids.h>

&soc {
	ad_hoc_bus: ad-hoc-bus {
		/* Version = 16 */
		compatible = "qcom,msm-bus-device";
		reg = <0x520000 0x40000>,
			<0x400000 0x62000>,
			<0x5C0000 0x3000>,
			<0x500000 0x1000>,
			<0x5A0000 0x40000>,
			<0x5A0000 0x40000>,
			<0x540000 0x9000>,
			<0x560000 0x7000>,
			<0x580000 0xA000>;
		reg-names = "snoc-base", "bimc-base", "pnoc-base", "cnoc-base",
			"mmnoc-base", "mmnoc-ahb-base", "a0noc-base",
			"a1noc-base", "a2noc-base";

		/*Buses*/
		fab_a0noc: fab-a0noc {
			cell-id = <MSM_BUS_FAB_A0_NOC>;
			label = "fab-a0noc";
			qcom,fab-dev;
			qcom,base-name = "a0noc-base";
			qcom,bus-type = <1>;
			qcom,qos-off = <4096>;
			qcom,base-offset = <12288>;
			qcom,enable-only-clk;
			clock-names = "bus_clk", "bus_a_clk";
			clocks = <&clock_gcc clk_gcc_aggre0_snoc_axi_clk>,
			     <&clock_gcc clk_gcc_aggre0_snoc_axi_clk>;
			bus-gdsc-supply = <&gdsc_aggre0_noc>;
			bus-a-gdsc-supply = <&gdsc_aggre0_noc>;

			coresight-id = <206>;
			coresight-name = "coresight-a0noc";
			coresight-nr-inports = <0>;
			coresight-outports = <0>;
			coresight-child-list = <&funnel_in1>;
			coresight-child-ports = <7>;
			aggre0-snoc-axi-no-rate-supply =<&gdsc_aggre0_noc>;
			qcom,node-qos-clks {
				clock-names = "aggre0-snoc-axi-no-rate",
				"aggre0-cnoc-ahb-no-rate",
				"aggre0-noc-mpu-cfg-no-rate";
				clocks =
				<&clock_gcc clk_gcc_aggre0_snoc_axi_clk>,
				<&clock_gcc clk_gcc_aggre0_cnoc_ahb_clk>,
				<&clock_gcc clk_gcc_aggre0_noc_mpu_cfg_ahb_clk>;
			};
		};

		fab_a1noc: fab-a1noc {
			cell-id = <MSM_BUS_FAB_A1_NOC>;
			label = "fab-a1noc";
			qcom,fab-dev;
			qcom,base-name = "a1noc-base";
			qcom,bus-type = <1>;
			qcom,qos-off = <4096>;
			qcom,base-offset = <8192>;
			clock-names = "bus_clk", "bus_a_clk";
			clocks = <&clock_gcc  clk_aggre1_noc_clk>,
			     <&clock_gcc  clk_aggre1_noc_a_clk>;
			coresight-id = <205>;
			coresight-name = "coresight-a1noc";
			coresight-nr-inports = <0>;
			coresight-outports = <0>;
			coresight-child-list = <&funnel_in0>;
			coresight-child-ports = <6>;
		};

		fab_a2noc: fab-a2noc {
			cell-id = <MSM_BUS_FAB_A2_NOC>;
			label = "fab-a2noc";
			qcom,fab-dev;
			qcom,base-name = "a2noc-base";
			qcom,bus-type = <1>;
			qcom,qos-off = <4096>;
			qcom,base-offset = <12288>;
			clock-names = "bus_clk", "bus_a_clk";
			clocks = <&clock_gcc  clk_aggre2_noc_clk>,
			     <&clock_gcc  clk_aggre2_noc_a_clk>;
			coresight-id = <204>;
			coresight-name = "coresight-a2noc";
			coresight-nr-inports = <0>;
			coresight-outports = <0>;
			coresight-child-list = <&funnel_in1>;
			coresight-child-ports = <5>;
			qcom,node-qos-clks {
				clock-names = "clk-aggre2-noc-clk-no-rate",
				"clk-gcc-ufs-axi-clk",
				"clk-aggre2-ufs-axi-clk-no-rate";
				clocks = <&clock_gcc clk_aggre2_noc_clk>,
				<&clock_gcc clk_gcc_ufs_axi_clk>,
				<&clock_gcc clk_gcc_aggre2_ufs_axi_clk>;
			};
		};

		fab_bimc: fab-bimc {
			cell-id = <MSM_BUS_FAB_BIMC>;
			label = "fab-bimc";
			qcom,fab-dev;
			qcom,base-name = "bimc-base";
			qcom,base-offset = <0x8000>;
			qcom,qos-off = <0x4000>;
			qcom,util-fact = <154>;
			qcom,bus-type = <2>;
			clock-names = "bus_clk", "bus_a_clk";
			clocks = <&clock_gcc  clk_bimc_msmbus_clk>,
			     <&clock_gcc  clk_bimc_msmbus_a_clk>;
			coresight-id = <203>;
			coresight-name = "coresight-bimc";
			coresight-nr-inports = <0>;
			coresight-outports = <0>;
			coresight-child-list = <&funnel_in1>;
			coresight-child-ports = <4>;
		};

		fab_cnoc: fab-cnoc {
			cell-id = <MSM_BUS_FAB_CONFIG_NOC>;
			label = "fab-cnoc";
			qcom,fab-dev;
			qcom,base-name = "cnoc-base";
			qcom,bypass-qos-prg;
			qcom,bus-type = <1>;
			clock-names = "bus_clk", "bus_a_clk";
			clocks = <&clock_gcc clk_cnoc_msmbus_clk>,
			     <&clock_gcc clk_cnoc_msmbus_a_clk>;
		};

		fab_mnoc: fab-mnoc {
			cell-id = <MSM_BUS_FAB_MMSS_NOC>;
			label = "fab-mnoc";
			qcom,fab-dev;
			qcom,base-name = "mmnoc-base";
			qcom,qos-off = <4096>;
			qcom,base-offset = <16384>;
			qcom,bus-type = <1>;
			qcom,util-fact = <154>;
			clock-names = "bus_clk", "bus_a_clk";
			clocks = <&clock_gcc clk_mmssnoc_axi_clk>,
				 <&clock_gcc clk_mmssnoc_axi_a_clk>;
			coresight-id = <202>;
			coresight-name = "coresight-mnoc";
			coresight-nr-inports = <0>;
			coresight-outports = <0>;
			coresight-child-list = <&funnel_in1>;
			coresight-child-ports = <0>;
			mmagic-ahb-no-rate-supply = <&gdsc_mmagic_bimc>;
			mmagic-mdss-axi-no-rate-supply =
						<&gdsc_mmagic_mdss>;
			mmagic-camss-axi-no-rate-supply =
						<&gdsc_mmagic_camss>;
			mmagic-video-axi-no-rate-supply =
						<&gdsc_mmagic_video>;
			qcom,node-qos-clks {
				clock-names = "mmagic-ahb-no-rate",
				"mmagic-cfg-ahb-no-rate",
				"mmagic-mdss-axi-no-rate",
				"mmagic-mdss-cfg-noc-ahb-no-rate",
				"mmagic-camss-axi-no-rate",
				"mmagic-camss-cfg-noc-ahb-no-rate",
				"mmagic-video-axi-no-rate",
				"mmagic-video-cfg-noc-ahb-no-rate";
				clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>,
			     <&clock_mmss clk_mmss_mmagic_cfg_ahb_clk>,
			     <&clock_mmss clk_mmagic_mdss_axi_clk>,
			     <&clock_mmss clk_mmagic_mdss_noc_cfg_ahb_clk>,
			     <&clock_mmss clk_mmagic_camss_axi_clk>,
			     <&clock_mmss clk_mmagic_camss_noc_cfg_ahb_clk>,
			     <&clock_mmss clk_mmagic_video_axi_clk>,
			     <&clock_mmss clk_mmagic_video_noc_cfg_ahb_clk>;
			};
		};

		fab_mnoc_ahb: fab-mnoc-ahb {
			cell-id = <MSM_BUS_FAB_MMSS_AHB>;
			label = "fab-mnoc-ahb";
			qcom,fab-dev;
			qcom,base-name = "mmnoc-ahb-base";
			qcom,bypass-qos-prg;
			qcom,setrate-only-clk;
			qcom,bus-type = <1>;
			clock-names = "bus_clk", "bus_a_clk";
			clocks = <&clock_mmss clk_ahb_clk_src>,
			     <&clock_mmss clk_ahb_clk_src>;
			bus-gdsc-supply = <&gdsc_mmagic_bimc>;
			bus-a-gdsc-supply = <&gdsc_mmagic_bimc>;
		};

		fab_pnoc: fab-pnoc {
			cell-id = <MSM_BUS_FAB_PERIPH_NOC>;
			label = "fab-pnoc";
			qcom,fab-dev;
			qcom,base-name = "pnoc-base";
			qcom,bypass-qos-prg;
			qcom,bus-type = <1>;
			clock-names = "bus_clk", "bus_a_clk";
			clocks = <&clock_gcc  clk_pnoc_msmbus_clk>,
			     <&clock_gcc  clk_pnoc_msmbus_a_clk>;
			coresight-id = <201>;
			coresight-name = "coresight-pnoc";
			coresight-nr-inports = <0>;
			coresight-outports = <0>;
			coresight-child-list = <&funnel_in1>;
			coresight-child-ports = <2>;
		};

		fab_snoc: fab-snoc {
			cell-id = <MSM_BUS_FAB_SYS_NOC>;
			label = "fab-snoc";
			qcom,fab-dev;
			qcom,base-name = "snoc-base";
			qcom,bus-type = <1>;
			qcom,qos-off = <4096>;
			qcom,base-offset = <16384>;
			clock-names = "bus_clk", "bus_a_clk";
			clocks = <&clock_gcc  clk_snoc_msmbus_clk>,
			     <&clock_gcc  clk_snoc_msmbus_a_clk>;
			coresight-id = <200>;
			coresight-name = "coresight-snoc";
			coresight-nr-inports = <0>;
			coresight-outports = <0>;
			coresight-child-list = <&funnel_in0>;
			coresight-child-ports = <5>;
		};

		/*Masters*/

		mas_pcie_0: mas-pcie-0 {
			cell-id = <MSM_BUS_MASTER_PCIE>;
			label = "mas-pcie-0";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,qport = <0>;
			qcom,qos-mode = "fixed";
			qcom,connections = <&slv_a0noc_snoc>;
			qcom,prio1 = <1>;
			qcom,prio0 = <1>;
			qcom,bus-dev = <&fab_a0noc>;
			qcom,mas-rpm-id = <ICBID_MASTER_PCIE_0>;
		};

		mas_pcie_1: mas-pcie-1 {
			cell-id = <MSM_BUS_MASTER_PCIE_1>;
			label = "mas-pcie-1";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,qport = <1>;
			qcom,qos-mode = "fixed";
			qcom,connections = <&slv_a0noc_snoc>;
			qcom,prio1 = <1>;
			qcom,prio0 = <1>;
			qcom,bus-dev = <&fab_a0noc>;
			qcom,mas-rpm-id = <ICBID_MASTER_PCIE_1>;
		};

		mas_pcie_2: mas-pcie-2 {
			cell-id = <MSM_BUS_MASTER_PCIE_2>;
			label = "mas-pcie-2";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,qport = <2>;
			qcom,qos-mode = "fixed";
			qcom,connections = <&slv_a0noc_snoc>;
			qcom,prio1 = <1>;
			qcom,prio0 = <1>;
			qcom,bus-dev = <&fab_a0noc>;
			qcom,mas-rpm-id = <ICBID_MASTER_PCIE_2>;
		};

		mas_cnoc_a1noc: mas-cnoc-a1noc {
			cell-id = <MSM_BUS_CNOC_A1NOC_MAS>;
			label = "mas-cnoc-a1noc";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,connections = <&slv_a1noc_snoc>;
			qcom,bus-dev = <&fab_a1noc>;
			qcom,mas-rpm-id = <ICBID_MASTER_CNOC_A1NOC>;
		};

		mas_crypto_c0: mas-crypto-c0 {
			cell-id = <MSM_BUS_MASTER_CRYPTO_CORE0>;
			label = "mas-crypto-c0";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,qport = <0>;
			qcom,qos-mode = "fixed";
			qcom,connections = <&slv_a1noc_snoc>;
			qcom,prio1 = <1>;
			qcom,prio0 = <1>;
			qcom,bus-dev = <&fab_a1noc>;
			qcom,mas-rpm-id = <ICBID_MASTER_CRYPTO_CORE0>;
		};

		mas_pnoc_a1noc: mas-pnoc-a1noc {
			cell-id = <MSM_BUS_PNOC_A1NOC_MAS>;
			label = "mas-pnoc-a1noc";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,qport = <1>;
			qcom,qos-mode = "fixed";
			qcom,connections = <&slv_a1noc_snoc>;
			qcom,bus-dev = <&fab_a1noc>;
			qcom,mas-rpm-id = <ICBID_MASTER_PNOC_A1NOC>;
		};

		mas_usb3: mas-usb3 {
			cell-id = <MSM_BUS_MASTER_USB3>;
			label = "mas-usb3";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,qport = <3>;
			qcom,qos-mode = "fixed";
			qcom,connections = <&slv_a2noc_snoc>;
			qcom,prio1 = <1>;
			qcom,prio0 = <1>;
			qcom,bus-dev = <&fab_a2noc>;
			qcom,mas-rpm-id = <ICBID_MASTER_USB3_0>;
		};

		mas_ipa: mas-ipa {
			cell-id = <MSM_BUS_MASTER_IPA>;
			label = "mas-ipa";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,qos-mode = "fixed";
			qcom,connections = <&slv_a2noc_snoc>;
			qcom,bus-dev = <&fab_a2noc>;
			qcom,mas-rpm-id = <ICBID_MASTER_IPA>;
		};

		mas_ufs: mas-ufs {
			cell-id = <MSM_BUS_MASTER_UFS>;
			label = "mas-ufs";
			qcom,buswidth = <8>;
			qcom,qport = <2>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,qos-mode = "fixed";
			qcom,connections = <&slv_a2noc_snoc>;
			qcom,prio1 = <1>;
			qcom,prio0 = <1>;
			qcom,bus-dev = <&fab_a2noc>;
			qcom,mas-rpm-id = <ICBID_MASTER_UFS>;
		};

		mas_apps_proc: mas-apps-proc {
			cell-id = <MSM_BUS_MASTER_AMPSS_M0>;
			label = "mas-apps-proc";
			qcom,buswidth = <8>;
			qcom,agg-ports = <2>;
			qcom,ap-owned;
			qcom,qport = <0>;
			qcom,qos-mode = "fixed";
			qcom,connections = < &slv_bimc_snoc_1&slv_ebi &slv_bimc_snoc_0>;
			qcom,prio-lvl = <0>;
			qcom,prio-rd = <0>;
			qcom,prio-wr = <0>;
			qcom,bus-dev = <&fab_bimc>;
			qcom,mas-rpm-id = <ICBID_MASTER_APPSS_PROC>;
		};

		mas_oxili: mas-oxili {
			cell-id = <MSM_BUS_MASTER_GRAPHICS_3D>;
			label = "mas-oxili";
			qcom,buswidth = <8>;
			qcom,agg-ports = <2>;
			qcom,ap-owned;
			qcom,qport = <1>;
			qcom,qos-mode = "bypass";
			qcom,connections = < &slv_bimc_snoc_1 &slv_hmss_l3&slv_ebi
				 &slv_bimc_snoc_0>;
			qcom,bus-dev = <&fab_bimc>;
			qcom,mas-rpm-id = <ICBID_MASTER_GFX3D>;
		};

		mas_mnoc_bimc: mas-mnoc-bimc {
			cell-id = <MSM_BUS_MNOC_BIMC_MAS>;
			label = "mas-mnoc-bimc";
			qcom,buswidth = <8>;
			qcom,agg-ports = <2>;
			qcom,ap-owned;
			qcom,qport = <2>;
			qcom,qos-mode = "bypass";
			qcom,connections = < &slv_bimc_snoc_1 &slv_hmss_l3&slv_ebi
				 &slv_bimc_snoc_0>;
			qcom,bus-dev = <&fab_bimc>;
			qcom,mas-rpm-id = <ICBID_MASTER_MNOC_BIMC>;
		};

		mas_snoc_bimc: mas-snoc-bimc {
			cell-id = <MSM_BUS_SNOC_BIMC_MAS>;
			label = "mas-snoc-bimc";
			qcom,buswidth = <8>;
			qcom,agg-ports = <2>;
			qcom,qos-mode = "bypass";
			qcom,connections = < &slv_hmss_l3&slv_ebi>;
			qcom,bus-dev = <&fab_bimc>;
			qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC>;
		};

		mas_snoc_cnoc: mas-snoc-cnoc {
			cell-id = <MSM_BUS_SNOC_CNOC_MAS>;
			label = "mas-snoc-cnoc";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,connections = <&slv_clk_ctl &slv_rbcpr_cx &slv_a2noc_smmu_cfg
				 &slv_a0noc_mpu_cfg &slv_message_ram
				 &slv_cnoc_mnoc_mmss_cfg &slv_pcie_0_cfg
				 &slv_tlmm &slv_mpm
				 &slv_a0noc_smmu_cfg &slv_ebi1_phy_cfg
				 &slv_bimc_cfg &slv_pimem_cfg
				 &slv_rbcpr_mx &slv_prng
				 &slv_pcie20_ahb2phy &slv_a2noc_mpu_cfg
				 &slv_qdss_cfg &slv_a2noc_cfg
				 &slv_a0noc_cfg &slv_ufs_cfg
				 &slv_crypto0_cfg &slv_pcie_1_cfg
				 &slv_snoc_cfg &slv_snoc_mpu_cfg
				 &slv_a1noc_mpu_cfg &slv_a1noc_smmu_cfg
				 &slv_pcie_2_cfg &slv_cnoc_mnoc_cfg
				 &slv_cpr_apu_cfg &slv_pmic_arb
				 &slv_imem_cfg &slv_a1noc_cfg
				 &slv_ssc_cfg &slv_tcsr
				 &slv_lpass_smmu_cfg &slv_dcc_cfg>;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_SNOC_CNOC>;
		};

		mas_qdss_dap: mas-qdss-dap {
			cell-id = <MSM_BUS_MASTER_QDSS_DAP>;
			label = "mas-qdss-dap";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,connections = < &slv_cpr_apu_cfg &slv_rbcpr_cx &slv_a2noc_smmu_cfg
				 &slv_a0noc_mpu_cfg &slv_message_ram
				 &slv_pcie_0_cfg &slv_tlmm
				 &slv_mpm &slv_a0noc_smmu_cfg
				 &slv_ebi1_phy_cfg &slv_bimc_cfg
				 &slv_pimem_cfg &slv_rbcpr_mx
				 &slv_clk_ctl &slv_prng
				 &slv_pcie20_ahb2phy &slv_a2noc_mpu_cfg
				 &slv_qdss_cfg &slv_a2noc_cfg
				 &slv_a0noc_cfg &slv_ufs_cfg
				 &slv_crypto0_cfg&slv_cnoc_a1noc
				 &slv_pcie_1_cfg &slv_snoc_cfg
				 &slv_snoc_mpu_cfg &slv_a1noc_mpu_cfg
				 &slv_a1noc_smmu_cfg &slv_pcie_2_cfg
				 &slv_cnoc_mnoc_cfg &slv_cnoc_mnoc_mmss_cfg
				 &slv_pmic_arb &slv_imem_cfg
				 &slv_a1noc_cfg &slv_ssc_cfg
				 &slv_tcsr &slv_lpass_smmu_cfg
				 &slv_dcc_cfg>;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_QDSS_DAP>;
		};

		mas_cnoc_mnoc_mmss_cfg: mas-cnoc-mnoc-mmss-cfg {
			cell-id = <MSM_BUS_MASTER_CNOC_MNOC_MMSS_CFG>;
			label = "mas-cnoc-mnoc-mmss-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,connections = <&slv_mmagic_cfg &slv_dsa_mpu_cfg &slv_mnoc_clocks_cfg
				 &slv_camera_throttle_cfg &slv_venus_cfg
				 &slv_smmu_vfe_cfg &slv_misc_cfg
				 &slv_smmu_cpp_cfg &slv_oxili_cfg
				 &slv_display_throttle_cfg &slv_venus_throttle_cfg
				 &slv_camera_cfg &slv_display_cfg
				 &slv_cpr_cfg &slv_smmu_rot_cfg
				 &slv_dsa_cfg &slv_smmu_venus_cfg
				 &slv_vmem_cfg &slv_smmu_jpeg_cfg
				 &slv_smmu_mdp_cfg &slv_mnoc_mpu_cfg>;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,mas-rpm-id = <ICBID_MASTER_CNOC_MNOC_MMSS_CFG>;
		};

		mas_cnoc_mnoc_cfg: mas-cnoc-mnoc-cfg {
			cell-id = <MSM_BUS_MASTER_CNOC_MNOC_CFG>;
			label = "mas-cnoc-mnoc-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,connections = <&slv_srvc_mnoc>;
			qcom,bus-dev = <&fab_mnoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_CNOC_MNOC_CFG>;
		};

		mas_cpp: mas-cpp {
			cell-id = <MSM_BUS_MASTER_CPP>;
			label = "mas-cpp";
			qcom,buswidth = <32>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,qport = <5>;
			qcom,qos-mode = "bypass";
			qcom,connections = <&slv_mnoc_bimc>;
			qcom,bus-dev = <&fab_mnoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_CPP>;
		};

		mas_jpeg: mas-jpeg {
			cell-id = <MSM_BUS_MASTER_JPEG>;
			label = "mas-jpeg";
			qcom,buswidth = <32>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,qport = <7>;
			qcom,qos-mode = "bypass";
			qcom,connections = <&slv_mnoc_bimc>;
			qcom,bus-dev = <&fab_mnoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_JPEG>;
		};

		mas_mdp_p0: mas-mdp-p0 {
			cell-id = <MSM_BUS_MASTER_MDP_PORT0>;
			label = "mas-mdp-p0";
			qcom,buswidth = <32>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,qport = <1>;
			qcom,qos-mode = "bypass";
			qcom,connections = <&slv_mnoc_bimc>;
			qcom,bus-dev = <&fab_mnoc>;
			qcom,vrail-comp = <25>;
			qcom,mas-rpm-id = <ICBID_MASTER_MDP0>;
		};

		mas_mdp_p1: mas-mdp-p1 {
			cell-id = <MSM_BUS_MASTER_MDP_PORT1>;
			label = "mas-mdp-p1";
			qcom,buswidth = <32>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,qport = <2>;
			qcom,qos-mode = "bypass";
			qcom,connections = <&slv_mnoc_bimc>;
			qcom,bus-dev = <&fab_mnoc>;
			qcom,vrail-comp = <25>;
			qcom,mas-rpm-id = <ICBID_MASTER_MDP1>;
		};

		mas_rotator: mas-rotator {
			cell-id = <MSM_BUS_MASTER_ROTATOR>;
			label = "mas-rotator";
			qcom,buswidth = <32>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,qport = <0>;
			qcom,qos-mode = "bypass";
			qcom,connections = <&slv_mnoc_bimc>;
			qcom,bus-dev = <&fab_mnoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_ROTATOR>;
		};

		mas_venus: mas-venus {
			cell-id = <MSM_BUS_MASTER_VIDEO_P0>;
			label = "mas-venus";
			qcom,buswidth = <32>;
			qcom,agg-ports = <2>;
			qcom,ap-owned;
			qcom,qport = <3 4>;
			qcom,qos-mode = "bypass";
			qcom,connections = <&slv_mnoc_bimc>;
			qcom,bus-dev = <&fab_mnoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_VIDEO>;
		};

		mas_vfe: mas-vfe {
			cell-id = <MSM_BUS_MASTER_VFE>;
			label = "mas-vfe";
			qcom,buswidth = <32>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,qport = <6>;
			qcom,qos-mode = "bypass";
			qcom,connections = <&slv_mnoc_bimc>;
			qcom,bus-dev = <&fab_mnoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_VFE>;
		};

		mas_snoc_vmem: mas-snoc-vmem {
			cell-id = <MSM_BUS_MASTER_SNOC_VMEM>;
			label = "mas-snoc-vmem";
			qcom,buswidth = <32>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,connections = <&slv_vmem>;
			qcom,bus-dev = <&fab_mnoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_SNOC_VMEM>;
		};

		mas_venus_vmem: mas-venus-vmem {
			cell-id = <MSM_BUS_MASTER_VIDEO_P0_OCMEM>;
			label = "mas-venus-vmem";
			qcom,buswidth = <32>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,connections = <&slv_vmem>;
			qcom,bus-dev = <&fab_mnoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_VENUS_VMEM>;
		};

		mas_snoc_pnoc: mas-snoc-pnoc {
			cell-id = <MSM_BUS_SNOC_PNOC_MAS>;
			label = "mas-snoc-pnoc";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,connections = < &slv_blsp_1 &slv_blsp_2&slv_usb_hs
				 &slv_sdcc_1 &slv_sdcc_2
				 &slv_sdcc_4 &slv_tsif
				 &slv_pdm &slv_ahb2phy>;
			qcom,bus-dev = <&fab_pnoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_SNOC_PNOC>;
		};

		mas_sdcc_1: mas-sdcc-1 {
			cell-id = <MSM_BUS_MASTER_SDCC_1>;
			label = "mas-sdcc-1";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,connections = <&slv_pnoc_a1noc>;
			qcom,bus-dev = <&fab_pnoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_SDCC_1>;
		};

		mas_sdcc_2: mas-sdcc-2 {
			cell-id = <MSM_BUS_MASTER_SDCC_2>;
			label = "mas-sdcc-2";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,connections = <&slv_pnoc_a1noc>;
			qcom,bus-dev = <&fab_pnoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_SDCC_2>;
		};

		mas_sdcc_4: mas-sdcc-4 {
			cell-id = <MSM_BUS_MASTER_SDCC_4>;
			label = "mas-sdcc-4";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,connections = <&slv_pnoc_a1noc>;
			qcom,bus-dev = <&fab_pnoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_SDCC_4>;
		};

		mas_usb_hs: mas-usb-hs {
			cell-id = <MSM_BUS_MASTER_USB_HS>;
			label = "mas-usb-hs";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,connections = <&slv_pnoc_a1noc>;
			qcom,bus-dev = <&fab_pnoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_USB_HS>;
		};

		mas_blsp_1: mas-blsp-1 {
			cell-id = <MSM_BUS_MASTER_BLSP_1>;
			label = "mas-blsp-1";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,connections = <&slv_pnoc_a1noc>;
			qcom,bus-dev = <&fab_pnoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_BLSP_1>;
		};

		mas_blsp_2: mas-blsp-2 {
			cell-id = <MSM_BUS_MASTER_BLSP_2>;
			label = "mas-blsp-2";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,connections = <&slv_pnoc_a1noc>;
			qcom,bus-dev = <&fab_pnoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_BLSP_2>;
		};

		mas_tsif: mas-tsif {
			cell-id = <MSM_BUS_MASTER_TSIF>;
			label = "mas-tsif";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,connections = <&slv_pnoc_a1noc>;
			qcom,bus-dev = <&fab_pnoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_TSIF>;
		};

		mas_hmss: mas-hmss {
			cell-id = <MSM_BUS_MASTER_HMSS>;
			label = "mas-hmss";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,qport = <4>;
			qcom,qos-mode = "fixed";
			qcom,connections = < &slv_pimem &slv_imem&slv_snoc_bimc>;
			qcom,prio1 = <1>;
			qcom,prio0 = <1>;
			qcom,bus-dev = <&fab_snoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_HMSS>;
		};

		mas_qdss_bam: mas-qdss-bam {
			cell-id = <MSM_BUS_MASTER_QDSS_BAM>;
			label = "mas-qdss-bam";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,qport = <2>;
			qcom,qos-mode = "fixed";
			qcom,connections = < &slv_pimem&slv_usb3 &slv_imem
				 &slv_snoc_bimc &slv_snoc_pnoc>;
			qcom,prio1 = <1>;
			qcom,prio0 = <1>;
			qcom,bus-dev = <&fab_snoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_QDSS_BAM>;
		};

		mas_snoc_cfg: mas-snoc-cfg {
			cell-id = <MSM_BUS_MASTER_SNOC_CFG>;
			label = "mas-snoc-cfg";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,connections = <&slv_srvc_snoc>;
			qcom,bus-dev = <&fab_snoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_SNOC_CFG>;
		};

		mas_bimc_snoc_0: mas-bimc-snoc-0 {
			cell-id = <MSM_BUS_BIMC_SNOC_MAS>;
			label = "mas-bimc-snoc-0";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,connections = < &slv_snoc_vmem &slv_usb3 &slv_pimem
				 &slv_lpass &slv_hmss
				 &slv_snoc_cnoc &slv_snoc_pnoc
				 &slv_imem &slv_qdss_stm>;
			qcom,bus-dev = <&fab_snoc>;
			qcom,ap-owned;
			qcom,mas-rpm-id = <ICBID_MASTER_BIMC_SNOC>;
		};

		mas_bimc_snoc_1: mas-bimc-snoc-1 {
			cell-id = <MSM_BUS_BIMC_SNOC_1_MAS>;
			label = "mas-bimc-snoc-1";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,connections = < &slv_pcie_2 &slv_pcie_1&slv_pcie_0>;
			qcom,bus-dev = <&fab_snoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_BIMC_SNOC_1>;
		};

		mas_a0noc_snoc: mas-a0noc-snoc {
			cell-id = <MSM_BUS_A0NOC_SNOC_MAS>;
			label = "mas-a0noc-snoc";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,connections = < &slv_snoc_pnoc &slv_imem&slv_hmss
				 &slv_snoc_bimc &slv_pimem>;
			qcom,bus-dev = <&fab_snoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_A0NOC_SNOC>;
		};

		mas_a1noc_snoc: mas-a1noc-snoc {
			cell-id = <MSM_BUS_A1NOC_SNOC_MAS>;
			label = "mas-a1noc-snoc";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,connections = < &slv_snoc_vmem &slv_usb3 &slv_pcie_0
				 &slv_pimem &slv_pcie_2
				 &slv_lpass &slv_pcie_1
				&slv_hmss &slv_snoc_bimc
				 &slv_snoc_cnoc &slv_snoc_pnoc
				 &slv_imem &slv_qdss_stm>;
			qcom,bus-dev = <&fab_snoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_A1NOC_SNOC>;
		};

		mas_a2noc_snoc: mas-a2noc-snoc {
			cell-id = <MSM_BUS_A2NOC_SNOC_MAS>;
			label = "mas-a2noc-snoc";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,connections = < &slv_snoc_vmem &slv_usb3 &slv_pcie_1
				 &slv_pimem &slv_pcie_2
				 &slv_qdss_stm&slv_lpass
				 &slv_snoc_bimc &slv_snoc_cnoc
				 &slv_snoc_pnoc &slv_imem
				 &slv_pcie_0>;
			qcom,bus-dev = <&fab_snoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_A2NOC_SNOC>;
		};

		mas_qdss_etr: mas-qdss-etr {
			cell-id = <MSM_BUS_MASTER_QDSS_ETR>;
			label = "mas-qdss-etr";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,qport = <3>;
			qcom,qos-mode = "fixed";
			qcom,connections = < &slv_pimem&slv_usb3 &slv_imem
				 &slv_snoc_bimc &slv_snoc_pnoc>;
			qcom,prio1 = <1>;
			qcom,prio0 = <1>;
			qcom,bus-dev = <&fab_snoc>;
			qcom,mas-rpm-id = <ICBID_MASTER_QDSS_ETR>;
		};

		/*Internal nodes*/

		/*Slaves*/

		slv_a0noc_snoc: slv-a0noc-snoc {
			cell-id = <MSM_BUS_A0NOC_SNOC_SLV>;
			label = "slv-a0noc-snoc";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_snoc>;
			qcom,connections = <&mas_a0noc_snoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_A0NOC_SNOC>;
			qcom,enable-only-clk;
			clock-names = "node_clk";
			clocks = <&clock_gcc clk_gcc_aggre0_cnoc_ahb_clk>;
		};

		slv_a1noc_snoc: slv-a1noc-snoc {
			cell-id = <MSM_BUS_A1NOC_SNOC_SLV>;
			label = "slv-a1noc-snoc";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_snoc>;
			qcom,connections = <&mas_a1noc_snoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_A1NOC_SNOC>;
		};

		slv_a2noc_snoc: slv-a2noc-snoc {
			cell-id = <MSM_BUS_A2NOC_SNOC_SLV>;
			label = "slv-a2noc-snoc";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_snoc>;
			qcom,connections = <&mas_a2noc_snoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_A2NOC_SNOC>;
		};

		slv_ebi: slv-ebi {
			cell-id = <MSM_BUS_SLAVE_EBI_CH0>;
			label = "slv-ebi";
			qcom,buswidth = <8>;
			qcom,agg-ports = <2>;
			qcom,bus-dev = <&fab_bimc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_EBI1>;
		};

		slv_hmss_l3: slv-hmss-l3 {
			cell-id = <MSM_BUS_SLAVE_HMSS_L3>;
			label = "slv-hmss-l3";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_bimc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_HMSS_L3>;
		};

		slv_bimc_snoc_0: slv-bimc-snoc-0 {
			cell-id = <MSM_BUS_BIMC_SNOC_SLV>;
			label = "slv-bimc-snoc-0";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_bimc>;
			qcom,ap-owned;
			qcom,connections = <&mas_bimc_snoc_0>;
			qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_SNOC>;
		};

		slv_bimc_snoc_1: slv-bimc-snoc-1 {
			cell-id = <MSM_BUS_BIMC_SNOC_1_SLV>;
			label = "slv-bimc-snoc-1";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_bimc>;
			qcom,connections = <&mas_bimc_snoc_1>;
			qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_SNOC_1>;
		};

		slv_cnoc_a1noc: slv-cnoc-a1noc {
			cell-id = <MSM_BUS_CNOC_SNOC_SLV>;
			label = "slv-cnoc-a1noc";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,connections = <&mas_cnoc_a1noc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_CNOC_SNOC>;
		};

		slv_clk_ctl: slv-clk-ctl {
			cell-id = <MSM_BUS_SLAVE_CLK_CTL>;
			label = "slv-clk-ctl";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_CLK_CTL>;
		};

		slv_tcsr: slv-tcsr {
			cell-id = <MSM_BUS_SLAVE_TCSR>;
			label = "slv-tcsr";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_TCSR>;
		};

		slv_tlmm: slv-tlmm {
			cell-id = <MSM_BUS_SLAVE_TLMM>;
			label = "slv-tlmm";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_TLMM>;
		};

		slv_crypto0_cfg:slv-crypto0-cfg {
			cell-id = <MSM_BUS_SLAVE_CRYPTO_0_CFG>;
			label = "slv-crypto0-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_CRYPTO_0_CFG>;
		};

		slv_mpm: slv-mpm {
			cell-id = <MSM_BUS_SLAVE_MPM>;
			label = "slv-mpm";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_MPM>;
		};

		slv_pimem_cfg: slv-pimem-cfg {
			cell-id = <MSM_BUS_SLAVE_PIMEM_CFG>;
			label = "slv-pimem-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_PIMEM_CFG>;
		};

		slv_imem_cfg: slv-imem-cfg {
			cell-id = <MSM_BUS_SLAVE_IMEM_CFG>;
			label = "slv-imem-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_IMEM_CFG>;
		};

		slv_message_ram: slv-message-ram {
			cell-id = <MSM_BUS_SLAVE_MESSAGE_RAM>;
			label = "slv-message-ram";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_MESSAGE_RAM>;
		};

		slv_bimc_cfg: slv-bimc-cfg {
			cell-id = <MSM_BUS_SLAVE_BIMC_CFG>;
			label = "slv-bimc-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_CFG>;
		};

		slv_pmic_arb: slv-pmic-arb {
			cell-id = <MSM_BUS_SLAVE_PMIC_ARB>;
			label = "slv-pmic-arb";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_PMIC_ARB>;
		};

		slv_prng: slv-prng {
			cell-id = <MSM_BUS_SLAVE_PRNG>;
			label = "slv-prng";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_PRNG>;
		};

		slv_dcc_cfg:slv-dcc-cfg {
			cell-id = <MSM_BUS_SLAVE_DCC_CFG>;
			label = "slv-dcc-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_DCC_CFG>;
		};

		slv_rbcpr_mx: slv-rbcpr-mx {
			cell-id = <MSM_BUS_SLAVE_RBCPR_MX>;
			label = "slv-rbcpr-mx";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_RBCPR_MX>;
		};

		slv_qdss_cfg: slv-qdss-cfg {
			cell-id = <MSM_BUS_SLAVE_QDSS_CFG>;
			label = "slv-qdss-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_CFG>;
		};

		slv_rbcpr_cx: slv-rbcpr-cx {
			cell-id = <MSM_BUS_SLAVE_RBCPR_CX>;
			label = "slv-rbcpr-cx";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_RBCPR_CX>;
		};

		slv_cpr_apu_cfg:slv-cpr-apu-cfg {
			cell-id = <MSM_BUS_SLAVE_QDSS_RBCPR_APU_CFG>;
			label = "slv-cpr-apu-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_RBCPR_APU_CFG>;
		};

		slv_cnoc_mnoc_cfg: slv-cnoc-mnoc-cfg {
			cell-id = <MSM_BUS_SLAVE_CNOC_MNOC_CFG>;
			label = "slv-cnoc-mnoc-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,connections = <&mas_cnoc_mnoc_cfg>;
			qcom,slv-rpm-id = <ICBID_SLAVE_CNOC_MNOC_CFG>;
		};

		slv_snoc_cfg: slv-snoc-cfg {
			cell-id = <MSM_BUS_SLAVE_SNOC_CFG>;
			label = "slv-snoc-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_CFG>;
		};

		slv_snoc_mpu_cfg: slv-snoc-mpu-cfg {
			cell-id = <MSM_BUS_SLAVE_SNOC_MPU_CFG>;
			label = "slv-snoc-mpu-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_MPU_CFG>;
		};

		slv_ebi1_phy_cfg: slv-ebi1-phy-cfg {
			cell-id = <MSM_BUS_SLAVE_EBI1_PHY_CFG>;
			label = "slv-ebi1-phy-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_EBI1_PHY_CFG>;
		};

		slv_a0noc_cfg: slv-a0noc-cfg {
			cell-id = <MSM_BUS_SLAVE_A0NOC_CFG>;
			label = "slv-a0noc-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_A0NOC_CFG>;
		};

		slv_pcie_1_cfg: slv-pcie-1-cfg {
			cell-id = <MSM_BUS_SLAVE_PCIE_1_CFG>;
			label = "slv-pcie-1-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_PCIE_1_CFG>;
		};

		slv_pcie_2_cfg: slv-pcie-2-cfg {
			cell-id = <MSM_BUS_SLAVE_PCIE_2_CFG>;
			label = "slv-pcie-2-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_PCIE_2_CFG>;
		};

		slv_pcie_0_cfg: slv-pcie-0-cfg {
			cell-id = <MSM_BUS_SLAVE_PCIE_0_CFG>;
			label = "slv-pcie-0-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_PCIE_0_CFG>;
		};

		slv_pcie20_ahb2phy: slv-pcie20-ahb2phy {
			cell-id = <MSM_BUS_SLAVE_PCIE20_AHB2PHY>;
			label = "slv-pcie20-ahb2phy";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_PCIE20_AHB2PHY>;
		};

		slv_a0noc_mpu_cfg: slv-a0noc-mpu-cfg {
			cell-id = <MSM_BUS_SLAVE_A0NOC_MPU_CFG>;
			label = "slv-a0noc-mpu-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_A0NOC_MPU_CFG>;
		};

		slv_ufs_cfg: slv-ufs-cfg {
			cell-id = <MSM_BUS_SLAVE_UFS_CFG>;
			label = "slv-ufs-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_UFS_CFG>;
		};

		slv_a1noc_cfg: slv-a1noc-cfg {
			cell-id = <MSM_BUS_SLAVE_A1NOC_CFG>;
			label = "slv-a1noc-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_A1NOC_CFG>;
		};

		slv_a1noc_mpu_cfg: slv-a1noc-mpu-cfg {
			cell-id = <MSM_BUS_SLAVE_A1NOC_MPU_CFG>;
			label = "slv-a1noc-mpu-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_A1NOC_MPU_CFG>;
		};

		slv_a2noc_cfg: slv-a2noc-cfg {
			cell-id = <MSM_BUS_SLAVE_A2NOC_CFG>;
			label = "slv-a2noc-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_A2NOC_CFG>;
		};

		slv_a2noc_mpu_cfg: slv-a2noc-mpu-cfg {
			cell-id = <MSM_BUS_SLAVE_A2NOC_MPU_CFG>;
			label = "slv-a2noc-mpu-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_A2NOC_MPU_CFG>;
		};

		slv_ssc_cfg: slv-ssc-cfg {
			cell-id = <MSM_BUS_SLAVE_SSC_CFG>;
			label = "slv-ssc-cfg";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_SSC_CFG>;
		};

		slv_a0noc_smmu_cfg: slv-a0noc-smmu-cfg {
			cell-id = <MSM_BUS_SLAVE_A0NOC_SMMU_CFG>;
			label = "slv-a0noc-smmu-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_A0NOC_SMMU_CFG>;
		};

		slv_a1noc_smmu_cfg: slv-a1noc-smmu-cfg {
			cell-id = <MSM_BUS_SLAVE_A1NOC_SMMU_CFG>;
			label = "slv-a1noc-smmu-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_A1NOC_SMMU_CFG>;
		};

		slv_a2noc_smmu_cfg: slv-a2noc-smmu-cfg {
			cell-id = <MSM_BUS_SLAVE_A2NOC_SMMU_CFG>;
			label = "slv-a2noc-smmu-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_A2NOC_SMMU_CFG>;
		};

		slv_lpass_smmu_cfg: slv-lpass-smmu-cfg {
			cell-id = <MSM_BUS_SLAVE_LPASS_SMMU_CFG>;
			label = "slv-lpass-smmu-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_LPASS_SMMU_CFG>;
		};

		slv_cnoc_mnoc_mmss_cfg: slv-cnoc-mnoc-mmss-cfg {
			cell-id = <MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG>;
			label = "slv-cnoc-mnoc-mmss-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_cnoc>;
			qcom,connections = <&mas_cnoc_mnoc_mmss_cfg>;
			qcom,slv-rpm-id = <ICBID_SLAVE_CNOC_MNOC_MMSS_CFG>;
		};

		slv_mmagic_cfg: slv-mmagic-cfg {
			cell-id = <MSM_BUS_SLAVE_MMAGIC_CFG>;
			label = "slv-mmagic-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_MMAGIC_CFG>;
		};

		slv_cpr_cfg: slv-cpr-cfg {
			cell-id = <MSM_BUS_SLAVE_CPR_CFG>;
			label = "slv-cpr-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_CPR_CFG>;
		};

		slv_misc_cfg: slv-misc-cfg {
			cell-id = <MSM_BUS_SLAVE_MISC_CFG>;
			label = "slv-misc-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_MISC_CFG>;
		};

		slv_venus_throttle_cfg: slv-venus-throttle-cfg {
			cell-id = <MSM_BUS_SLAVE_VENUS_THROTTLE_CFG>;
			label = "slv-venus-throttle-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_VENUS_THROTTLE_CFG>;
		};

		slv_venus_cfg: slv-venus-cfg {
			cell-id = <MSM_BUS_SLAVE_VENUS_CFG>;
			label = "slv-venus-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_VENUS_CFG>;
		};

		slv_vmem_cfg: slv-vmem-cfg {
			cell-id = <MSM_BUS_SLAVE_VMEM_CFG>;
			label = "slv-vmem-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_VMEM_CFG>;
			qcom,enable-only-clk;
			clock-names = "node_clk";
			clocks = <&clock_mmss clk_mmss_mmagic_maxi_clk>;
			node-gdsc-supply = <&gdsc_mmagic_video>;
		};

		slv_dsa_cfg: slv-dsa-cfg {
			cell-id = <MSM_BUS_SLAVE_DSA_CFG>;
			label = "slv-dsa-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_DSA_CFG>;
		};

		slv_mnoc_clocks_cfg: slv-mnoc-clocks-cfg {
			cell-id = <MSM_BUS_SLAVE_MMSS_CLK_CFG>;
			label = "slv-mnoc-clocks-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_MMSS_CLK_CFG>;
		};

		slv_dsa_mpu_cfg: slv-dsa-mpu-cfg {
			cell-id = <MSM_BUS_SLAVE_DSA_MPU_CFG>;
			label = "slv-dsa-mpu-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_DSA_MPU_CFG>;
		};

		slv_mnoc_mpu_cfg: slv-mnoc-mpu-cfg {
			cell-id = <MSM_BUS_SLAVE_MNOC_MPU_CFG>;
			label = "slv-mnoc-mpu-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_MNOC_MPU_CFG>;
		};

		slv_display_cfg: slv-display-cfg {
			cell-id = <MSM_BUS_SLAVE_DISPLAY_CFG>;
			label = "slv-display-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_DISPLAY_CFG>;
		};

		slv_display_throttle_cfg: slv-display-throttle-cfg {
			cell-id = <MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG>;
			label = "slv-display-throttle-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_DISPLAY_THROTTLE_CFG>;
		};

		slv_camera_cfg: slv-camera-cfg {
			cell-id = <MSM_BUS_SLAVE_CAMERA_CFG>;
			label = "slv-camera-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_CAMERA_CFG>;
		};

		slv_camera_throttle_cfg: slv-camera-throttle-cfg {
			cell-id = <MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG>;
			label = "slv-camera-throttle-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_CAMERA_THROTTLE_CFG>;
		};

		slv_oxili_cfg: slv-oxili-cfg {
			cell-id = <MSM_BUS_SLAVE_GRAPHICS_3D_CFG>;
			label = "slv-oxili-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_GFX3D_CFG>;
		};

		slv_smmu_mdp_cfg: slv-smmu-mdp-cfg {
			cell-id = <MSM_BUS_SLAVE_SMMU_MDP_CFG>;
			label = "slv-smmu-mdp-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_SMMU_MDP_CFG>;
		};

		slv_smmu_rot_cfg: slv-smmu-rot-cfg {
			cell-id = <MSM_BUS_SLAVE_SMMU_ROTATOR_CFG>;
			label = "slv-smmu-rot-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_SMMU_ROTATOR_CFG>;
		};

		slv_smmu_venus_cfg: slv-smmu-venus-cfg {
			cell-id = <MSM_BUS_SLAVE_SMMU_VENUS_CFG>;
			label = "slv-smmu-venus-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_SMMU_VENUS_CFG>;
		};

		slv_smmu_cpp_cfg: slv-smmu-cpp-cfg {
			cell-id = <MSM_BUS_SLAVE_SMMU_CPP_CFG>;
			label = "slv-smmu-cpp-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_SMMU_CPP_CFG>;
		};

		slv_smmu_jpeg_cfg: slv-smmu-jpeg-cfg {
			cell-id = <MSM_BUS_SLAVE_SMMU_JPEG_CFG>;
			label = "slv-smmu-jpeg-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_SMMU_JPEG_CFG>;
		};

		slv_smmu_vfe_cfg: slv-smmu-vfe-cfg {
			cell-id = <MSM_BUS_SLAVE_SMMU_VFE_CFG>;
			label = "slv-smmu-vfe-cfg";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc_ahb>;
			qcom,slv-rpm-id = <ICBID_SLAVE_SMMU_VFE_CFG>;
		};

		slv_mnoc_bimc: slv-mnoc-bimc {
			cell-id = <MSM_BUS_MNOC_BIMC_SLV>;
			label = "slv-mnoc-bimc";
			qcom,buswidth = <32>;
			qcom,agg-ports = <2>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc>;
			qcom,connections = <&mas_mnoc_bimc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_MNOC_BIMC>;
			qcom,enable-only-clk;
			clock-names = "node_clk";
			clocks = <&clock_gcc clk_mmssnoc_axi_clk>;
		};

		slv_vmem: slv-vmem {
			cell-id = <MSM_BUS_SLAVE_VMEM>;
			label = "slv-vmem";
			qcom,buswidth = <32>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_VMEM>;
			clock-names = "node_clk";
			clocks = <&clock_mmss clk_mmss_mmagic_maxi_clk>;
			node-gdsc-supply = <&gdsc_mmagic_video>;
		};

		slv_srvc_mnoc: slv-srvc-mnoc {
			cell-id = <MSM_BUS_SLAVE_SERVICE_MNOC>;
			label = "slv-srvc-mnoc";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_mnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_SERVICE_MNOC>;
		};

		slv_pnoc_a1noc: slv-pnoc-a1noc {
			cell-id = <MSM_BUS_PNOC_A1NOC_SLV>;
			label = "slv-pnoc-a1noc";
			qcom,buswidth = <8>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_pnoc>;
			qcom,connections = <&mas_pnoc_a1noc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_PNOC_A1NOC>;
		};

		slv_usb_hs: slv-usb-hs {
			cell-id = <MSM_BUS_SLAVE_USB_HS>;
			label = "slv-usb-hs";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_pnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_USB_HS>;
		};

		slv_sdcc_2: slv-sdcc-2 {
			cell-id = <MSM_BUS_SLAVE_SDCC_2>;
			label = "slv-sdcc-2";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_pnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_2>;
		};

		slv_sdcc_4: slv-sdcc-4 {
			cell-id = <MSM_BUS_SLAVE_SDCC_4>;
			label = "slv-sdcc-4";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_pnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_4>;
		};

		slv_tsif: slv-tsif {
			cell-id = <MSM_BUS_SLAVE_TSIF>;
			label = "slv-tsif";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_pnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_TSIF>;
		};

		slv_blsp_2: slv-blsp-2 {
			cell-id = <MSM_BUS_SLAVE_BLSP_2>;
			label = "slv-blsp-2";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_pnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_2>;
		};

		slv_sdcc_1:slv-sdcc-1 {
			cell-id = <MSM_BUS_SLAVE_SDCC_1>;
			label = "slv-sdcc-1";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_pnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_1>;
		};

		slv_blsp_1: slv-blsp-1 {
			cell-id = <MSM_BUS_SLAVE_BLSP_1>;
			label = "slv-blsp-1";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_pnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_1>;
		};

		slv_pdm: slv-pdm {
			cell-id = <MSM_BUS_SLAVE_PDM>;
			label = "slv-pdm";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_pnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_PDM>;
		};

		slv_ahb2phy: slv-ahb2phy {
			cell-id = <MSM_BUS_SLAVE_AHB2PHY>;
			label = "slv-ahb2phy";
			qcom,buswidth = <4>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_pnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_AHB2PHY>;
		};

		slv_hmss: slv-hmss {
			cell-id = <MSM_BUS_SLAVE_APPSS>;
			label = "slv-hmss";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_snoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_APPSS>;
		};

		slv_lpass: slv-lpass {
			cell-id = <MSM_BUS_SLAVE_LPASS>;
			label = "slv-lpass";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_snoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_LPASS>;
		};

		slv_usb3: slv-usb3 {
			cell-id = <MSM_BUS_SLAVE_USB3>;
			label = "slv-usb3";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_snoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_USB3_0>;
		};

		slv_snoc_bimc: slv-snoc-bimc {
			cell-id = <MSM_BUS_SNOC_BIMC_SLV>;
			label = "slv-snoc-bimc";
			qcom,buswidth = <32>;
			qcom,agg-ports = <2>;
			qcom,bus-dev = <&fab_snoc>;
			qcom,connections = <&mas_snoc_bimc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC>;
		};

		slv_snoc_cnoc: slv-snoc-cnoc {
			cell-id = <MSM_BUS_SNOC_CNOC_SLV>;
			label = "slv-snoc-cnoc";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_snoc>;
			qcom,connections = <&mas_snoc_cnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_CNOC>;
		};

		slv_imem: slv-imem {
			cell-id = <MSM_BUS_SLAVE_OCIMEM>;
			label = "slv-imem";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_snoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_IMEM>;
		};

		slv_pimem: slv-pimem {
			cell-id = <MSM_BUS_SLAVE_PIMEM>;
			label = "slv-pimem";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_snoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_PIMEM>;
		};

		slv_snoc_vmem: slv-snoc-vmem {
			cell-id = <MSM_BUS_SLAVE_SNOC_VMEM>;
			label = "slv-snoc-vmem";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_snoc>;
			qcom,connections = <&mas_snoc_vmem>;
			qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_VMEM>;
		};

		slv_snoc_pnoc: slv-snoc-pnoc {
			cell-id = <MSM_BUS_SNOC_PNOC_SLV>;
			label = "slv-snoc-pnoc";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_snoc>;
			qcom,connections = <&mas_snoc_pnoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_PNOC>;
		};

		slv_qdss_stm: slv-qdss-stm {
			cell-id = <MSM_BUS_SLAVE_QDSS_STM>;
			label = "slv-qdss-stm";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,bus-dev = <&fab_snoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_STM>;
		};

		slv_pcie_0: slv-pcie-0 {
			cell-id = <MSM_BUS_SLAVE_PCIE_0>;
			label = "slv-pcie-0";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_snoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_PCIE_0>;
		};

		slv_pcie_1: slv-pcie-1 {
			cell-id = <MSM_BUS_SLAVE_PCIE_1>;
			label = "slv-pcie-1";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_snoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_PCIE_1>;
		};

		slv_pcie_2: slv-pcie-2 {
			cell-id = <MSM_BUS_SLAVE_PCIE_2>;
			label = "slv-pcie-2";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_snoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_PCIE_2>;
		};

		slv_srvc_snoc: slv-srvc-snoc {
			cell-id = <MSM_BUS_SLAVE_SERVICE_SNOC>;
			label = "slv-srvc-snoc";
			qcom,buswidth = <16>;
			qcom,agg-ports = <1>;
			qcom,ap-owned;
			qcom,bus-dev = <&fab_snoc>;
			qcom,slv-rpm-id = <ICBID_SLAVE_SERVICE_SNOC>;
		};
	};

	devfreq_spdm_cpu {
		compatible = "qcom,devfreq_spdm";
		qcom,msm-bus,name = "devfreq_spdm";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
				<1 512 0 0>,
				<1 512 0 0>;
		qcom,msm-bus,active-only;
		qcom,spdm-client = <0>;

		clock-names = "cci_clk";
		clocks = <&clock_cpu clk_cbf_clk>;

		qcom,bw-upstep = <1000>;
		qcom,bw-dwnstep = <1000>;
		qcom,max-vote = <10000>;
		qcom,up-step-multp = <2>;
		qcom,spdm-interval = <100>;

		qcom,ports = <24>;
		qcom,alpha-up = <12>;
		qcom,alpha-down = <15>;
		qcom,bucket-size = <8>;

		/*max pl1 freq, max pl2 freq*/
		qcom,pl-freqs = <260000 770000>;

		/* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */
		qcom,reject-rate = <5000 5000 5000 5000 5000 5000>;
		/* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */
		qcom,response-time-us = <10000 10000 10000 10000 10000 10000>;
		/* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */
		qcom,cci-response-time-us = <10000 10000 10000 10000 10000 10000>;
		qcom,max-cci-freq = <1036800> ;
	};

	devfreq_spdm_gov {
		compatible = "qcom,gov_spdm_hyp";
		interrupt-names = "spdm-irq";
		interrupts = <0 192 0>;
	};
};