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2024-09-09 08:52:07 +00:00
commit f9cc65cfda
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wlan/include/AR6002/AR6K_version.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2013, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#define __VER_MAJOR_ 3
#define __VER_MINOR_ 1
#define __VER_PATCH_ 1
/* The makear6ksdk script (used for release builds) modifies the following line. */
#define __BUILD_NUMBER_ 855
/* Format of the version number. */
#define VER_MAJOR_BIT_OFFSET 28
#define VER_MINOR_BIT_OFFSET 24
#define VER_PATCH_BIT_OFFSET 16
#define VER_BUILD_NUM_BIT_OFFSET 0
/*
* The version has the following format:
* Bits 28-31: Major version
* Bits 24-27: Minor version
* Bits 16-23: Patch version
* Bits 0-15: Build number (automatically generated during build process )
* E.g. Build 1.1.3.7 would be represented as 0x11030007.
*
* DO NOT split the following macro into multiple lines as this may confuse the build scripts.
*/
#define AR6K_SW_VERSION ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) )
/* ABI Version. Reflects the version of binary interface exposed by AR6K target firmware. Needs to be incremented by 1 for any change in the firmware that requires upgrade of the driver on the host side for the change to work correctly */
#define AR6K_ABI_VERSION 1
wlan/include/AR6002/addrs.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __ADDRS_H__
#define __ADDRS_H__
/*
* Special AR6002 Addresses that may be needed by special
* applications (e.g. ART) on the Host as well as Target.
*/
#if defined(AR6002_REV2)
#define AR6K_RAM_START 0x00500000
#define TARG_RAM_OFFSET(vaddr) ((A_UINT32)(vaddr) & 0xfffff)
#define TARG_RAM_SZ (184*1024)
#define TARG_ROM_SZ (80*1024)
#endif
#if defined(AR6002_REV4) || defined(AR6003)
#define AR6K_RAM_START 0x00540000
#define TARG_RAM_OFFSET(vaddr) (((A_UINT32)(vaddr) & 0xfffff) - 0x40000)
#define TARG_RAM_SZ (256*1024)
#define TARG_ROM_SZ (256*1024)
#endif
#if defined(AR6002_REV6) || defined(AR6004)
#define AR6K_RAM_START 0x00400000
#define TARG_RAM_OFFSET(vaddr) (((A_UINT32)(vaddr) & 0x3fffff))
#define TARG_RAM_SZ (256*1024)
#define TARG_ROM_SZ (512*1024)
#define TARG_IRAM_START 0x00998000
#define TARG_IRAM_SZ ((128+32)*1024)
#define TARG_RAM_ACS_RESERVE 32
#endif
#define AR6002_BOARD_DATA_SZ 768
#define AR6002_BOARD_EXT_DATA_SZ 0
#define AR6003_BOARD_DATA_SZ 1024
/* Reserve space for extended board data */
/* AR6003 v2 has only 768 bytes for extended board data */
#define AR6003_VER2_BOARD_EXT_DATA_SZ 768
#if defined(AR6002_REV42)
#define AR6003_BOARD_EXT_DATA_SZ AR6003_VER2_BOARD_EXT_DATA_SZ
#else
#define AR6003_BOARD_EXT_DATA_SZ 1024
#endif /* AR6002_REV42 */
#define MCKINLEY_BOARD_DATA_SZ 1024
#define MCKINLEY_BOARD_EXT_DATA_SZ 0
#define AR6K_RAM_ADDR(byte_offset) (AR6K_RAM_START+(byte_offset))
#define TARG_RAM_ADDRS(byte_offset) AR6K_RAM_ADDR(byte_offset)
#if defined(AR6002_REV2) || defined(AR6002_REV4)
#define AR6K_ROM_START 0x004e0000
#define TARG_ROM_OFFSET(vaddr) (((A_UINT32)(vaddr) & 0x1fffff) - 0xe0000)
#endif /* AR6002_REV2 || AR6002_REV4 */
#if defined(AR6002_REV6)
#define AR6K_ROM_START 0x00900000
#define TARG_ROM_OFFSET(vaddr) ((A_UINT32)(vaddr) & 0xfffff)
#endif /* AR6002_REV6 */
#define AR6K_ROM_ADDR(byte_offset) (AR6K_ROM_START+(byte_offset))
#define TARG_ROM_ADDRS(byte_offset) AR6K_ROM_ADDR(byte_offset)
/*
* At this ROM address is a pointer to the start of the ROM DataSet Index.
* If there are no ROM DataSets, there's a 0 at this address.
*/
#define ROM_DATASET_INDEX_ADDR (TARG_ROM_ADDRS(TARG_ROM_SZ)-8)
#define ROM_MBIST_CKSUM_ADDR (TARG_ROM_ADDRS(TARG_ROM_SZ)-4)
/*
* The API A_BOARD_DATA_ADDR() is the proper way to get a read pointer to
* board data.
*/
/* Size of Board Data, in bytes */
#if defined(AR6002_REV4) || defined(AR6003)
#define BOARD_DATA_SZ (AR6003_BOARD_DATA_SZ + AR6003_BOARD_EXT_DATA_SZ)
#endif
#if defined(AR6002_REV6)
#define BOARD_DATA_SZ MCKINLEY_BOARD_DATA_SZ
#endif
#if !defined(BOARD_DATA_SZ)
#define BOARD_DATA_SZ AR6002_BOARD_DATA_SZ
#endif
/*
* Constants used by ASM code to access fields of host_interest_s,
* which is at a fixed location in RAM.
*/
#if defined(AR6002_REV4) || defined(AR6003) || defined(AR6002_REV6)
#define HOST_INTEREST_FLASH_IS_PRESENT_ADDR (AR6K_RAM_START + 0x60c)
#endif
#if !defined(HOST_INTEREST_FLASH_IS_PRESENT_ADDR)
#define HOST_INTEREST_FLASH_IS_PRESENT_ADDR (AR6K_RAM_START + 0x40c)
#endif
#define FLASH_IS_PRESENT_TARGADDR HOST_INTEREST_FLASH_IS_PRESENT_ADDR
#endif /* __ADDRS_H__ */
wlan/include/AR6002/hw4.0/hw/apb_athr_wlan_map.h
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// ------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2007, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _APB_ATHR_WLAN_MAP_H_
#define _APB_ATHR_WLAN_MAP_H_
#define WLAN_RTC_BASE_ADDRESS 0x00004000
#define WLAN_VMC_BASE_ADDRESS 0x00008000
#define WLAN_UART_BASE_ADDRESS 0x0000c000
#define WLAN_DBG_UART_BASE_ADDRESS 0x0000d000
#define WLAN_UMBOX_BASE_ADDRESS 0x0000e000
#define WLAN_SI_BASE_ADDRESS 0x00010000
#define WLAN_GPIO_BASE_ADDRESS 0x00014000
#define WLAN_MBOX_BASE_ADDRESS 0x00018000
#define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
#define WLAN_MAC_BASE_ADDRESS 0x00020000
#define WLAN_RDMA_BASE_ADDRESS 0x00030100
#define EFUSE_BASE_ADDRESS 0x00031000
#endif /* _APB_ATHR_WLAN_MAP_REG_H_ */
wlan/include/AR6002/hw4.0/hw/apb_map.h
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// ------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2007, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifdef WLAN_HEADERS
#include "apb_athr_wlan_map.h"
#ifndef BT_HEADERS
#define RTC_BASE_ADDRESS WLAN_RTC_BASE_ADDRESS
#define VMC_BASE_ADDRESS WLAN_VMC_BASE_ADDRESS
#define UART_BASE_ADDRESS WLAN_UART_BASE_ADDRESS
#define DBG_UART_BASE_ADDRESS WLAN_DBG_UART_BASE_ADDRESS
#define UMBOX_BASE_ADDRESS WLAN_UMBOX_BASE_ADDRESS
#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS
#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS
#define MBOX_BASE_ADDRESS WLAN_MBOX_BASE_ADDRESS
#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS
#define MAC_BASE_ADDRESS WLAN_MAC_BASE_ADDRESS
#define RDMA_BASE_ADDRESS WLAN_RDMA_BASE_ADDRESS
#endif
#endif
wlan/include/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h
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wlan/include/AR6002/hw4.0/hw/gpio_reg.h
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wlan/include/AR6002/hw4.0/hw/mbox_reg.h
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// ------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2007, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifdef WLAN_HEADERS
#include "mbox_wlan_reg.h"
#ifndef BT_HEADERS
#define MBOX_FIFO_ADDRESS WLAN_MBOX_FIFO_ADDRESS
#define MBOX_FIFO_OFFSET WLAN_MBOX_FIFO_OFFSET
#define MBOX_FIFO_DATA_MSB WLAN_MBOX_FIFO_DATA_MSB
#define MBOX_FIFO_DATA_LSB WLAN_MBOX_FIFO_DATA_LSB
#define MBOX_FIFO_DATA_MASK WLAN_MBOX_FIFO_DATA_MASK
#define MBOX_FIFO_DATA_GET(x) WLAN_MBOX_FIFO_DATA_GET(x)
#define MBOX_FIFO_DATA_SET(x) WLAN_MBOX_FIFO_DATA_SET(x)
#define MBOX_FIFO_STATUS_ADDRESS WLAN_MBOX_FIFO_STATUS_ADDRESS
#define MBOX_FIFO_STATUS_OFFSET WLAN_MBOX_FIFO_STATUS_OFFSET
#define MBOX_FIFO_STATUS_EMPTY_MSB WLAN_MBOX_FIFO_STATUS_EMPTY_MSB
#define MBOX_FIFO_STATUS_EMPTY_LSB WLAN_MBOX_FIFO_STATUS_EMPTY_LSB
#define MBOX_FIFO_STATUS_EMPTY_MASK WLAN_MBOX_FIFO_STATUS_EMPTY_MASK
#define MBOX_FIFO_STATUS_EMPTY_GET(x) WLAN_MBOX_FIFO_STATUS_EMPTY_GET(x)
#define MBOX_FIFO_STATUS_EMPTY_SET(x) WLAN_MBOX_FIFO_STATUS_EMPTY_SET(x)
#define MBOX_FIFO_STATUS_FULL_MSB WLAN_MBOX_FIFO_STATUS_FULL_MSB
#define MBOX_FIFO_STATUS_FULL_LSB WLAN_MBOX_FIFO_STATUS_FULL_LSB
#define MBOX_FIFO_STATUS_FULL_MASK WLAN_MBOX_FIFO_STATUS_FULL_MASK
#define MBOX_FIFO_STATUS_FULL_GET(x) WLAN_MBOX_FIFO_STATUS_FULL_GET(x)
#define MBOX_FIFO_STATUS_FULL_SET(x) WLAN_MBOX_FIFO_STATUS_FULL_SET(x)
#define MBOX_DMA_POLICY_ADDRESS WLAN_MBOX_DMA_POLICY_ADDRESS
#define MBOX_DMA_POLICY_OFFSET WLAN_MBOX_DMA_POLICY_OFFSET
#define MBOX_DMA_POLICY_TX_QUANTUM_MSB WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MSB
#define MBOX_DMA_POLICY_TX_QUANTUM_LSB WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB
#define MBOX_DMA_POLICY_TX_QUANTUM_MASK WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK
#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) WLAN_MBOX_DMA_POLICY_TX_QUANTUM_GET(x)
#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) WLAN_MBOX_DMA_POLICY_TX_QUANTUM_SET(x)
#define MBOX_DMA_POLICY_TX_ORDER_MSB WLAN_MBOX_DMA_POLICY_TX_ORDER_MSB
#define MBOX_DMA_POLICY_TX_ORDER_LSB WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB
#define MBOX_DMA_POLICY_TX_ORDER_MASK WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK
#define MBOX_DMA_POLICY_TX_ORDER_GET(x) WLAN_MBOX_DMA_POLICY_TX_ORDER_GET(x)
#define MBOX_DMA_POLICY_TX_ORDER_SET(x) WLAN_MBOX_DMA_POLICY_TX_ORDER_SET(x)
#define MBOX_DMA_POLICY_RX_QUANTUM_MSB WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MSB
#define MBOX_DMA_POLICY_RX_QUANTUM_LSB WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB
#define MBOX_DMA_POLICY_RX_QUANTUM_MASK WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK
#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) WLAN_MBOX_DMA_POLICY_RX_QUANTUM_GET(x)
#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) WLAN_MBOX_DMA_POLICY_RX_QUANTUM_SET(x)
#define MBOX_DMA_POLICY_RX_ORDER_MSB WLAN_MBOX_DMA_POLICY_RX_ORDER_MSB
#define MBOX_DMA_POLICY_RX_ORDER_LSB WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB
#define MBOX_DMA_POLICY_RX_ORDER_MASK WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK
#define MBOX_DMA_POLICY_RX_ORDER_GET(x) WLAN_MBOX_DMA_POLICY_RX_ORDER_GET(x)
#define MBOX_DMA_POLICY_RX_ORDER_SET(x) WLAN_MBOX_DMA_POLICY_RX_ORDER_SET(x)
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
#define MBOX0_DMA_RX_CONTROL_ADDRESS WLAN_MBOX0_DMA_RX_CONTROL_ADDRESS
#define MBOX0_DMA_RX_CONTROL_OFFSET WLAN_MBOX0_DMA_RX_CONTROL_OFFSET
#define MBOX0_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MSB
#define MBOX0_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB
#define MBOX0_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK
#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_RESUME_GET(x)
#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_RESUME_SET(x)
#define MBOX0_DMA_RX_CONTROL_START_MSB WLAN_MBOX0_DMA_RX_CONTROL_START_MSB
#define MBOX0_DMA_RX_CONTROL_START_LSB WLAN_MBOX0_DMA_RX_CONTROL_START_LSB
#define MBOX0_DMA_RX_CONTROL_START_MASK WLAN_MBOX0_DMA_RX_CONTROL_START_MASK
#define MBOX0_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_START_GET(x)
#define MBOX0_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_START_SET(x)
#define MBOX0_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX0_DMA_RX_CONTROL_STOP_MSB
#define MBOX0_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB
#define MBOX0_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK
#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_STOP_GET(x)
#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_STOP_SET(x)
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
#define MBOX0_DMA_TX_CONTROL_ADDRESS WLAN_MBOX0_DMA_TX_CONTROL_ADDRESS
#define MBOX0_DMA_TX_CONTROL_OFFSET WLAN_MBOX0_DMA_TX_CONTROL_OFFSET
#define MBOX0_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MSB
#define MBOX0_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB
#define MBOX0_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK
#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_RESUME_GET(x)
#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_RESUME_SET(x)
#define MBOX0_DMA_TX_CONTROL_START_MSB WLAN_MBOX0_DMA_TX_CONTROL_START_MSB
#define MBOX0_DMA_TX_CONTROL_START_LSB WLAN_MBOX0_DMA_TX_CONTROL_START_LSB
#define MBOX0_DMA_TX_CONTROL_START_MASK WLAN_MBOX0_DMA_TX_CONTROL_START_MASK
#define MBOX0_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_START_GET(x)
#define MBOX0_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_START_SET(x)
#define MBOX0_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX0_DMA_TX_CONTROL_STOP_MSB
#define MBOX0_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB
#define MBOX0_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK
#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_STOP_GET(x)
#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_STOP_SET(x)
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
#define MBOX1_DMA_RX_CONTROL_ADDRESS WLAN_MBOX1_DMA_RX_CONTROL_ADDRESS
#define MBOX1_DMA_RX_CONTROL_OFFSET WLAN_MBOX1_DMA_RX_CONTROL_OFFSET
#define MBOX1_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MSB
#define MBOX1_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB
#define MBOX1_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK
#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_RESUME_GET(x)
#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_RESUME_SET(x)
#define MBOX1_DMA_RX_CONTROL_START_MSB WLAN_MBOX1_DMA_RX_CONTROL_START_MSB
#define MBOX1_DMA_RX_CONTROL_START_LSB WLAN_MBOX1_DMA_RX_CONTROL_START_LSB
#define MBOX1_DMA_RX_CONTROL_START_MASK WLAN_MBOX1_DMA_RX_CONTROL_START_MASK
#define MBOX1_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_START_GET(x)
#define MBOX1_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_START_SET(x)
#define MBOX1_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX1_DMA_RX_CONTROL_STOP_MSB
#define MBOX1_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB
#define MBOX1_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK
#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_STOP_GET(x)
#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_STOP_SET(x)
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
#define MBOX1_DMA_TX_CONTROL_ADDRESS WLAN_MBOX1_DMA_TX_CONTROL_ADDRESS
#define MBOX1_DMA_TX_CONTROL_OFFSET WLAN_MBOX1_DMA_TX_CONTROL_OFFSET
#define MBOX1_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MSB
#define MBOX1_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB
#define MBOX1_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK
#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_RESUME_GET(x)
#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_RESUME_SET(x)
#define MBOX1_DMA_TX_CONTROL_START_MSB WLAN_MBOX1_DMA_TX_CONTROL_START_MSB
#define MBOX1_DMA_TX_CONTROL_START_LSB WLAN_MBOX1_DMA_TX_CONTROL_START_LSB
#define MBOX1_DMA_TX_CONTROL_START_MASK WLAN_MBOX1_DMA_TX_CONTROL_START_MASK
#define MBOX1_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_START_GET(x)
#define MBOX1_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_START_SET(x)
#define MBOX1_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX1_DMA_TX_CONTROL_STOP_MSB
#define MBOX1_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB
#define MBOX1_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK
#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_STOP_GET(x)
#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_STOP_SET(x)
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
#define MBOX2_DMA_RX_CONTROL_ADDRESS WLAN_MBOX2_DMA_RX_CONTROL_ADDRESS
#define MBOX2_DMA_RX_CONTROL_OFFSET WLAN_MBOX2_DMA_RX_CONTROL_OFFSET
#define MBOX2_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MSB
#define MBOX2_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB
#define MBOX2_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK
#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_RESUME_GET(x)
#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_RESUME_SET(x)
#define MBOX2_DMA_RX_CONTROL_START_MSB WLAN_MBOX2_DMA_RX_CONTROL_START_MSB
#define MBOX2_DMA_RX_CONTROL_START_LSB WLAN_MBOX2_DMA_RX_CONTROL_START_LSB
#define MBOX2_DMA_RX_CONTROL_START_MASK WLAN_MBOX2_DMA_RX_CONTROL_START_MASK
#define MBOX2_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_START_GET(x)
#define MBOX2_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_START_SET(x)
#define MBOX2_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX2_DMA_RX_CONTROL_STOP_MSB
#define MBOX2_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB
#define MBOX2_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK
#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_STOP_GET(x)
#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_STOP_SET(x)
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
#define MBOX2_DMA_TX_CONTROL_ADDRESS WLAN_MBOX2_DMA_TX_CONTROL_ADDRESS
#define MBOX2_DMA_TX_CONTROL_OFFSET WLAN_MBOX2_DMA_TX_CONTROL_OFFSET
#define MBOX2_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MSB
#define MBOX2_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB
#define MBOX2_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK
#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_RESUME_GET(x)
#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_RESUME_SET(x)
#define MBOX2_DMA_TX_CONTROL_START_MSB WLAN_MBOX2_DMA_TX_CONTROL_START_MSB
#define MBOX2_DMA_TX_CONTROL_START_LSB WLAN_MBOX2_DMA_TX_CONTROL_START_LSB
#define MBOX2_DMA_TX_CONTROL_START_MASK WLAN_MBOX2_DMA_TX_CONTROL_START_MASK
#define MBOX2_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_START_GET(x)
#define MBOX2_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_START_SET(x)
#define MBOX2_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX2_DMA_TX_CONTROL_STOP_MSB
#define MBOX2_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB
#define MBOX2_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK
#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_STOP_GET(x)
#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_STOP_SET(x)
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
#define MBOX3_DMA_RX_CONTROL_ADDRESS WLAN_MBOX3_DMA_RX_CONTROL_ADDRESS
#define MBOX3_DMA_RX_CONTROL_OFFSET WLAN_MBOX3_DMA_RX_CONTROL_OFFSET
#define MBOX3_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MSB
#define MBOX3_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB
#define MBOX3_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK
#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_RESUME_GET(x)
#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_RESUME_SET(x)
#define MBOX3_DMA_RX_CONTROL_START_MSB WLAN_MBOX3_DMA_RX_CONTROL_START_MSB
#define MBOX3_DMA_RX_CONTROL_START_LSB WLAN_MBOX3_DMA_RX_CONTROL_START_LSB
#define MBOX3_DMA_RX_CONTROL_START_MASK WLAN_MBOX3_DMA_RX_CONTROL_START_MASK
#define MBOX3_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_START_GET(x)
#define MBOX3_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_START_SET(x)
#define MBOX3_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX3_DMA_RX_CONTROL_STOP_MSB
#define MBOX3_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB
#define MBOX3_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK
#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_STOP_GET(x)
#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_STOP_SET(x)
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
#define MBOX3_DMA_TX_CONTROL_ADDRESS WLAN_MBOX3_DMA_TX_CONTROL_ADDRESS
#define MBOX3_DMA_TX_CONTROL_OFFSET WLAN_MBOX3_DMA_TX_CONTROL_OFFSET
#define MBOX3_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MSB
#define MBOX3_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB
#define MBOX3_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK
#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_RESUME_GET(x)
#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_RESUME_SET(x)
#define MBOX3_DMA_TX_CONTROL_START_MSB WLAN_MBOX3_DMA_TX_CONTROL_START_MSB
#define MBOX3_DMA_TX_CONTROL_START_LSB WLAN_MBOX3_DMA_TX_CONTROL_START_LSB
#define MBOX3_DMA_TX_CONTROL_START_MASK WLAN_MBOX3_DMA_TX_CONTROL_START_MASK
#define MBOX3_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_START_GET(x)
#define MBOX3_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_START_SET(x)
#define MBOX3_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX3_DMA_TX_CONTROL_STOP_MSB
#define MBOX3_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB
#define MBOX3_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK
#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_STOP_GET(x)
#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_STOP_SET(x)
#define MBOX_INT_STATUS_ADDRESS WLAN_MBOX_INT_STATUS_ADDRESS
#define MBOX_INT_STATUS_OFFSET WLAN_MBOX_INT_STATUS_OFFSET
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x)
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x)
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x)
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x)
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x)
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x)
#define MBOX_INT_STATUS_TX_OVERFLOW_MSB WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MSB
#define MBOX_INT_STATUS_TX_OVERFLOW_LSB WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB
#define MBOX_INT_STATUS_TX_OVERFLOW_MASK WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK
#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) WLAN_MBOX_INT_STATUS_TX_OVERFLOW_GET(x)
#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) WLAN_MBOX_INT_STATUS_TX_OVERFLOW_SET(x)
#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MSB
#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB
#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK
#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET(x)
#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET(x)
#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MSB
#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB
#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK
#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x)
#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x)
#define MBOX_INT_STATUS_RX_NOT_FULL_MSB WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MSB
#define MBOX_INT_STATUS_RX_NOT_FULL_LSB WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB
#define MBOX_INT_STATUS_RX_NOT_FULL_MASK WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK
#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) WLAN_MBOX_INT_STATUS_RX_NOT_FULL_GET(x)
#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) WLAN_MBOX_INT_STATUS_RX_NOT_FULL_SET(x)
#define MBOX_INT_STATUS_HOST_MSB WLAN_MBOX_INT_STATUS_HOST_MSB
#define MBOX_INT_STATUS_HOST_LSB WLAN_MBOX_INT_STATUS_HOST_LSB
#define MBOX_INT_STATUS_HOST_MASK WLAN_MBOX_INT_STATUS_HOST_MASK
#define MBOX_INT_STATUS_HOST_GET(x) WLAN_MBOX_INT_STATUS_HOST_GET(x)
#define MBOX_INT_STATUS_HOST_SET(x) WLAN_MBOX_INT_STATUS_HOST_SET(x)
#define MBOX_INT_ENABLE_ADDRESS WLAN_MBOX_INT_ENABLE_ADDRESS
#define MBOX_INT_ENABLE_OFFSET WLAN_MBOX_INT_ENABLE_OFFSET
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x)
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x)
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x)
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x)
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x)
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x)
#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MSB
#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB
#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK
#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET(x)
#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET(x)
#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MSB
#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB
#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK
#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x)
#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x)
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x)
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x)
#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MSB
#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB
#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK
#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET(x)
#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET(x)
#define MBOX_INT_ENABLE_HOST_MSB WLAN_MBOX_INT_ENABLE_HOST_MSB
#define MBOX_INT_ENABLE_HOST_LSB WLAN_MBOX_INT_ENABLE_HOST_LSB
#define MBOX_INT_ENABLE_HOST_MASK WLAN_MBOX_INT_ENABLE_HOST_MASK
#define MBOX_INT_ENABLE_HOST_GET(x) WLAN_MBOX_INT_ENABLE_HOST_GET(x)
#define MBOX_INT_ENABLE_HOST_SET(x) WLAN_MBOX_INT_ENABLE_HOST_SET(x)
#define INT_HOST_ADDRESS WLAN_INT_HOST_ADDRESS
#define INT_HOST_OFFSET WLAN_INT_HOST_OFFSET
#define INT_HOST_VECTOR_MSB WLAN_INT_HOST_VECTOR_MSB
#define INT_HOST_VECTOR_LSB WLAN_INT_HOST_VECTOR_LSB
#define INT_HOST_VECTOR_MASK WLAN_INT_HOST_VECTOR_MASK
#define INT_HOST_VECTOR_GET(x) WLAN_INT_HOST_VECTOR_GET(x)
#define INT_HOST_VECTOR_SET(x) WLAN_INT_HOST_VECTOR_SET(x)
#define LOCAL_COUNT_ADDRESS WLAN_LOCAL_COUNT_ADDRESS
#define LOCAL_COUNT_OFFSET WLAN_LOCAL_COUNT_OFFSET
#define LOCAL_COUNT_VALUE_MSB WLAN_LOCAL_COUNT_VALUE_MSB
#define LOCAL_COUNT_VALUE_LSB WLAN_LOCAL_COUNT_VALUE_LSB
#define LOCAL_COUNT_VALUE_MASK WLAN_LOCAL_COUNT_VALUE_MASK
#define LOCAL_COUNT_VALUE_GET(x) WLAN_LOCAL_COUNT_VALUE_GET(x)
#define LOCAL_COUNT_VALUE_SET(x) WLAN_LOCAL_COUNT_VALUE_SET(x)
#define COUNT_INC_ADDRESS WLAN_COUNT_INC_ADDRESS
#define COUNT_INC_OFFSET WLAN_COUNT_INC_OFFSET
#define COUNT_INC_VALUE_MSB WLAN_COUNT_INC_VALUE_MSB
#define COUNT_INC_VALUE_LSB WLAN_COUNT_INC_VALUE_LSB
#define COUNT_INC_VALUE_MASK WLAN_COUNT_INC_VALUE_MASK
#define COUNT_INC_VALUE_GET(x) WLAN_COUNT_INC_VALUE_GET(x)
#define COUNT_INC_VALUE_SET(x) WLAN_COUNT_INC_VALUE_SET(x)
#define LOCAL_SCRATCH_ADDRESS WLAN_LOCAL_SCRATCH_ADDRESS
#define LOCAL_SCRATCH_OFFSET WLAN_LOCAL_SCRATCH_OFFSET
#define LOCAL_SCRATCH_VALUE_MSB WLAN_LOCAL_SCRATCH_VALUE_MSB
#define LOCAL_SCRATCH_VALUE_LSB WLAN_LOCAL_SCRATCH_VALUE_LSB
#define LOCAL_SCRATCH_VALUE_MASK WLAN_LOCAL_SCRATCH_VALUE_MASK
#define LOCAL_SCRATCH_VALUE_GET(x) WLAN_LOCAL_SCRATCH_VALUE_GET(x)
#define LOCAL_SCRATCH_VALUE_SET(x) WLAN_LOCAL_SCRATCH_VALUE_SET(x)
#define USE_LOCAL_BUS_ADDRESS WLAN_USE_LOCAL_BUS_ADDRESS
#define USE_LOCAL_BUS_OFFSET WLAN_USE_LOCAL_BUS_OFFSET
#define USE_LOCAL_BUS_PIN_INIT_MSB WLAN_USE_LOCAL_BUS_PIN_INIT_MSB
#define USE_LOCAL_BUS_PIN_INIT_LSB WLAN_USE_LOCAL_BUS_PIN_INIT_LSB
#define USE_LOCAL_BUS_PIN_INIT_MASK WLAN_USE_LOCAL_BUS_PIN_INIT_MASK
#define USE_LOCAL_BUS_PIN_INIT_GET(x) WLAN_USE_LOCAL_BUS_PIN_INIT_GET(x)
#define USE_LOCAL_BUS_PIN_INIT_SET(x) WLAN_USE_LOCAL_BUS_PIN_INIT_SET(x)
#define SDIO_CONFIG_ADDRESS WLAN_SDIO_CONFIG_ADDRESS
#define SDIO_CONFIG_OFFSET WLAN_SDIO_CONFIG_OFFSET
#define SDIO_CONFIG_CCCR_IOR1_MSB WLAN_SDIO_CONFIG_CCCR_IOR1_MSB
#define SDIO_CONFIG_CCCR_IOR1_LSB WLAN_SDIO_CONFIG_CCCR_IOR1_LSB
#define SDIO_CONFIG_CCCR_IOR1_MASK WLAN_SDIO_CONFIG_CCCR_IOR1_MASK
#define SDIO_CONFIG_CCCR_IOR1_GET(x) WLAN_SDIO_CONFIG_CCCR_IOR1_GET(x)
#define SDIO_CONFIG_CCCR_IOR1_SET(x) WLAN_SDIO_CONFIG_CCCR_IOR1_SET(x)
#define MBOX_DEBUG_ADDRESS WLAN_MBOX_DEBUG_ADDRESS
#define MBOX_DEBUG_OFFSET WLAN_MBOX_DEBUG_OFFSET
#define MBOX_DEBUG_SEL_MSB WLAN_MBOX_DEBUG_SEL_MSB
#define MBOX_DEBUG_SEL_LSB WLAN_MBOX_DEBUG_SEL_LSB
#define MBOX_DEBUG_SEL_MASK WLAN_MBOX_DEBUG_SEL_MASK
#define MBOX_DEBUG_SEL_GET(x) WLAN_MBOX_DEBUG_SEL_GET(x)
#define MBOX_DEBUG_SEL_SET(x) WLAN_MBOX_DEBUG_SEL_SET(x)
#define MBOX_FIFO_RESET_ADDRESS WLAN_MBOX_FIFO_RESET_ADDRESS
#define MBOX_FIFO_RESET_OFFSET WLAN_MBOX_FIFO_RESET_OFFSET
#define MBOX_FIFO_RESET_INIT_MSB WLAN_MBOX_FIFO_RESET_INIT_MSB
#define MBOX_FIFO_RESET_INIT_LSB WLAN_MBOX_FIFO_RESET_INIT_LSB
#define MBOX_FIFO_RESET_INIT_MASK WLAN_MBOX_FIFO_RESET_INIT_MASK
#define MBOX_FIFO_RESET_INIT_GET(x) WLAN_MBOX_FIFO_RESET_INIT_GET(x)
#define MBOX_FIFO_RESET_INIT_SET(x) WLAN_MBOX_FIFO_RESET_INIT_SET(x)
#define MBOX_TXFIFO_POP_ADDRESS WLAN_MBOX_TXFIFO_POP_ADDRESS
#define MBOX_TXFIFO_POP_OFFSET WLAN_MBOX_TXFIFO_POP_OFFSET
#define MBOX_TXFIFO_POP_DATA_MSB WLAN_MBOX_TXFIFO_POP_DATA_MSB
#define MBOX_TXFIFO_POP_DATA_LSB WLAN_MBOX_TXFIFO_POP_DATA_LSB
#define MBOX_TXFIFO_POP_DATA_MASK WLAN_MBOX_TXFIFO_POP_DATA_MASK
#define MBOX_TXFIFO_POP_DATA_GET(x) WLAN_MBOX_TXFIFO_POP_DATA_GET(x)
#define MBOX_TXFIFO_POP_DATA_SET(x) WLAN_MBOX_TXFIFO_POP_DATA_SET(x)
#define MBOX_RXFIFO_POP_ADDRESS WLAN_MBOX_RXFIFO_POP_ADDRESS
#define MBOX_RXFIFO_POP_OFFSET WLAN_MBOX_RXFIFO_POP_OFFSET
#define MBOX_RXFIFO_POP_DATA_MSB WLAN_MBOX_RXFIFO_POP_DATA_MSB
#define MBOX_RXFIFO_POP_DATA_LSB WLAN_MBOX_RXFIFO_POP_DATA_LSB
#define MBOX_RXFIFO_POP_DATA_MASK WLAN_MBOX_RXFIFO_POP_DATA_MASK
#define MBOX_RXFIFO_POP_DATA_GET(x) WLAN_MBOX_RXFIFO_POP_DATA_GET(x)
#define MBOX_RXFIFO_POP_DATA_SET(x) WLAN_MBOX_RXFIFO_POP_DATA_SET(x)
#define SDIO_DEBUG_ADDRESS WLAN_SDIO_DEBUG_ADDRESS
#define SDIO_DEBUG_OFFSET WLAN_SDIO_DEBUG_OFFSET
#define SDIO_DEBUG_SEL_MSB WLAN_SDIO_DEBUG_SEL_MSB
#define SDIO_DEBUG_SEL_LSB WLAN_SDIO_DEBUG_SEL_LSB
#define SDIO_DEBUG_SEL_MASK WLAN_SDIO_DEBUG_SEL_MASK
#define SDIO_DEBUG_SEL_GET(x) WLAN_SDIO_DEBUG_SEL_GET(x)
#define SDIO_DEBUG_SEL_SET(x) WLAN_SDIO_DEBUG_SEL_SET(x)
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
#define GMBOX0_DMA_RX_CONTROL_ADDRESS WLAN_GMBOX0_DMA_RX_CONTROL_ADDRESS
#define GMBOX0_DMA_RX_CONTROL_OFFSET WLAN_GMBOX0_DMA_RX_CONTROL_OFFSET
#define GMBOX0_DMA_RX_CONTROL_RESUME_MSB WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MSB
#define GMBOX0_DMA_RX_CONTROL_RESUME_LSB WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB
#define GMBOX0_DMA_RX_CONTROL_RESUME_MASK WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK
#define GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_GET(x)
#define GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_SET(x)
#define GMBOX0_DMA_RX_CONTROL_START_MSB WLAN_GMBOX0_DMA_RX_CONTROL_START_MSB
#define GMBOX0_DMA_RX_CONTROL_START_LSB WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB
#define GMBOX0_DMA_RX_CONTROL_START_MASK WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK
#define GMBOX0_DMA_RX_CONTROL_START_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_START_GET(x)
#define GMBOX0_DMA_RX_CONTROL_START_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_START_SET(x)
#define GMBOX0_DMA_RX_CONTROL_STOP_MSB WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MSB
#define GMBOX0_DMA_RX_CONTROL_STOP_LSB WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB
#define GMBOX0_DMA_RX_CONTROL_STOP_MASK WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK
#define GMBOX0_DMA_RX_CONTROL_STOP_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_STOP_GET(x)
#define GMBOX0_DMA_RX_CONTROL_STOP_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_STOP_SET(x)
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
#define GMBOX0_DMA_TX_CONTROL_ADDRESS WLAN_GMBOX0_DMA_TX_CONTROL_ADDRESS
#define GMBOX0_DMA_TX_CONTROL_OFFSET WLAN_GMBOX0_DMA_TX_CONTROL_OFFSET
#define GMBOX0_DMA_TX_CONTROL_RESUME_MSB WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MSB
#define GMBOX0_DMA_TX_CONTROL_RESUME_LSB WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB
#define GMBOX0_DMA_TX_CONTROL_RESUME_MASK WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK
#define GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_GET(x)
#define GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_SET(x)
#define GMBOX0_DMA_TX_CONTROL_START_MSB WLAN_GMBOX0_DMA_TX_CONTROL_START_MSB
#define GMBOX0_DMA_TX_CONTROL_START_LSB WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB
#define GMBOX0_DMA_TX_CONTROL_START_MASK WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK
#define GMBOX0_DMA_TX_CONTROL_START_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_START_GET(x)
#define GMBOX0_DMA_TX_CONTROL_START_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_START_SET(x)
#define GMBOX0_DMA_TX_CONTROL_STOP_MSB WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MSB
#define GMBOX0_DMA_TX_CONTROL_STOP_LSB WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB
#define GMBOX0_DMA_TX_CONTROL_STOP_MASK WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK
#define GMBOX0_DMA_TX_CONTROL_STOP_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_STOP_GET(x)
#define GMBOX0_DMA_TX_CONTROL_STOP_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_STOP_SET(x)
#define GMBOX_INT_STATUS_ADDRESS WLAN_GMBOX_INT_STATUS_ADDRESS
#define GMBOX_INT_STATUS_OFFSET WLAN_GMBOX_INT_STATUS_OFFSET
#define GMBOX_INT_STATUS_TX_OVERFLOW_MSB WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MSB
#define GMBOX_INT_STATUS_TX_OVERFLOW_LSB WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB
#define GMBOX_INT_STATUS_TX_OVERFLOW_MASK WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK
#define GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_GET(x)
#define GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_SET(x)
#define GMBOX_INT_STATUS_RX_UNDERFLOW_MSB WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MSB
#define GMBOX_INT_STATUS_RX_UNDERFLOW_LSB WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB
#define GMBOX_INT_STATUS_RX_UNDERFLOW_MASK WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK
#define GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x)
#define GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x)
#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB
#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB
#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK
#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x)
#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x)
#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB
#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB
#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK
#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x)
#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x)
#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB
#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB
#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK
#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x)
#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x)
#define GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB
#define GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB
#define GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK
#define GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x)
#define GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x)
#define GMBOX_INT_STATUS_RX_NOT_FULL_MSB WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MSB
#define GMBOX_INT_STATUS_RX_NOT_FULL_LSB WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB
#define GMBOX_INT_STATUS_RX_NOT_FULL_MASK WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK
#define GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_GET(x)
#define GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_SET(x)
#define GMBOX_INT_ENABLE_ADDRESS WLAN_GMBOX_INT_ENABLE_ADDRESS
#define GMBOX_INT_ENABLE_OFFSET WLAN_GMBOX_INT_ENABLE_OFFSET
#define GMBOX_INT_ENABLE_TX_OVERFLOW_MSB WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MSB
#define GMBOX_INT_ENABLE_TX_OVERFLOW_LSB WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB
#define GMBOX_INT_ENABLE_TX_OVERFLOW_MASK WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK
#define GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x)
#define GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x)
#define GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB
#define GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB
#define GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK
#define GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x)
#define GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x)
#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB
#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB
#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK
#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x)
#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x)
#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB
#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB
#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK
#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x)
#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x)
#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB
#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB
#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK
#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x)
#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x)
#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB
#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB
#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK
#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x)
#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x)
#define GMBOX_INT_ENABLE_RX_NOT_FULL_MSB WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MSB
#define GMBOX_INT_ENABLE_RX_NOT_FULL_LSB WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB
#define GMBOX_INT_ENABLE_RX_NOT_FULL_MASK WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK
#define GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x)
#define GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x)
#define HOST_IF_WINDOW_ADDRESS WLAN_HOST_IF_WINDOW_ADDRESS
#define HOST_IF_WINDOW_OFFSET WLAN_HOST_IF_WINDOW_OFFSET
#define HOST_IF_WINDOW_DATA_MSB WLAN_HOST_IF_WINDOW_DATA_MSB
#define HOST_IF_WINDOW_DATA_LSB WLAN_HOST_IF_WINDOW_DATA_LSB
#define HOST_IF_WINDOW_DATA_MASK WLAN_HOST_IF_WINDOW_DATA_MASK
#define HOST_IF_WINDOW_DATA_GET(x) WLAN_HOST_IF_WINDOW_DATA_GET(x)
#define HOST_IF_WINDOW_DATA_SET(x) WLAN_HOST_IF_WINDOW_DATA_SET(x)
#endif
#endif
wlan/include/AR6002/hw4.0/hw/mbox_wlan_host_reg.h
+526
View File
@@ -0,0 +1,526 @@
// ------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2007, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _MBOX_WLAN_HOST_REG_REG_H_
#define _MBOX_WLAN_HOST_REG_REG_H_
#define HOST_INT_STATUS_ADDRESS 0x00000400
#define HOST_INT_STATUS_OFFSET 0x00000400
#define HOST_INT_STATUS_ERROR_MSB 7
#define HOST_INT_STATUS_ERROR_LSB 7
#define HOST_INT_STATUS_ERROR_MASK 0x00000080
#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
#define HOST_INT_STATUS_CPU_MSB 6
#define HOST_INT_STATUS_CPU_LSB 6
#define HOST_INT_STATUS_CPU_MASK 0x00000040
#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
#define HOST_INT_STATUS_INT_MSB 5
#define HOST_INT_STATUS_INT_LSB 5
#define HOST_INT_STATUS_INT_MASK 0x00000020
#define HOST_INT_STATUS_INT_GET(x) (((x) & HOST_INT_STATUS_INT_MASK) >> HOST_INT_STATUS_INT_LSB)
#define HOST_INT_STATUS_INT_SET(x) (((x) << HOST_INT_STATUS_INT_LSB) & HOST_INT_STATUS_INT_MASK)
#define HOST_INT_STATUS_COUNTER_MSB 4
#define HOST_INT_STATUS_COUNTER_LSB 4
#define HOST_INT_STATUS_COUNTER_MASK 0x00000010
#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
#define HOST_INT_STATUS_MBOX_DATA_MSB 3
#define HOST_INT_STATUS_MBOX_DATA_LSB 0
#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f
#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB)
#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK)
#define CPU_INT_STATUS_ADDRESS 0x00000401
#define CPU_INT_STATUS_OFFSET 0x00000401
#define CPU_INT_STATUS_BIT_MSB 7
#define CPU_INT_STATUS_BIT_LSB 0
#define CPU_INT_STATUS_BIT_MASK 0x000000ff
#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB)
#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK)
#define ERROR_INT_STATUS_ADDRESS 0x00000402
#define ERROR_INT_STATUS_OFFSET 0x00000402
#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MSB 6
#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB 6
#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040
#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB)
#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK)
#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MSB 5
#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB 5
#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020
#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB)
#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK)
#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MSB 4
#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB 4
#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010
#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB)
#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK)
#define ERROR_INT_STATUS_SPI_MSB 3
#define ERROR_INT_STATUS_SPI_LSB 3
#define ERROR_INT_STATUS_SPI_MASK 0x00000008
#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB)
#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK)
#define ERROR_INT_STATUS_WAKEUP_MSB 2
#define ERROR_INT_STATUS_WAKEUP_LSB 2
#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004
#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1
#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1
#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0
#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0
#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
#define COUNTER_INT_STATUS_ADDRESS 0x00000403
#define COUNTER_INT_STATUS_OFFSET 0x00000403
#define COUNTER_INT_STATUS_COUNTER_MSB 7
#define COUNTER_INT_STATUS_COUNTER_LSB 0
#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff
#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB)
#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK)
#define MBOX_FRAME_ADDRESS 0x00000404
#define MBOX_FRAME_OFFSET 0x00000404
#define MBOX_FRAME_RX_EOM_MSB 7
#define MBOX_FRAME_RX_EOM_LSB 4
#define MBOX_FRAME_RX_EOM_MASK 0x000000f0
#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB)
#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK)
#define MBOX_FRAME_RX_SOM_MSB 3
#define MBOX_FRAME_RX_SOM_LSB 0
#define MBOX_FRAME_RX_SOM_MASK 0x0000000f
#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB)
#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK)
#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405
#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405
#define RX_LOOKAHEAD_VALID_MBOX_MSB 3
#define RX_LOOKAHEAD_VALID_MBOX_LSB 0
#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f
#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB)
#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK)
#define HOST_INT_STATUS2_ADDRESS 0x00000406
#define HOST_INT_STATUS2_OFFSET 0x00000406
#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MSB 2
#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB 2
#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK 0x00000004
#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB)
#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK)
#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MSB 1
#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB 1
#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK 0x00000002
#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB)
#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK)
#define HOST_INT_STATUS2_GMBOX_DATA_MSB 0
#define HOST_INT_STATUS2_GMBOX_DATA_LSB 0
#define HOST_INT_STATUS2_GMBOX_DATA_MASK 0x00000001
#define HOST_INT_STATUS2_GMBOX_DATA_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_DATA_MASK) >> HOST_INT_STATUS2_GMBOX_DATA_LSB)
#define HOST_INT_STATUS2_GMBOX_DATA_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_DATA_LSB) & HOST_INT_STATUS2_GMBOX_DATA_MASK)
#define GMBOX_RX_AVAIL_ADDRESS 0x00000407
#define GMBOX_RX_AVAIL_OFFSET 0x00000407
#define GMBOX_RX_AVAIL_BYTE_MSB 6
#define GMBOX_RX_AVAIL_BYTE_LSB 0
#define GMBOX_RX_AVAIL_BYTE_MASK 0x0000007f
#define GMBOX_RX_AVAIL_BYTE_GET(x) (((x) & GMBOX_RX_AVAIL_BYTE_MASK) >> GMBOX_RX_AVAIL_BYTE_LSB)
#define GMBOX_RX_AVAIL_BYTE_SET(x) (((x) << GMBOX_RX_AVAIL_BYTE_LSB) & GMBOX_RX_AVAIL_BYTE_MASK)
#define RX_LOOKAHEAD0_ADDRESS 0x00000408
#define RX_LOOKAHEAD0_OFFSET 0x00000408
#define RX_LOOKAHEAD0_DATA_MSB 7
#define RX_LOOKAHEAD0_DATA_LSB 0
#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff
#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB)
#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK)
#define RX_LOOKAHEAD1_ADDRESS 0x0000040c
#define RX_LOOKAHEAD1_OFFSET 0x0000040c
#define RX_LOOKAHEAD1_DATA_MSB 7
#define RX_LOOKAHEAD1_DATA_LSB 0
#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff
#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB)
#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK)
#define RX_LOOKAHEAD2_ADDRESS 0x00000410
#define RX_LOOKAHEAD2_OFFSET 0x00000410
#define RX_LOOKAHEAD2_DATA_MSB 7
#define RX_LOOKAHEAD2_DATA_LSB 0
#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff
#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB)
#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK)
#define RX_LOOKAHEAD3_ADDRESS 0x00000414
#define RX_LOOKAHEAD3_OFFSET 0x00000414
#define RX_LOOKAHEAD3_DATA_MSB 7
#define RX_LOOKAHEAD3_DATA_LSB 0
#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff
#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB)
#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK)
#define INT_STATUS_ENABLE_ADDRESS 0x00000418
#define INT_STATUS_ENABLE_OFFSET 0x00000418
#define INT_STATUS_ENABLE_ERROR_MSB 7
#define INT_STATUS_ENABLE_ERROR_LSB 7
#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080
#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
#define INT_STATUS_ENABLE_CPU_MSB 6
#define INT_STATUS_ENABLE_CPU_LSB 6
#define INT_STATUS_ENABLE_CPU_MASK 0x00000040
#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
#define INT_STATUS_ENABLE_INT_MSB 5
#define INT_STATUS_ENABLE_INT_LSB 5
#define INT_STATUS_ENABLE_INT_MASK 0x00000020
#define INT_STATUS_ENABLE_INT_GET(x) (((x) & INT_STATUS_ENABLE_INT_MASK) >> INT_STATUS_ENABLE_INT_LSB)
#define INT_STATUS_ENABLE_INT_SET(x) (((x) << INT_STATUS_ENABLE_INT_LSB) & INT_STATUS_ENABLE_INT_MASK)
#define INT_STATUS_ENABLE_COUNTER_MSB 4
#define INT_STATUS_ENABLE_COUNTER_LSB 4
#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3
#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0
#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419
#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419
#define CPU_INT_STATUS_ENABLE_BIT_MSB 7
#define CPU_INT_STATUS_ENABLE_BIT_LSB 0
#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a
#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MSB 6
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB 6
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB)
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK)
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MSB 5
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB 5
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB)
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK)
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MSB 4
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB 4
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB)
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK)
#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2
#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2
#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004
#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB)
#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK)
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b
#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b
#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7
#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
#define COUNT_ADDRESS 0x00000420
#define COUNT_OFFSET 0x00000420
#define COUNT_VALUE_MSB 7
#define COUNT_VALUE_LSB 0
#define COUNT_VALUE_MASK 0x000000ff
#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB)
#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK)
#define COUNT_DEC_ADDRESS 0x00000440
#define COUNT_DEC_OFFSET 0x00000440
#define COUNT_DEC_VALUE_MSB 7
#define COUNT_DEC_VALUE_LSB 0
#define COUNT_DEC_VALUE_MASK 0x000000ff
#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB)
#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK)
#define SCRATCH_ADDRESS 0x00000460
#define SCRATCH_OFFSET 0x00000460
#define SCRATCH_VALUE_MSB 7
#define SCRATCH_VALUE_LSB 0
#define SCRATCH_VALUE_MASK 0x000000ff
#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB)
#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK)
#define FIFO_TIMEOUT_ADDRESS 0x00000468
#define FIFO_TIMEOUT_OFFSET 0x00000468
#define FIFO_TIMEOUT_VALUE_MSB 7
#define FIFO_TIMEOUT_VALUE_LSB 0
#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff
#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB)
#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK)
#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469
#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469
#define FIFO_TIMEOUT_ENABLE_SET_MSB 0
#define FIFO_TIMEOUT_ENABLE_SET_LSB 0
#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001
#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB)
#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK)
#define DISABLE_SLEEP_ADDRESS 0x0000046a
#define DISABLE_SLEEP_OFFSET 0x0000046a
#define DISABLE_SLEEP_FOR_INT_MSB 1
#define DISABLE_SLEEP_FOR_INT_LSB 1
#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002
#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB)
#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK)
#define DISABLE_SLEEP_ON_MSB 0
#define DISABLE_SLEEP_ON_LSB 0
#define DISABLE_SLEEP_ON_MASK 0x00000001
#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB)
#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK)
#define LOCAL_BUS_ADDRESS 0x00000470
#define LOCAL_BUS_OFFSET 0x00000470
#define LOCAL_BUS_STATE_MSB 1
#define LOCAL_BUS_STATE_LSB 0
#define LOCAL_BUS_STATE_MASK 0x00000003
#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB)
#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK)
#define INT_WLAN_ADDRESS 0x00000472
#define INT_WLAN_OFFSET 0x00000472
#define INT_WLAN_VECTOR_MSB 7
#define INT_WLAN_VECTOR_LSB 0
#define INT_WLAN_VECTOR_MASK 0x000000ff
#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB)
#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK)
#define WINDOW_DATA_ADDRESS 0x00000474
#define WINDOW_DATA_OFFSET 0x00000474
#define WINDOW_DATA_DATA_MSB 7
#define WINDOW_DATA_DATA_LSB 0
#define WINDOW_DATA_DATA_MASK 0x000000ff
#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB)
#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK)
#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478
#define WINDOW_WRITE_ADDR_OFFSET 0x00000478
#define WINDOW_WRITE_ADDR_ADDR_MSB 7
#define WINDOW_WRITE_ADDR_ADDR_LSB 0
#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff
#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB)
#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK)
#define WINDOW_READ_ADDR_ADDRESS 0x0000047c
#define WINDOW_READ_ADDR_OFFSET 0x0000047c
#define WINDOW_READ_ADDR_ADDR_MSB 7
#define WINDOW_READ_ADDR_ADDR_LSB 0
#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff
#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB)
#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK)
#define HOST_CTRL_SPI_CONFIG_ADDRESS 0x00000480
#define HOST_CTRL_SPI_CONFIG_OFFSET 0x00000480
#define HOST_CTRL_SPI_CONFIG_SPI_RESET_MSB 4
#define HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB 4
#define HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK 0x00000010
#define HOST_CTRL_SPI_CONFIG_SPI_RESET_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK) >> HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB)
#define HOST_CTRL_SPI_CONFIG_SPI_RESET_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK)
#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MSB 3
#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB 3
#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008
#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB)
#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK)
#define HOST_CTRL_SPI_CONFIG_TEST_MODE_MSB 2
#define HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB 2
#define HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK 0x00000004
#define HOST_CTRL_SPI_CONFIG_TEST_MODE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK) >> HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB)
#define HOST_CTRL_SPI_CONFIG_TEST_MODE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK)
#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MSB 1
#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB 0
#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK 0x00000003
#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK) >> HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB)
#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK)
#define HOST_CTRL_SPI_STATUS_ADDRESS 0x00000481
#define HOST_CTRL_SPI_STATUS_OFFSET 0x00000481
#define HOST_CTRL_SPI_STATUS_ADDR_ERR_MSB 3
#define HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB 3
#define HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK 0x00000008
#define HOST_CTRL_SPI_STATUS_ADDR_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB)
#define HOST_CTRL_SPI_STATUS_ADDR_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK)
#define HOST_CTRL_SPI_STATUS_RD_ERR_MSB 2
#define HOST_CTRL_SPI_STATUS_RD_ERR_LSB 2
#define HOST_CTRL_SPI_STATUS_RD_ERR_MASK 0x00000004
#define HOST_CTRL_SPI_STATUS_RD_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK) >> HOST_CTRL_SPI_STATUS_RD_ERR_LSB)
#define HOST_CTRL_SPI_STATUS_RD_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_RD_ERR_LSB) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK)
#define HOST_CTRL_SPI_STATUS_WR_ERR_MSB 1
#define HOST_CTRL_SPI_STATUS_WR_ERR_LSB 1
#define HOST_CTRL_SPI_STATUS_WR_ERR_MASK 0x00000002
#define HOST_CTRL_SPI_STATUS_WR_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_WR_ERR_LSB)
#define HOST_CTRL_SPI_STATUS_WR_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_WR_ERR_LSB) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK)
#define HOST_CTRL_SPI_STATUS_READY_MSB 0
#define HOST_CTRL_SPI_STATUS_READY_LSB 0
#define HOST_CTRL_SPI_STATUS_READY_MASK 0x00000001
#define HOST_CTRL_SPI_STATUS_READY_GET(x) (((x) & HOST_CTRL_SPI_STATUS_READY_MASK) >> HOST_CTRL_SPI_STATUS_READY_LSB)
#define HOST_CTRL_SPI_STATUS_READY_SET(x) (((x) << HOST_CTRL_SPI_STATUS_READY_LSB) & HOST_CTRL_SPI_STATUS_READY_MASK)
#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482
#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482
#define NON_ASSOC_SLEEP_EN_BIT_MSB 0
#define NON_ASSOC_SLEEP_EN_BIT_LSB 0
#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001
#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB)
#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK)
#define CPU_DBG_SEL_ADDRESS 0x00000483
#define CPU_DBG_SEL_OFFSET 0x00000483
#define CPU_DBG_SEL_BIT_MSB 5
#define CPU_DBG_SEL_BIT_LSB 0
#define CPU_DBG_SEL_BIT_MASK 0x0000003f
#define CPU_DBG_SEL_BIT_GET(x) (((x) & CPU_DBG_SEL_BIT_MASK) >> CPU_DBG_SEL_BIT_LSB)
#define CPU_DBG_SEL_BIT_SET(x) (((x) << CPU_DBG_SEL_BIT_LSB) & CPU_DBG_SEL_BIT_MASK)
#define CPU_DBG_ADDRESS 0x00000484
#define CPU_DBG_OFFSET 0x00000484
#define CPU_DBG_DATA_MSB 7
#define CPU_DBG_DATA_LSB 0
#define CPU_DBG_DATA_MASK 0x000000ff
#define CPU_DBG_DATA_GET(x) (((x) & CPU_DBG_DATA_MASK) >> CPU_DBG_DATA_LSB)
#define CPU_DBG_DATA_SET(x) (((x) << CPU_DBG_DATA_LSB) & CPU_DBG_DATA_MASK)
#define INT_STATUS2_ENABLE_ADDRESS 0x00000488
#define INT_STATUS2_ENABLE_OFFSET 0x00000488
#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MSB 2
#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB 2
#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK 0x00000004
#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB)
#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK)
#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MSB 1
#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB 1
#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK 0x00000002
#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB)
#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK)
#define INT_STATUS2_ENABLE_GMBOX_DATA_MSB 0
#define INT_STATUS2_ENABLE_GMBOX_DATA_LSB 0
#define INT_STATUS2_ENABLE_GMBOX_DATA_MASK 0x00000001
#define INT_STATUS2_ENABLE_GMBOX_DATA_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK) >> INT_STATUS2_ENABLE_GMBOX_DATA_LSB)
#define INT_STATUS2_ENABLE_GMBOX_DATA_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_DATA_LSB) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK)
#define GMBOX_RX_LOOKAHEAD_ADDRESS 0x00000490
#define GMBOX_RX_LOOKAHEAD_OFFSET 0x00000490
#define GMBOX_RX_LOOKAHEAD_DATA_MSB 7
#define GMBOX_RX_LOOKAHEAD_DATA_LSB 0
#define GMBOX_RX_LOOKAHEAD_DATA_MASK 0x000000ff
#define GMBOX_RX_LOOKAHEAD_DATA_GET(x) (((x) & GMBOX_RX_LOOKAHEAD_DATA_MASK) >> GMBOX_RX_LOOKAHEAD_DATA_LSB)
#define GMBOX_RX_LOOKAHEAD_DATA_SET(x) (((x) << GMBOX_RX_LOOKAHEAD_DATA_LSB) & GMBOX_RX_LOOKAHEAD_DATA_MASK)
#define GMBOX_RX_LOOKAHEAD_MUX_ADDRESS 0x00000498
#define GMBOX_RX_LOOKAHEAD_MUX_OFFSET 0x00000498
#define GMBOX_RX_LOOKAHEAD_MUX_SEL_MSB 0
#define GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB 0
#define GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK 0x00000001
#define GMBOX_RX_LOOKAHEAD_MUX_SEL_GET(x) (((x) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK) >> GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB)
#define GMBOX_RX_LOOKAHEAD_MUX_SEL_SET(x) (((x) << GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK)
#define CIS_WINDOW_ADDRESS 0x00000600
#define CIS_WINDOW_OFFSET 0x00000600
#define CIS_WINDOW_DATA_MSB 7
#define CIS_WINDOW_DATA_LSB 0
#define CIS_WINDOW_DATA_MASK 0x000000ff
#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB)
#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
#ifndef __ASSEMBLER__
typedef struct mbox_wlan_host_reg_reg_s {
unsigned char pad0[1024]; /* pad to 0x400 */
volatile unsigned char host_int_status;
volatile unsigned char cpu_int_status;
volatile unsigned char error_int_status;
volatile unsigned char counter_int_status;
volatile unsigned char mbox_frame;
volatile unsigned char rx_lookahead_valid;
volatile unsigned char host_int_status2;
volatile unsigned char gmbox_rx_avail;
volatile unsigned char rx_lookahead0[4];
volatile unsigned char rx_lookahead1[4];
volatile unsigned char rx_lookahead2[4];
volatile unsigned char rx_lookahead3[4];
volatile unsigned char int_status_enable;
volatile unsigned char cpu_int_status_enable;
volatile unsigned char error_status_enable;
volatile unsigned char counter_int_status_enable;
unsigned char pad1[4]; /* pad to 0x420 */
volatile unsigned char count[8];
unsigned char pad2[24]; /* pad to 0x440 */
volatile unsigned char count_dec[32];
volatile unsigned char scratch[8];
volatile unsigned char fifo_timeout;
volatile unsigned char fifo_timeout_enable;
volatile unsigned char disable_sleep;
unsigned char pad3[5]; /* pad to 0x470 */
volatile unsigned char local_bus;
unsigned char pad4[1]; /* pad to 0x472 */
volatile unsigned char int_wlan;
unsigned char pad5[1]; /* pad to 0x474 */
volatile unsigned char window_data[4];
volatile unsigned char window_write_addr[4];
volatile unsigned char window_read_addr[4];
volatile unsigned char host_ctrl_spi_config;
volatile unsigned char host_ctrl_spi_status;
volatile unsigned char non_assoc_sleep_en;
volatile unsigned char cpu_dbg_sel;
volatile unsigned char cpu_dbg[4];
volatile unsigned char int_status2_enable;
unsigned char pad6[7]; /* pad to 0x490 */
volatile unsigned char gmbox_rx_lookahead[8];
volatile unsigned char gmbox_rx_lookahead_mux;
unsigned char pad7[359]; /* pad to 0x600 */
volatile unsigned char cis_window[512];
} mbox_wlan_host_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _MBOX_WLAN_HOST_REG_H_ */
wlan/include/AR6002/hw4.0/hw/mbox_wlan_reg.h
+642
View File
@@ -0,0 +1,642 @@
// ------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2007, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _MBOX_WLAN_REG_REG_H_
#define _MBOX_WLAN_REG_REG_H_
#define WLAN_MBOX_FIFO_ADDRESS 0x00000000
#define WLAN_MBOX_FIFO_OFFSET 0x00000000
#define WLAN_MBOX_FIFO_DATA_MSB 19
#define WLAN_MBOX_FIFO_DATA_LSB 0
#define WLAN_MBOX_FIFO_DATA_MASK 0x000fffff
#define WLAN_MBOX_FIFO_DATA_GET(x) (((x) & WLAN_MBOX_FIFO_DATA_MASK) >> WLAN_MBOX_FIFO_DATA_LSB)
#define WLAN_MBOX_FIFO_DATA_SET(x) (((x) << WLAN_MBOX_FIFO_DATA_LSB) & WLAN_MBOX_FIFO_DATA_MASK)
#define WLAN_MBOX_FIFO_STATUS_ADDRESS 0x00000010
#define WLAN_MBOX_FIFO_STATUS_OFFSET 0x00000010
#define WLAN_MBOX_FIFO_STATUS_EMPTY_MSB 19
#define WLAN_MBOX_FIFO_STATUS_EMPTY_LSB 16
#define WLAN_MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000
#define WLAN_MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & WLAN_MBOX_FIFO_STATUS_EMPTY_MASK) >> WLAN_MBOX_FIFO_STATUS_EMPTY_LSB)
#define WLAN_MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << WLAN_MBOX_FIFO_STATUS_EMPTY_LSB) & WLAN_MBOX_FIFO_STATUS_EMPTY_MASK)
#define WLAN_MBOX_FIFO_STATUS_FULL_MSB 15
#define WLAN_MBOX_FIFO_STATUS_FULL_LSB 12
#define WLAN_MBOX_FIFO_STATUS_FULL_MASK 0x0000f000
#define WLAN_MBOX_FIFO_STATUS_FULL_GET(x) (((x) & WLAN_MBOX_FIFO_STATUS_FULL_MASK) >> WLAN_MBOX_FIFO_STATUS_FULL_LSB)
#define WLAN_MBOX_FIFO_STATUS_FULL_SET(x) (((x) << WLAN_MBOX_FIFO_STATUS_FULL_LSB) & WLAN_MBOX_FIFO_STATUS_FULL_MASK)
#define WLAN_MBOX_DMA_POLICY_ADDRESS 0x00000014
#define WLAN_MBOX_DMA_POLICY_OFFSET 0x00000014
#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MSB 3
#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB 3
#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008
#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB)
#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB) & WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK)
#define WLAN_MBOX_DMA_POLICY_TX_ORDER_MSB 2
#define WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB 2
#define WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004
#define WLAN_MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK) >> WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB)
#define WLAN_MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB) & WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK)
#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MSB 1
#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB 1
#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002
#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB)
#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB) & WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK)
#define WLAN_MBOX_DMA_POLICY_RX_ORDER_MSB 0
#define WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB 0
#define WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001
#define WLAN_MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK) >> WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB)
#define WLAN_MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB) & WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK)
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define WLAN_MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c
#define WLAN_MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c
#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MSB 2
#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB 2
#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB)
#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK)
#define WLAN_MBOX0_DMA_RX_CONTROL_START_MSB 1
#define WLAN_MBOX0_DMA_RX_CONTROL_START_LSB 1
#define WLAN_MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
#define WLAN_MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_START_LSB)
#define WLAN_MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_START_MASK)
#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_MSB 0
#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB 0
#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB)
#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK)
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define WLAN_MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024
#define WLAN_MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024
#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MSB 2
#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB 2
#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB)
#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK)
#define WLAN_MBOX0_DMA_TX_CONTROL_START_MSB 1
#define WLAN_MBOX0_DMA_TX_CONTROL_START_LSB 1
#define WLAN_MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
#define WLAN_MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_START_LSB)
#define WLAN_MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_START_MASK)
#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_MSB 0
#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB 0
#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB)
#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK)
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define WLAN_MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c
#define WLAN_MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c
#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MSB 2
#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB 2
#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB)
#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK)
#define WLAN_MBOX1_DMA_RX_CONTROL_START_MSB 1
#define WLAN_MBOX1_DMA_RX_CONTROL_START_LSB 1
#define WLAN_MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002
#define WLAN_MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_START_LSB)
#define WLAN_MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_START_MASK)
#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_MSB 0
#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB 0
#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB)
#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK)
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define WLAN_MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034
#define WLAN_MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034
#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MSB 2
#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB 2
#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB)
#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK)
#define WLAN_MBOX1_DMA_TX_CONTROL_START_MSB 1
#define WLAN_MBOX1_DMA_TX_CONTROL_START_LSB 1
#define WLAN_MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002
#define WLAN_MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_START_LSB)
#define WLAN_MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_START_MASK)
#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_MSB 0
#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB 0
#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB)
#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK)
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define WLAN_MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c
#define WLAN_MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c
#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MSB 2
#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB 2
#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB)
#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK)
#define WLAN_MBOX2_DMA_RX_CONTROL_START_MSB 1
#define WLAN_MBOX2_DMA_RX_CONTROL_START_LSB 1
#define WLAN_MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002
#define WLAN_MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_START_LSB)
#define WLAN_MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_START_MASK)
#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_MSB 0
#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB 0
#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB)
#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK)
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define WLAN_MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044
#define WLAN_MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044
#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MSB 2
#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB 2
#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB)
#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK)
#define WLAN_MBOX2_DMA_TX_CONTROL_START_MSB 1
#define WLAN_MBOX2_DMA_TX_CONTROL_START_LSB 1
#define WLAN_MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002
#define WLAN_MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_START_LSB)
#define WLAN_MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_START_MASK)
#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_MSB 0
#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB 0
#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB)
#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK)
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define WLAN_MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c
#define WLAN_MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c
#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MSB 2
#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB 2
#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB)
#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK)
#define WLAN_MBOX3_DMA_RX_CONTROL_START_MSB 1
#define WLAN_MBOX3_DMA_RX_CONTROL_START_LSB 1
#define WLAN_MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002
#define WLAN_MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_START_LSB)
#define WLAN_MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_START_MASK)
#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_MSB 0
#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB 0
#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB)
#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK)
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define WLAN_MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054
#define WLAN_MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054
#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MSB 2
#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB 2
#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB)
#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK)
#define WLAN_MBOX3_DMA_TX_CONTROL_START_MSB 1
#define WLAN_MBOX3_DMA_TX_CONTROL_START_LSB 1
#define WLAN_MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002
#define WLAN_MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_START_LSB)
#define WLAN_MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_START_MASK)
#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_MSB 0
#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB 0
#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB)
#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK)
#define WLAN_MBOX_INT_STATUS_ADDRESS 0x00000058
#define WLAN_MBOX_INT_STATUS_OFFSET 0x00000058
#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31
#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28
#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000
#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27
#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24
#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23
#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20
#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000
#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MSB 17
#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB 17
#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000
#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB)
#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB) & WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK)
#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16
#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16
#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000
#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB)
#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK)
#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15
#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12
#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000
#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MSB 11
#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB 8
#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00
#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB)
#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB) & WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK)
#define WLAN_MBOX_INT_STATUS_HOST_MSB 7
#define WLAN_MBOX_INT_STATUS_HOST_LSB 0
#define WLAN_MBOX_INT_STATUS_HOST_MASK 0x000000ff
#define WLAN_MBOX_INT_STATUS_HOST_GET(x) (((x) & WLAN_MBOX_INT_STATUS_HOST_MASK) >> WLAN_MBOX_INT_STATUS_HOST_LSB)
#define WLAN_MBOX_INT_STATUS_HOST_SET(x) (((x) << WLAN_MBOX_INT_STATUS_HOST_LSB) & WLAN_MBOX_INT_STATUS_HOST_MASK)
#define WLAN_MBOX_INT_ENABLE_ADDRESS 0x0000005c
#define WLAN_MBOX_INT_ENABLE_OFFSET 0x0000005c
#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31
#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28
#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000
#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27
#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24
#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23
#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20
#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000
#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17
#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17
#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000
#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB)
#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK)
#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16
#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16
#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000
#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15
#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12
#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000
#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11
#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8
#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00
#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB)
#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK)
#define WLAN_MBOX_INT_ENABLE_HOST_MSB 7
#define WLAN_MBOX_INT_ENABLE_HOST_LSB 0
#define WLAN_MBOX_INT_ENABLE_HOST_MASK 0x000000ff
#define WLAN_MBOX_INT_ENABLE_HOST_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_HOST_MASK) >> WLAN_MBOX_INT_ENABLE_HOST_LSB)
#define WLAN_MBOX_INT_ENABLE_HOST_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_HOST_LSB) & WLAN_MBOX_INT_ENABLE_HOST_MASK)
#define WLAN_INT_HOST_ADDRESS 0x00000060
#define WLAN_INT_HOST_OFFSET 0x00000060
#define WLAN_INT_HOST_VECTOR_MSB 7
#define WLAN_INT_HOST_VECTOR_LSB 0
#define WLAN_INT_HOST_VECTOR_MASK 0x000000ff
#define WLAN_INT_HOST_VECTOR_GET(x) (((x) & WLAN_INT_HOST_VECTOR_MASK) >> WLAN_INT_HOST_VECTOR_LSB)
#define WLAN_INT_HOST_VECTOR_SET(x) (((x) << WLAN_INT_HOST_VECTOR_LSB) & WLAN_INT_HOST_VECTOR_MASK)
#define WLAN_LOCAL_COUNT_ADDRESS 0x00000080
#define WLAN_LOCAL_COUNT_OFFSET 0x00000080
#define WLAN_LOCAL_COUNT_VALUE_MSB 7
#define WLAN_LOCAL_COUNT_VALUE_LSB 0
#define WLAN_LOCAL_COUNT_VALUE_MASK 0x000000ff
#define WLAN_LOCAL_COUNT_VALUE_GET(x) (((x) & WLAN_LOCAL_COUNT_VALUE_MASK) >> WLAN_LOCAL_COUNT_VALUE_LSB)
#define WLAN_LOCAL_COUNT_VALUE_SET(x) (((x) << WLAN_LOCAL_COUNT_VALUE_LSB) & WLAN_LOCAL_COUNT_VALUE_MASK)
#define WLAN_COUNT_INC_ADDRESS 0x000000a0
#define WLAN_COUNT_INC_OFFSET 0x000000a0
#define WLAN_COUNT_INC_VALUE_MSB 7
#define WLAN_COUNT_INC_VALUE_LSB 0
#define WLAN_COUNT_INC_VALUE_MASK 0x000000ff
#define WLAN_COUNT_INC_VALUE_GET(x) (((x) & WLAN_COUNT_INC_VALUE_MASK) >> WLAN_COUNT_INC_VALUE_LSB)
#define WLAN_COUNT_INC_VALUE_SET(x) (((x) << WLAN_COUNT_INC_VALUE_LSB) & WLAN_COUNT_INC_VALUE_MASK)
#define WLAN_LOCAL_SCRATCH_ADDRESS 0x000000c0
#define WLAN_LOCAL_SCRATCH_OFFSET 0x000000c0
#define WLAN_LOCAL_SCRATCH_VALUE_MSB 7
#define WLAN_LOCAL_SCRATCH_VALUE_LSB 0
#define WLAN_LOCAL_SCRATCH_VALUE_MASK 0x000000ff
#define WLAN_LOCAL_SCRATCH_VALUE_GET(x) (((x) & WLAN_LOCAL_SCRATCH_VALUE_MASK) >> WLAN_LOCAL_SCRATCH_VALUE_LSB)
#define WLAN_LOCAL_SCRATCH_VALUE_SET(x) (((x) << WLAN_LOCAL_SCRATCH_VALUE_LSB) & WLAN_LOCAL_SCRATCH_VALUE_MASK)
#define WLAN_USE_LOCAL_BUS_ADDRESS 0x000000e0
#define WLAN_USE_LOCAL_BUS_OFFSET 0x000000e0
#define WLAN_USE_LOCAL_BUS_PIN_INIT_MSB 0
#define WLAN_USE_LOCAL_BUS_PIN_INIT_LSB 0
#define WLAN_USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001
#define WLAN_USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & WLAN_USE_LOCAL_BUS_PIN_INIT_MASK) >> WLAN_USE_LOCAL_BUS_PIN_INIT_LSB)
#define WLAN_USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << WLAN_USE_LOCAL_BUS_PIN_INIT_LSB) & WLAN_USE_LOCAL_BUS_PIN_INIT_MASK)
#define WLAN_SDIO_CONFIG_ADDRESS 0x000000e4
#define WLAN_SDIO_CONFIG_OFFSET 0x000000e4
#define WLAN_SDIO_CONFIG_CCCR_IOR1_MSB 0
#define WLAN_SDIO_CONFIG_CCCR_IOR1_LSB 0
#define WLAN_SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001
#define WLAN_SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & WLAN_SDIO_CONFIG_CCCR_IOR1_MASK) >> WLAN_SDIO_CONFIG_CCCR_IOR1_LSB)
#define WLAN_SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << WLAN_SDIO_CONFIG_CCCR_IOR1_LSB) & WLAN_SDIO_CONFIG_CCCR_IOR1_MASK)
#define WLAN_MBOX_DEBUG_ADDRESS 0x000000e8
#define WLAN_MBOX_DEBUG_OFFSET 0x000000e8
#define WLAN_MBOX_DEBUG_SEL_MSB 2
#define WLAN_MBOX_DEBUG_SEL_LSB 0
#define WLAN_MBOX_DEBUG_SEL_MASK 0x00000007
#define WLAN_MBOX_DEBUG_SEL_GET(x) (((x) & WLAN_MBOX_DEBUG_SEL_MASK) >> WLAN_MBOX_DEBUG_SEL_LSB)
#define WLAN_MBOX_DEBUG_SEL_SET(x) (((x) << WLAN_MBOX_DEBUG_SEL_LSB) & WLAN_MBOX_DEBUG_SEL_MASK)
#define WLAN_MBOX_FIFO_RESET_ADDRESS 0x000000ec
#define WLAN_MBOX_FIFO_RESET_OFFSET 0x000000ec
#define WLAN_MBOX_FIFO_RESET_INIT_MSB 0
#define WLAN_MBOX_FIFO_RESET_INIT_LSB 0
#define WLAN_MBOX_FIFO_RESET_INIT_MASK 0x00000001
#define WLAN_MBOX_FIFO_RESET_INIT_GET(x) (((x) & WLAN_MBOX_FIFO_RESET_INIT_MASK) >> WLAN_MBOX_FIFO_RESET_INIT_LSB)
#define WLAN_MBOX_FIFO_RESET_INIT_SET(x) (((x) << WLAN_MBOX_FIFO_RESET_INIT_LSB) & WLAN_MBOX_FIFO_RESET_INIT_MASK)
#define WLAN_MBOX_TXFIFO_POP_ADDRESS 0x000000f0
#define WLAN_MBOX_TXFIFO_POP_OFFSET 0x000000f0
#define WLAN_MBOX_TXFIFO_POP_DATA_MSB 0
#define WLAN_MBOX_TXFIFO_POP_DATA_LSB 0
#define WLAN_MBOX_TXFIFO_POP_DATA_MASK 0x00000001
#define WLAN_MBOX_TXFIFO_POP_DATA_GET(x) (((x) & WLAN_MBOX_TXFIFO_POP_DATA_MASK) >> WLAN_MBOX_TXFIFO_POP_DATA_LSB)
#define WLAN_MBOX_TXFIFO_POP_DATA_SET(x) (((x) << WLAN_MBOX_TXFIFO_POP_DATA_LSB) & WLAN_MBOX_TXFIFO_POP_DATA_MASK)
#define WLAN_MBOX_RXFIFO_POP_ADDRESS 0x00000100
#define WLAN_MBOX_RXFIFO_POP_OFFSET 0x00000100
#define WLAN_MBOX_RXFIFO_POP_DATA_MSB 0
#define WLAN_MBOX_RXFIFO_POP_DATA_LSB 0
#define WLAN_MBOX_RXFIFO_POP_DATA_MASK 0x00000001
#define WLAN_MBOX_RXFIFO_POP_DATA_GET(x) (((x) & WLAN_MBOX_RXFIFO_POP_DATA_MASK) >> WLAN_MBOX_RXFIFO_POP_DATA_LSB)
#define WLAN_MBOX_RXFIFO_POP_DATA_SET(x) (((x) << WLAN_MBOX_RXFIFO_POP_DATA_LSB) & WLAN_MBOX_RXFIFO_POP_DATA_MASK)
#define WLAN_SDIO_DEBUG_ADDRESS 0x00000110
#define WLAN_SDIO_DEBUG_OFFSET 0x00000110
#define WLAN_SDIO_DEBUG_SEL_MSB 3
#define WLAN_SDIO_DEBUG_SEL_LSB 0
#define WLAN_SDIO_DEBUG_SEL_MASK 0x0000000f
#define WLAN_SDIO_DEBUG_SEL_GET(x) (((x) & WLAN_SDIO_DEBUG_SEL_MASK) >> WLAN_SDIO_DEBUG_SEL_LSB)
#define WLAN_SDIO_DEBUG_SEL_SET(x) (((x) << WLAN_SDIO_DEBUG_SEL_LSB) & WLAN_SDIO_DEBUG_SEL_MASK)
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000114
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000114
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define WLAN_GMBOX0_DMA_RX_CONTROL_ADDRESS 0x00000118
#define WLAN_GMBOX0_DMA_RX_CONTROL_OFFSET 0x00000118
#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MSB 2
#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB 2
#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB)
#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK)
#define WLAN_GMBOX0_DMA_RX_CONTROL_START_MSB 1
#define WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB 1
#define WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
#define WLAN_GMBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB)
#define WLAN_GMBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK)
#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MSB 0
#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB 0
#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB)
#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK)
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x0000011c
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x0000011c
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define WLAN_GMBOX0_DMA_TX_CONTROL_ADDRESS 0x00000120
#define WLAN_GMBOX0_DMA_TX_CONTROL_OFFSET 0x00000120
#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MSB 2
#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB 2
#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB)
#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK)
#define WLAN_GMBOX0_DMA_TX_CONTROL_START_MSB 1
#define WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB 1
#define WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
#define WLAN_GMBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB)
#define WLAN_GMBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK)
#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MSB 0
#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB 0
#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB)
#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK)
#define WLAN_GMBOX_INT_STATUS_ADDRESS 0x00000124
#define WLAN_GMBOX_INT_STATUS_OFFSET 0x00000124
#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MSB 6
#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB 6
#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00000040
#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB)
#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB) & WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK)
#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MSB 5
#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB 5
#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00000020
#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB)
#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK)
#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 4
#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 4
#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0x00000010
#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 3
#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 3
#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000008
#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 2
#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 2
#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00000004
#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB 1
#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB 1
#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x00000002
#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MSB 0
#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB 0
#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000001
#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB)
#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB) & WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK)
#define WLAN_GMBOX_INT_ENABLE_ADDRESS 0x00000128
#define WLAN_GMBOX_INT_ENABLE_OFFSET 0x00000128
#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MSB 6
#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB 6
#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00000040
#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB)
#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK)
#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB 5
#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB 5
#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00000020
#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 4
#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 4
#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0x00000010
#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 3
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 3
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000008
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 2
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 2
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00000004
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 1
#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 1
#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x00000002
#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MSB 0
#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB 0
#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000001
#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB)
#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK)
#define WLAN_HOST_IF_WINDOW_ADDRESS 0x00002000
#define WLAN_HOST_IF_WINDOW_OFFSET 0x00002000
#define WLAN_HOST_IF_WINDOW_DATA_MSB 7
#define WLAN_HOST_IF_WINDOW_DATA_LSB 0
#define WLAN_HOST_IF_WINDOW_DATA_MASK 0x000000ff
#define WLAN_HOST_IF_WINDOW_DATA_GET(x) (((x) & WLAN_HOST_IF_WINDOW_DATA_MASK) >> WLAN_HOST_IF_WINDOW_DATA_LSB)
#define WLAN_HOST_IF_WINDOW_DATA_SET(x) (((x) << WLAN_HOST_IF_WINDOW_DATA_LSB) & WLAN_HOST_IF_WINDOW_DATA_MASK)
#ifndef __ASSEMBLER__
typedef struct mbox_wlan_reg_reg_s {
volatile unsigned int wlan_mbox_fifo[4];
volatile unsigned int wlan_mbox_fifo_status;
volatile unsigned int wlan_mbox_dma_policy;
volatile unsigned int wlan_mbox0_dma_rx_descriptor_base;
volatile unsigned int wlan_mbox0_dma_rx_control;
volatile unsigned int wlan_mbox0_dma_tx_descriptor_base;
volatile unsigned int wlan_mbox0_dma_tx_control;
volatile unsigned int wlan_mbox1_dma_rx_descriptor_base;
volatile unsigned int wlan_mbox1_dma_rx_control;
volatile unsigned int wlan_mbox1_dma_tx_descriptor_base;
volatile unsigned int wlan_mbox1_dma_tx_control;
volatile unsigned int wlan_mbox2_dma_rx_descriptor_base;
volatile unsigned int wlan_mbox2_dma_rx_control;
volatile unsigned int wlan_mbox2_dma_tx_descriptor_base;
volatile unsigned int wlan_mbox2_dma_tx_control;
volatile unsigned int wlan_mbox3_dma_rx_descriptor_base;
volatile unsigned int wlan_mbox3_dma_rx_control;
volatile unsigned int wlan_mbox3_dma_tx_descriptor_base;
volatile unsigned int wlan_mbox3_dma_tx_control;
volatile unsigned int wlan_mbox_int_status;
volatile unsigned int wlan_mbox_int_enable;
volatile unsigned int wlan_int_host;
unsigned char pad0[28]; /* pad to 0x80 */
volatile unsigned int wlan_local_count[8];
volatile unsigned int wlan_count_inc[8];
volatile unsigned int wlan_local_scratch[8];
volatile unsigned int wlan_use_local_bus;
volatile unsigned int wlan_sdio_config;
volatile unsigned int wlan_mbox_debug;
volatile unsigned int wlan_mbox_fifo_reset;
volatile unsigned int wlan_mbox_txfifo_pop[4];
volatile unsigned int wlan_mbox_rxfifo_pop[4];
volatile unsigned int wlan_sdio_debug;
volatile unsigned int wlan_gmbox0_dma_rx_descriptor_base;
volatile unsigned int wlan_gmbox0_dma_rx_control;
volatile unsigned int wlan_gmbox0_dma_tx_descriptor_base;
volatile unsigned int wlan_gmbox0_dma_tx_control;
volatile unsigned int wlan_gmbox_int_status;
volatile unsigned int wlan_gmbox_int_enable;
unsigned char pad1[7892]; /* pad to 0x2000 */
volatile unsigned int wlan_host_if_window[2048];
} mbox_wlan_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _MBOX_WLAN_REG_H_ */
wlan/include/AR6002/hw4.0/hw/rtc_reg.h
+979
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@@ -0,0 +1,979 @@
// ------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2007, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifdef WLAN_HEADERS
#include "rtc_wlan_reg.h"
#ifndef BT_HEADERS
#define RESET_CONTROL_ADDRESS WLAN_RESET_CONTROL_ADDRESS
#define RESET_CONTROL_OFFSET WLAN_RESET_CONTROL_OFFSET
#define RESET_CONTROL_DEBUG_UART_RST_MSB WLAN_RESET_CONTROL_DEBUG_UART_RST_MSB
#define RESET_CONTROL_DEBUG_UART_RST_LSB WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB
#define RESET_CONTROL_DEBUG_UART_RST_MASK WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK
#define RESET_CONTROL_DEBUG_UART_RST_GET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_GET(x)
#define RESET_CONTROL_DEBUG_UART_RST_SET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_SET(x)
#define RESET_CONTROL_BB_COLD_RST_MSB WLAN_RESET_CONTROL_BB_COLD_RST_MSB
#define RESET_CONTROL_BB_COLD_RST_LSB WLAN_RESET_CONTROL_BB_COLD_RST_LSB
#define RESET_CONTROL_BB_COLD_RST_MASK WLAN_RESET_CONTROL_BB_COLD_RST_MASK
#define RESET_CONTROL_BB_COLD_RST_GET(x) WLAN_RESET_CONTROL_BB_COLD_RST_GET(x)
#define RESET_CONTROL_BB_COLD_RST_SET(x) WLAN_RESET_CONTROL_BB_COLD_RST_SET(x)
#define RESET_CONTROL_BB_WARM_RST_MSB WLAN_RESET_CONTROL_BB_WARM_RST_MSB
#define RESET_CONTROL_BB_WARM_RST_LSB WLAN_RESET_CONTROL_BB_WARM_RST_LSB
#define RESET_CONTROL_BB_WARM_RST_MASK WLAN_RESET_CONTROL_BB_WARM_RST_MASK
#define RESET_CONTROL_BB_WARM_RST_GET(x) WLAN_RESET_CONTROL_BB_WARM_RST_GET(x)
#define RESET_CONTROL_BB_WARM_RST_SET(x) WLAN_RESET_CONTROL_BB_WARM_RST_SET(x)
#define RESET_CONTROL_CPU_INIT_RESET_MSB WLAN_RESET_CONTROL_CPU_INIT_RESET_MSB
#define RESET_CONTROL_CPU_INIT_RESET_LSB WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB
#define RESET_CONTROL_CPU_INIT_RESET_MASK WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK
#define RESET_CONTROL_CPU_INIT_RESET_GET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_GET(x)
#define RESET_CONTROL_CPU_INIT_RESET_SET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_SET(x)
#define RESET_CONTROL_VMC_REMAP_RESET_MSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_MSB
#define RESET_CONTROL_VMC_REMAP_RESET_LSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB
#define RESET_CONTROL_VMC_REMAP_RESET_MASK WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK
#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_GET(x)
#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_SET(x)
#define RESET_CONTROL_RST_OUT_MSB WLAN_RESET_CONTROL_RST_OUT_MSB
#define RESET_CONTROL_RST_OUT_LSB WLAN_RESET_CONTROL_RST_OUT_LSB
#define RESET_CONTROL_RST_OUT_MASK WLAN_RESET_CONTROL_RST_OUT_MASK
#define RESET_CONTROL_RST_OUT_GET(x) WLAN_RESET_CONTROL_RST_OUT_GET(x)
#define RESET_CONTROL_RST_OUT_SET(x) WLAN_RESET_CONTROL_RST_OUT_SET(x)
#define RESET_CONTROL_COLD_RST_MSB WLAN_RESET_CONTROL_COLD_RST_MSB
#define RESET_CONTROL_COLD_RST_LSB WLAN_RESET_CONTROL_COLD_RST_LSB
#define RESET_CONTROL_COLD_RST_MASK WLAN_RESET_CONTROL_COLD_RST_MASK
#define RESET_CONTROL_COLD_RST_GET(x) WLAN_RESET_CONTROL_COLD_RST_GET(x)
#define RESET_CONTROL_COLD_RST_SET(x) WLAN_RESET_CONTROL_COLD_RST_SET(x)
#define RESET_CONTROL_WARM_RST_MSB WLAN_RESET_CONTROL_WARM_RST_MSB
#define RESET_CONTROL_WARM_RST_LSB WLAN_RESET_CONTROL_WARM_RST_LSB
#define RESET_CONTROL_WARM_RST_MASK WLAN_RESET_CONTROL_WARM_RST_MASK
#define RESET_CONTROL_WARM_RST_GET(x) WLAN_RESET_CONTROL_WARM_RST_GET(x)
#define RESET_CONTROL_WARM_RST_SET(x) WLAN_RESET_CONTROL_WARM_RST_SET(x)
#define RESET_CONTROL_CPU_WARM_RST_MSB WLAN_RESET_CONTROL_CPU_WARM_RST_MSB
#define RESET_CONTROL_CPU_WARM_RST_LSB WLAN_RESET_CONTROL_CPU_WARM_RST_LSB
#define RESET_CONTROL_CPU_WARM_RST_MASK WLAN_RESET_CONTROL_CPU_WARM_RST_MASK
#define RESET_CONTROL_CPU_WARM_RST_GET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_GET(x)
#define RESET_CONTROL_CPU_WARM_RST_SET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_SET(x)
#define RESET_CONTROL_MAC_COLD_RST_MSB WLAN_RESET_CONTROL_MAC_COLD_RST_MSB
#define RESET_CONTROL_MAC_COLD_RST_LSB WLAN_RESET_CONTROL_MAC_COLD_RST_LSB
#define RESET_CONTROL_MAC_COLD_RST_MASK WLAN_RESET_CONTROL_MAC_COLD_RST_MASK
#define RESET_CONTROL_MAC_COLD_RST_GET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_GET(x)
#define RESET_CONTROL_MAC_COLD_RST_SET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_SET(x)
#define RESET_CONTROL_MAC_WARM_RST_MSB WLAN_RESET_CONTROL_MAC_WARM_RST_MSB
#define RESET_CONTROL_MAC_WARM_RST_LSB WLAN_RESET_CONTROL_MAC_WARM_RST_LSB
#define RESET_CONTROL_MAC_WARM_RST_MASK WLAN_RESET_CONTROL_MAC_WARM_RST_MASK
#define RESET_CONTROL_MAC_WARM_RST_GET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_GET(x)
#define RESET_CONTROL_MAC_WARM_RST_SET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_SET(x)
#define RESET_CONTROL_MBOX_RST_MSB WLAN_RESET_CONTROL_MBOX_RST_MSB
#define RESET_CONTROL_MBOX_RST_LSB WLAN_RESET_CONTROL_MBOX_RST_LSB
#define RESET_CONTROL_MBOX_RST_MASK WLAN_RESET_CONTROL_MBOX_RST_MASK
#define RESET_CONTROL_MBOX_RST_GET(x) WLAN_RESET_CONTROL_MBOX_RST_GET(x)
#define RESET_CONTROL_MBOX_RST_SET(x) WLAN_RESET_CONTROL_MBOX_RST_SET(x)
#define RESET_CONTROL_UART_RST_MSB WLAN_RESET_CONTROL_UART_RST_MSB
#define RESET_CONTROL_UART_RST_LSB WLAN_RESET_CONTROL_UART_RST_LSB
#define RESET_CONTROL_UART_RST_MASK WLAN_RESET_CONTROL_UART_RST_MASK
#define RESET_CONTROL_UART_RST_GET(x) WLAN_RESET_CONTROL_UART_RST_GET(x)
#define RESET_CONTROL_UART_RST_SET(x) WLAN_RESET_CONTROL_UART_RST_SET(x)
#define RESET_CONTROL_SI0_RST_MSB WLAN_RESET_CONTROL_SI0_RST_MSB
#define RESET_CONTROL_SI0_RST_LSB WLAN_RESET_CONTROL_SI0_RST_LSB
#define RESET_CONTROL_SI0_RST_MASK WLAN_RESET_CONTROL_SI0_RST_MASK
#define RESET_CONTROL_SI0_RST_GET(x) WLAN_RESET_CONTROL_SI0_RST_GET(x)
#define RESET_CONTROL_SI0_RST_SET(x) WLAN_RESET_CONTROL_SI0_RST_SET(x)
#define XTAL_CONTROL_ADDRESS WLAN_XTAL_CONTROL_ADDRESS
#define XTAL_CONTROL_OFFSET WLAN_XTAL_CONTROL_OFFSET
#define XTAL_CONTROL_TCXO_MSB WLAN_XTAL_CONTROL_TCXO_MSB
#define XTAL_CONTROL_TCXO_LSB WLAN_XTAL_CONTROL_TCXO_LSB
#define XTAL_CONTROL_TCXO_MASK WLAN_XTAL_CONTROL_TCXO_MASK
#define XTAL_CONTROL_TCXO_GET(x) WLAN_XTAL_CONTROL_TCXO_GET(x)
#define XTAL_CONTROL_TCXO_SET(x) WLAN_XTAL_CONTROL_TCXO_SET(x)
#define TCXO_DETECT_ADDRESS WLAN_TCXO_DETECT_ADDRESS
#define TCXO_DETECT_OFFSET WLAN_TCXO_DETECT_OFFSET
#define TCXO_DETECT_PRESENT_MSB WLAN_TCXO_DETECT_PRESENT_MSB
#define TCXO_DETECT_PRESENT_LSB WLAN_TCXO_DETECT_PRESENT_LSB
#define TCXO_DETECT_PRESENT_MASK WLAN_TCXO_DETECT_PRESENT_MASK
#define TCXO_DETECT_PRESENT_GET(x) WLAN_TCXO_DETECT_PRESENT_GET(x)
#define TCXO_DETECT_PRESENT_SET(x) WLAN_TCXO_DETECT_PRESENT_SET(x)
#define XTAL_TEST_ADDRESS WLAN_XTAL_TEST_ADDRESS
#define XTAL_TEST_OFFSET WLAN_XTAL_TEST_OFFSET
#define XTAL_TEST_NOTCXODET_MSB WLAN_XTAL_TEST_NOTCXODET_MSB
#define XTAL_TEST_NOTCXODET_LSB WLAN_XTAL_TEST_NOTCXODET_LSB
#define XTAL_TEST_NOTCXODET_MASK WLAN_XTAL_TEST_NOTCXODET_MASK
#define XTAL_TEST_NOTCXODET_GET(x) WLAN_XTAL_TEST_NOTCXODET_GET(x)
#define XTAL_TEST_NOTCXODET_SET(x) WLAN_XTAL_TEST_NOTCXODET_SET(x)
#define QUADRATURE_ADDRESS WLAN_QUADRATURE_ADDRESS
#define QUADRATURE_OFFSET WLAN_QUADRATURE_OFFSET
#define QUADRATURE_ADC_MSB WLAN_QUADRATURE_ADC_MSB
#define QUADRATURE_ADC_LSB WLAN_QUADRATURE_ADC_LSB
#define QUADRATURE_ADC_MASK WLAN_QUADRATURE_ADC_MASK
#define QUADRATURE_ADC_GET(x) WLAN_QUADRATURE_ADC_GET(x)
#define QUADRATURE_ADC_SET(x) WLAN_QUADRATURE_ADC_SET(x)
#define QUADRATURE_SEL_MSB WLAN_QUADRATURE_SEL_MSB
#define QUADRATURE_SEL_LSB WLAN_QUADRATURE_SEL_LSB
#define QUADRATURE_SEL_MASK WLAN_QUADRATURE_SEL_MASK
#define QUADRATURE_SEL_GET(x) WLAN_QUADRATURE_SEL_GET(x)
#define QUADRATURE_SEL_SET(x) WLAN_QUADRATURE_SEL_SET(x)
#define QUADRATURE_DAC_MSB WLAN_QUADRATURE_DAC_MSB
#define QUADRATURE_DAC_LSB WLAN_QUADRATURE_DAC_LSB
#define QUADRATURE_DAC_MASK WLAN_QUADRATURE_DAC_MASK
#define QUADRATURE_DAC_GET(x) WLAN_QUADRATURE_DAC_GET(x)
#define QUADRATURE_DAC_SET(x) WLAN_QUADRATURE_DAC_SET(x)
#define PLL_CONTROL_ADDRESS WLAN_PLL_CONTROL_ADDRESS
#define PLL_CONTROL_OFFSET WLAN_PLL_CONTROL_OFFSET
#define PLL_CONTROL_DIG_TEST_CLK_MSB WLAN_PLL_CONTROL_DIG_TEST_CLK_MSB
#define PLL_CONTROL_DIG_TEST_CLK_LSB WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB
#define PLL_CONTROL_DIG_TEST_CLK_MASK WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK
#define PLL_CONTROL_DIG_TEST_CLK_GET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_GET(x)
#define PLL_CONTROL_DIG_TEST_CLK_SET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_SET(x)
#define PLL_CONTROL_MAC_OVERRIDE_MSB WLAN_PLL_CONTROL_MAC_OVERRIDE_MSB
#define PLL_CONTROL_MAC_OVERRIDE_LSB WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB
#define PLL_CONTROL_MAC_OVERRIDE_MASK WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK
#define PLL_CONTROL_MAC_OVERRIDE_GET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_GET(x)
#define PLL_CONTROL_MAC_OVERRIDE_SET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_SET(x)
#define PLL_CONTROL_NOPWD_MSB WLAN_PLL_CONTROL_NOPWD_MSB
#define PLL_CONTROL_NOPWD_LSB WLAN_PLL_CONTROL_NOPWD_LSB
#define PLL_CONTROL_NOPWD_MASK WLAN_PLL_CONTROL_NOPWD_MASK
#define PLL_CONTROL_NOPWD_GET(x) WLAN_PLL_CONTROL_NOPWD_GET(x)
#define PLL_CONTROL_NOPWD_SET(x) WLAN_PLL_CONTROL_NOPWD_SET(x)
#define PLL_CONTROL_UPDATING_MSB WLAN_PLL_CONTROL_UPDATING_MSB
#define PLL_CONTROL_UPDATING_LSB WLAN_PLL_CONTROL_UPDATING_LSB
#define PLL_CONTROL_UPDATING_MASK WLAN_PLL_CONTROL_UPDATING_MASK
#define PLL_CONTROL_UPDATING_GET(x) WLAN_PLL_CONTROL_UPDATING_GET(x)
#define PLL_CONTROL_UPDATING_SET(x) WLAN_PLL_CONTROL_UPDATING_SET(x)
#define PLL_CONTROL_BYPASS_MSB WLAN_PLL_CONTROL_BYPASS_MSB
#define PLL_CONTROL_BYPASS_LSB WLAN_PLL_CONTROL_BYPASS_LSB
#define PLL_CONTROL_BYPASS_MASK WLAN_PLL_CONTROL_BYPASS_MASK
#define PLL_CONTROL_BYPASS_GET(x) WLAN_PLL_CONTROL_BYPASS_GET(x)
#define PLL_CONTROL_BYPASS_SET(x) WLAN_PLL_CONTROL_BYPASS_SET(x)
#define PLL_CONTROL_REFDIV_MSB WLAN_PLL_CONTROL_REFDIV_MSB
#define PLL_CONTROL_REFDIV_LSB WLAN_PLL_CONTROL_REFDIV_LSB
#define PLL_CONTROL_REFDIV_MASK WLAN_PLL_CONTROL_REFDIV_MASK
#define PLL_CONTROL_REFDIV_GET(x) WLAN_PLL_CONTROL_REFDIV_GET(x)
#define PLL_CONTROL_REFDIV_SET(x) WLAN_PLL_CONTROL_REFDIV_SET(x)
#define PLL_CONTROL_DIV_MSB WLAN_PLL_CONTROL_DIV_MSB
#define PLL_CONTROL_DIV_LSB WLAN_PLL_CONTROL_DIV_LSB
#define PLL_CONTROL_DIV_MASK WLAN_PLL_CONTROL_DIV_MASK
#define PLL_CONTROL_DIV_GET(x) WLAN_PLL_CONTROL_DIV_GET(x)
#define PLL_CONTROL_DIV_SET(x) WLAN_PLL_CONTROL_DIV_SET(x)
#define PLL_SETTLE_ADDRESS WLAN_PLL_SETTLE_ADDRESS
#define PLL_SETTLE_OFFSET WLAN_PLL_SETTLE_OFFSET
#define PLL_SETTLE_TIME_MSB WLAN_PLL_SETTLE_TIME_MSB
#define PLL_SETTLE_TIME_LSB WLAN_PLL_SETTLE_TIME_LSB
#define PLL_SETTLE_TIME_MASK WLAN_PLL_SETTLE_TIME_MASK
#define PLL_SETTLE_TIME_GET(x) WLAN_PLL_SETTLE_TIME_GET(x)
#define PLL_SETTLE_TIME_SET(x) WLAN_PLL_SETTLE_TIME_SET(x)
#define XTAL_SETTLE_ADDRESS WLAN_XTAL_SETTLE_ADDRESS
#define XTAL_SETTLE_OFFSET WLAN_XTAL_SETTLE_OFFSET
#define XTAL_SETTLE_TIME_MSB WLAN_XTAL_SETTLE_TIME_MSB
#define XTAL_SETTLE_TIME_LSB WLAN_XTAL_SETTLE_TIME_LSB
#define XTAL_SETTLE_TIME_MASK WLAN_XTAL_SETTLE_TIME_MASK
#define XTAL_SETTLE_TIME_GET(x) WLAN_XTAL_SETTLE_TIME_GET(x)
#define XTAL_SETTLE_TIME_SET(x) WLAN_XTAL_SETTLE_TIME_SET(x)
#define CPU_CLOCK_ADDRESS WLAN_CPU_CLOCK_ADDRESS
#define CPU_CLOCK_OFFSET WLAN_CPU_CLOCK_OFFSET
#define CPU_CLOCK_STANDARD_MSB WLAN_CPU_CLOCK_STANDARD_MSB
#define CPU_CLOCK_STANDARD_LSB WLAN_CPU_CLOCK_STANDARD_LSB
#define CPU_CLOCK_STANDARD_MASK WLAN_CPU_CLOCK_STANDARD_MASK
#define CPU_CLOCK_STANDARD_GET(x) WLAN_CPU_CLOCK_STANDARD_GET(x)
#define CPU_CLOCK_STANDARD_SET(x) WLAN_CPU_CLOCK_STANDARD_SET(x)
#define CLOCK_OUT_ADDRESS WLAN_CLOCK_OUT_ADDRESS
#define CLOCK_OUT_OFFSET WLAN_CLOCK_OUT_OFFSET
#define CLOCK_OUT_SELECT_MSB WLAN_CLOCK_OUT_SELECT_MSB
#define CLOCK_OUT_SELECT_LSB WLAN_CLOCK_OUT_SELECT_LSB
#define CLOCK_OUT_SELECT_MASK WLAN_CLOCK_OUT_SELECT_MASK
#define CLOCK_OUT_SELECT_GET(x) WLAN_CLOCK_OUT_SELECT_GET(x)
#define CLOCK_OUT_SELECT_SET(x) WLAN_CLOCK_OUT_SELECT_SET(x)
#define CLOCK_CONTROL_ADDRESS WLAN_CLOCK_CONTROL_ADDRESS
#define CLOCK_CONTROL_OFFSET WLAN_CLOCK_CONTROL_OFFSET
#define CLOCK_CONTROL_LF_CLK32_MSB WLAN_CLOCK_CONTROL_LF_CLK32_MSB
#define CLOCK_CONTROL_LF_CLK32_LSB WLAN_CLOCK_CONTROL_LF_CLK32_LSB
#define CLOCK_CONTROL_LF_CLK32_MASK WLAN_CLOCK_CONTROL_LF_CLK32_MASK
#define CLOCK_CONTROL_LF_CLK32_GET(x) WLAN_CLOCK_CONTROL_LF_CLK32_GET(x)
#define CLOCK_CONTROL_LF_CLK32_SET(x) WLAN_CLOCK_CONTROL_LF_CLK32_SET(x)
#define CLOCK_CONTROL_SI0_CLK_MSB WLAN_CLOCK_CONTROL_SI0_CLK_MSB
#define CLOCK_CONTROL_SI0_CLK_LSB WLAN_CLOCK_CONTROL_SI0_CLK_LSB
#define CLOCK_CONTROL_SI0_CLK_MASK WLAN_CLOCK_CONTROL_SI0_CLK_MASK
#define CLOCK_CONTROL_SI0_CLK_GET(x) WLAN_CLOCK_CONTROL_SI0_CLK_GET(x)
#define CLOCK_CONTROL_SI0_CLK_SET(x) WLAN_CLOCK_CONTROL_SI0_CLK_SET(x)
#define BIAS_OVERRIDE_ADDRESS WLAN_BIAS_OVERRIDE_ADDRESS
#define BIAS_OVERRIDE_OFFSET WLAN_BIAS_OVERRIDE_OFFSET
#define BIAS_OVERRIDE_ON_MSB WLAN_BIAS_OVERRIDE_ON_MSB
#define BIAS_OVERRIDE_ON_LSB WLAN_BIAS_OVERRIDE_ON_LSB
#define BIAS_OVERRIDE_ON_MASK WLAN_BIAS_OVERRIDE_ON_MASK
#define BIAS_OVERRIDE_ON_GET(x) WLAN_BIAS_OVERRIDE_ON_GET(x)
#define BIAS_OVERRIDE_ON_SET(x) WLAN_BIAS_OVERRIDE_ON_SET(x)
#define WDT_CONTROL_ADDRESS WLAN_WDT_CONTROL_ADDRESS
#define WDT_CONTROL_OFFSET WLAN_WDT_CONTROL_OFFSET
#define WDT_CONTROL_ACTION_MSB WLAN_WDT_CONTROL_ACTION_MSB
#define WDT_CONTROL_ACTION_LSB WLAN_WDT_CONTROL_ACTION_LSB
#define WDT_CONTROL_ACTION_MASK WLAN_WDT_CONTROL_ACTION_MASK
#define WDT_CONTROL_ACTION_GET(x) WLAN_WDT_CONTROL_ACTION_GET(x)
#define WDT_CONTROL_ACTION_SET(x) WLAN_WDT_CONTROL_ACTION_SET(x)
#define WDT_STATUS_ADDRESS WLAN_WDT_STATUS_ADDRESS
#define WDT_STATUS_OFFSET WLAN_WDT_STATUS_OFFSET
#define WDT_STATUS_INTERRUPT_MSB WLAN_WDT_STATUS_INTERRUPT_MSB
#define WDT_STATUS_INTERRUPT_LSB WLAN_WDT_STATUS_INTERRUPT_LSB
#define WDT_STATUS_INTERRUPT_MASK WLAN_WDT_STATUS_INTERRUPT_MASK
#define WDT_STATUS_INTERRUPT_GET(x) WLAN_WDT_STATUS_INTERRUPT_GET(x)
#define WDT_STATUS_INTERRUPT_SET(x) WLAN_WDT_STATUS_INTERRUPT_SET(x)
#define WDT_ADDRESS WLAN_WDT_ADDRESS
#define WDT_OFFSET WLAN_WDT_OFFSET
#define WDT_TARGET_MSB WLAN_WDT_TARGET_MSB
#define WDT_TARGET_LSB WLAN_WDT_TARGET_LSB
#define WDT_TARGET_MASK WLAN_WDT_TARGET_MASK
#define WDT_TARGET_GET(x) WLAN_WDT_TARGET_GET(x)
#define WDT_TARGET_SET(x) WLAN_WDT_TARGET_SET(x)
#define WDT_COUNT_ADDRESS WLAN_WDT_COUNT_ADDRESS
#define WDT_COUNT_OFFSET WLAN_WDT_COUNT_OFFSET
#define WDT_COUNT_VALUE_MSB WLAN_WDT_COUNT_VALUE_MSB
#define WDT_COUNT_VALUE_LSB WLAN_WDT_COUNT_VALUE_LSB
#define WDT_COUNT_VALUE_MASK WLAN_WDT_COUNT_VALUE_MASK
#define WDT_COUNT_VALUE_GET(x) WLAN_WDT_COUNT_VALUE_GET(x)
#define WDT_COUNT_VALUE_SET(x) WLAN_WDT_COUNT_VALUE_SET(x)
#define WDT_RESET_ADDRESS WLAN_WDT_RESET_ADDRESS
#define WDT_RESET_OFFSET WLAN_WDT_RESET_OFFSET
#define WDT_RESET_VALUE_MSB WLAN_WDT_RESET_VALUE_MSB
#define WDT_RESET_VALUE_LSB WLAN_WDT_RESET_VALUE_LSB
#define WDT_RESET_VALUE_MASK WLAN_WDT_RESET_VALUE_MASK
#define WDT_RESET_VALUE_GET(x) WLAN_WDT_RESET_VALUE_GET(x)
#define WDT_RESET_VALUE_SET(x) WLAN_WDT_RESET_VALUE_SET(x)
#define INT_STATUS_ADDRESS WLAN_INT_STATUS_ADDRESS
#define INT_STATUS_OFFSET WLAN_INT_STATUS_OFFSET
#define INT_STATUS_HCI_UART_MSB WLAN_INT_STATUS_HCI_UART_MSB
#define INT_STATUS_HCI_UART_LSB WLAN_INT_STATUS_HCI_UART_LSB
#define INT_STATUS_HCI_UART_MASK WLAN_INT_STATUS_HCI_UART_MASK
#define INT_STATUS_HCI_UART_GET(x) WLAN_INT_STATUS_HCI_UART_GET(x)
#define INT_STATUS_HCI_UART_SET(x) WLAN_INT_STATUS_HCI_UART_SET(x)
#define INT_STATUS_THERM_MSB WLAN_INT_STATUS_THERM_MSB
#define INT_STATUS_THERM_LSB WLAN_INT_STATUS_THERM_LSB
#define INT_STATUS_THERM_MASK WLAN_INT_STATUS_THERM_MASK
#define INT_STATUS_THERM_GET(x) WLAN_INT_STATUS_THERM_GET(x)
#define INT_STATUS_THERM_SET(x) WLAN_INT_STATUS_THERM_SET(x)
#define INT_STATUS_EFUSE_OVERWRITE_MSB WLAN_INT_STATUS_EFUSE_OVERWRITE_MSB
#define INT_STATUS_EFUSE_OVERWRITE_LSB WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB
#define INT_STATUS_EFUSE_OVERWRITE_MASK WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK
#define INT_STATUS_EFUSE_OVERWRITE_GET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_GET(x)
#define INT_STATUS_EFUSE_OVERWRITE_SET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_SET(x)
#define INT_STATUS_UART_MBOX_MSB WLAN_INT_STATUS_UART_MBOX_MSB
#define INT_STATUS_UART_MBOX_LSB WLAN_INT_STATUS_UART_MBOX_LSB
#define INT_STATUS_UART_MBOX_MASK WLAN_INT_STATUS_UART_MBOX_MASK
#define INT_STATUS_UART_MBOX_GET(x) WLAN_INT_STATUS_UART_MBOX_GET(x)
#define INT_STATUS_UART_MBOX_SET(x) WLAN_INT_STATUS_UART_MBOX_SET(x)
#define INT_STATUS_GENERIC_MBOX_MSB WLAN_INT_STATUS_GENERIC_MBOX_MSB
#define INT_STATUS_GENERIC_MBOX_LSB WLAN_INT_STATUS_GENERIC_MBOX_LSB
#define INT_STATUS_GENERIC_MBOX_MASK WLAN_INT_STATUS_GENERIC_MBOX_MASK
#define INT_STATUS_GENERIC_MBOX_GET(x) WLAN_INT_STATUS_GENERIC_MBOX_GET(x)
#define INT_STATUS_GENERIC_MBOX_SET(x) WLAN_INT_STATUS_GENERIC_MBOX_SET(x)
#define INT_STATUS_RDMA_MSB WLAN_INT_STATUS_RDMA_MSB
#define INT_STATUS_RDMA_LSB WLAN_INT_STATUS_RDMA_LSB
#define INT_STATUS_RDMA_MASK WLAN_INT_STATUS_RDMA_MASK
#define INT_STATUS_RDMA_GET(x) WLAN_INT_STATUS_RDMA_GET(x)
#define INT_STATUS_RDMA_SET(x) WLAN_INT_STATUS_RDMA_SET(x)
#define INT_STATUS_BTCOEX_MSB WLAN_INT_STATUS_BTCOEX_MSB
#define INT_STATUS_BTCOEX_LSB WLAN_INT_STATUS_BTCOEX_LSB
#define INT_STATUS_BTCOEX_MASK WLAN_INT_STATUS_BTCOEX_MASK
#define INT_STATUS_BTCOEX_GET(x) WLAN_INT_STATUS_BTCOEX_GET(x)
#define INT_STATUS_BTCOEX_SET(x) WLAN_INT_STATUS_BTCOEX_SET(x)
#define INT_STATUS_RTC_POWER_MSB WLAN_INT_STATUS_RTC_POWER_MSB
#define INT_STATUS_RTC_POWER_LSB WLAN_INT_STATUS_RTC_POWER_LSB
#define INT_STATUS_RTC_POWER_MASK WLAN_INT_STATUS_RTC_POWER_MASK
#define INT_STATUS_RTC_POWER_GET(x) WLAN_INT_STATUS_RTC_POWER_GET(x)
#define INT_STATUS_RTC_POWER_SET(x) WLAN_INT_STATUS_RTC_POWER_SET(x)
#define INT_STATUS_MAC_MSB WLAN_INT_STATUS_MAC_MSB
#define INT_STATUS_MAC_LSB WLAN_INT_STATUS_MAC_LSB
#define INT_STATUS_MAC_MASK WLAN_INT_STATUS_MAC_MASK
#define INT_STATUS_MAC_GET(x) WLAN_INT_STATUS_MAC_GET(x)
#define INT_STATUS_MAC_SET(x) WLAN_INT_STATUS_MAC_SET(x)
#define INT_STATUS_MAILBOX_MSB WLAN_INT_STATUS_MAILBOX_MSB
#define INT_STATUS_MAILBOX_LSB WLAN_INT_STATUS_MAILBOX_LSB
#define INT_STATUS_MAILBOX_MASK WLAN_INT_STATUS_MAILBOX_MASK
#define INT_STATUS_MAILBOX_GET(x) WLAN_INT_STATUS_MAILBOX_GET(x)
#define INT_STATUS_MAILBOX_SET(x) WLAN_INT_STATUS_MAILBOX_SET(x)
#define INT_STATUS_RTC_ALARM_MSB WLAN_INT_STATUS_RTC_ALARM_MSB
#define INT_STATUS_RTC_ALARM_LSB WLAN_INT_STATUS_RTC_ALARM_LSB
#define INT_STATUS_RTC_ALARM_MASK WLAN_INT_STATUS_RTC_ALARM_MASK
#define INT_STATUS_RTC_ALARM_GET(x) WLAN_INT_STATUS_RTC_ALARM_GET(x)
#define INT_STATUS_RTC_ALARM_SET(x) WLAN_INT_STATUS_RTC_ALARM_SET(x)
#define INT_STATUS_HF_TIMER_MSB WLAN_INT_STATUS_HF_TIMER_MSB
#define INT_STATUS_HF_TIMER_LSB WLAN_INT_STATUS_HF_TIMER_LSB
#define INT_STATUS_HF_TIMER_MASK WLAN_INT_STATUS_HF_TIMER_MASK
#define INT_STATUS_HF_TIMER_GET(x) WLAN_INT_STATUS_HF_TIMER_GET(x)
#define INT_STATUS_HF_TIMER_SET(x) WLAN_INT_STATUS_HF_TIMER_SET(x)
#define INT_STATUS_LF_TIMER3_MSB WLAN_INT_STATUS_LF_TIMER3_MSB
#define INT_STATUS_LF_TIMER3_LSB WLAN_INT_STATUS_LF_TIMER3_LSB
#define INT_STATUS_LF_TIMER3_MASK WLAN_INT_STATUS_LF_TIMER3_MASK
#define INT_STATUS_LF_TIMER3_GET(x) WLAN_INT_STATUS_LF_TIMER3_GET(x)
#define INT_STATUS_LF_TIMER3_SET(x) WLAN_INT_STATUS_LF_TIMER3_SET(x)
#define INT_STATUS_LF_TIMER2_MSB WLAN_INT_STATUS_LF_TIMER2_MSB
#define INT_STATUS_LF_TIMER2_LSB WLAN_INT_STATUS_LF_TIMER2_LSB
#define INT_STATUS_LF_TIMER2_MASK WLAN_INT_STATUS_LF_TIMER2_MASK
#define INT_STATUS_LF_TIMER2_GET(x) WLAN_INT_STATUS_LF_TIMER2_GET(x)
#define INT_STATUS_LF_TIMER2_SET(x) WLAN_INT_STATUS_LF_TIMER2_SET(x)
#define INT_STATUS_LF_TIMER1_MSB WLAN_INT_STATUS_LF_TIMER1_MSB
#define INT_STATUS_LF_TIMER1_LSB WLAN_INT_STATUS_LF_TIMER1_LSB
#define INT_STATUS_LF_TIMER1_MASK WLAN_INT_STATUS_LF_TIMER1_MASK
#define INT_STATUS_LF_TIMER1_GET(x) WLAN_INT_STATUS_LF_TIMER1_GET(x)
#define INT_STATUS_LF_TIMER1_SET(x) WLAN_INT_STATUS_LF_TIMER1_SET(x)
#define INT_STATUS_LF_TIMER0_MSB WLAN_INT_STATUS_LF_TIMER0_MSB
#define INT_STATUS_LF_TIMER0_LSB WLAN_INT_STATUS_LF_TIMER0_LSB
#define INT_STATUS_LF_TIMER0_MASK WLAN_INT_STATUS_LF_TIMER0_MASK
#define INT_STATUS_LF_TIMER0_GET(x) WLAN_INT_STATUS_LF_TIMER0_GET(x)
#define INT_STATUS_LF_TIMER0_SET(x) WLAN_INT_STATUS_LF_TIMER0_SET(x)
#define INT_STATUS_KEYPAD_MSB WLAN_INT_STATUS_KEYPAD_MSB
#define INT_STATUS_KEYPAD_LSB WLAN_INT_STATUS_KEYPAD_LSB
#define INT_STATUS_KEYPAD_MASK WLAN_INT_STATUS_KEYPAD_MASK
#define INT_STATUS_KEYPAD_GET(x) WLAN_INT_STATUS_KEYPAD_GET(x)
#define INT_STATUS_KEYPAD_SET(x) WLAN_INT_STATUS_KEYPAD_SET(x)
#define INT_STATUS_SI_MSB WLAN_INT_STATUS_SI_MSB
#define INT_STATUS_SI_LSB WLAN_INT_STATUS_SI_LSB
#define INT_STATUS_SI_MASK WLAN_INT_STATUS_SI_MASK
#define INT_STATUS_SI_GET(x) WLAN_INT_STATUS_SI_GET(x)
#define INT_STATUS_SI_SET(x) WLAN_INT_STATUS_SI_SET(x)
#define INT_STATUS_GPIO_MSB WLAN_INT_STATUS_GPIO_MSB
#define INT_STATUS_GPIO_LSB WLAN_INT_STATUS_GPIO_LSB
#define INT_STATUS_GPIO_MASK WLAN_INT_STATUS_GPIO_MASK
#define INT_STATUS_GPIO_GET(x) WLAN_INT_STATUS_GPIO_GET(x)
#define INT_STATUS_GPIO_SET(x) WLAN_INT_STATUS_GPIO_SET(x)
#define INT_STATUS_UART_MSB WLAN_INT_STATUS_UART_MSB
#define INT_STATUS_UART_LSB WLAN_INT_STATUS_UART_LSB
#define INT_STATUS_UART_MASK WLAN_INT_STATUS_UART_MASK
#define INT_STATUS_UART_GET(x) WLAN_INT_STATUS_UART_GET(x)
#define INT_STATUS_UART_SET(x) WLAN_INT_STATUS_UART_SET(x)
#define INT_STATUS_ERROR_MSB WLAN_INT_STATUS_ERROR_MSB
#define INT_STATUS_ERROR_LSB WLAN_INT_STATUS_ERROR_LSB
#define INT_STATUS_ERROR_MASK WLAN_INT_STATUS_ERROR_MASK
#define INT_STATUS_ERROR_GET(x) WLAN_INT_STATUS_ERROR_GET(x)
#define INT_STATUS_ERROR_SET(x) WLAN_INT_STATUS_ERROR_SET(x)
#define INT_STATUS_WDT_INT_MSB WLAN_INT_STATUS_WDT_INT_MSB
#define INT_STATUS_WDT_INT_LSB WLAN_INT_STATUS_WDT_INT_LSB
#define INT_STATUS_WDT_INT_MASK WLAN_INT_STATUS_WDT_INT_MASK
#define INT_STATUS_WDT_INT_GET(x) WLAN_INT_STATUS_WDT_INT_GET(x)
#define INT_STATUS_WDT_INT_SET(x) WLAN_INT_STATUS_WDT_INT_SET(x)
#define LF_TIMER0_ADDRESS WLAN_LF_TIMER0_ADDRESS
#define LF_TIMER0_OFFSET WLAN_LF_TIMER0_OFFSET
#define LF_TIMER0_TARGET_MSB WLAN_LF_TIMER0_TARGET_MSB
#define LF_TIMER0_TARGET_LSB WLAN_LF_TIMER0_TARGET_LSB
#define LF_TIMER0_TARGET_MASK WLAN_LF_TIMER0_TARGET_MASK
#define LF_TIMER0_TARGET_GET(x) WLAN_LF_TIMER0_TARGET_GET(x)
#define LF_TIMER0_TARGET_SET(x) WLAN_LF_TIMER0_TARGET_SET(x)
#define LF_TIMER_COUNT0_ADDRESS WLAN_LF_TIMER_COUNT0_ADDRESS
#define LF_TIMER_COUNT0_OFFSET WLAN_LF_TIMER_COUNT0_OFFSET
#define LF_TIMER_COUNT0_VALUE_MSB WLAN_LF_TIMER_COUNT0_VALUE_MSB
#define LF_TIMER_COUNT0_VALUE_LSB WLAN_LF_TIMER_COUNT0_VALUE_LSB
#define LF_TIMER_COUNT0_VALUE_MASK WLAN_LF_TIMER_COUNT0_VALUE_MASK
#define LF_TIMER_COUNT0_VALUE_GET(x) WLAN_LF_TIMER_COUNT0_VALUE_GET(x)
#define LF_TIMER_COUNT0_VALUE_SET(x) WLAN_LF_TIMER_COUNT0_VALUE_SET(x)
#define LF_TIMER_CONTROL0_ADDRESS WLAN_LF_TIMER_CONTROL0_ADDRESS
#define LF_TIMER_CONTROL0_OFFSET WLAN_LF_TIMER_CONTROL0_OFFSET
#define LF_TIMER_CONTROL0_ENABLE_MSB WLAN_LF_TIMER_CONTROL0_ENABLE_MSB
#define LF_TIMER_CONTROL0_ENABLE_LSB WLAN_LF_TIMER_CONTROL0_ENABLE_LSB
#define LF_TIMER_CONTROL0_ENABLE_MASK WLAN_LF_TIMER_CONTROL0_ENABLE_MASK
#define LF_TIMER_CONTROL0_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_GET(x)
#define LF_TIMER_CONTROL0_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_SET(x)
#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MSB
#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB
#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK
#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x)
#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x)
#define LF_TIMER_CONTROL0_RESET_MSB WLAN_LF_TIMER_CONTROL0_RESET_MSB
#define LF_TIMER_CONTROL0_RESET_LSB WLAN_LF_TIMER_CONTROL0_RESET_LSB
#define LF_TIMER_CONTROL0_RESET_MASK WLAN_LF_TIMER_CONTROL0_RESET_MASK
#define LF_TIMER_CONTROL0_RESET_GET(x) WLAN_LF_TIMER_CONTROL0_RESET_GET(x)
#define LF_TIMER_CONTROL0_RESET_SET(x) WLAN_LF_TIMER_CONTROL0_RESET_SET(x)
#define LF_TIMER_STATUS0_ADDRESS WLAN_LF_TIMER_STATUS0_ADDRESS
#define LF_TIMER_STATUS0_OFFSET WLAN_LF_TIMER_STATUS0_OFFSET
#define LF_TIMER_STATUS0_INTERRUPT_MSB WLAN_LF_TIMER_STATUS0_INTERRUPT_MSB
#define LF_TIMER_STATUS0_INTERRUPT_LSB WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB
#define LF_TIMER_STATUS0_INTERRUPT_MASK WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK
#define LF_TIMER_STATUS0_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_GET(x)
#define LF_TIMER_STATUS0_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_SET(x)
#define LF_TIMER1_ADDRESS WLAN_LF_TIMER1_ADDRESS
#define LF_TIMER1_OFFSET WLAN_LF_TIMER1_OFFSET
#define LF_TIMER1_TARGET_MSB WLAN_LF_TIMER1_TARGET_MSB
#define LF_TIMER1_TARGET_LSB WLAN_LF_TIMER1_TARGET_LSB
#define LF_TIMER1_TARGET_MASK WLAN_LF_TIMER1_TARGET_MASK
#define LF_TIMER1_TARGET_GET(x) WLAN_LF_TIMER1_TARGET_GET(x)
#define LF_TIMER1_TARGET_SET(x) WLAN_LF_TIMER1_TARGET_SET(x)
#define LF_TIMER_COUNT1_ADDRESS WLAN_LF_TIMER_COUNT1_ADDRESS
#define LF_TIMER_COUNT1_OFFSET WLAN_LF_TIMER_COUNT1_OFFSET
#define LF_TIMER_COUNT1_VALUE_MSB WLAN_LF_TIMER_COUNT1_VALUE_MSB
#define LF_TIMER_COUNT1_VALUE_LSB WLAN_LF_TIMER_COUNT1_VALUE_LSB
#define LF_TIMER_COUNT1_VALUE_MASK WLAN_LF_TIMER_COUNT1_VALUE_MASK
#define LF_TIMER_COUNT1_VALUE_GET(x) WLAN_LF_TIMER_COUNT1_VALUE_GET(x)
#define LF_TIMER_COUNT1_VALUE_SET(x) WLAN_LF_TIMER_COUNT1_VALUE_SET(x)
#define LF_TIMER_CONTROL1_ADDRESS WLAN_LF_TIMER_CONTROL1_ADDRESS
#define LF_TIMER_CONTROL1_OFFSET WLAN_LF_TIMER_CONTROL1_OFFSET
#define LF_TIMER_CONTROL1_ENABLE_MSB WLAN_LF_TIMER_CONTROL1_ENABLE_MSB
#define LF_TIMER_CONTROL1_ENABLE_LSB WLAN_LF_TIMER_CONTROL1_ENABLE_LSB
#define LF_TIMER_CONTROL1_ENABLE_MASK WLAN_LF_TIMER_CONTROL1_ENABLE_MASK
#define LF_TIMER_CONTROL1_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_GET(x)
#define LF_TIMER_CONTROL1_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_SET(x)
#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MSB
#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB
#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK
#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x)
#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x)
#define LF_TIMER_CONTROL1_RESET_MSB WLAN_LF_TIMER_CONTROL1_RESET_MSB
#define LF_TIMER_CONTROL1_RESET_LSB WLAN_LF_TIMER_CONTROL1_RESET_LSB
#define LF_TIMER_CONTROL1_RESET_MASK WLAN_LF_TIMER_CONTROL1_RESET_MASK
#define LF_TIMER_CONTROL1_RESET_GET(x) WLAN_LF_TIMER_CONTROL1_RESET_GET(x)
#define LF_TIMER_CONTROL1_RESET_SET(x) WLAN_LF_TIMER_CONTROL1_RESET_SET(x)
#define LF_TIMER_STATUS1_ADDRESS WLAN_LF_TIMER_STATUS1_ADDRESS
#define LF_TIMER_STATUS1_OFFSET WLAN_LF_TIMER_STATUS1_OFFSET
#define LF_TIMER_STATUS1_INTERRUPT_MSB WLAN_LF_TIMER_STATUS1_INTERRUPT_MSB
#define LF_TIMER_STATUS1_INTERRUPT_LSB WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB
#define LF_TIMER_STATUS1_INTERRUPT_MASK WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK
#define LF_TIMER_STATUS1_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_GET(x)
#define LF_TIMER_STATUS1_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_SET(x)
#define LF_TIMER2_ADDRESS WLAN_LF_TIMER2_ADDRESS
#define LF_TIMER2_OFFSET WLAN_LF_TIMER2_OFFSET
#define LF_TIMER2_TARGET_MSB WLAN_LF_TIMER2_TARGET_MSB
#define LF_TIMER2_TARGET_LSB WLAN_LF_TIMER2_TARGET_LSB
#define LF_TIMER2_TARGET_MASK WLAN_LF_TIMER2_TARGET_MASK
#define LF_TIMER2_TARGET_GET(x) WLAN_LF_TIMER2_TARGET_GET(x)
#define LF_TIMER2_TARGET_SET(x) WLAN_LF_TIMER2_TARGET_SET(x)
#define LF_TIMER_COUNT2_ADDRESS WLAN_LF_TIMER_COUNT2_ADDRESS
#define LF_TIMER_COUNT2_OFFSET WLAN_LF_TIMER_COUNT2_OFFSET
#define LF_TIMER_COUNT2_VALUE_MSB WLAN_LF_TIMER_COUNT2_VALUE_MSB
#define LF_TIMER_COUNT2_VALUE_LSB WLAN_LF_TIMER_COUNT2_VALUE_LSB
#define LF_TIMER_COUNT2_VALUE_MASK WLAN_LF_TIMER_COUNT2_VALUE_MASK
#define LF_TIMER_COUNT2_VALUE_GET(x) WLAN_LF_TIMER_COUNT2_VALUE_GET(x)
#define LF_TIMER_COUNT2_VALUE_SET(x) WLAN_LF_TIMER_COUNT2_VALUE_SET(x)
#define LF_TIMER_CONTROL2_ADDRESS WLAN_LF_TIMER_CONTROL2_ADDRESS
#define LF_TIMER_CONTROL2_OFFSET WLAN_LF_TIMER_CONTROL2_OFFSET
#define LF_TIMER_CONTROL2_ENABLE_MSB WLAN_LF_TIMER_CONTROL2_ENABLE_MSB
#define LF_TIMER_CONTROL2_ENABLE_LSB WLAN_LF_TIMER_CONTROL2_ENABLE_LSB
#define LF_TIMER_CONTROL2_ENABLE_MASK WLAN_LF_TIMER_CONTROL2_ENABLE_MASK
#define LF_TIMER_CONTROL2_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_GET(x)
#define LF_TIMER_CONTROL2_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_SET(x)
#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MSB
#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB
#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK
#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x)
#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x)
#define LF_TIMER_CONTROL2_RESET_MSB WLAN_LF_TIMER_CONTROL2_RESET_MSB
#define LF_TIMER_CONTROL2_RESET_LSB WLAN_LF_TIMER_CONTROL2_RESET_LSB
#define LF_TIMER_CONTROL2_RESET_MASK WLAN_LF_TIMER_CONTROL2_RESET_MASK
#define LF_TIMER_CONTROL2_RESET_GET(x) WLAN_LF_TIMER_CONTROL2_RESET_GET(x)
#define LF_TIMER_CONTROL2_RESET_SET(x) WLAN_LF_TIMER_CONTROL2_RESET_SET(x)
#define LF_TIMER_STATUS2_ADDRESS WLAN_LF_TIMER_STATUS2_ADDRESS
#define LF_TIMER_STATUS2_OFFSET WLAN_LF_TIMER_STATUS2_OFFSET
#define LF_TIMER_STATUS2_INTERRUPT_MSB WLAN_LF_TIMER_STATUS2_INTERRUPT_MSB
#define LF_TIMER_STATUS2_INTERRUPT_LSB WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB
#define LF_TIMER_STATUS2_INTERRUPT_MASK WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK
#define LF_TIMER_STATUS2_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_GET(x)
#define LF_TIMER_STATUS2_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_SET(x)
#define LF_TIMER3_ADDRESS WLAN_LF_TIMER3_ADDRESS
#define LF_TIMER3_OFFSET WLAN_LF_TIMER3_OFFSET
#define LF_TIMER3_TARGET_MSB WLAN_LF_TIMER3_TARGET_MSB
#define LF_TIMER3_TARGET_LSB WLAN_LF_TIMER3_TARGET_LSB
#define LF_TIMER3_TARGET_MASK WLAN_LF_TIMER3_TARGET_MASK
#define LF_TIMER3_TARGET_GET(x) WLAN_LF_TIMER3_TARGET_GET(x)
#define LF_TIMER3_TARGET_SET(x) WLAN_LF_TIMER3_TARGET_SET(x)
#define LF_TIMER_COUNT3_ADDRESS WLAN_LF_TIMER_COUNT3_ADDRESS
#define LF_TIMER_COUNT3_OFFSET WLAN_LF_TIMER_COUNT3_OFFSET
#define LF_TIMER_COUNT3_VALUE_MSB WLAN_LF_TIMER_COUNT3_VALUE_MSB
#define LF_TIMER_COUNT3_VALUE_LSB WLAN_LF_TIMER_COUNT3_VALUE_LSB
#define LF_TIMER_COUNT3_VALUE_MASK WLAN_LF_TIMER_COUNT3_VALUE_MASK
#define LF_TIMER_COUNT3_VALUE_GET(x) WLAN_LF_TIMER_COUNT3_VALUE_GET(x)
#define LF_TIMER_COUNT3_VALUE_SET(x) WLAN_LF_TIMER_COUNT3_VALUE_SET(x)
#define LF_TIMER_CONTROL3_ADDRESS WLAN_LF_TIMER_CONTROL3_ADDRESS
#define LF_TIMER_CONTROL3_OFFSET WLAN_LF_TIMER_CONTROL3_OFFSET
#define LF_TIMER_CONTROL3_ENABLE_MSB WLAN_LF_TIMER_CONTROL3_ENABLE_MSB
#define LF_TIMER_CONTROL3_ENABLE_LSB WLAN_LF_TIMER_CONTROL3_ENABLE_LSB
#define LF_TIMER_CONTROL3_ENABLE_MASK WLAN_LF_TIMER_CONTROL3_ENABLE_MASK
#define LF_TIMER_CONTROL3_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_GET(x)
#define LF_TIMER_CONTROL3_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_SET(x)
#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MSB
#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB
#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK
#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x)
#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x)
#define LF_TIMER_CONTROL3_RESET_MSB WLAN_LF_TIMER_CONTROL3_RESET_MSB
#define LF_TIMER_CONTROL3_RESET_LSB WLAN_LF_TIMER_CONTROL3_RESET_LSB
#define LF_TIMER_CONTROL3_RESET_MASK WLAN_LF_TIMER_CONTROL3_RESET_MASK
#define LF_TIMER_CONTROL3_RESET_GET(x) WLAN_LF_TIMER_CONTROL3_RESET_GET(x)
#define LF_TIMER_CONTROL3_RESET_SET(x) WLAN_LF_TIMER_CONTROL3_RESET_SET(x)
#define LF_TIMER_STATUS3_ADDRESS WLAN_LF_TIMER_STATUS3_ADDRESS
#define LF_TIMER_STATUS3_OFFSET WLAN_LF_TIMER_STATUS3_OFFSET
#define LF_TIMER_STATUS3_INTERRUPT_MSB WLAN_LF_TIMER_STATUS3_INTERRUPT_MSB
#define LF_TIMER_STATUS3_INTERRUPT_LSB WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB
#define LF_TIMER_STATUS3_INTERRUPT_MASK WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK
#define LF_TIMER_STATUS3_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_GET(x)
#define LF_TIMER_STATUS3_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_SET(x)
#define HF_TIMER_ADDRESS WLAN_HF_TIMER_ADDRESS
#define HF_TIMER_OFFSET WLAN_HF_TIMER_OFFSET
#define HF_TIMER_TARGET_MSB WLAN_HF_TIMER_TARGET_MSB
#define HF_TIMER_TARGET_LSB WLAN_HF_TIMER_TARGET_LSB
#define HF_TIMER_TARGET_MASK WLAN_HF_TIMER_TARGET_MASK
#define HF_TIMER_TARGET_GET(x) WLAN_HF_TIMER_TARGET_GET(x)
#define HF_TIMER_TARGET_SET(x) WLAN_HF_TIMER_TARGET_SET(x)
#define HF_TIMER_COUNT_ADDRESS WLAN_HF_TIMER_COUNT_ADDRESS
#define HF_TIMER_COUNT_OFFSET WLAN_HF_TIMER_COUNT_OFFSET
#define HF_TIMER_COUNT_VALUE_MSB WLAN_HF_TIMER_COUNT_VALUE_MSB
#define HF_TIMER_COUNT_VALUE_LSB WLAN_HF_TIMER_COUNT_VALUE_LSB
#define HF_TIMER_COUNT_VALUE_MASK WLAN_HF_TIMER_COUNT_VALUE_MASK
#define HF_TIMER_COUNT_VALUE_GET(x) WLAN_HF_TIMER_COUNT_VALUE_GET(x)
#define HF_TIMER_COUNT_VALUE_SET(x) WLAN_HF_TIMER_COUNT_VALUE_SET(x)
#define HF_LF_COUNT_ADDRESS WLAN_HF_LF_COUNT_ADDRESS
#define HF_LF_COUNT_OFFSET WLAN_HF_LF_COUNT_OFFSET
#define HF_LF_COUNT_VALUE_MSB WLAN_HF_LF_COUNT_VALUE_MSB
#define HF_LF_COUNT_VALUE_LSB WLAN_HF_LF_COUNT_VALUE_LSB
#define HF_LF_COUNT_VALUE_MASK WLAN_HF_LF_COUNT_VALUE_MASK
#define HF_LF_COUNT_VALUE_GET(x) WLAN_HF_LF_COUNT_VALUE_GET(x)
#define HF_LF_COUNT_VALUE_SET(x) WLAN_HF_LF_COUNT_VALUE_SET(x)
#define HF_TIMER_CONTROL_ADDRESS WLAN_HF_TIMER_CONTROL_ADDRESS
#define HF_TIMER_CONTROL_OFFSET WLAN_HF_TIMER_CONTROL_OFFSET
#define HF_TIMER_CONTROL_ENABLE_MSB WLAN_HF_TIMER_CONTROL_ENABLE_MSB
#define HF_TIMER_CONTROL_ENABLE_LSB WLAN_HF_TIMER_CONTROL_ENABLE_LSB
#define HF_TIMER_CONTROL_ENABLE_MASK WLAN_HF_TIMER_CONTROL_ENABLE_MASK
#define HF_TIMER_CONTROL_ENABLE_GET(x) WLAN_HF_TIMER_CONTROL_ENABLE_GET(x)
#define HF_TIMER_CONTROL_ENABLE_SET(x) WLAN_HF_TIMER_CONTROL_ENABLE_SET(x)
#define HF_TIMER_CONTROL_ON_MSB WLAN_HF_TIMER_CONTROL_ON_MSB
#define HF_TIMER_CONTROL_ON_LSB WLAN_HF_TIMER_CONTROL_ON_LSB
#define HF_TIMER_CONTROL_ON_MASK WLAN_HF_TIMER_CONTROL_ON_MASK
#define HF_TIMER_CONTROL_ON_GET(x) WLAN_HF_TIMER_CONTROL_ON_GET(x)
#define HF_TIMER_CONTROL_ON_SET(x) WLAN_HF_TIMER_CONTROL_ON_SET(x)
#define HF_TIMER_CONTROL_AUTO_RESTART_MSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MSB
#define HF_TIMER_CONTROL_AUTO_RESTART_LSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB
#define HF_TIMER_CONTROL_AUTO_RESTART_MASK WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK
#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_GET(x)
#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_SET(x)
#define HF_TIMER_CONTROL_RESET_MSB WLAN_HF_TIMER_CONTROL_RESET_MSB
#define HF_TIMER_CONTROL_RESET_LSB WLAN_HF_TIMER_CONTROL_RESET_LSB
#define HF_TIMER_CONTROL_RESET_MASK WLAN_HF_TIMER_CONTROL_RESET_MASK
#define HF_TIMER_CONTROL_RESET_GET(x) WLAN_HF_TIMER_CONTROL_RESET_GET(x)
#define HF_TIMER_CONTROL_RESET_SET(x) WLAN_HF_TIMER_CONTROL_RESET_SET(x)
#define HF_TIMER_STATUS_ADDRESS WLAN_HF_TIMER_STATUS_ADDRESS
#define HF_TIMER_STATUS_OFFSET WLAN_HF_TIMER_STATUS_OFFSET
#define HF_TIMER_STATUS_INTERRUPT_MSB WLAN_HF_TIMER_STATUS_INTERRUPT_MSB
#define HF_TIMER_STATUS_INTERRUPT_LSB WLAN_HF_TIMER_STATUS_INTERRUPT_LSB
#define HF_TIMER_STATUS_INTERRUPT_MASK WLAN_HF_TIMER_STATUS_INTERRUPT_MASK
#define HF_TIMER_STATUS_INTERRUPT_GET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_GET(x)
#define HF_TIMER_STATUS_INTERRUPT_SET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_SET(x)
#define RTC_CONTROL_ADDRESS WLAN_RTC_CONTROL_ADDRESS
#define RTC_CONTROL_OFFSET WLAN_RTC_CONTROL_OFFSET
#define RTC_CONTROL_ENABLE_MSB WLAN_RTC_CONTROL_ENABLE_MSB
#define RTC_CONTROL_ENABLE_LSB WLAN_RTC_CONTROL_ENABLE_LSB
#define RTC_CONTROL_ENABLE_MASK WLAN_RTC_CONTROL_ENABLE_MASK
#define RTC_CONTROL_ENABLE_GET(x) WLAN_RTC_CONTROL_ENABLE_GET(x)
#define RTC_CONTROL_ENABLE_SET(x) WLAN_RTC_CONTROL_ENABLE_SET(x)
#define RTC_CONTROL_LOAD_RTC_MSB WLAN_RTC_CONTROL_LOAD_RTC_MSB
#define RTC_CONTROL_LOAD_RTC_LSB WLAN_RTC_CONTROL_LOAD_RTC_LSB
#define RTC_CONTROL_LOAD_RTC_MASK WLAN_RTC_CONTROL_LOAD_RTC_MASK
#define RTC_CONTROL_LOAD_RTC_GET(x) WLAN_RTC_CONTROL_LOAD_RTC_GET(x)
#define RTC_CONTROL_LOAD_RTC_SET(x) WLAN_RTC_CONTROL_LOAD_RTC_SET(x)
#define RTC_CONTROL_LOAD_ALARM_MSB WLAN_RTC_CONTROL_LOAD_ALARM_MSB
#define RTC_CONTROL_LOAD_ALARM_LSB WLAN_RTC_CONTROL_LOAD_ALARM_LSB
#define RTC_CONTROL_LOAD_ALARM_MASK WLAN_RTC_CONTROL_LOAD_ALARM_MASK
#define RTC_CONTROL_LOAD_ALARM_GET(x) WLAN_RTC_CONTROL_LOAD_ALARM_GET(x)
#define RTC_CONTROL_LOAD_ALARM_SET(x) WLAN_RTC_CONTROL_LOAD_ALARM_SET(x)
#define RTC_TIME_ADDRESS WLAN_RTC_TIME_ADDRESS
#define RTC_TIME_OFFSET WLAN_RTC_TIME_OFFSET
#define RTC_TIME_WEEK_DAY_MSB WLAN_RTC_TIME_WEEK_DAY_MSB
#define RTC_TIME_WEEK_DAY_LSB WLAN_RTC_TIME_WEEK_DAY_LSB
#define RTC_TIME_WEEK_DAY_MASK WLAN_RTC_TIME_WEEK_DAY_MASK
#define RTC_TIME_WEEK_DAY_GET(x) WLAN_RTC_TIME_WEEK_DAY_GET(x)
#define RTC_TIME_WEEK_DAY_SET(x) WLAN_RTC_TIME_WEEK_DAY_SET(x)
#define RTC_TIME_HOUR_MSB WLAN_RTC_TIME_HOUR_MSB
#define RTC_TIME_HOUR_LSB WLAN_RTC_TIME_HOUR_LSB
#define RTC_TIME_HOUR_MASK WLAN_RTC_TIME_HOUR_MASK
#define RTC_TIME_HOUR_GET(x) WLAN_RTC_TIME_HOUR_GET(x)
#define RTC_TIME_HOUR_SET(x) WLAN_RTC_TIME_HOUR_SET(x)
#define RTC_TIME_MINUTE_MSB WLAN_RTC_TIME_MINUTE_MSB
#define RTC_TIME_MINUTE_LSB WLAN_RTC_TIME_MINUTE_LSB
#define RTC_TIME_MINUTE_MASK WLAN_RTC_TIME_MINUTE_MASK
#define RTC_TIME_MINUTE_GET(x) WLAN_RTC_TIME_MINUTE_GET(x)
#define RTC_TIME_MINUTE_SET(x) WLAN_RTC_TIME_MINUTE_SET(x)
#define RTC_TIME_SECOND_MSB WLAN_RTC_TIME_SECOND_MSB
#define RTC_TIME_SECOND_LSB WLAN_RTC_TIME_SECOND_LSB
#define RTC_TIME_SECOND_MASK WLAN_RTC_TIME_SECOND_MASK
#define RTC_TIME_SECOND_GET(x) WLAN_RTC_TIME_SECOND_GET(x)
#define RTC_TIME_SECOND_SET(x) WLAN_RTC_TIME_SECOND_SET(x)
#define RTC_DATE_ADDRESS WLAN_RTC_DATE_ADDRESS
#define RTC_DATE_OFFSET WLAN_RTC_DATE_OFFSET
#define RTC_DATE_YEAR_MSB WLAN_RTC_DATE_YEAR_MSB
#define RTC_DATE_YEAR_LSB WLAN_RTC_DATE_YEAR_LSB
#define RTC_DATE_YEAR_MASK WLAN_RTC_DATE_YEAR_MASK
#define RTC_DATE_YEAR_GET(x) WLAN_RTC_DATE_YEAR_GET(x)
#define RTC_DATE_YEAR_SET(x) WLAN_RTC_DATE_YEAR_SET(x)
#define RTC_DATE_MONTH_MSB WLAN_RTC_DATE_MONTH_MSB
#define RTC_DATE_MONTH_LSB WLAN_RTC_DATE_MONTH_LSB
#define RTC_DATE_MONTH_MASK WLAN_RTC_DATE_MONTH_MASK
#define RTC_DATE_MONTH_GET(x) WLAN_RTC_DATE_MONTH_GET(x)
#define RTC_DATE_MONTH_SET(x) WLAN_RTC_DATE_MONTH_SET(x)
#define RTC_DATE_MONTH_DAY_MSB WLAN_RTC_DATE_MONTH_DAY_MSB
#define RTC_DATE_MONTH_DAY_LSB WLAN_RTC_DATE_MONTH_DAY_LSB
#define RTC_DATE_MONTH_DAY_MASK WLAN_RTC_DATE_MONTH_DAY_MASK
#define RTC_DATE_MONTH_DAY_GET(x) WLAN_RTC_DATE_MONTH_DAY_GET(x)
#define RTC_DATE_MONTH_DAY_SET(x) WLAN_RTC_DATE_MONTH_DAY_SET(x)
#define RTC_SET_TIME_ADDRESS WLAN_RTC_SET_TIME_ADDRESS
#define RTC_SET_TIME_OFFSET WLAN_RTC_SET_TIME_OFFSET
#define RTC_SET_TIME_WEEK_DAY_MSB WLAN_RTC_SET_TIME_WEEK_DAY_MSB
#define RTC_SET_TIME_WEEK_DAY_LSB WLAN_RTC_SET_TIME_WEEK_DAY_LSB
#define RTC_SET_TIME_WEEK_DAY_MASK WLAN_RTC_SET_TIME_WEEK_DAY_MASK
#define RTC_SET_TIME_WEEK_DAY_GET(x) WLAN_RTC_SET_TIME_WEEK_DAY_GET(x)
#define RTC_SET_TIME_WEEK_DAY_SET(x) WLAN_RTC_SET_TIME_WEEK_DAY_SET(x)
#define RTC_SET_TIME_HOUR_MSB WLAN_RTC_SET_TIME_HOUR_MSB
#define RTC_SET_TIME_HOUR_LSB WLAN_RTC_SET_TIME_HOUR_LSB
#define RTC_SET_TIME_HOUR_MASK WLAN_RTC_SET_TIME_HOUR_MASK
#define RTC_SET_TIME_HOUR_GET(x) WLAN_RTC_SET_TIME_HOUR_GET(x)
#define RTC_SET_TIME_HOUR_SET(x) WLAN_RTC_SET_TIME_HOUR_SET(x)
#define RTC_SET_TIME_MINUTE_MSB WLAN_RTC_SET_TIME_MINUTE_MSB
#define RTC_SET_TIME_MINUTE_LSB WLAN_RTC_SET_TIME_MINUTE_LSB
#define RTC_SET_TIME_MINUTE_MASK WLAN_RTC_SET_TIME_MINUTE_MASK
#define RTC_SET_TIME_MINUTE_GET(x) WLAN_RTC_SET_TIME_MINUTE_GET(x)
#define RTC_SET_TIME_MINUTE_SET(x) WLAN_RTC_SET_TIME_MINUTE_SET(x)
#define RTC_SET_TIME_SECOND_MSB WLAN_RTC_SET_TIME_SECOND_MSB
#define RTC_SET_TIME_SECOND_LSB WLAN_RTC_SET_TIME_SECOND_LSB
#define RTC_SET_TIME_SECOND_MASK WLAN_RTC_SET_TIME_SECOND_MASK
#define RTC_SET_TIME_SECOND_GET(x) WLAN_RTC_SET_TIME_SECOND_GET(x)
#define RTC_SET_TIME_SECOND_SET(x) WLAN_RTC_SET_TIME_SECOND_SET(x)
#define RTC_SET_DATE_ADDRESS WLAN_RTC_SET_DATE_ADDRESS
#define RTC_SET_DATE_OFFSET WLAN_RTC_SET_DATE_OFFSET
#define RTC_SET_DATE_YEAR_MSB WLAN_RTC_SET_DATE_YEAR_MSB
#define RTC_SET_DATE_YEAR_LSB WLAN_RTC_SET_DATE_YEAR_LSB
#define RTC_SET_DATE_YEAR_MASK WLAN_RTC_SET_DATE_YEAR_MASK
#define RTC_SET_DATE_YEAR_GET(x) WLAN_RTC_SET_DATE_YEAR_GET(x)
#define RTC_SET_DATE_YEAR_SET(x) WLAN_RTC_SET_DATE_YEAR_SET(x)
#define RTC_SET_DATE_MONTH_MSB WLAN_RTC_SET_DATE_MONTH_MSB
#define RTC_SET_DATE_MONTH_LSB WLAN_RTC_SET_DATE_MONTH_LSB
#define RTC_SET_DATE_MONTH_MASK WLAN_RTC_SET_DATE_MONTH_MASK
#define RTC_SET_DATE_MONTH_GET(x) WLAN_RTC_SET_DATE_MONTH_GET(x)
#define RTC_SET_DATE_MONTH_SET(x) WLAN_RTC_SET_DATE_MONTH_SET(x)
#define RTC_SET_DATE_MONTH_DAY_MSB WLAN_RTC_SET_DATE_MONTH_DAY_MSB
#define RTC_SET_DATE_MONTH_DAY_LSB WLAN_RTC_SET_DATE_MONTH_DAY_LSB
#define RTC_SET_DATE_MONTH_DAY_MASK WLAN_RTC_SET_DATE_MONTH_DAY_MASK
#define RTC_SET_DATE_MONTH_DAY_GET(x) WLAN_RTC_SET_DATE_MONTH_DAY_GET(x)
#define RTC_SET_DATE_MONTH_DAY_SET(x) WLAN_RTC_SET_DATE_MONTH_DAY_SET(x)
#define RTC_SET_ALARM_ADDRESS WLAN_RTC_SET_ALARM_ADDRESS
#define RTC_SET_ALARM_OFFSET WLAN_RTC_SET_ALARM_OFFSET
#define RTC_SET_ALARM_HOUR_MSB WLAN_RTC_SET_ALARM_HOUR_MSB
#define RTC_SET_ALARM_HOUR_LSB WLAN_RTC_SET_ALARM_HOUR_LSB
#define RTC_SET_ALARM_HOUR_MASK WLAN_RTC_SET_ALARM_HOUR_MASK
#define RTC_SET_ALARM_HOUR_GET(x) WLAN_RTC_SET_ALARM_HOUR_GET(x)
#define RTC_SET_ALARM_HOUR_SET(x) WLAN_RTC_SET_ALARM_HOUR_SET(x)
#define RTC_SET_ALARM_MINUTE_MSB WLAN_RTC_SET_ALARM_MINUTE_MSB
#define RTC_SET_ALARM_MINUTE_LSB WLAN_RTC_SET_ALARM_MINUTE_LSB
#define RTC_SET_ALARM_MINUTE_MASK WLAN_RTC_SET_ALARM_MINUTE_MASK
#define RTC_SET_ALARM_MINUTE_GET(x) WLAN_RTC_SET_ALARM_MINUTE_GET(x)
#define RTC_SET_ALARM_MINUTE_SET(x) WLAN_RTC_SET_ALARM_MINUTE_SET(x)
#define RTC_SET_ALARM_SECOND_MSB WLAN_RTC_SET_ALARM_SECOND_MSB
#define RTC_SET_ALARM_SECOND_LSB WLAN_RTC_SET_ALARM_SECOND_LSB
#define RTC_SET_ALARM_SECOND_MASK WLAN_RTC_SET_ALARM_SECOND_MASK
#define RTC_SET_ALARM_SECOND_GET(x) WLAN_RTC_SET_ALARM_SECOND_GET(x)
#define RTC_SET_ALARM_SECOND_SET(x) WLAN_RTC_SET_ALARM_SECOND_SET(x)
#define RTC_CONFIG_ADDRESS WLAN_RTC_CONFIG_ADDRESS
#define RTC_CONFIG_OFFSET WLAN_RTC_CONFIG_OFFSET
#define RTC_CONFIG_BCD_MSB WLAN_RTC_CONFIG_BCD_MSB
#define RTC_CONFIG_BCD_LSB WLAN_RTC_CONFIG_BCD_LSB
#define RTC_CONFIG_BCD_MASK WLAN_RTC_CONFIG_BCD_MASK
#define RTC_CONFIG_BCD_GET(x) WLAN_RTC_CONFIG_BCD_GET(x)
#define RTC_CONFIG_BCD_SET(x) WLAN_RTC_CONFIG_BCD_SET(x)
#define RTC_CONFIG_TWELVE_HOUR_MSB WLAN_RTC_CONFIG_TWELVE_HOUR_MSB
#define RTC_CONFIG_TWELVE_HOUR_LSB WLAN_RTC_CONFIG_TWELVE_HOUR_LSB
#define RTC_CONFIG_TWELVE_HOUR_MASK WLAN_RTC_CONFIG_TWELVE_HOUR_MASK
#define RTC_CONFIG_TWELVE_HOUR_GET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_GET(x)
#define RTC_CONFIG_TWELVE_HOUR_SET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_SET(x)
#define RTC_CONFIG_DSE_MSB WLAN_RTC_CONFIG_DSE_MSB
#define RTC_CONFIG_DSE_LSB WLAN_RTC_CONFIG_DSE_LSB
#define RTC_CONFIG_DSE_MASK WLAN_RTC_CONFIG_DSE_MASK
#define RTC_CONFIG_DSE_GET(x) WLAN_RTC_CONFIG_DSE_GET(x)
#define RTC_CONFIG_DSE_SET(x) WLAN_RTC_CONFIG_DSE_SET(x)
#define RTC_ALARM_STATUS_ADDRESS WLAN_RTC_ALARM_STATUS_ADDRESS
#define RTC_ALARM_STATUS_OFFSET WLAN_RTC_ALARM_STATUS_OFFSET
#define RTC_ALARM_STATUS_ENABLE_MSB WLAN_RTC_ALARM_STATUS_ENABLE_MSB
#define RTC_ALARM_STATUS_ENABLE_LSB WLAN_RTC_ALARM_STATUS_ENABLE_LSB
#define RTC_ALARM_STATUS_ENABLE_MASK WLAN_RTC_ALARM_STATUS_ENABLE_MASK
#define RTC_ALARM_STATUS_ENABLE_GET(x) WLAN_RTC_ALARM_STATUS_ENABLE_GET(x)
#define RTC_ALARM_STATUS_ENABLE_SET(x) WLAN_RTC_ALARM_STATUS_ENABLE_SET(x)
#define RTC_ALARM_STATUS_INTERRUPT_MSB WLAN_RTC_ALARM_STATUS_INTERRUPT_MSB
#define RTC_ALARM_STATUS_INTERRUPT_LSB WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB
#define RTC_ALARM_STATUS_INTERRUPT_MASK WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK
#define RTC_ALARM_STATUS_INTERRUPT_GET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_GET(x)
#define RTC_ALARM_STATUS_INTERRUPT_SET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_SET(x)
#define UART_WAKEUP_ADDRESS WLAN_UART_WAKEUP_ADDRESS
#define UART_WAKEUP_OFFSET WLAN_UART_WAKEUP_OFFSET
#define UART_WAKEUP_ENABLE_MSB WLAN_UART_WAKEUP_ENABLE_MSB
#define UART_WAKEUP_ENABLE_LSB WLAN_UART_WAKEUP_ENABLE_LSB
#define UART_WAKEUP_ENABLE_MASK WLAN_UART_WAKEUP_ENABLE_MASK
#define UART_WAKEUP_ENABLE_GET(x) WLAN_UART_WAKEUP_ENABLE_GET(x)
#define UART_WAKEUP_ENABLE_SET(x) WLAN_UART_WAKEUP_ENABLE_SET(x)
#define RESET_CAUSE_ADDRESS WLAN_RESET_CAUSE_ADDRESS
#define RESET_CAUSE_OFFSET WLAN_RESET_CAUSE_OFFSET
#define RESET_CAUSE_LAST_MSB WLAN_RESET_CAUSE_LAST_MSB
#define RESET_CAUSE_LAST_LSB WLAN_RESET_CAUSE_LAST_LSB
#define RESET_CAUSE_LAST_MASK WLAN_RESET_CAUSE_LAST_MASK
#define RESET_CAUSE_LAST_GET(x) WLAN_RESET_CAUSE_LAST_GET(x)
#define RESET_CAUSE_LAST_SET(x) WLAN_RESET_CAUSE_LAST_SET(x)
#define SYSTEM_SLEEP_ADDRESS WLAN_SYSTEM_SLEEP_ADDRESS
#define SYSTEM_SLEEP_OFFSET WLAN_SYSTEM_SLEEP_OFFSET
#define SYSTEM_SLEEP_HOST_IF_MSB WLAN_SYSTEM_SLEEP_HOST_IF_MSB
#define SYSTEM_SLEEP_HOST_IF_LSB WLAN_SYSTEM_SLEEP_HOST_IF_LSB
#define SYSTEM_SLEEP_HOST_IF_MASK WLAN_SYSTEM_SLEEP_HOST_IF_MASK
#define SYSTEM_SLEEP_HOST_IF_GET(x) WLAN_SYSTEM_SLEEP_HOST_IF_GET(x)
#define SYSTEM_SLEEP_HOST_IF_SET(x) WLAN_SYSTEM_SLEEP_HOST_IF_SET(x)
#define SYSTEM_SLEEP_MBOX_MSB WLAN_SYSTEM_SLEEP_MBOX_MSB
#define SYSTEM_SLEEP_MBOX_LSB WLAN_SYSTEM_SLEEP_MBOX_LSB
#define SYSTEM_SLEEP_MBOX_MASK WLAN_SYSTEM_SLEEP_MBOX_MASK
#define SYSTEM_SLEEP_MBOX_GET(x) WLAN_SYSTEM_SLEEP_MBOX_GET(x)
#define SYSTEM_SLEEP_MBOX_SET(x) WLAN_SYSTEM_SLEEP_MBOX_SET(x)
#define SYSTEM_SLEEP_MAC_IF_MSB WLAN_SYSTEM_SLEEP_MAC_IF_MSB
#define SYSTEM_SLEEP_MAC_IF_LSB WLAN_SYSTEM_SLEEP_MAC_IF_LSB
#define SYSTEM_SLEEP_MAC_IF_MASK WLAN_SYSTEM_SLEEP_MAC_IF_MASK
#define SYSTEM_SLEEP_MAC_IF_GET(x) WLAN_SYSTEM_SLEEP_MAC_IF_GET(x)
#define SYSTEM_SLEEP_MAC_IF_SET(x) WLAN_SYSTEM_SLEEP_MAC_IF_SET(x)
#define SYSTEM_SLEEP_LIGHT_MSB WLAN_SYSTEM_SLEEP_LIGHT_MSB
#define SYSTEM_SLEEP_LIGHT_LSB WLAN_SYSTEM_SLEEP_LIGHT_LSB
#define SYSTEM_SLEEP_LIGHT_MASK WLAN_SYSTEM_SLEEP_LIGHT_MASK
#define SYSTEM_SLEEP_LIGHT_GET(x) WLAN_SYSTEM_SLEEP_LIGHT_GET(x)
#define SYSTEM_SLEEP_LIGHT_SET(x) WLAN_SYSTEM_SLEEP_LIGHT_SET(x)
#define SYSTEM_SLEEP_DISABLE_MSB WLAN_SYSTEM_SLEEP_DISABLE_MSB
#define SYSTEM_SLEEP_DISABLE_LSB WLAN_SYSTEM_SLEEP_DISABLE_LSB
#define SYSTEM_SLEEP_DISABLE_MASK WLAN_SYSTEM_SLEEP_DISABLE_MASK
#define SYSTEM_SLEEP_DISABLE_GET(x) WLAN_SYSTEM_SLEEP_DISABLE_GET(x)
#define SYSTEM_SLEEP_DISABLE_SET(x) WLAN_SYSTEM_SLEEP_DISABLE_SET(x)
#define SDIO_WRAPPER_ADDRESS WLAN_SDIO_WRAPPER_ADDRESS
#define SDIO_WRAPPER_OFFSET WLAN_SDIO_WRAPPER_OFFSET
#define SDIO_WRAPPER_SLEEP_MSB WLAN_SDIO_WRAPPER_SLEEP_MSB
#define SDIO_WRAPPER_SLEEP_LSB WLAN_SDIO_WRAPPER_SLEEP_LSB
#define SDIO_WRAPPER_SLEEP_MASK WLAN_SDIO_WRAPPER_SLEEP_MASK
#define SDIO_WRAPPER_SLEEP_GET(x) WLAN_SDIO_WRAPPER_SLEEP_GET(x)
#define SDIO_WRAPPER_SLEEP_SET(x) WLAN_SDIO_WRAPPER_SLEEP_SET(x)
#define SDIO_WRAPPER_WAKEUP_MSB WLAN_SDIO_WRAPPER_WAKEUP_MSB
#define SDIO_WRAPPER_WAKEUP_LSB WLAN_SDIO_WRAPPER_WAKEUP_LSB
#define SDIO_WRAPPER_WAKEUP_MASK WLAN_SDIO_WRAPPER_WAKEUP_MASK
#define SDIO_WRAPPER_WAKEUP_GET(x) WLAN_SDIO_WRAPPER_WAKEUP_GET(x)
#define SDIO_WRAPPER_WAKEUP_SET(x) WLAN_SDIO_WRAPPER_WAKEUP_SET(x)
#define SDIO_WRAPPER_SOC_ON_MSB WLAN_SDIO_WRAPPER_SOC_ON_MSB
#define SDIO_WRAPPER_SOC_ON_LSB WLAN_SDIO_WRAPPER_SOC_ON_LSB
#define SDIO_WRAPPER_SOC_ON_MASK WLAN_SDIO_WRAPPER_SOC_ON_MASK
#define SDIO_WRAPPER_SOC_ON_GET(x) WLAN_SDIO_WRAPPER_SOC_ON_GET(x)
#define SDIO_WRAPPER_SOC_ON_SET(x) WLAN_SDIO_WRAPPER_SOC_ON_SET(x)
#define SDIO_WRAPPER_ON_MSB WLAN_SDIO_WRAPPER_ON_MSB
#define SDIO_WRAPPER_ON_LSB WLAN_SDIO_WRAPPER_ON_LSB
#define SDIO_WRAPPER_ON_MASK WLAN_SDIO_WRAPPER_ON_MASK
#define SDIO_WRAPPER_ON_GET(x) WLAN_SDIO_WRAPPER_ON_GET(x)
#define SDIO_WRAPPER_ON_SET(x) WLAN_SDIO_WRAPPER_ON_SET(x)
#define MAC_SLEEP_CONTROL_ADDRESS WLAN_MAC_SLEEP_CONTROL_ADDRESS
#define MAC_SLEEP_CONTROL_OFFSET WLAN_MAC_SLEEP_CONTROL_OFFSET
#define MAC_SLEEP_CONTROL_ENABLE_MSB WLAN_MAC_SLEEP_CONTROL_ENABLE_MSB
#define MAC_SLEEP_CONTROL_ENABLE_LSB WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB
#define MAC_SLEEP_CONTROL_ENABLE_MASK WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK
#define MAC_SLEEP_CONTROL_ENABLE_GET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_GET(x)
#define MAC_SLEEP_CONTROL_ENABLE_SET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_SET(x)
#define KEEP_AWAKE_ADDRESS WLAN_KEEP_AWAKE_ADDRESS
#define KEEP_AWAKE_OFFSET WLAN_KEEP_AWAKE_OFFSET
#define KEEP_AWAKE_COUNT_MSB WLAN_KEEP_AWAKE_COUNT_MSB
#define KEEP_AWAKE_COUNT_LSB WLAN_KEEP_AWAKE_COUNT_LSB
#define KEEP_AWAKE_COUNT_MASK WLAN_KEEP_AWAKE_COUNT_MASK
#define KEEP_AWAKE_COUNT_GET(x) WLAN_KEEP_AWAKE_COUNT_GET(x)
#define KEEP_AWAKE_COUNT_SET(x) WLAN_KEEP_AWAKE_COUNT_SET(x)
#define LPO_CAL_TIME_ADDRESS WLAN_LPO_CAL_TIME_ADDRESS
#define LPO_CAL_TIME_OFFSET WLAN_LPO_CAL_TIME_OFFSET
#define LPO_CAL_TIME_LENGTH_MSB WLAN_LPO_CAL_TIME_LENGTH_MSB
#define LPO_CAL_TIME_LENGTH_LSB WLAN_LPO_CAL_TIME_LENGTH_LSB
#define LPO_CAL_TIME_LENGTH_MASK WLAN_LPO_CAL_TIME_LENGTH_MASK
#define LPO_CAL_TIME_LENGTH_GET(x) WLAN_LPO_CAL_TIME_LENGTH_GET(x)
#define LPO_CAL_TIME_LENGTH_SET(x) WLAN_LPO_CAL_TIME_LENGTH_SET(x)
#define LPO_INIT_DIVIDEND_INT_ADDRESS WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS
#define LPO_INIT_DIVIDEND_INT_OFFSET WLAN_LPO_INIT_DIVIDEND_INT_OFFSET
#define LPO_INIT_DIVIDEND_INT_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB
#define LPO_INIT_DIVIDEND_INT_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB
#define LPO_INIT_DIVIDEND_INT_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK
#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_GET(x)
#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_SET(x)
#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS WLAN_LPO_INIT_DIVIDEND_FRACTION_ADDRESS
#define LPO_INIT_DIVIDEND_FRACTION_OFFSET WLAN_LPO_INIT_DIVIDEND_FRACTION_OFFSET
#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB
#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB
#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK
#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x)
#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x)
#define LPO_CAL_ADDRESS WLAN_LPO_CAL_ADDRESS
#define LPO_CAL_OFFSET WLAN_LPO_CAL_OFFSET
#define LPO_CAL_ENABLE_MSB WLAN_LPO_CAL_ENABLE_MSB
#define LPO_CAL_ENABLE_LSB WLAN_LPO_CAL_ENABLE_LSB
#define LPO_CAL_ENABLE_MASK WLAN_LPO_CAL_ENABLE_MASK
#define LPO_CAL_ENABLE_GET(x) WLAN_LPO_CAL_ENABLE_GET(x)
#define LPO_CAL_ENABLE_SET(x) WLAN_LPO_CAL_ENABLE_SET(x)
#define LPO_CAL_COUNT_MSB WLAN_LPO_CAL_COUNT_MSB
#define LPO_CAL_COUNT_LSB WLAN_LPO_CAL_COUNT_LSB
#define LPO_CAL_COUNT_MASK WLAN_LPO_CAL_COUNT_MASK
#define LPO_CAL_COUNT_GET(x) WLAN_LPO_CAL_COUNT_GET(x)
#define LPO_CAL_COUNT_SET(x) WLAN_LPO_CAL_COUNT_SET(x)
#define LPO_CAL_TEST_CONTROL_ADDRESS WLAN_LPO_CAL_TEST_CONTROL_ADDRESS
#define LPO_CAL_TEST_CONTROL_OFFSET WLAN_LPO_CAL_TEST_CONTROL_OFFSET
#define LPO_CAL_TEST_CONTROL_ENABLE_MSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MSB
#define LPO_CAL_TEST_CONTROL_ENABLE_LSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB
#define LPO_CAL_TEST_CONTROL_ENABLE_MASK WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK
#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_GET(x)
#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_SET(x)
#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB
#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB
#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK
#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x)
#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x)
#define LPO_CAL_TEST_STATUS_ADDRESS WLAN_LPO_CAL_TEST_STATUS_ADDRESS
#define LPO_CAL_TEST_STATUS_OFFSET WLAN_LPO_CAL_TEST_STATUS_OFFSET
#define LPO_CAL_TEST_STATUS_READY_MSB WLAN_LPO_CAL_TEST_STATUS_READY_MSB
#define LPO_CAL_TEST_STATUS_READY_LSB WLAN_LPO_CAL_TEST_STATUS_READY_LSB
#define LPO_CAL_TEST_STATUS_READY_MASK WLAN_LPO_CAL_TEST_STATUS_READY_MASK
#define LPO_CAL_TEST_STATUS_READY_GET(x) WLAN_LPO_CAL_TEST_STATUS_READY_GET(x)
#define LPO_CAL_TEST_STATUS_READY_SET(x) WLAN_LPO_CAL_TEST_STATUS_READY_SET(x)
#define LPO_CAL_TEST_STATUS_COUNT_MSB WLAN_LPO_CAL_TEST_STATUS_COUNT_MSB
#define LPO_CAL_TEST_STATUS_COUNT_LSB WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB
#define LPO_CAL_TEST_STATUS_COUNT_MASK WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK
#define LPO_CAL_TEST_STATUS_COUNT_GET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_GET(x)
#define LPO_CAL_TEST_STATUS_COUNT_SET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_SET(x)
#define CHIP_ID_ADDRESS WLAN_CHIP_ID_ADDRESS
#define CHIP_ID_OFFSET WLAN_CHIP_ID_OFFSET
#define CHIP_ID_DEVICE_ID_MSB WLAN_CHIP_ID_DEVICE_ID_MSB
#define CHIP_ID_DEVICE_ID_LSB WLAN_CHIP_ID_DEVICE_ID_LSB
#define CHIP_ID_DEVICE_ID_MASK WLAN_CHIP_ID_DEVICE_ID_MASK
#define CHIP_ID_DEVICE_ID_GET(x) WLAN_CHIP_ID_DEVICE_ID_GET(x)
#define CHIP_ID_DEVICE_ID_SET(x) WLAN_CHIP_ID_DEVICE_ID_SET(x)
#define CHIP_ID_CONFIG_ID_MSB WLAN_CHIP_ID_CONFIG_ID_MSB
#define CHIP_ID_CONFIG_ID_LSB WLAN_CHIP_ID_CONFIG_ID_LSB
#define CHIP_ID_CONFIG_ID_MASK WLAN_CHIP_ID_CONFIG_ID_MASK
#define CHIP_ID_CONFIG_ID_GET(x) WLAN_CHIP_ID_CONFIG_ID_GET(x)
#define CHIP_ID_CONFIG_ID_SET(x) WLAN_CHIP_ID_CONFIG_ID_SET(x)
#define CHIP_ID_VERSION_ID_MSB WLAN_CHIP_ID_VERSION_ID_MSB
#define CHIP_ID_VERSION_ID_LSB WLAN_CHIP_ID_VERSION_ID_LSB
#define CHIP_ID_VERSION_ID_MASK WLAN_CHIP_ID_VERSION_ID_MASK
#define CHIP_ID_VERSION_ID_GET(x) WLAN_CHIP_ID_VERSION_ID_GET(x)
#define CHIP_ID_VERSION_ID_SET(x) WLAN_CHIP_ID_VERSION_ID_SET(x)
#define DERIVED_RTC_CLK_ADDRESS WLAN_DERIVED_RTC_CLK_ADDRESS
#define DERIVED_RTC_CLK_OFFSET WLAN_DERIVED_RTC_CLK_OFFSET
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x)
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x)
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x)
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x)
#define DERIVED_RTC_CLK_FORCE_MSB WLAN_DERIVED_RTC_CLK_FORCE_MSB
#define DERIVED_RTC_CLK_FORCE_LSB WLAN_DERIVED_RTC_CLK_FORCE_LSB
#define DERIVED_RTC_CLK_FORCE_MASK WLAN_DERIVED_RTC_CLK_FORCE_MASK
#define DERIVED_RTC_CLK_FORCE_GET(x) WLAN_DERIVED_RTC_CLK_FORCE_GET(x)
#define DERIVED_RTC_CLK_FORCE_SET(x) WLAN_DERIVED_RTC_CLK_FORCE_SET(x)
#define DERIVED_RTC_CLK_PERIOD_MSB WLAN_DERIVED_RTC_CLK_PERIOD_MSB
#define DERIVED_RTC_CLK_PERIOD_LSB WLAN_DERIVED_RTC_CLK_PERIOD_LSB
#define DERIVED_RTC_CLK_PERIOD_MASK WLAN_DERIVED_RTC_CLK_PERIOD_MASK
#define DERIVED_RTC_CLK_PERIOD_GET(x) WLAN_DERIVED_RTC_CLK_PERIOD_GET(x)
#define DERIVED_RTC_CLK_PERIOD_SET(x) WLAN_DERIVED_RTC_CLK_PERIOD_SET(x)
#define POWER_REG_ADDRESS WLAN_POWER_REG_ADDRESS
#define POWER_REG_OFFSET WLAN_POWER_REG_OFFSET
#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB
#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB
#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK
#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x)
#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x)
#define POWER_REG_DEBUG_EN_MSB WLAN_POWER_REG_DEBUG_EN_MSB
#define POWER_REG_DEBUG_EN_LSB WLAN_POWER_REG_DEBUG_EN_LSB
#define POWER_REG_DEBUG_EN_MASK WLAN_POWER_REG_DEBUG_EN_MASK
#define POWER_REG_DEBUG_EN_GET(x) WLAN_POWER_REG_DEBUG_EN_GET(x)
#define POWER_REG_DEBUG_EN_SET(x) WLAN_POWER_REG_DEBUG_EN_SET(x)
#define POWER_REG_WLAN_BB_PWD_EN_MSB WLAN_POWER_REG_WLAN_BB_PWD_EN_MSB
#define POWER_REG_WLAN_BB_PWD_EN_LSB WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB
#define POWER_REG_WLAN_BB_PWD_EN_MASK WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK
#define POWER_REG_WLAN_BB_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_GET(x)
#define POWER_REG_WLAN_BB_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_SET(x)
#define POWER_REG_WLAN_MAC_PWD_EN_MSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_MSB
#define POWER_REG_WLAN_MAC_PWD_EN_LSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB
#define POWER_REG_WLAN_MAC_PWD_EN_MASK WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK
#define POWER_REG_WLAN_MAC_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_GET(x)
#define POWER_REG_WLAN_MAC_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_SET(x)
#define POWER_REG_VLVL_MSB WLAN_POWER_REG_VLVL_MSB
#define POWER_REG_VLVL_LSB WLAN_POWER_REG_VLVL_LSB
#define POWER_REG_VLVL_MASK WLAN_POWER_REG_VLVL_MASK
#define POWER_REG_VLVL_GET(x) WLAN_POWER_REG_VLVL_GET(x)
#define POWER_REG_VLVL_SET(x) WLAN_POWER_REG_VLVL_SET(x)
#define POWER_REG_CPU_INT_ENABLE_MSB WLAN_POWER_REG_CPU_INT_ENABLE_MSB
#define POWER_REG_CPU_INT_ENABLE_LSB WLAN_POWER_REG_CPU_INT_ENABLE_LSB
#define POWER_REG_CPU_INT_ENABLE_MASK WLAN_POWER_REG_CPU_INT_ENABLE_MASK
#define POWER_REG_CPU_INT_ENABLE_GET(x) WLAN_POWER_REG_CPU_INT_ENABLE_GET(x)
#define POWER_REG_CPU_INT_ENABLE_SET(x) WLAN_POWER_REG_CPU_INT_ENABLE_SET(x)
#define POWER_REG_WLAN_ISO_DIS_MSB WLAN_POWER_REG_WLAN_ISO_DIS_MSB
#define POWER_REG_WLAN_ISO_DIS_LSB WLAN_POWER_REG_WLAN_ISO_DIS_LSB
#define POWER_REG_WLAN_ISO_DIS_MASK WLAN_POWER_REG_WLAN_ISO_DIS_MASK
#define POWER_REG_WLAN_ISO_DIS_GET(x) WLAN_POWER_REG_WLAN_ISO_DIS_GET(x)
#define POWER_REG_WLAN_ISO_DIS_SET(x) WLAN_POWER_REG_WLAN_ISO_DIS_SET(x)
#define POWER_REG_WLAN_ISO_CNTL_MSB WLAN_POWER_REG_WLAN_ISO_CNTL_MSB
#define POWER_REG_WLAN_ISO_CNTL_LSB WLAN_POWER_REG_WLAN_ISO_CNTL_LSB
#define POWER_REG_WLAN_ISO_CNTL_MASK WLAN_POWER_REG_WLAN_ISO_CNTL_MASK
#define POWER_REG_WLAN_ISO_CNTL_GET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_GET(x)
#define POWER_REG_WLAN_ISO_CNTL_SET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_SET(x)
#define POWER_REG_RADIO_PWD_EN_MSB WLAN_POWER_REG_RADIO_PWD_EN_MSB
#define POWER_REG_RADIO_PWD_EN_LSB WLAN_POWER_REG_RADIO_PWD_EN_LSB
#define POWER_REG_RADIO_PWD_EN_MASK WLAN_POWER_REG_RADIO_PWD_EN_MASK
#define POWER_REG_RADIO_PWD_EN_GET(x) WLAN_POWER_REG_RADIO_PWD_EN_GET(x)
#define POWER_REG_RADIO_PWD_EN_SET(x) WLAN_POWER_REG_RADIO_PWD_EN_SET(x)
#define POWER_REG_SOC_ISO_EN_MSB WLAN_POWER_REG_SOC_ISO_EN_MSB
#define POWER_REG_SOC_ISO_EN_LSB WLAN_POWER_REG_SOC_ISO_EN_LSB
#define POWER_REG_SOC_ISO_EN_MASK WLAN_POWER_REG_SOC_ISO_EN_MASK
#define POWER_REG_SOC_ISO_EN_GET(x) WLAN_POWER_REG_SOC_ISO_EN_GET(x)
#define POWER_REG_SOC_ISO_EN_SET(x) WLAN_POWER_REG_SOC_ISO_EN_SET(x)
#define POWER_REG_WLAN_ISO_EN_MSB WLAN_POWER_REG_WLAN_ISO_EN_MSB
#define POWER_REG_WLAN_ISO_EN_LSB WLAN_POWER_REG_WLAN_ISO_EN_LSB
#define POWER_REG_WLAN_ISO_EN_MASK WLAN_POWER_REG_WLAN_ISO_EN_MASK
#define POWER_REG_WLAN_ISO_EN_GET(x) WLAN_POWER_REG_WLAN_ISO_EN_GET(x)
#define POWER_REG_WLAN_ISO_EN_SET(x) WLAN_POWER_REG_WLAN_ISO_EN_SET(x)
#define POWER_REG_WLAN_PWD_EN_MSB WLAN_POWER_REG_WLAN_PWD_EN_MSB
#define POWER_REG_WLAN_PWD_EN_LSB WLAN_POWER_REG_WLAN_PWD_EN_LSB
#define POWER_REG_WLAN_PWD_EN_MASK WLAN_POWER_REG_WLAN_PWD_EN_MASK
#define POWER_REG_WLAN_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_PWD_EN_GET(x)
#define POWER_REG_WLAN_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_PWD_EN_SET(x)
#define POWER_REG_POWER_EN_MSB WLAN_POWER_REG_POWER_EN_MSB
#define POWER_REG_POWER_EN_LSB WLAN_POWER_REG_POWER_EN_LSB
#define POWER_REG_POWER_EN_MASK WLAN_POWER_REG_POWER_EN_MASK
#define POWER_REG_POWER_EN_GET(x) WLAN_POWER_REG_POWER_EN_GET(x)
#define POWER_REG_POWER_EN_SET(x) WLAN_POWER_REG_POWER_EN_SET(x)
#define CORE_CLK_CTRL_ADDRESS WLAN_CORE_CLK_CTRL_ADDRESS
#define CORE_CLK_CTRL_OFFSET WLAN_CORE_CLK_CTRL_OFFSET
#define CORE_CLK_CTRL_DIV_MSB WLAN_CORE_CLK_CTRL_DIV_MSB
#define CORE_CLK_CTRL_DIV_LSB WLAN_CORE_CLK_CTRL_DIV_LSB
#define CORE_CLK_CTRL_DIV_MASK WLAN_CORE_CLK_CTRL_DIV_MASK
#define CORE_CLK_CTRL_DIV_GET(x) WLAN_CORE_CLK_CTRL_DIV_GET(x)
#define CORE_CLK_CTRL_DIV_SET(x) WLAN_CORE_CLK_CTRL_DIV_SET(x)
#define GPIO_WAKEUP_CONTROL_ADDRESS WLAN_GPIO_WAKEUP_CONTROL_ADDRESS
#define GPIO_WAKEUP_CONTROL_OFFSET WLAN_GPIO_WAKEUP_CONTROL_OFFSET
#define GPIO_WAKEUP_CONTROL_ENABLE_MSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MSB
#define GPIO_WAKEUP_CONTROL_ENABLE_LSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB
#define GPIO_WAKEUP_CONTROL_ENABLE_MASK WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK
#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_GET(x)
#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_SET(x)
#endif
#endif
wlan/include/AR6002/hw4.0/hw/rtc_wlan_reg.h
+2069
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wlan/include/AR6002/hw4.0/hw/si_reg.h
+213
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@@ -0,0 +1,213 @@
// ------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2007, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _SI_REG_REG_H_
#define _SI_REG_REG_H_
#define SI_CONFIG_ADDRESS 0x00000000
#define SI_CONFIG_OFFSET 0x00000000
#define SI_CONFIG_ERR_INT_MSB 19
#define SI_CONFIG_ERR_INT_LSB 19
#define SI_CONFIG_ERR_INT_MASK 0x00080000
#define SI_CONFIG_ERR_INT_GET(x) (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB)
#define SI_CONFIG_ERR_INT_SET(x) (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK)
#define SI_CONFIG_BIDIR_OD_DATA_MSB 18
#define SI_CONFIG_BIDIR_OD_DATA_LSB 18
#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
#define SI_CONFIG_BIDIR_OD_DATA_GET(x) (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB)
#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
#define SI_CONFIG_I2C_MSB 16
#define SI_CONFIG_I2C_LSB 16
#define SI_CONFIG_I2C_MASK 0x00010000
#define SI_CONFIG_I2C_GET(x) (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB)
#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
#define SI_CONFIG_POS_SAMPLE_MSB 7
#define SI_CONFIG_POS_SAMPLE_LSB 7
#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
#define SI_CONFIG_POS_SAMPLE_GET(x) (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB)
#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
#define SI_CONFIG_POS_DRIVE_MSB 6
#define SI_CONFIG_POS_DRIVE_LSB 6
#define SI_CONFIG_POS_DRIVE_MASK 0x00000040
#define SI_CONFIG_POS_DRIVE_GET(x) (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB)
#define SI_CONFIG_POS_DRIVE_SET(x) (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK)
#define SI_CONFIG_INACTIVE_DATA_MSB 5
#define SI_CONFIG_INACTIVE_DATA_LSB 5
#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
#define SI_CONFIG_INACTIVE_DATA_GET(x) (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB)
#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
#define SI_CONFIG_INACTIVE_CLK_MSB 4
#define SI_CONFIG_INACTIVE_CLK_LSB 4
#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
#define SI_CONFIG_INACTIVE_CLK_GET(x) (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB)
#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
#define SI_CONFIG_DIVIDER_MSB 3
#define SI_CONFIG_DIVIDER_LSB 0
#define SI_CONFIG_DIVIDER_MASK 0x0000000f
#define SI_CONFIG_DIVIDER_GET(x) (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB)
#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
#define SI_CS_ADDRESS 0x00000004
#define SI_CS_OFFSET 0x00000004
#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB 13
#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB 11
#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK 0x00003800
#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x) (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB)
#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x) (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK)
#define SI_CS_DONE_ERR_MSB 10
#define SI_CS_DONE_ERR_LSB 10
#define SI_CS_DONE_ERR_MASK 0x00000400
#define SI_CS_DONE_ERR_GET(x) (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB)
#define SI_CS_DONE_ERR_SET(x) (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK)
#define SI_CS_DONE_INT_MSB 9
#define SI_CS_DONE_INT_LSB 9
#define SI_CS_DONE_INT_MASK 0x00000200
#define SI_CS_DONE_INT_GET(x) (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB)
#define SI_CS_DONE_INT_SET(x) (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK)
#define SI_CS_START_MSB 8
#define SI_CS_START_LSB 8
#define SI_CS_START_MASK 0x00000100
#define SI_CS_START_GET(x) (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB)
#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
#define SI_CS_RX_CNT_MSB 7
#define SI_CS_RX_CNT_LSB 4
#define SI_CS_RX_CNT_MASK 0x000000f0
#define SI_CS_RX_CNT_GET(x) (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB)
#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
#define SI_CS_TX_CNT_MSB 3
#define SI_CS_TX_CNT_LSB 0
#define SI_CS_TX_CNT_MASK 0x0000000f
#define SI_CS_TX_CNT_GET(x) (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB)
#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
#define SI_TX_DATA0_ADDRESS 0x00000008
#define SI_TX_DATA0_OFFSET 0x00000008
#define SI_TX_DATA0_DATA3_MSB 31
#define SI_TX_DATA0_DATA3_LSB 24
#define SI_TX_DATA0_DATA3_MASK 0xff000000
#define SI_TX_DATA0_DATA3_GET(x) (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB)
#define SI_TX_DATA0_DATA3_SET(x) (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK)
#define SI_TX_DATA0_DATA2_MSB 23
#define SI_TX_DATA0_DATA2_LSB 16
#define SI_TX_DATA0_DATA2_MASK 0x00ff0000
#define SI_TX_DATA0_DATA2_GET(x) (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB)
#define SI_TX_DATA0_DATA2_SET(x) (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK)
#define SI_TX_DATA0_DATA1_MSB 15
#define SI_TX_DATA0_DATA1_LSB 8
#define SI_TX_DATA0_DATA1_MASK 0x0000ff00
#define SI_TX_DATA0_DATA1_GET(x) (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB)
#define SI_TX_DATA0_DATA1_SET(x) (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK)
#define SI_TX_DATA0_DATA0_MSB 7
#define SI_TX_DATA0_DATA0_LSB 0
#define SI_TX_DATA0_DATA0_MASK 0x000000ff
#define SI_TX_DATA0_DATA0_GET(x) (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB)
#define SI_TX_DATA0_DATA0_SET(x) (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK)
#define SI_TX_DATA1_ADDRESS 0x0000000c
#define SI_TX_DATA1_OFFSET 0x0000000c
#define SI_TX_DATA1_DATA7_MSB 31
#define SI_TX_DATA1_DATA7_LSB 24
#define SI_TX_DATA1_DATA7_MASK 0xff000000
#define SI_TX_DATA1_DATA7_GET(x) (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB)
#define SI_TX_DATA1_DATA7_SET(x) (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK)
#define SI_TX_DATA1_DATA6_MSB 23
#define SI_TX_DATA1_DATA6_LSB 16
#define SI_TX_DATA1_DATA6_MASK 0x00ff0000
#define SI_TX_DATA1_DATA6_GET(x) (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB)
#define SI_TX_DATA1_DATA6_SET(x) (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK)
#define SI_TX_DATA1_DATA5_MSB 15
#define SI_TX_DATA1_DATA5_LSB 8
#define SI_TX_DATA1_DATA5_MASK 0x0000ff00
#define SI_TX_DATA1_DATA5_GET(x) (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB)
#define SI_TX_DATA1_DATA5_SET(x) (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK)
#define SI_TX_DATA1_DATA4_MSB 7
#define SI_TX_DATA1_DATA4_LSB 0
#define SI_TX_DATA1_DATA4_MASK 0x000000ff
#define SI_TX_DATA1_DATA4_GET(x) (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB)
#define SI_TX_DATA1_DATA4_SET(x) (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK)
#define SI_RX_DATA0_ADDRESS 0x00000010
#define SI_RX_DATA0_OFFSET 0x00000010
#define SI_RX_DATA0_DATA3_MSB 31
#define SI_RX_DATA0_DATA3_LSB 24
#define SI_RX_DATA0_DATA3_MASK 0xff000000
#define SI_RX_DATA0_DATA3_GET(x) (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB)
#define SI_RX_DATA0_DATA3_SET(x) (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK)
#define SI_RX_DATA0_DATA2_MSB 23
#define SI_RX_DATA0_DATA2_LSB 16
#define SI_RX_DATA0_DATA2_MASK 0x00ff0000
#define SI_RX_DATA0_DATA2_GET(x) (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB)
#define SI_RX_DATA0_DATA2_SET(x) (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK)
#define SI_RX_DATA0_DATA1_MSB 15
#define SI_RX_DATA0_DATA1_LSB 8
#define SI_RX_DATA0_DATA1_MASK 0x0000ff00
#define SI_RX_DATA0_DATA1_GET(x) (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB)
#define SI_RX_DATA0_DATA1_SET(x) (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK)
#define SI_RX_DATA0_DATA0_MSB 7
#define SI_RX_DATA0_DATA0_LSB 0
#define SI_RX_DATA0_DATA0_MASK 0x000000ff
#define SI_RX_DATA0_DATA0_GET(x) (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB)
#define SI_RX_DATA0_DATA0_SET(x) (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK)
#define SI_RX_DATA1_ADDRESS 0x00000014
#define SI_RX_DATA1_OFFSET 0x00000014
#define SI_RX_DATA1_DATA7_MSB 31
#define SI_RX_DATA1_DATA7_LSB 24
#define SI_RX_DATA1_DATA7_MASK 0xff000000
#define SI_RX_DATA1_DATA7_GET(x) (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB)
#define SI_RX_DATA1_DATA7_SET(x) (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK)
#define SI_RX_DATA1_DATA6_MSB 23
#define SI_RX_DATA1_DATA6_LSB 16
#define SI_RX_DATA1_DATA6_MASK 0x00ff0000
#define SI_RX_DATA1_DATA6_GET(x) (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB)
#define SI_RX_DATA1_DATA6_SET(x) (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK)
#define SI_RX_DATA1_DATA5_MSB 15
#define SI_RX_DATA1_DATA5_LSB 8
#define SI_RX_DATA1_DATA5_MASK 0x0000ff00
#define SI_RX_DATA1_DATA5_GET(x) (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB)
#define SI_RX_DATA1_DATA5_SET(x) (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK)
#define SI_RX_DATA1_DATA4_MSB 7
#define SI_RX_DATA1_DATA4_LSB 0
#define SI_RX_DATA1_DATA4_MASK 0x000000ff
#define SI_RX_DATA1_DATA4_GET(x) (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB)
#define SI_RX_DATA1_DATA4_SET(x) (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK)
#ifndef __ASSEMBLER__
typedef struct si_reg_reg_s {
volatile unsigned int si_config;
volatile unsigned int si_cs;
volatile unsigned int si_tx_data0;
volatile unsigned int si_tx_data1;
volatile unsigned int si_rx_data0;
volatile unsigned int si_rx_data1;
} si_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _SI_REG_H_ */
wlan/include/athdefs.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __ATHDEFS_H__
#define __ATHDEFS_H__
/*
* This file contains definitions that may be used across both
* Host and Target software. Nothing here is module-dependent
* or platform-dependent.
*/
/*
* Generic error codes that can be used by hw, sta, ap, sim, dk
* and any other environments. Since these are enums, feel free to
* add any more codes that you need.
*/
typedef enum {
A_ERROR = -1, /* Generic error return */
A_OK = 0, /* success */
/* Following values start at 1 */
A_DEVICE_NOT_FOUND, /* not able to find PCI device */
A_NO_MEMORY, /* not able to allocate memory, not available */
A_MEMORY_NOT_AVAIL, /* memory region is not free for mapping */
A_NO_FREE_DESC, /* no free descriptors available */
A_BAD_ADDRESS, /* address does not match descriptor */
A_WIN_DRIVER_ERROR, /* used in NT_HW version, if problem at init */
A_REGS_NOT_MAPPED, /* registers not correctly mapped */
A_EPERM, /* Not superuser */
A_EACCES, /* Access denied */
A_ENOENT, /* No such entry, search failed, etc. */
A_EEXIST, /* The object already exists (can't create) */
A_EFAULT, /* Bad address fault */
A_EBUSY, /* Object is busy */
A_EINVAL, /* Invalid parameter */
A_EMSGSIZE, /* Inappropriate message buffer length */
A_ECANCELED, /* Operation canceled */
A_ENOTSUP, /* Operation not supported */
A_ECOMM, /* Communication error on send */
A_EPROTO, /* Protocol error */
A_ENODEV, /* No such device */
A_EDEVNOTUP, /* device is not UP */
A_NO_RESOURCE, /* No resources for requested operation */
A_HARDWARE, /* Hardware failure */
A_PENDING, /* Asynchronous routine; will send up results la
ter (typically in callback) */
A_EBADCHANNEL, /* The channel cannot be used */
A_DECRYPT_ERROR, /* Decryption error */
A_PHY_ERROR, /* RX PHY error */
A_CONSUMED /* Object was consumed */
} A_STATUS;
#define A_SUCCESS(x) (x == A_OK)
#define A_FAILED(x) (!A_SUCCESS(x))
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#endif /* __ATHDEFS_H__ */
wlan/include/bmi_msg.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __BMI_MSG_H__
#define __BMI_MSG_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/*
* Bootloader Messaging Interface (BMI)
*
* BMI is a very simple messaging interface used during initialization
* to read memory, write memory, execute code, and to define an
* application entry PC.
*
* It is used to download an application to AR6K, to provide
* patches to code that is already resident on AR6K, and generally
* to examine and modify state. The Host has an opportunity to use
* BMI only once during bootup. Once the Host issues a BMI_DONE
* command, this opportunity ends.
*
* The Host writes BMI requests to mailbox0, and reads BMI responses
* from mailbox0. BMI requests all begin with a command
* (see below for specific commands), and are followed by
* command-specific data.
*
* Flow control:
* The Host can only issue a command once the Target gives it a
* "BMI Command Credit", using AR6K Counter #4. As soon as the
* Target has completed a command, it issues another BMI Command
* Credit (so the Host can issue the next command).
*
* BMI handles all required Target-side cache flushing.
*/
/* Maximum data size used for BMI transfers */
#define BMI_DATASZ_MAX 256
/* BMI Commands */
#define BMI_NO_COMMAND 0
#define BMI_DONE 1
/*
* Semantics: Host is done using BMI
* Request format:
* A_UINT32 command (BMI_DONE)
* Response format: none
*/
#define BMI_READ_MEMORY 2
/*
* Semantics: Host reads AR6K memory
* Request format:
* A_UINT32 command (BMI_READ_MEMORY)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* Response format:
* A_UINT8 data[length]
*/
#define BMI_WRITE_MEMORY 3
/*
* Semantics: Host writes AR6K memory
* Request format:
* A_UINT32 command (BMI_WRITE_MEMORY)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* A_UINT8 data[length]
* Response format: none
*/
/*
* Capbility to write "segmented files" is provided for two reasons
* 1) backwards compatibility for certain situations where Hosts
* have limited flexibility
* 2) because it's darn convenient.
*
* A segmented file consists of a file header followed by an arbitrary number
* of segments. Each segment contains segment metadata -- a Target address and
* a length -- followed by "length" bytes of data. A segmented file ends with
* a segment that specifies length=BMI_SGMTFILE_DONE. When a segmented file
* is sent to the Target, firmware writes each segment to the specified address.
*
* Special cases:
* 1) If a segment's metadata indicates length=BMI_SGMTFILE_EXEC, then the
* specified address is used as a function entry point for a brief function
* with prototype "(void *)(void)". That function is called immediately.
* After execution of the function completes, firmware continues with the
* next segment. No data is expected when length=BMI_SGMTFILE_EXEC.
*
* 2) If a segment's metadata indicates length=BMI_SGMTFILE_BEGINADDR, then
* the specified address is established as the application start address
* so that a subsequent BMI_DONE jumps there.
*
* 3) If a segment's metadata indicates length=BMI_SGMTFILE_BDDATA, then
* the specified address is used as the (possibly compressed) length of board
* data, which is loaded into the proper Target address as specified by
* hi_board_data. In addition, the hi_board_data_initialized flag is set.
*
* A segmented file is sent to the Target using a sequence of 1 or more
* BMI_WRITE_MEMORY commands. The first such command must have
* address=BMI_SEGMENTED_WRITE_ADDR. Subsequent BMI_WRITE_MEMORY commands
* can use an arbitrary address. In each BMI_WRITE_MEMORY command, the
* length specifies the number of data bytes transmitted (except for the
* special cases listed above).
*
* Alternatively, a segmented file may be sent to the Target using a
* BMI_LZ_STREAM_START command with address=BMI_SEGMENTED_WRITE_ADDR
* followed by a series of BMI_LZ_DATA commands that each send the next portion
* of the segmented file.
*
* The data segments may be lz77 compressed. In this case, the segmented file
* header flag, BMI_SGMTFILE_FLAG_COMPRESS, must be set. Note that segmented
* file METAdata is never compressed; only the data segments themselves are
* compressed. There is no way to mix compressed and uncompressed data segments
* in a single segmented file. Compressed (or uncompressed) segments are handled
* by both BMI_WRITE_MEMORY and by BMI_LZ_DATA commands. (Compression is an
* attribute of the segmented file rather than of the command used to transmit
* it.)
*/
#define BMI_SEGMENTED_WRITE_ADDR 0x1234
/* File header for a segmented file */
struct bmi_segmented_file_header {
A_UINT32 magic_num;
A_UINT32 file_flags;
};
#define BMI_SGMTFILE_MAGIC_NUM 0x544d4753 /* "SGMT" */
#define BMI_SGMTFILE_FLAG_COMPRESS 1
/* Metadata for a segmented file segment */
struct bmi_segmented_metadata {
A_UINT32 addr;
A_UINT32 length;
};
/* Special values for bmi_segmented_metadata.length (all have high bit set) */
#define BMI_SGMTFILE_DONE 0xffffffff /* end of segmented data */
#define BMI_SGMTFILE_BDDATA 0xfffffffe /* Board Data segment */
#define BMI_SGMTFILE_BEGINADDR 0xfffffffd /* set beginning address */
#define BMI_SGMTFILE_EXEC 0xfffffffc /* immediate function execution */
#define BMI_EXECUTE 4
/*
* Semantics: Causes AR6K to execute code
* Request format:
* A_UINT32 command (BMI_EXECUTE)
* A_UINT32 address
* A_UINT32 parameter
* Response format:
* A_UINT32 return value
*/
/*
* Note: In order to support the segmented file feature
* (see BMI_WRITE_MEMORY), when the address specified in a
* BMI_EXECUTE command matches (same physical address)
* BMI_SEGMENTED_WRITE_ADDR, it is ignored. Instead, execution
* begins at the address specified by hi_app_start.
*/
#define BMI_SET_APP_START 5
/*
* Semantics: Set Target application starting address
* Request format:
* A_UINT32 command (BMI_SET_APP_START)
* A_UINT32 address
* Response format: none
*/
#define BMI_READ_SOC_REGISTER 6
/*
* Semantics: Read a 32-bit Target SOC register.
* Request format:
* A_UINT32 command (BMI_READ_REGISTER)
* A_UINT32 address
* Response format:
* A_UINT32 value
*/
#define BMI_WRITE_SOC_REGISTER 7
/*
* Semantics: Write a 32-bit Target SOC register.
* Request format:
* A_UINT32 command (BMI_WRITE_REGISTER)
* A_UINT32 address
* A_UINT32 value
*
* Response format: none
*/
#define BMI_GET_TARGET_ID 8
#define BMI_GET_TARGET_INFO 8
/*
* Semantics: Fetch the 4-byte Target information
* Request format:
* A_UINT32 command (BMI_GET_TARGET_ID/INFO)
* Response format1 (old firmware):
* A_UINT32 TargetVersionID
* Response format2 (newer firmware):
* A_UINT32 TARGET_VERSION_SENTINAL
* struct bmi_target_info;
*/
PREPACK struct bmi_target_info {
A_UINT32 target_info_byte_count; /* size of this structure */
A_UINT32 target_ver; /* Target Version ID */
A_UINT32 target_type; /* Target type */
} POSTPACK;
#define TARGET_VERSION_SENTINAL 0xffffffff
#define TARGET_TYPE_AR6001 1
#define TARGET_TYPE_AR6002 2
#define TARGET_TYPE_AR6003 3
#define TARGET_TYPE_MCKINLEY 5
#define BMI_ROMPATCH_INSTALL 9
/*
* Semantics: Install a ROM Patch.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_INSTALL)
* A_UINT32 Target ROM Address
* A_UINT32 Target RAM Address or Value (depending on Target Type)
* A_UINT32 Size, in bytes
* A_UINT32 Activate? 1-->activate;
* 0-->install but do not activate
* Response format:
* A_UINT32 PatchID
*/
#define BMI_ROMPATCH_UNINSTALL 10
/*
* Semantics: Uninstall a previously-installed ROM Patch,
* automatically deactivating, if necessary.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_UNINSTALL)
* A_UINT32 PatchID
*
* Response format: none
*/
#define BMI_ROMPATCH_ACTIVATE 11
/*
* Semantics: Activate a list of previously-installed ROM Patches.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_ACTIVATE)
* A_UINT32 rompatch_count
* A_UINT32 PatchID[rompatch_count]
*
* Response format: none
*/
#define BMI_ROMPATCH_DEACTIVATE 12
/*
* Semantics: Deactivate a list of active ROM Patches.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_DEACTIVATE)
* A_UINT32 rompatch_count
* A_UINT32 PatchID[rompatch_count]
*
* Response format: none
*/
#define BMI_LZ_STREAM_START 13
/*
* Semantics: Begin an LZ-compressed stream of input
* which is to be uncompressed by the Target to an
* output buffer at address. The output buffer must
* be sufficiently large to hold the uncompressed
* output from the compressed input stream. This BMI
* command should be followed by a series of 1 or more
* BMI_LZ_DATA commands.
* A_UINT32 command (BMI_LZ_STREAM_START)
* A_UINT32 address
* Note: Not supported on all versions of ROM firmware.
*/
#define BMI_LZ_DATA 14
/*
* Semantics: Host writes AR6K memory with LZ-compressed
* data which is uncompressed by the Target. This command
* must be preceded by a BMI_LZ_STREAM_START command. A series
* of BMI_LZ_DATA commands are considered part of a single
* input stream until another BMI_LZ_STREAM_START is issued.
* Request format:
* A_UINT32 command (BMI_LZ_DATA)
* A_UINT32 length (of compressed data),
* at most BMI_DATASZ_MAX
* A_UINT8 CompressedData[length]
* Response format: none
* Note: Not supported on all versions of ROM firmware.
*/
#define BMI_NVRAM_PROCESS 15
#define BMI_NVRAM_SEG_NAME_SZ 16
/*
* Semantics: Cause Target to search NVRAM (if any) for a
* segment with the specified name and process it according
* to NVRAM metadata.
* Request format:
* A_UINT32 command (BMI_NVRAM_PROCESS)
* A_UCHAR name[BMI_NVRAM_SEG_NAME_SZ] name (LE format)
* Response format:
* A_UINT32 0, if nothing was executed;
* otherwise the value returned from the
* last NVRAM segment that was executed
*/
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __BMI_MSG_H__ */
wlan/include/cnxmgmt.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef _CNXMGMT_H_
#define _CNXMGMT_H_
typedef enum {
CM_CONNECT_WITHOUT_SCAN = 0x0001,
CM_CONNECT_ASSOC_POLICY_USER = 0x0002,
CM_CONNECT_SEND_REASSOC = 0x0004,
CM_CONNECT_WITHOUT_ROAMTABLE_UPDATE = 0x0008,
CM_CONNECT_DO_WPA_OFFLOAD = 0x0010,
CM_CONNECT_DO_NOT_DEAUTH = 0x0020,
CM_CONNECT_IGNORE_BSSID_HINT = 0x0040,
CM_CONNECT_STAY_AWAKE = 0x0080,
} CM_CONNECT_TYPE;
#endif /* _CNXMGMT_H_ */
wlan/include/dbglog.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef _DBGLOG_H_
#define _DBGLOG_H_
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#define DBGLOG_TIMESTAMP_OFFSET 0
#define DBGLOG_TIMESTAMP_MASK 0x0000FFFF /* Bit 0-15. Contains bit
8-23 of the LF0 timer */
#define DBGLOG_DBGID_OFFSET 16
#define DBGLOG_DBGID_MASK 0x03FF0000 /* Bit 16-25 */
#define DBGLOG_DBGID_NUM_MAX 256 /* Upper limit is width of mask */
#define DBGLOG_MODULEID_OFFSET 26
#define DBGLOG_MODULEID_MASK 0x3C000000 /* Bit 26-29 */
#define DBGLOG_MODULEID_NUM_MAX 16 /* Upper limit is width of mask */
/*
* Please ensure that the definition of any new module intrduced is captured
* between the DBGLOG_MODULEID_START and DBGLOG_MODULEID_END defines. The
* structure is required for the parser to correctly pick up the values for
* different modules.
*/
#define DBGLOG_MODULEID_START
#define DBGLOG_MODULEID_INF 0
#define DBGLOG_MODULEID_WMI 1
#define DBGLOG_MODULEID_MISC 2
#define DBGLOG_MODULEID_PM 3
#define DBGLOG_MODULEID_TXRX_MGMTBUF 4
#define DBGLOG_MODULEID_TXRX_TXBUF 5
#define DBGLOG_MODULEID_TXRX_RXBUF 6
#define DBGLOG_MODULEID_WOW 7
#define DBGLOG_MODULEID_WHAL 8
#define DBGLOG_MODULEID_DC 9
#define DBGLOG_MODULEID_CO 10
#define DBGLOG_MODULEID_RO 11
#define DBGLOG_MODULEID_CM 12
#define DBGLOG_MODULEID_MGMT 13
#define DBGLOG_MODULEID_TMR 14
#define DBGLOG_MODULEID_BTCOEX 15
#define DBGLOG_MODULEID_END
#define DBGLOG_NUM_ARGS_OFFSET 30
#define DBGLOG_NUM_ARGS_MASK 0xC0000000 /* Bit 30-31 */
#define DBGLOG_NUM_ARGS_MAX 2 /* Upper limit is width of mask */
#define DBGLOG_MODULE_LOG_ENABLE_OFFSET 0
#define DBGLOG_MODULE_LOG_ENABLE_MASK 0x0000FFFF
#define DBGLOG_REPORTING_ENABLED_OFFSET 16
#define DBGLOG_REPORTING_ENABLED_MASK 0x00010000
#define DBGLOG_TIMESTAMP_RESOLUTION_OFFSET 17
#define DBGLOG_TIMESTAMP_RESOLUTION_MASK 0x000E0000
#define DBGLOG_REPORT_SIZE_OFFSET 20
#define DBGLOG_REPORT_SIZE_MASK 0x3FF00000
#define DBGLOG_LOG_BUFFER_SIZE 1500
#define DBGLOG_DBGID_DEFINITION_LEN_MAX 90
PREPACK struct dbglog_buf_s {
struct dbglog_buf_s *next;
A_UINT8 *buffer;
A_UINT32 bufsize;
A_UINT32 length;
A_UINT32 count;
A_UINT32 free;
} POSTPACK;
PREPACK struct dbglog_hdr_s {
struct dbglog_buf_s *dbuf;
A_UINT32 dropped;
} POSTPACK;
PREPACK struct dbglog_config_s {
A_UINT32 cfgvalid; /* Mask with valid config bits */
union {
/* TODO: Take care of endianness */
struct {
A_UINT32 mmask:16; /* Mask of modules with logging on */
A_UINT32 rep:1; /* Reporting enabled or not */
A_UINT32 tsr:3; /* Time stamp resolution. Def: 1 ms */
A_UINT32 size:10; /* Report size in number of messages */
A_UINT32 reserved:2;
} dbglog_config;
A_UINT32 value;
} u;
} POSTPACK;
#define cfgmmask u.dbglog_config.mmask
#define cfgrep u.dbglog_config.rep
#define cfgtsr u.dbglog_config.tsr
#define cfgsize u.dbglog_config.size
#define cfgvalue u.value
#ifdef __cplusplus
}
#endif
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* _DBGLOG_H_ */
wlan/include/dbglog_id.h
+596
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@@ -0,0 +1,596 @@
//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef _DBGLOG_ID_H_
#define _DBGLOG_ID_H_
#ifdef __cplusplus
extern "C" {
#endif
/*
* The nomenclature for the debug identifiers is MODULE_DESCRIPTION.
* Please ensure that the definition of any new debugid introduced is captured
* between the <MODULE>_DBGID_DEFINITION_START and
* <MODULE>_DBGID_DEFINITION_END defines. The structure is required for the
* parser to correctly pick up the values for different debug identifiers.
*/
/* INF debug identifier definitions */
#define INF_DBGID_DEFINITION_START
#define INF_ASSERTION_FAILED 1
#define INF_TARGET_ID 2
#define INF_DBGID_DEFINITION_END
/* WMI debug identifier definitions */
#define WMI_DBGID_DEFINITION_START
#define WMI_CMD_RX_XTND_PKT_TOO_SHORT 1
#define WMI_EXTENDED_CMD_NOT_HANDLED 2
#define WMI_CMD_RX_PKT_TOO_SHORT 3
#define WMI_CALLING_WMI_EXTENSION_FN 4
#define WMI_CMD_NOT_HANDLED 5
#define WMI_IN_SYNC 6
#define WMI_TARGET_WMI_SYNC_CMD 7
#define WMI_SET_SNR_THRESHOLD_PARAMS 8
#define WMI_SET_RSSI_THRESHOLD_PARAMS 9
#define WMI_SET_LQ_TRESHOLD_PARAMS 10
#define WMI_TARGET_CREATE_PSTREAM_CMD 11
#define WMI_WI_DTM_INUSE 12
#define WMI_TARGET_DELETE_PSTREAM_CMD 13
#define WMI_TARGET_IMPLICIT_DELETE_PSTREAM_CMD 14
#define WMI_TARGET_GET_BIT_RATE_CMD 15
#define WMI_GET_RATE_MASK_CMD_FIX_RATE_MASK_IS 16
#define WMI_TARGET_GET_AVAILABLE_CHANNELS_CMD 17
#define WMI_TARGET_GET_TX_PWR_CMD 18
#define WMI_FREE_EVBUF_WMIBUF 19
#define WMI_FREE_EVBUF_DATABUF 20
#define WMI_FREE_EVBUF_BADFLAG 21
#define WMI_HTC_RX_ERROR_DATA_PACKET 22
#define WMI_HTC_RX_SYNC_PAUSING_FOR_MBOX 23
#define WMI_INCORRECT_WMI_DATA_HDR_DROPPING_PKT 24
#define WMI_SENDING_READY_EVENT 25
#define WMI_SETPOWER_MDOE_TO_MAXPERF 26
#define WMI_SETPOWER_MDOE_TO_REC 27
#define WMI_BSSINFO_EVENT_FROM 28
#define WMI_TARGET_GET_STATS_CMD 29
#define WMI_SENDING_SCAN_COMPLETE_EVENT 30
#define WMI_SENDING_RSSI_INDB_THRESHOLD_EVENT 31
#define WMI_SENDING_RSSI_INDBM_THRESHOLD_EVENT 32
#define WMI_SENDING_LINK_QUALITY_THRESHOLD_EVENT 33
#define WMI_SENDING_ERROR_REPORT_EVENT 34
#define WMI_SENDING_CAC_EVENT 35
#define WMI_TARGET_GET_ROAM_TABLE_CMD 36
#define WMI_TARGET_GET_ROAM_DATA_CMD 37
#define WMI_SENDING_GPIO_INTR_EVENT 38
#define WMI_SENDING_GPIO_ACK_EVENT 39
#define WMI_SENDING_GPIO_DATA_EVENT 40
#define WMI_CMD_RX 41
#define WMI_CMD_RX_XTND 42
#define WMI_EVENT_SEND 43
#define WMI_EVENT_SEND_XTND 44
#define WMI_CMD_PARAMS_DUMP_START 45
#define WMI_CMD_PARAMS_DUMP_END 46
#define WMI_CMD_PARAMS 47
#define WMI_DBGID_DEFINITION_END
/* MISC debug identifier definitions */
#define MISC_DBGID_DEFINITION_START
#define MISC_WLAN_SCHEDULER_EVENT_REGISTER_ERROR 1
#define TLPM_INIT 2
#define TLPM_FILTER_POWER_STATE 3
#define TLPM_NOTIFY_NOT_IDLE 4
#define TLPM_TIMEOUT_IDLE_HANDLER 5
#define TLPM_TIMEOUT_WAKEUP_HANDLER 6
#define TLPM_WAKEUP_SIGNAL_HANDLER 7
#define TLPM_UNEXPECTED_GPIO_INTR_ERROR 8
#define TLPM_BREAK_ON_NOT_RECEIVED_ERROR 9
#define TLPM_BREAK_OFF_NOT_RECIVED_ERROR 10
#define TLPM_ACK_GPIO_INTR 11
#define TLPM_ON 12
#define TLPM_OFF 13
#define TLPM_WAKEUP_FROM_HOST 14
#define TLPM_WAKEUP_FROM_BT 15
#define TLPM_TX_BREAK_RECIVED 16
#define TLPM_IDLE_TIMER_NOT_RUNNING 17
#define WAC_ENABLE 18
#define WAC_SCAN_DONE 19
#define WAC_REPORT_BSS 20
#define WAC_START_WPS 21
#define WAC_SCAN_REPLY 22
#define WAC_UPDATE_BSS 23
#define WAC_PIN_STATUS 24
#define WAC_PIN_STATUS_REJECT 25
#define WAC_RSSI_BELOW_THRESHOLD 26
#define WAC_CTRL_REQ_CMD 27
#define WAC_CTRL_REQ_REPLY 28
#define DV_SET_ANTENNA 29
#define MISC_DBGID_DEFINITION_END
/* TXRX debug identifier definitions */
#define TXRX_TXBUF_DBGID_DEFINITION_START
#define TXRX_TXBUF_ALLOCATE_BUF 1
#define TXRX_TXBUF_QUEUE_BUF_TO_MBOX 2
#define TXRX_TXBUF_QUEUE_BUF_TO_TXQ 3
#define TXRX_TXBUF_TXQ_DEPTH 4
#define TXRX_TXBUF_IBSS_QUEUE_TO_SFQ 5
#define TXRX_TXBUF_IBSS_QUEUE_TO_TXQ_FRM_SFQ 6
#define TXRX_TXBUF_INITIALIZE_TIMER 7
#define TXRX_TXBUF_ARM_TIMER 8
#define TXRX_TXBUF_DISARM_TIMER 9
#define TXRX_TXBUF_UNINITIALIZE_TIMER 10
#define TXRX_TXBUF_DBGID_DEFINITION_END
#define TXRX_RXBUF_DBGID_DEFINITION_START
#define TXRX_RXBUF_ALLOCATE_BUF 1
#define TXRX_RXBUF_QUEUE_TO_HOST 2
#define TXRX_RXBUF_QUEUE_TO_WLAN 3
#define TXRX_RXBUF_ZERO_LEN_BUF 4
#define TXRX_RXBUF_QUEUE_TO_HOST_LASTBUF_IN_RXCHAIN 5
#define TXRX_RXBUF_LASTBUF_IN_RXCHAIN_ZEROBUF 6
#define TXRX_RXBUF_QUEUE_EMPTY_QUEUE_TO_WLAN 7
#define TXRX_RXBUF_SEND_TO_RECV_MGMT 8
#define TXRX_RXBUF_SEND_TO_IEEE_LAYER 9
#define TXRX_RXBUF_REQUEUE_ERROR 10
#define TXRX_RXBUF_DBGID_DEFINITION_END
#define TXRX_MGMTBUF_DBGID_DEFINITION_START
#define TXRX_MGMTBUF_ALLOCATE_BUF 1
#define TXRX_MGMTBUF_ALLOCATE_SM_BUF 2
#define TXRX_MGMTBUF_ALLOCATE_RMBUF 3
#define TXRX_MGMTBUF_GET_BUF 4
#define TXRX_MGMTBUF_GET_SM_BUF 5
#define TXRX_MGMTBUF_QUEUE_BUF_TO_TXQ 6
#define TXRX_MGMTBUF_REAPED_BUF 7
#define TXRX_MGMTBUF_REAPED_SM_BUF 8
#define TXRX_MGMTBUF_WAIT_FOR_TXQ_DRAIN 9
#define TXRX_MGMTBUF_WAIT_FOR_TXQ_SFQ_DRAIN 10
#define TXRX_MGMTBUF_ENQUEUE_INTO_DATA_SFQ 11
#define TXRX_MGMTBUF_DEQUEUE_FROM_DATA_SFQ 12
#define TXRX_MGMTBUF_PAUSE_DATA_TXQ 13
#define TXRX_MGMTBUF_RESUME_DATA_TXQ 14
#define TXRX_MGMTBUF_WAIT_FORTXQ_DRAIN_TIMEOUT 15
#define TXRX_MGMTBUF_DRAINQ 16
#define TXRX_MGMTBUF_INDICATE_Q_DRAINED 17
#define TXRX_MGMTBUF_ENQUEUE_INTO_HW_SFQ 18
#define TXRX_MGMTBUF_DEQUEUE_FROM_HW_SFQ 19
#define TXRX_MGMTBUF_PAUSE_HW_TXQ 20
#define TXRX_MGMTBUF_RESUME_HW_TXQ 21
#define TXRX_MGMTBUF_TEAR_DOWN_BA 22
#define TXRX_MGMTBUF_PROCESS_ADDBA_REQ 23
#define TXRX_MGMTBUF_PROCESS_DELBA 24
#define TXRX_MGMTBUF_PERFORM_BA 25
#define TXRX_MGMTBUF_WLAN_RESET_ON_ERROR 26
#define TXRX_MGMTBUF_DBGID_DEFINITION_END
/* PM (Power Module) debug identifier definitions */
#define PM_DBGID_DEFINITION_START
#define PM_INIT 1
#define PM_ENABLE 2
#define PM_SET_STATE 3
#define PM_SET_POWERMODE 4
#define PM_CONN_NOTIFY 5
#define PM_REF_COUNT_NEGATIVE 6
#define PM_INFRA_STA_APSD_ENABLE 7
#define PM_INFRA_STA_UPDATE_APSD_STATE 8
#define PM_CHAN_OP_REQ 9
#define PM_SET_MY_BEACON_POLICY 10
#define PM_SET_ALL_BEACON_POLICY 11
#define PM_INFRA_STA_SET_PM_PARAMS1 12
#define PM_INFRA_STA_SET_PM_PARAMS2 13
#define PM_ADHOC_SET_PM_CAPS_FAIL 14
#define PM_ADHOC_UNKNOWN_IBSS_ATTRIB_ID 15
#define PM_ADHOC_SET_PM_PARAMS 16
#define PM_ADHOC_STATE1 18
#define PM_ADHOC_STATE2 19
#define PM_ADHOC_CONN_MAP 20
#define PM_FAKE_SLEEP 21
#define PM_AP_STATE1 22
#define PM_AP_SET_PM_PARAMS 23
#define PM_P2P_STATE1 24
#define PM_DBGID_DEFINITION_END
/* Wake on Wireless debug identifier definitions */
#define WOW_DBGID_DEFINITION_START
#define WOW_INIT 1
#define WOW_GET_CONFIG_DSET 2
#define WOW_NO_CONFIG_DSET 3
#define WOW_INVALID_CONFIG_DSET 4
#define WOW_USE_DEFAULT_CONFIG 5
#define WOW_SETUP_GPIO 6
#define WOW_INIT_DONE 7
#define WOW_SET_GPIO_PIN 8
#define WOW_CLEAR_GPIO_PIN 9
#define WOW_SET_WOW_MODE_CMD 10
#define WOW_SET_HOST_MODE_CMD 11
#define WOW_ADD_WOW_PATTERN_CMD 12
#define WOW_NEW_WOW_PATTERN_AT_INDEX 13
#define WOW_DEL_WOW_PATTERN_CMD 14
#define WOW_LIST_CONTAINS_PATTERNS 15
#define WOW_GET_WOW_LIST_CMD 16
#define WOW_INVALID_FILTER_ID 17
#define WOW_INVALID_FILTER_LISTID 18
#define WOW_NO_VALID_FILTER_AT_ID 19
#define WOW_NO_VALID_LIST_AT_ID 20
#define WOW_NUM_PATTERNS_EXCEEDED 21
#define WOW_NUM_LISTS_EXCEEDED 22
#define WOW_GET_WOW_STATS 23
#define WOW_CLEAR_WOW_STATS 24
#define WOW_WAKEUP_HOST 25
#define WOW_EVENT_WAKEUP_HOST 26
#define WOW_EVENT_DISCARD 27
#define WOW_PATTERN_MATCH 28
#define WOW_PATTERN_NOT_MATCH 29
#define WOW_PATTERN_NOT_MATCH_OFFSET 30
#define WOW_DISABLED_HOST_ASLEEP 31
#define WOW_ENABLED_HOST_ASLEEP_NO_PATTERNS 32
#define WOW_ENABLED_HOST_ASLEEP_NO_MATCH_FOUND 33
#define WOW_DBGID_DEFINITION_END
/* WHAL debug identifier definitions */
#define WHAL_DBGID_DEFINITION_START
#define WHAL_ERROR_ANI_CONTROL 1
#define WHAL_ERROR_CHIP_TEST1 2
#define WHAL_ERROR_CHIP_TEST2 3
#define WHAL_ERROR_EEPROM_CHECKSUM 4
#define WHAL_ERROR_EEPROM_MACADDR 5
#define WHAL_ERROR_INTERRUPT_HIU 6
#define WHAL_ERROR_KEYCACHE_RESET 7
#define WHAL_ERROR_KEYCACHE_SET 8
#define WHAL_ERROR_KEYCACHE_TYPE 9
#define WHAL_ERROR_KEYCACHE_TKIPENTRY 10
#define WHAL_ERROR_KEYCACHE_WEPLENGTH 11
#define WHAL_ERROR_PHY_INVALID_CHANNEL 12
#define WHAL_ERROR_POWER_AWAKE 13
#define WHAL_ERROR_POWER_SET 14
#define WHAL_ERROR_RECV_STOPDMA 15
#define WHAL_ERROR_RECV_STOPPCU 16
#define WHAL_ERROR_RESET_CHANNF1 17
#define WHAL_ERROR_RESET_CHANNF2 18
#define WHAL_ERROR_RESET_PM 19
#define WHAL_ERROR_RESET_OFFSETCAL 20
#define WHAL_ERROR_RESET_RFGRANT 21
#define WHAL_ERROR_RESET_RXFRAME 22
#define WHAL_ERROR_RESET_STOPDMA 23
#define WHAL_ERROR_RESET_RECOVER 24
#define WHAL_ERROR_XMIT_COMPUTE 25
#define WHAL_ERROR_XMIT_NOQUEUE 26
#define WHAL_ERROR_XMIT_ACTIVEQUEUE 27
#define WHAL_ERROR_XMIT_BADTYPE 28
#define WHAL_ERROR_XMIT_STOPDMA 29
#define WHAL_ERROR_INTERRUPT_BB_PANIC 30
#define WHAL_ERROR_RESET_TXIQCAL 31
#define WHAL_ERROR_PAPRD_MAXGAIN_ABOVE_WINDOW 32
#define WHAL_DBGID_DEFINITION_END
/* DC debug identifier definitions */
#define DC_DBGID_DEFINITION_START
#define DC_SCAN_CHAN_START 1
#define DC_SCAN_CHAN_FINISH 2
#define DC_BEACON_RECEIVE7 3
#define DC_SSID_PROBE_CB 4
#define DC_SEND_NEXT_SSID_PROBE 5
#define DC_START_SEARCH 6
#define DC_CANCEL_SEARCH_CB 7
#define DC_STOP_SEARCH 8
#define DC_END_SEARCH 9
#define DC_MIN_CHDWELL_TIMEOUT 10
#define DC_START_SEARCH_CANCELED 11
#define DC_SET_POWER_MODE 12
#define DC_INIT 13
#define DC_SEARCH_OPPORTUNITY 14
#define DC_RECEIVED_ANY_BEACON 15
#define DC_RECEIVED_MY_BEACON 16
#define DC_PROFILE_IS_ADHOC_BUT_BSS_IS_INFRA 17
#define DC_PS_ENABLED_BUT_ATHEROS_IE_ABSENT 18
#define DC_BSS_ADHOC_CHANNEL_NOT_ALLOWED 19
#define DC_SET_BEACON_UPDATE 20
#define DC_BEACON_UPDATE_COMPLETE 21
#define DC_END_SEARCH_BEACON_UPDATE_COMP_CB 22
#define DC_BSSINFO_EVENT_DROPPED 23
#define DC_IEEEPS_ENABLED_BUT_ATIM_ABSENT 24
#define DC_DBGID_DEFINITION_END
/* CO debug identifier definitions */
#define CO_DBGID_DEFINITION_START
#define CO_INIT 1
#define CO_ACQUIRE_LOCK 2
#define CO_START_OP1 3
#define CO_START_OP2 4
#define CO_DRAIN_TX_COMPLETE_CB 5
#define CO_CHANGE_CHANNEL_CB 6
#define CO_RETURN_TO_HOME_CHANNEL 7
#define CO_FINISH_OP_TIMEOUT 8
#define CO_OP_END 9
#define CO_CANCEL_OP 10
#define CO_CHANGE_CHANNEL 11
#define CO_RELEASE_LOCK 12
#define CO_CHANGE_STATE 13
#define CO_DBGID_DEFINITION_END
/* RO debug identifier definitions */
#define RO_DBGID_DEFINITION_START
#define RO_REFRESH_ROAM_TABLE 1
#define RO_UPDATE_ROAM_CANDIDATE 2
#define RO_UPDATE_ROAM_CANDIDATE_CB 3
#define RO_UPDATE_ROAM_CANDIDATE_FINISH 4
#define RO_REFRESH_ROAM_TABLE_DONE 5
#define RO_PERIODIC_SEARCH_CB 6
#define RO_PERIODIC_SEARCH_TIMEOUT 7
#define RO_INIT 8
#define RO_BMISS_STATE1 9
#define RO_BMISS_STATE2 10
#define RO_SET_PERIODIC_SEARCH_ENABLE 11
#define RO_SET_PERIODIC_SEARCH_DISABLE 12
#define RO_ENABLE_SQ_THRESHOLD 13
#define RO_DISABLE_SQ_THRESHOLD 14
#define RO_ADD_BSS_TO_ROAM_TABLE 15
#define RO_SET_PERIODIC_SEARCH_MODE 16
#define RO_CONFIGURE_SQ_THRESHOLD1 17
#define RO_CONFIGURE_SQ_THRESHOLD2 18
#define RO_CONFIGURE_SQ_PARAMS 19
#define RO_LOW_SIGNAL_QUALITY_EVENT 20
#define RO_HIGH_SIGNAL_QUALITY_EVENT 21
#define RO_REMOVE_BSS_FROM_ROAM_TABLE 22
#define RO_UPDATE_CONNECTION_STATE_METRIC 23
#define RO_LOWRSSI_SCAN_PARAMS 24
#define RO_LOWRSSI_SCAN_START 25
#define RO_LOWRSSI_SCAN_END 26
#define RO_LOWRSSI_SCAN_CANCEL 27
#define RO_LOWRSSI_ROAM_CANCEL 28
#define RO_REFRESH_ROAM_CANDIDATE 29
#define RO_DBGID_DEFINITION_END
/* CM debug identifier definitions */
#define CM_DBGID_DEFINITION_START
#define CM_INITIATE_HANDOFF 1
#define CM_INITIATE_HANDOFF_CB 2
#define CM_CONNECT_EVENT 3
#define CM_DISCONNECT_EVENT 4
#define CM_INIT 5
#define CM_HANDOFF_SOURCE 6
#define CM_SET_HANDOFF_TRIGGERS 7
#define CM_CONNECT_REQUEST 8
#define CM_CONNECT_REQUEST_CB 9
#define CM_CONTINUE_SCAN_CB 10
#define CM_DBGID_DEFINITION_END
/* mgmt debug identifier definitions */
#define MGMT_DBGID_DEFINITION_START
#define KEYMGMT_CONNECTION_INIT 1
#define KEYMGMT_CONNECTION_COMPLETE 2
#define KEYMGMT_CONNECTION_CLOSE 3
#define KEYMGMT_ADD_KEY 4
#define MLME_NEW_STATE 5
#define MLME_CONN_INIT 6
#define MLME_CONN_COMPLETE 7
#define MLME_CONN_CLOSE 8
#define MLME_WLAN_OPMODE 9
#define MLME_WLAN_SLOTTIME 10
#define MGMT_DBGID_DEFINITION_END
/* TMR debug identifier definitions */
#define TMR_DBGID_DEFINITION_START
#define TMR_HANG_DETECTED 1
#define TMR_WDT_TRIGGERED 2
#define TMR_WDT_RESET 3
#define TMR_HANDLER_ENTRY 4
#define TMR_HANDLER_EXIT 5
#define TMR_SAVED_START 6
#define TMR_SAVED_END 7
#define TMR_DBGID_DEFINITION_END
/* BTCOEX debug identifier definitions */
#define BTCOEX_DBGID_DEFINITION_START
#define BTCOEX_STATUS_CMD 1
#define BTCOEX_PARAMS_CMD 2
#define BTCOEX_ANT_CONFIG 3
#define BTCOEX_COLOCATED_BT_DEVICE 4
#define BTCOEX_CLOSE_RANGE_SCO_ON 5
#define BTCOEX_CLOSE_RANGE_SCO_OFF 6
#define BTCOEX_CLOSE_RANGE_A2DP_ON 7
#define BTCOEX_CLOSE_RANGE_A2DP_OFF 8
#define BTCOEX_A2DP_PROTECT_ON 9
#define BTCOEX_A2DP_PROTECT_OFF 10
#define BTCOEX_SCO_PROTECT_ON 11
#define BTCOEX_SCO_PROTECT_OFF 12
#define BTCOEX_CLOSE_RANGE_DETECTOR_START 13
#define BTCOEX_CLOSE_RANGE_DETECTOR_STOP 14
#define BTCOEX_CLOSE_RANGE_TOGGLE 15
#define BTCOEX_CLOSE_RANGE_TOGGLE_RSSI_LRCNT 16
#define BTCOEX_CLOSE_RANGE_RSSI_THRESH 17
#define BTCOEX_CLOSE_RANGE_LOW_RATE_THRESH 18
#define BTCOEX_PTA_PRI_INTR_HANDLER 19
#define BTCOEX_PSPOLL_QUEUED 20
#define BTCOEX_PSPOLL_COMPLETE 21
#define BTCOEX_DBG_PM_AWAKE 22
#define BTCOEX_DBG_PM_SLEEP 23
#define BTCOEX_DBG_SCO_COEX_ON 24
#define BTCOEX_SCO_DATARECEIVE 25
#define BTCOEX_INTR_INIT 26
#define BTCOEX_PTA_PRI_DIFF 27
#define BTCOEX_TIM_NOTIFICATION 28
#define BTCOEX_SCO_WAKEUP_ON_DATA 29
#define BTCOEX_SCO_SLEEP 30
#define BTCOEX_SET_WEIGHTS 31
#define BTCOEX_SCO_DATARECEIVE_LATENCY_VAL 32
#define BTCOEX_SCO_MEASURE_TIME_DIFF 33
#define BTCOEX_SET_EOL_VAL 34
#define BTCOEX_OPT_DETECT_HANDLER 35
#define BTCOEX_SCO_TOGGLE_STATE 36
#define BTCOEX_SCO_STOMP 37
#define BTCOEX_NULL_COMP_CALLBACK 38
#define BTCOEX_RX_INCOMING 39
#define BTCOEX_RX_INCOMING_CTL 40
#define BTCOEX_RX_INCOMING_MGMT 41
#define BTCOEX_RX_INCOMING_DATA 42
#define BTCOEX_RTS_RECEPTION 43
#define BTCOEX_FRAME_PRI_LOW_RATE_THRES 44
#define BTCOEX_PM_FAKE_SLEEP 45
#define BTCOEX_ACL_COEX_STATUS 46
#define BTCOEX_ACL_COEX_DETECTION 47
#define BTCOEX_A2DP_COEX_STATUS 48
#define BTCOEX_SCO_STATUS 49
#define BTCOEX_WAKEUP_ON_DATA 50
#define BTCOEX_DATARECEIVE 51
#define BTCOEX_GET_MAX_AGGR_SIZE 53
#define BTCOEX_MAX_AGGR_AVAIL_TIME 54
#define BTCOEX_DBG_WBTIMER_INTR 55
#define BTCOEX_DBG_SCO_SYNC 57
#define BTCOEX_UPLINK_QUEUED_RATE 59
#define BTCOEX_DBG_UPLINK_ENABLE_EOL 60
#define BTCOEX_UPLINK_FRAME_DURATION 61
#define BTCOEX_UPLINK_SET_EOL 62
#define BTCOEX_DBG_EOL_EXPIRED 63
#define BTCOEX_DBG_DATA_COMPLETE 64
#define BTCOEX_UPLINK_QUEUED_TIMESTAMP 65
#define BTCOEX_DBG_DATA_COMPLETE_TIME 66
#define BTCOEX_DBG_A2DP_ROLE_IS_SLAVE 67
#define BTCOEX_DBG_A2DP_ROLE_IS_MASTER 68
#define BTCOEX_DBG_UPLINK_SEQ_NUM 69
#define BTCOEX_UPLINK_AGGR_SEQ 70
#define BTCOEX_DBG_TX_COMP_SEQ_NO 71
#define BTCOEX_DBG_MAX_AGGR_PAUSE_STATE 72
#define BTCOEX_DBG_ACL_TRAFFIC 73
#define BTCOEX_CURR_AGGR_PROP 74
#define BTCOEX_DBG_SCO_GET_PER_TIME_DIFF 75
#define BTCOEX_PSPOLL_PROCESS 76
#define BTCOEX_RETURN_FROM_MAC 77
#define BTCOEX_FREED_REQUEUED_CNT 78
#define BTCOEX_DBG_TOGGLE_LOW_RATES 79
#define BTCOEX_MAC_GOES_TO_SLEEP 80
#define BTCOEX_DBG_A2DP_NO_SYNC 81
#define BTCOEX_RETURN_FROM_MAC_HOLD_Q_INFO 82
#define BTCOEX_RETURN_FROM_MAC_AC 83
#define BTCOEX_DBG_DTIM_RECV 84
#define BTCOEX_IS_PRE_UPDATE 86
#define BTCOEX_ENQUEUED_BIT_MAP 87
#define BTCOEX_TX_COMPLETE_FIRST_DESC_STATS 88
#define BTCOEX_UPLINK_DESC 89
#define BTCOEX_SCO_GET_PER_FIRST_FRM_TIMESTAMP 90
#define BTCOEX_DBG_RECV_ACK 94
#define BTCOEX_DBG_ADDBA_INDICATION 95
#define BTCOEX_TX_COMPLETE_EOL_FAILED 96
#define BTCOEX_DBG_A2DP_USAGE_COMPLETE 97
#define BTCOEX_DBG_A2DP_STOMP_FOR_BCN_HANDLER 98
#define BTCOEX_DBG_A2DP_SYNC_INTR 99
#define BTCOEX_DBG_A2DP_STOMP_FOR_BCN_RECEPTION 100
#define BTCOEX_FORM_AGGR_CURR_AGGR 101
#define BTCOEX_DBG_TOGGLE_A2DP_BURST_CNT 102
#define BTCOEX_DBG_BT_TRAFFIC 103
#define BTCOEX_DBG_STOMP_BT_TRAFFIC 104
#define BTCOEX_RECV_NULL 105
#define BTCOEX_DBG_A2DP_MASTER_BT_END 106
#define BTCOEX_DBG_A2DP_BT_START 107
#define BTCOEX_DBG_A2DP_SLAVE_BT_END 108
#define BTCOEX_DBG_A2DP_STOMP_BT 109
#define BTCOEX_DBG_GO_TO_SLEEP 110
#define BTCOEX_DBG_A2DP_PKT 111
#define BTCOEX_DBG_A2DP_PSPOLL_DATA_RECV 112
#define BTCOEX_DBG_A2DP_NULL 113
#define BTCOEX_DBG_UPLINK_DATA 114
#define BTCOEX_DBG_A2DP_STOMP_LOW_PRIO_NULL 115
#define BTCOEX_DBG_ADD_BA_RESP_TIMEOUT 116
#define BTCOEX_DBG_TXQ_STATE 117
#define BTCOEX_DBG_ALLOW_SCAN 118
#define BTCOEX_DBG_SCAN_REQUEST 119
#define BTCOEX_A2DP_SLEEP 127
#define BTCOEX_DBG_DATA_ACTIV_TIMEOUT 128
#define BTCOEX_DBG_SWITCH_TO_PSPOLL_ON_MODE 129
#define BTCOEX_DBG_SWITCH_TO_PSPOLL_OFF_MODE 130
#define BTCOEX_DATARECEIVE_AGGR 131
#define BTCOEX_DBG_DATA_RECV_SLEEPING_PENDING 132
#define BTCOEX_DBG_DATARESP_TIMEOUT 133
#define BTCOEX_BDG_BMISS 134
#define BTCOEX_DBG_DATA_RECV_WAKEUP_TIM 135
#define BTCOEX_DBG_SECOND_BMISS 136
#define BTCOEX_DBG_SET_WLAN_STATE 138
#define BTCOEX_BDG_FIRST_BMISS 139
#define BTCOEX_DBG_A2DP_CHAN_OP 140
#define BTCOEX_DBG_A2DP_INTR 141
#define BTCOEX_DBG_BT_INQUIRY 142
#define BTCOEX_DBG_BT_INQUIRY_DATA_FETCH 143
#define BTCOEX_DBG_POST_INQUIRY_FINISH 144
#define BTCOEX_DBG_SCO_OPT_MODE_TIMER_HANDLER 145
#define BTCOEX_DBG_NULL_FRAME_SLEEP 146
#define BTCOEX_DBG_NULL_FRAME_AWAKE 147
#define BTCOEX_DBG_SET_AGGR_SIZE 152
#define BTCOEX_DBG_TEAR_BA_TIMEOUT 153
#define BTCOEX_DBG_MGMT_FRAME_SEQ_NO 154
#define BTCOEX_DBG_SCO_STOMP_HIGH_PRI 155
#define BTCOEX_DBG_COLOCATED_BT_DEV 156
#define BTCOEX_DBG_FE_ANT_TYPE 157
#define BTCOEX_DBG_BT_INQUIRY_CMD 158
#define BTCOEX_DBG_SCO_CONFIG 159
#define BTCOEX_DBG_SCO_PSPOLL_CONFIG 160
#define BTCOEX_DBG_SCO_OPTMODE_CONFIG 161
#define BTCOEX_DBG_A2DP_CONFIG 162
#define BTCOEX_DBG_A2DP_PSPOLL_CONFIG 163
#define BTCOEX_DBG_A2DP_OPTMODE_CONFIG 164
#define BTCOEX_DBG_ACLCOEX_CONFIG 165
#define BTCOEX_DBG_ACLCOEX_PSPOLL_CONFIG 166
#define BTCOEX_DBG_ACLCOEX_OPTMODE_CONFIG 167
#define BTCOEX_DBG_DEBUG_CMD 168
#define BTCOEX_DBG_SET_BT_OPERATING_STATUS 169
#define BTCOEX_DBG_GET_CONFIG 170
#define BTCOEX_DBG_GET_STATS 171
#define BTCOEX_DBG_BT_OPERATING_STATUS 172
#define BTCOEX_DBG_PERFORM_RECONNECT 173
#define BTCOEX_DBG_ACL_WLAN_MED 175
#define BTCOEX_DBG_ACL_BT_MED 176
#define BTCOEX_DBG_WLAN_CONNECT 177
#define BTCOEX_DBG_A2DP_DUAL_START 178
#define BTCOEX_DBG_PMAWAKE_NOTIFY 179
#define BTCOEX_DBG_BEACON_SCAN_ENABLE 180
#define BTCOEX_DBG_BEACON_SCAN_DISABLE 181
#define BTCOEX_DBG_RX_NOTIFY 182
#define BTCOEX_SCO_GET_PER_SECOND_FRM_TIMESTAMP 183
#define BTCOEX_DBG_TXQ_DETAILS 184
#define BTCOEX_DBG_SCO_STOMP_LOW_PRI 185
#define BTCOEX_DBG_A2DP_FORCE_SCAN 186
#define BTCOEX_DBG_DTIM_STOMP_COMP 187
#define BTCOEX_ACL_PRESENCE_TIMER 188
#define BTCOEX_DBG_QUEUE_SELF_CTS 189
#define BTCOEX_DBG_SELF_CTS_COMP 190
#define BTCOEX_DBG_APMODE_WAIT_FOR_CTS_COMP_FAILED 191
#define BTCOEX_DBG_APMODE_A2DP_MED_TO_BT 192
#define BTCOEX_DBG_APMODE_SET_BTSTATE 193
#define BTCOEX_DBG_APMODE_A2DP_STATUS 194
#define BTCOEX_DBG_APMODE_SCO_CTS_HANDLER 195
#define BTCOEX_DBG_APMODE_SCO_STATUS 196
#define BTCOEX_DBG_APMODE_TXQ_DRAINED 197
#define BTCOEX_DBG_APMODE_SCO_ARM_TIMER 198
#define BTCOEX_DBG_APMODE_SWITCH_MED_TO_WLAN 199
#define BTCOEX_APMODE_BCN_TX_HANDLER 200
#define BTCOEX_APMODE_BCN_TX 201
#define BTCOEX_APMODE_SCO_RTS_HANDLER 202
#define BTCOEX_DBGID_DEFINITION_END
#ifdef __cplusplus
}
#endif
#endif /* _DBGLOG_ID_H_ */
wlan/include/discovery.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef _DISCOVERY_H_
#define _DISCOVERY_H_
/*
* DC_SCAN_PRIORITY is an 8-bit bitmap of the scan priority of a channel
*/
typedef enum {
DEFAULT_SCPRI = 0x01,
POPULAR_SCPRI = 0x02,
SSIDS_SCPRI = 0x04,
PROF_SCPRI = 0x08,
DISABLE_SCPRI = 0x10,
} DC_SCAN_PRIORITY;
/* The following search type construct can be used to manipulate the behavior of the search module based on different bits set */
typedef enum {
SCAN_RESET = 0,
SCAN_ALL = (DEFAULT_SCPRI | POPULAR_SCPRI | \
SSIDS_SCPRI | PROF_SCPRI),
SCAN_POPULAR = (POPULAR_SCPRI | SSIDS_SCPRI | PROF_SCPRI),
SCAN_SSIDS = (SSIDS_SCPRI | PROF_SCPRI),
SCAN_PROF_MASK = (PROF_SCPRI),
SCAN_MULTI_CHANNEL = 0x000100,
SCAN_DETERMINISTIC = 0x000200,
SCAN_PROFILE_MATCH_TERMINATED = 0x000400,
SCAN_HOME_CHANNEL_SKIP = 0x000800,
SCAN_CHANNEL_LIST_CONTINUE = 0x001000,
SCAN_CURRENT_SSID_SKIP = 0x002000,
SCAN_ACTIVE_PROBE_DISABLE = 0x004000,
SCAN_CHANNEL_HINT_ONLY = 0x008000,
SCAN_ACTIVE_CHANNELS_ONLY = 0x010000,
SCAN_UNUSED1 = 0x020000, /* unused */
SCAN_PERIODIC = 0x040000,
SCAN_FIXED_DURATION = 0x080000,
SCAN_AP_ASSISTED = 0x100000,
SCAN_DONOT_RETURN_TO_HOME_AFTERSCAN = 0x200000,
} DC_SCAN_TYPE;
typedef enum {
BSS_REPORTING_DEFAULT = 0x0,
EXCLUDE_NON_SCAN_RESULTS = 0x1, /* Exclude results outside of scan */
} DC_BSS_REPORTING_POLICY;
typedef enum {
DC_IGNORE_WPAx_GROUP_CIPHER = 0x01,
DC_PROFILE_MATCH_DONE = 0x02,
DC_IGNORE_AAC_BEACON = 0x04,
DC_CSA_FOLLOW_BSS = 0x08,
} DC_PROFILE_FILTER;
#define DEFAULT_DC_PROFILE_FILTER (DC_CSA_FOLLOW_BSS)
#endif /* _DISCOVERY_H_ */
wlan/include/dset_internal.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __DSET_INTERNAL_H__
#define __DSET_INTERNAL_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/*
* Internal dset definitions, common for DataSet layer.
*/
#define DSET_TYPE_STANDARD 0
#define DSET_TYPE_BPATCHED 1
#define DSET_TYPE_COMPRESSED 2
/* Dataset descriptor */
typedef PREPACK struct dset_descriptor_s {
struct dset_descriptor_s *next; /* List link. NULL only at the last
descriptor */
A_UINT16 id; /* Dset ID */
A_UINT16 size; /* Dset size. */
void *DataPtr; /* Pointer to raw data for standard
DataSet or pointer to original
dset_descriptor for patched
DataSet */
A_UINT32 data_type; /* DSET_TYPE_*, above */
void *AuxPtr; /* Additional data that might
needed for data_type. For
example, pointer to patch
Dataset descriptor for BPatch. */
} POSTPACK dset_descriptor_t;
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __DSET_INTERNAL_H__ */
wlan/include/dsetid.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __DSETID_H__
#define __DSETID_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/* Well-known DataSet IDs */
#define DSETID_UNUSED 0x00000000
#define DSETID_BOARD_DATA 0x00000001 /* Cal and board data */
#define DSETID_REGDB 0x00000002 /* Regulatory Database */
#define DSETID_POWER_CONTROL 0x00000003 /* TX Pwr Lim & Ant Gain */
#define DSETID_USER_CONFIG 0x00000004 /* User Configuration */
#define DSETID_ANALOG_CONTROL_DATA_START 0x00000005
#define DSETID_ANALOG_CONTROL_DATA_END 0x00000025
/*
* Get DSETID for various reference clock speeds.
* For each speed there are three DataSets that correspond
* to the three columns of bank6 data (addr, 11a, 11b/g).
* This macro returns the dsetid of the first of those
* three DataSets.
*/
#define ANALOG_CONTROL_DATA_DSETID(refclk) \
(DSETID_ANALOG_CONTROL_DATA_START + 3*refclk)
/*
* There are TWO STARTUP_PATCH DataSets.
* DSETID_STARTUP_PATCH is historical, and was applied before BMI on
* earlier systems. On AR6002, it is applied after BMI, just like
* DSETID_STARTUP_PATCH2.
*/
#define DSETID_STARTUP_PATCH 0x00000026
#define DSETID_GPIO_CONFIG_PATCH 0x00000027
#define DSETID_WLANREGS 0x00000028 /* override wlan regs */
#define DSETID_STARTUP_PATCH2 0x00000029
#define DSETID_WOW_CONFIG 0x00000090 /* WoW Configuration */
/* Add WHAL_INI_DATA_ID to DSETID_INI_DATA for a specific WHAL INI table. */
#define DSETID_INI_DATA 0x00000100
/* Reserved for WHAL INI Tables: 0x100..0x11f */
#define DSETID_INI_DATA_END 0x0000011f
#define DSETID_VENDOR_START 0x00010000 /* Vendor-defined DataSets */
#define DSETID_INDEX_END 0xfffffffe /* Reserved to indicate the
end of a memory-based
DataSet Index */
#define DSETID_INDEX_FREE 0xffffffff /* An unused index entry */
/*
* PATCH DataSet format:
* A list of patches, terminated by a patch with
* address=PATCH_END.
*
* This allows for patches to be stored in flash.
*/
PREPACK struct patch_s {
A_UINT32 *address;
A_UINT32 data;
} POSTPACK ;
/*
* Skip some patches. Can be used to erase a single patch in a
* patch DataSet without having to re-write the DataSet. May
* also be used to embed information for use by subsequent
* patch code. The "data" in a PATCH_SKIP tells how many
* bytes of length "patch_s" to skip.
*/
#define PATCH_SKIP ((A_UINT32 *)0x00000000)
/*
* Execute code at the address specified by "data".
* The address of the patch structure is passed as
* the one parameter.
*/
#define PATCH_CODE_ABS ((A_UINT32 *)0x00000001)
/*
* Same as PATCH_CODE_ABS, but treat "data" as an
* offset from the start of the patch word.
*/
#define PATCH_CODE_REL ((A_UINT32 *)0x00000002)
/* Mark the end of this patch DataSet. */
#define PATCH_END ((A_UINT32 *)0xffffffff)
/*
* A DataSet which contains a Binary Patch to some other DataSet
* uses the original dsetid with the DSETID_BPATCH_FLAG bit set.
* Such a BPatch DataSet consists of BPatch metadata followed by
* the bdiff bytes. BPatch metadata consists of a single 32-bit
* word that contains the size of the BPatched final image.
*
* To create a suitable bdiff DataSet, use bdiff in host/tools/bdiff
* to create "diffs":
* bdiff -q -O -nooldmd5 -nonewmd5 -d ORIGfile NEWfile diffs
* Then add BPatch metadata to the start of "diffs".
*
* NB: There are some implementation-induced restrictions
* on which DataSets can be BPatched.
*/
#define DSETID_BPATCH_FLAG 0x80000000
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __DSETID_H__ */
wlan/include/epping_test.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2009-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//
/* This file contains shared definitions for the host/target endpoint ping test */
#ifndef EPPING_TEST_H_
#define EPPING_TEST_H_
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/* alignment to 4-bytes */
#define EPPING_ALIGNMENT_PAD (((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR))
#ifndef A_OFFSETOF
#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field))
#endif
#define EPPING_RSVD_FILL 0xCC
#define HCI_RSVD_EXPECTED_PKT_TYPE_RECV_OFFSET 7
typedef PREPACK struct {
A_UINT8 _HCIRsvd[8]; /* reserved for HCI packet header (GMBOX) testing */
A_UINT8 StreamEcho_h; /* stream no. to echo this packet on (filled by host) */
A_UINT8 StreamEchoSent_t; /* stream no. packet was echoed to (filled by target)
When echoed: StreamEchoSent_t == StreamEcho_h */
A_UINT8 StreamRecv_t; /* stream no. that target received this packet on (filled by target) */
A_UINT8 StreamNo_h; /* stream number to send on (filled by host) */
A_UINT8 Magic_h[4]; /* magic number to filter for this packet on the host*/
A_UINT8 _rsvd[6]; /* reserved fields that must be set to a "reserved" value
since this packet maps to a 14-byte ethernet frame we want
to make sure ethertype field is set to something unknown */
A_UINT8 _pad[2]; /* padding for alignment */
A_UINT8 TimeStamp[8]; /* timestamp of packet (host or target) */
A_UINT32 HostContext_h; /* 4 byte host context, target echos this back */
A_UINT32 SeqNo; /* sequence number (set by host or target) */
A_UINT16 Cmd_h; /* ping command (filled by host) */
A_UINT16 CmdFlags_h; /* optional flags */
A_UINT8 CmdBuffer_h[8]; /* buffer for command (host -> target) */
A_UINT8 CmdBuffer_t[8]; /* buffer for command (target -> host) */
A_UINT16 DataLength; /* length of data */
A_UINT16 DataCRC; /* 16 bit CRC of data */
A_UINT16 HeaderCRC; /* header CRC (fields : StreamNo_h to end, minus HeaderCRC) */
} POSTPACK EPPING_HEADER;
#define EPPING_PING_MAGIC_0 0xAA
#define EPPING_PING_MAGIC_1 0x55
#define EPPING_PING_MAGIC_2 0xCE
#define EPPING_PING_MAGIC_3 0xEC
#define IS_EPPING_PACKET(pPkt) (((pPkt)->Magic_h[0] == EPPING_PING_MAGIC_0) && \
((pPkt)->Magic_h[1] == EPPING_PING_MAGIC_1) && \
((pPkt)->Magic_h[2] == EPPING_PING_MAGIC_2) && \
((pPkt)->Magic_h[3] == EPPING_PING_MAGIC_3))
#define SET_EPPING_PACKET_MAGIC(pPkt) { (pPkt)->Magic_h[0] = EPPING_PING_MAGIC_0; \
(pPkt)->Magic_h[1] = EPPING_PING_MAGIC_1; \
(pPkt)->Magic_h[2] = EPPING_PING_MAGIC_2; \
(pPkt)->Magic_h[3] = EPPING_PING_MAGIC_3;}
#define CMD_FLAGS_DATA_CRC (1 << 0) /* DataCRC field is valid */
#define CMD_FLAGS_DELAY_ECHO (1 << 1) /* delay the echo of the packet */
#define CMD_FLAGS_NO_DROP (1 << 2) /* do not drop at HTC layer no matter what the stream is */
#define IS_EPING_PACKET_NO_DROP(pPkt) ((pPkt)->CmdFlags_h & CMD_FLAGS_NO_DROP)
#define EPPING_CMD_ECHO_PACKET 1 /* echo packet test */
#define EPPING_CMD_RESET_RECV_CNT 2 /* reset recv count */
#define EPPING_CMD_CAPTURE_RECV_CNT 3 /* fetch recv count, 4-byte count returned in CmdBuffer_t */
#define EPPING_CMD_NO_ECHO 4 /* non-echo packet test (tx-only) */
#define EPPING_CMD_CONT_RX_START 5 /* continous RX packets, parameters are in CmdBuffer_h */
#define EPPING_CMD_CONT_RX_STOP 6 /* stop continuous RX packet transmission */
/* test command parameters may be no more than 8 bytes */
typedef PREPACK struct {
A_UINT16 BurstCnt; /* number of packets to burst together (for HTC 2.1 testing) */
A_UINT16 PacketLength; /* length of packet to generate including header */
A_UINT16 Flags; /* flags */
#define EPPING_CONT_RX_DATA_CRC (1 << 0) /* Add CRC to all data */
#define EPPING_CONT_RX_RANDOM_DATA (1 << 1) /* randomize the data pattern */
#define EPPING_CONT_RX_RANDOM_LEN (1 << 2) /* randomize the packet lengths */
} POSTPACK EPPING_CONT_RX_PARAMS;
#define EPPING_HDR_CRC_OFFSET A_OFFSETOF(EPPING_HEADER,StreamNo_h)
#define EPPING_HDR_BYTES_CRC (sizeof(EPPING_HEADER) - EPPING_HDR_CRC_OFFSET - (sizeof(A_UINT16)))
#define HCI_TRANSPORT_STREAM_NUM 16 /* this number is higher than the define WMM AC classes so we
can use this to distinguish packets */
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /*EPPING_TEST_H_*/
wlan/include/gmboxif.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2009-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __GMBOXIF_H__
#define __GMBOXIF_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/* GMBOX interface definitions */
#define AR6K_GMBOX_CREDIT_COUNTER 1 /* we use credit counter 1 to track credits */
#define AR6K_GMBOX_CREDIT_SIZE_COUNTER 2 /* credit counter 2 is used to pass the size of each credit */
/* HCI UART transport definitions when used over GMBOX interface */
#define HCI_UART_COMMAND_PKT 0x01
#define HCI_UART_ACL_PKT 0x02
#define HCI_UART_SCO_PKT 0x03
#define HCI_UART_EVENT_PKT 0x04
/* definitions for BT HCI packets */
typedef PREPACK struct {
A_UINT16 Flags_ConnHandle;
A_UINT16 Length;
} POSTPACK BT_HCI_ACL_HEADER;
typedef PREPACK struct {
A_UINT16 Flags_ConnHandle;
A_UINT8 Length;
} POSTPACK BT_HCI_SCO_HEADER;
typedef PREPACK struct {
A_UINT16 OpCode;
A_UINT8 ParamLength;
} POSTPACK BT_HCI_COMMAND_HEADER;
typedef PREPACK struct {
A_UINT8 EventCode;
A_UINT8 ParamLength;
} POSTPACK BT_HCI_EVENT_HEADER;
/* MBOX host interrupt signal assignments */
#define MBOX_SIG_HCI_BRIDGE_MAX 8
#define MBOX_SIG_HCI_BRIDGE_BT_ON 0
#define MBOX_SIG_HCI_BRIDGE_BT_OFF 1
#define MBOX_SIG_HCI_BRIDGE_BAUD_SET 2
#define MBOX_SIG_HCI_BRIDGE_PWR_SAV_ON 3
#define MBOX_SIG_HCI_BRIDGE_PWR_SAV_OFF 4
/* Host interrupts target to change baud rate and
* baud rate info is stored in scratch registers 4 and 5
*/
#define LSB_SCRATCH_IDX 4
#define MSB_SCRATCH_IDX 5
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __GMBOXIF_H__ */
wlan/include/gpio.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2005-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#define AR6001_GPIO_PIN_COUNT 18
#define AR6002_GPIO_PIN_COUNT 18
#define AR6003_GPIO_PIN_COUNT 28
#define MCKINLEY_GPIO_PIN_COUNT 57
/*
* Values of gpioreg_id in the WMIX_GPIO_REGISTER_SET_CMDID and WMIX_GPIO_REGISTER_GET_CMDID
* commands come in two flavors. If the upper bit of gpioreg_id is CLEAR, then the
* remainder is interpreted as one of these values. This provides platform-independent
* access to GPIO registers. If the upper bit (GPIO_ID_OFFSET_FLAG) of gpioreg_id is SET,
* then the remainder is interpreted as a platform-specific GPIO register offset.
*/
#define GPIO_ID_OUT 0x00000000
#define GPIO_ID_OUT_W1TS 0x00000001
#define GPIO_ID_OUT_W1TC 0x00000002
#define GPIO_ID_ENABLE 0x00000003
#define GPIO_ID_ENABLE_W1TS 0x00000004
#define GPIO_ID_ENABLE_W1TC 0x00000005
#define GPIO_ID_IN 0x00000006
#define GPIO_ID_STATUS 0x00000007
#define GPIO_ID_STATUS_W1TS 0x00000008
#define GPIO_ID_STATUS_W1TC 0x00000009
#define GPIO_ID_PIN0 0x0000000a
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
#define GPIO_ID_NONE 0xffffffff
#define GPIO_ID_OFFSET_FLAG 0x80000000
#define GPIO_ID_REG_MASK 0x7fffffff
#define GPIO_ID_IS_OFFSET(reg_id) (((reg_id) & GPIO_ID_OFFSET_FLAG) != 0)
wlan/include/host_proxy_iface.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2011, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
/*
* This file contains the definitions of the host_proxy interface.
*/
#ifndef _HOST_PROXY_IFACE_H_
#define _HOST_PROXY_IFACE_H_
/* Host proxy initializes shared memory with HOST_PROXY_INIT to
* indicate that it is ready to receive instruction */
#define HOST_PROXY_INIT (1)
/* Host writes HOST_PROXY_NORMAL_BOOT to shared memory to
* indicate to host proxy that it should proceed to boot
* normally (bypassing BMI).
*/
#define HOST_PROXY_NORMAL_BOOT (2)
/* Host writes HOST_PROXY_BMI_BOOT to shared memory to
* indicate to host proxy that is should enable BMI and
* exit. This allows a host to reprogram the on board
* flash.
*/
#define HOST_PROXY_BMI_BOOT (3)
#endif /* _HOST_PROXY_IFACE_H_ */
wlan/include/htc.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __HTC_H__
#define __HTC_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
#ifndef A_OFFSETOF
#define A_OFFSETOF(type,field) (unsigned long)(&(((type *)NULL)->field))
#endif
#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \
(((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)]))
/* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a
* structure using only the type and field name.
* Use these macros if there is the potential for unaligned buffer accesses. */
#define A_GET_UINT16_FIELD(p,type,field) \
ASSEMBLE_UNALIGNED_UINT16(p,\
A_OFFSETOF(type,field) + 1, \
A_OFFSETOF(type,field))
#define A_SET_UINT16_FIELD(p,type,field,value) \
{ \
((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (A_UINT8)(value); \
((A_UINT8 *)(p))[A_OFFSETOF(type,field) + 1] = (A_UINT8)((value) >> 8); \
}
#define A_GET_UINT8_FIELD(p,type,field) \
((A_UINT8 *)(p))[A_OFFSETOF(type,field)]
#define A_SET_UINT8_FIELD(p,type,field,value) \
((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (value)
/****** DANGER DANGER ***************
*
* The frame header length and message formats defined herein were
* selected to accommodate optimal alignment for target processing. This reduces code
* size and improves performance.
*
* Any changes to the header length may alter the alignment and cause exceptions
* on the target. When adding to the message structures insure that fields are
* properly aligned.
*
*/
/* HTC frame header */
typedef PREPACK struct _HTC_FRAME_HDR{
/* do not remove or re-arrange these fields, these are minimally required
* to take advantage of 4-byte lookaheads in some hardware implementations */
A_UINT8 EndpointID;
A_UINT8 Flags;
A_UINT16 PayloadLen; /* length of data (including trailer) that follows the header */
/***** end of 4-byte lookahead ****/
A_UINT8 ControlBytes[2];
/* message payload starts after the header */
} POSTPACK HTC_FRAME_HDR;
/* frame header flags */
/* send direction */
#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0)
#define HTC_FLAGS_SEND_BUNDLE (1 << 1) /* start or part of bundle */
/* receive direction */
#define HTC_FLAGS_RECV_UNUSED_0 (1 << 0) /* bit 0 unused */
#define HTC_FLAGS_RECV_TRAILER (1 << 1) /* bit 1 trailer data present */
#define HTC_FLAGS_RECV_UNUSED_2 (1 << 0) /* bit 2 unused */
#define HTC_FLAGS_RECV_UNUSED_3 (1 << 0) /* bit 3 unused */
#define HTC_FLAGS_RECV_BUNDLE_CNT_MASK (0xF0) /* bits 7..4 */
#define HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT 4
#define HTC_HDR_LENGTH (sizeof(HTC_FRAME_HDR))
#define HTC_MAX_TRAILER_LENGTH 255
#define HTC_MAX_PAYLOAD_LENGTH (4096 - sizeof(HTC_FRAME_HDR))
/* HTC control message IDs */
#define HTC_MSG_READY_ID 1
#define HTC_MSG_CONNECT_SERVICE_ID 2
#define HTC_MSG_CONNECT_SERVICE_RESPONSE_ID 3
#define HTC_MSG_SETUP_COMPLETE_ID 4
#define HTC_MSG_SETUP_COMPLETE_EX_ID 5
#define HTC_MAX_CONTROL_MESSAGE_LENGTH 256
/* base message ID header */
typedef PREPACK struct {
A_UINT16 MessageID;
} POSTPACK HTC_UNKNOWN_MSG;
/* HTC ready message
* direction : target-to-host */
typedef PREPACK struct {
A_UINT16 MessageID; /* ID */
A_UINT16 CreditCount; /* number of credits the target can offer */
A_UINT16 CreditSize; /* size of each credit */
A_UINT8 MaxEndpoints; /* maximum number of endpoints the target has resources for */
A_UINT8 _Pad1;
} POSTPACK HTC_READY_MSG;
/* extended HTC ready message */
typedef PREPACK struct {
HTC_READY_MSG Version2_0_Info; /* legacy version 2.0 information at the front... */
/* extended information */
A_UINT8 HTCVersion;
A_UINT8 MaxMsgsPerHTCBundle;
} POSTPACK HTC_READY_EX_MSG;
#define HTC_VERSION_2P0 0x00
#define HTC_VERSION_2P1 0x01 /* HTC 2.1 */
#define HTC_SERVICE_META_DATA_MAX_LENGTH 128
/* connect service
* direction : host-to-target */
typedef PREPACK struct {
A_UINT16 MessageID;
A_UINT16 ServiceID; /* service ID of the service to connect to */
A_UINT16 ConnectionFlags; /* connection flags */
#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2) /* reduce credit dribbling when
the host needs credits */
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3)
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3
A_UINT8 ServiceMetaLength; /* length of meta data that follows */
A_UINT8 _Pad1;
/* service-specific meta data starts after the header */
} POSTPACK HTC_CONNECT_SERVICE_MSG;
/* connect response
* direction : target-to-host */
typedef PREPACK struct {
A_UINT16 MessageID;
A_UINT16 ServiceID; /* service ID that the connection request was made */
A_UINT8 Status; /* service connection status */
A_UINT8 EndpointID; /* assigned endpoint ID */
A_UINT16 MaxMsgSize; /* maximum expected message size on this endpoint */
A_UINT8 ServiceMetaLength; /* length of meta data that follows */
A_UINT8 _Pad1;
/* service-specific meta data starts after the header */
} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG;
typedef PREPACK struct {
A_UINT16 MessageID;
/* currently, no other fields */
} POSTPACK HTC_SETUP_COMPLETE_MSG;
/* extended setup completion message */
typedef PREPACK struct {
A_UINT16 MessageID;
A_UINT32 SetupFlags;
A_UINT8 MaxMsgsPerBundledRecv;
A_UINT8 Rsvd[3];
} POSTPACK HTC_SETUP_COMPLETE_EX_MSG;
#define HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV (1 << 0)
/* connect response status codes */
#define HTC_SERVICE_SUCCESS 0 /* success */
#define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */
#define HTC_SERVICE_FAILED 2 /* specific service failed the connect */
#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */
#define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more
endpoints */
/* report record IDs */
#define HTC_RECORD_NULL 0
#define HTC_RECORD_CREDITS 1
#define HTC_RECORD_LOOKAHEAD 2
#define HTC_RECORD_LOOKAHEAD_BUNDLE 3
typedef PREPACK struct {
A_UINT8 RecordID; /* Record ID */
A_UINT8 Length; /* Length of record */
} POSTPACK HTC_RECORD_HDR;
typedef PREPACK struct {
A_UINT8 EndpointID; /* Endpoint that owns these credits */
A_UINT8 Credits; /* credits to report since last report */
} POSTPACK HTC_CREDIT_REPORT;
typedef PREPACK struct {
A_UINT8 PreValid; /* pre valid guard */
A_UINT8 LookAhead[4]; /* 4 byte lookahead */
A_UINT8 PostValid; /* post valid guard */
/* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes.
* The PreValid bytes must equal the inverse of the PostValid byte */
} POSTPACK HTC_LOOKAHEAD_REPORT;
typedef PREPACK struct {
A_UINT8 LookAhead[4]; /* 4 byte lookahead */
} POSTPACK HTC_BUNDLED_LOOKAHEAD_REPORT;
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __HTC_H__ */
wlan/include/htc_services.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2007, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __HTC_SERVICES_H__
#define __HTC_SERVICES_H__
/* Current service IDs */
typedef enum {
RSVD_SERVICE_GROUP = 0,
WMI_SERVICE_GROUP = 1,
HTC_TEST_GROUP = 254,
HTC_SERVICE_GROUP_LAST = 255
}HTC_SERVICE_GROUP_IDS;
#define MAKE_SERVICE_ID(group,index) \
(int)(((int)group << 8) | (int)(index))
/* NOTE: service ID of 0x0000 is reserved and should never be used */
#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1)
#define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0)
#define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1)
#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2)
#define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3)
#define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4)
#define WMI_MAX_SERVICES 5
/* raw stream service (i.e. flash, tcmd, calibration apps) */
#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0)
#endif /*HTC_SERVICES_H_*/
wlan/include/ini_dset.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef _INI_DSET_H_
#define _INI_DSET_H_
/*
* Each of these represents a WHAL INI table, which consists
* of an "address column" followed by 1 or more "value columns".
*
* Software uses the base WHAL_INI_DATA_ID+column to access a
* DataSet that holds a particular column of data.
*/
typedef enum {
#if defined(AR6002_REV4) || defined(AR6003) || defined(AR6002_REV6)
/* Add these definitions for compatability */
#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN
#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 WHAL_INI_DATA_ID_BB_RFGAIN
WHAL_INI_DATA_ID_NULL =0,
WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3,4,5 */
WHAL_INI_DATA_ID_COMMON =6, /* 7 */
WHAL_INI_DATA_ID_BB_RFGAIN =8, /* 9,10 */
#ifdef FPGA
WHAL_INI_DATA_ID_ANALOG_BANK0 =11, /* 12 */
WHAL_INI_DATA_ID_ANALOG_BANK1 =13, /* 14 */
WHAL_INI_DATA_ID_ANALOG_BANK2 =15, /* 16 */
WHAL_INI_DATA_ID_ANALOG_BANK3 =17, /* 18, 19 */
WHAL_INI_DATA_ID_ANALOG_BANK6 =20, /* 21,22 */
WHAL_INI_DATA_ID_ANALOG_BANK7 =23, /* 24 */
WHAL_INI_DATA_ID_ADDAC =25, /* 26 */
#else
WHAL_INI_DATA_ID_ANALOG_COMMON =11, /* 12 */
WHAL_INI_DATA_ID_ANALOG_MODE_SPECIFIC=13, /* 14,15 */
WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17,18 */
WHAL_INI_DATA_ID_MODE_OVERRIDES =19, /* 20,21,22,23 */
WHAL_INI_DATA_ID_COMMON_OVERRIDES =24, /* 25 */
WHAL_INI_DATA_ID_ANALOG_OVERRIDES =26, /* 27,28 */
#endif /* FPGA */
#else
WHAL_INI_DATA_ID_NULL =0,
WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3 */
WHAL_INI_DATA_ID_COMMON =4, /* 5 */
WHAL_INI_DATA_ID_BB_RFGAIN =6, /* 7,8 */
#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN
WHAL_INI_DATA_ID_ANALOG_BANK1 =9, /* 10 */
WHAL_INI_DATA_ID_ANALOG_BANK2 =11, /* 12 */
WHAL_INI_DATA_ID_ANALOG_BANK3 =13, /* 14, 15 */
WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17, 18 */
WHAL_INI_DATA_ID_ANALOG_BANK7 =19, /* 20 */
WHAL_INI_DATA_ID_MODE_OVERRIDES =21, /* 22,23 */
WHAL_INI_DATA_ID_COMMON_OVERRIDES =24, /* 25 */
WHAL_INI_DATA_ID_ANALOG_OVERRIDES =26, /* 27,28 */
WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 =29, /* 30,31 */
#endif
WHAL_INI_DATA_ID_MAX =31
} WHAL_INI_DATA_ID;
typedef PREPACK struct {
A_UINT16 freqIndex; // 1 - A mode 2 - B or G mode 0 - common
A_UINT16 offset;
A_UINT32 newValue;
} POSTPACK INI_DSET_REG_OVERRIDE;
#endif
wlan/include/pkt_log.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2005-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __PKT_LOG_H__
#define __PKT_LOG_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Pkt log info */
typedef PREPACK struct pkt_log_t {
struct info_t {
A_UINT16 st;
A_UINT16 end;
A_UINT16 cur;
}info[4096];
A_UINT16 last_idx;
}POSTPACK PACKET_LOG;
#ifdef __cplusplus
}
#endif
#endif /* __PKT_LOG_H__ */
wlan/include/regDb.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2005-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __REG_DB_H__
#define __REG_DB_H__
#include "./regulatory/reg_dbschema.h"
#include "./regulatory/reg_dbvalues.h"
#endif /* __REG_DB_H__ */
wlan/include/regdump.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __REGDUMP_H__
#define __REGDUMP_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
#if defined(AR6001)
#include "AR6001/AR6001_regdump.h"
#endif
#if defined(AR6002)
#include "AR6002/AR6002_regdump.h"
#endif
#if !defined(__ASSEMBLER__)
/*
* Target CPU state at the time of failure is reflected
* in a register dump, which the Host can fetch through
* the diagnostic window.
*/
PREPACK struct register_dump_s {
A_UINT32 target_id; /* Target ID */
A_UINT32 assline; /* Line number (if assertion failure) */
A_UINT32 pc; /* Program Counter at time of exception */
A_UINT32 badvaddr; /* Virtual address causing exception */
CPU_exception_frame_t exc_frame; /* CPU-specific exception info */
/* Could copy top of stack here, too.... */
} POSTPACK;
#endif /* __ASSEMBLER__ */
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __REGDUMP_H__ */
wlan/include/regulatory/reg_dbschema.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2005-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __REG_DBSCHEMA_H__
#define __REG_DBSCHEMA_H__
/*
* This file describes the regulatory DB schema, which is common between the
* 'generator' and 'parser'. The 'generator' runs on a host(typically a x86
* Linux) and spits outs two binary files, which follow the DB file
* format(described below). The resultant output "regulatoryData_AG.bin"
* is binary file which has information regarding A and G regulatory
* information, while the "regulatoryData_G.bin" consists of G-ONLY regulatory
* information. This binary file is parsed in the target for extracting
* regulatory information.
*
* The DB values used to populate the regulatory DB are defined in
* reg_dbvalues.h
*
*/
/* Binary data file - Representation of Regulatory DB*/
#define REG_DATA_FILE_AG "./regulatoryData_AG.bin"
#define REG_DATA_FILE_G "./regulatoryData_G.bin"
/* Table tags used to encode different tables in the database */
enum data_tags_t{
REG_DMN_PAIR_MAPPING_TAG = 0,
REG_COUNTRY_CODE_TO_ENUM_RD_TAG,
REG_DMN_FREQ_BAND_regDmn5GhzFreq_TAG,
REG_DMN_FREQ_BAND_regDmn2Ghz11_BG_Freq_TAG,
REG_DOMAIN_TAG,
MAX_DB_TABLE_TAGS
};
/*
****************************************************************************
* Regulatory DB file format :
* 4-bytes : "RGDB" (Magic Key)
* 4-bytes : version (Default is 5379(my extn))
* 4-bytes : length of file
* dbType(4)
* TAG(4)
* Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data....
* TAG(4)
* Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data....
* TAG(4)
* Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data....
* ...
* ...
****************************************************************************
*
*/
/*
* Length of the file would be filled in when the file is created and
* it would include the header size.
*/
#define REG_DB_KEY "RGDB" /* Should be EXACTLY 4-bytes */
#define REG_DB_VER 7803 /* Between 0-9999 */
/* REG_DB_VER history in reverse chronological order:
* 7803: 78 (ASCII code of N) + 03 (minor version number) - updated 08/03/10, p4#21
* 7802: 78 (ASCII code of N) + 02 (minor version number) - updated 10/21/09, p4#17
* 7801: 78 (ASCII code of N) + 01 (minor version number, increment on further changes)
* 1178: '11N' = 11 + ASCII code of N(78)
* 5379: initial version, no 11N support
*/
#define MAGIC_KEY_OFFSET 0
#define VERSION_OFFSET 4
#define FILE_SZ_OFFSET 8
#define DB_TYPE_OFFSET 12
#define MAGIC_KEY_SZ 4
#define VERSION_SZ 4
#define FILE_SZ_SZ 4
#define DB_TYPE_SZ 4
#define DB_TAG_SZ 4
#define REGDB_GET_MAGICKEY(x) ((char *)x + MAGIC_KEY_OFFSET)
#define REGDB_GET_VERSION(x) ((char *)x + VERSION_OFFSET)
#define REGDB_GET_FILESIZE(x) *((unsigned int *)((char *)x + FILE_SZ_OFFSET))
#define REGDB_GET_DBTYPE(x) *((char *)x + DB_TYPE_OFFSET)
#define REGDB_SET_FILESIZE(x, sz_) *((unsigned int *)((char *)x + FILE_SZ_OFFSET)) = (sz_)
#define REGDB_IS_EOF(cur, begin) ( REGDB_GET_FILESIZE(begin) > ((cur) - (begin)) )
/* A Table can be search based on key as a parameter or accessed directly
* by giving its index in to the table.
*/
enum searchType {
KEY_BASED_TABLE_SEARCH = 1,
INDEX_BASED_TABLE_ACCESS
};
/* Data is organised as different tables. There is a Master table, which
* holds information regarding all the tables. It does not have any
* knowledge about the attributes of the table it is holding
* but has external view of the same(for ex, how many entries, record size,
* how to search the table, total table size and reference to the data
* instance of table).
*/
typedef PREPACK struct dbMasterTable_t { /* Hold ptrs to Table data structures */
A_UCHAR numOfEntries;
A_CHAR entrySize; /* Entry size per table row */
A_CHAR searchType; /* Index based access or key based */
A_CHAR reserved[3]; /* for alignment */
A_UINT16 tableSize; /* Size of this table */
A_CHAR *dataPtr; /* Ptr to the actual Table */
} POSTPACK dbMasterTable; /* Master table - table of tables */
/* used to get the number of rows in a table */
#define REGDB_NUM_OF_ROWS(a) (sizeof (a) / sizeof (a[0]))
/*
* Used to set the RegDomain bitmask which chooses which frequency
* band specs are used.
*/
#define BMLEN 2 /* Use 2 32-bit uint for channel bitmask */
#define BMZERO {0,0} /* BMLEN zeros */
#define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh) \
{((((_fa >= 0) && (_fa < 32)) ? (((A_UINT32) 1) << _fa) : 0) | \
(((_fb >= 0) && (_fb < 32)) ? (((A_UINT32) 1) << _fb) : 0) | \
(((_fc >= 0) && (_fc < 32)) ? (((A_UINT32) 1) << _fc) : 0) | \
(((_fd >= 0) && (_fd < 32)) ? (((A_UINT32) 1) << _fd) : 0) | \
(((_fe >= 0) && (_fe < 32)) ? (((A_UINT32) 1) << _fe) : 0) | \
(((_ff >= 0) && (_ff < 32)) ? (((A_UINT32) 1) << _ff) : 0) | \
(((_fg >= 0) && (_fg < 32)) ? (((A_UINT32) 1) << _fg) : 0) | \
(((_fh >= 0) && (_fh < 32)) ? (((A_UINT32) 1) << _fh) : 0)), \
((((_fa > 31) && (_fa < 64)) ? (((A_UINT32) 1) << (_fa - 32)) : 0) | \
(((_fb > 31) && (_fb < 64)) ? (((A_UINT32) 1) << (_fb - 32)) : 0) | \
(((_fc > 31) && (_fc < 64)) ? (((A_UINT32) 1) << (_fc - 32)) : 0) | \
(((_fd > 31) && (_fd < 64)) ? (((A_UINT32) 1) << (_fd - 32)) : 0) | \
(((_fe > 31) && (_fe < 64)) ? (((A_UINT32) 1) << (_fe - 32)) : 0) | \
(((_ff > 31) && (_ff < 64)) ? (((A_UINT32) 1) << (_ff - 32)) : 0) | \
(((_fg > 31) && (_fg < 64)) ? (((A_UINT32) 1) << (_fg - 32)) : 0) | \
(((_fh > 31) && (_fh < 64)) ? (((A_UINT32) 1) << (_fh - 32)) : 0))}
/*
* THE following table is the mapping of regdomain pairs specified by
* a regdomain value to the individual unitary reg domains
*/
typedef PREPACK struct reg_dmn_pair_mapping {
A_UINT16 regDmnEnum; /* 16 bit reg domain pair */
A_UINT16 regDmn5GHz; /* 5GHz reg domain */
A_UINT16 regDmn2GHz; /* 2GHz reg domain */
A_UINT8 flags5GHz; /* Requirements flags (AdHoc disallow etc) */
A_UINT8 flags2GHz; /* Requirements flags (AdHoc disallow etc) */
A_UINT32 pscanMask; /* Passive Scan flags which can override unitary domain passive scan
flags. This value is used as a mask on the unitary flags*/
} POSTPACK REG_DMN_PAIR_MAPPING;
#define OFDM_YES (1 << 0)
#define OFDM_NO (0 << 0)
#define MCS_HT20_YES (1 << 1)
#define MCS_HT20_NO (0 << 1)
#define MCS_HT40_A_YES (1 << 2)
#define MCS_HT40_A_NO (0 << 2)
#define MCS_HT40_G_YES (1 << 3)
#define MCS_HT40_G_NO (0 << 3)
typedef PREPACK struct {
A_UINT16 countryCode;
A_UINT16 regDmnEnum;
A_CHAR isoName[3];
A_CHAR allowMode; /* what mode is allowed - bit 0: OFDM; bit 1: MCS_HT20; bit 2: MCS_HT40_A; bit 3: MCS_HT40_G */
} POSTPACK COUNTRY_CODE_TO_ENUM_RD;
/* lower 16 bits of ht40ChanMask */
#define NO_FREQ_HT40 0x0 /* no freq is HT40 capable */
#define F1_TO_F4_HT40 0xF /* freq 1 to 4 in the block is ht40 capable */
#define F2_TO_F3_HT40 0x6 /* freq 2 to 3 in the block is ht40 capable */
#define F1_TO_F10_HT40 0x3FF /* freq 1 to 10 in the block is ht40 capable */
#define F3_TO_F11_HT40 0x7FC /* freq 3 to 11 in the block is ht40 capable */
#define F3_TO_F9_HT40 0x1FC /* freq 3 to 9 in the block is ht40 capable */
#define F1_TO_F8_HT40 0xFF /* freq 1 to 8 in the block is ht40 capable */
#define F1_TO_F4_F9_TO_F10_HT40 0x30F /* freq 1 to 4, 9 to 10 in the block is ht40 capable */
/* upper 16 bits of ht40ChanMask */
#define FREQ_HALF_RATE 0x10000
#define FREQ_QUARTER_RATE 0x20000
typedef PREPACK struct RegDmnFreqBand {
A_UINT16 lowChannel; /* Low channel center in MHz */
A_UINT16 highChannel; /* High Channel center in MHz */
A_UINT8 power; /* Max power (dBm) for channel range */
A_UINT8 channelSep; /* Channel separation within the band */
A_UINT8 useDfs; /* Use DFS in the RegDomain if corresponding bit is set */
A_UINT8 mode; /* Mode of operation */
A_UINT32 usePassScan; /* Use Passive Scan in the RegDomain if corresponding bit is set */
A_UINT32 ht40ChanMask; /* lower 16 bits: indicate which frequencies in the block is HT40 capable
upper 16 bits: what rate (half/quarter) the channel is */
} POSTPACK REG_DMN_FREQ_BAND;
typedef PREPACK struct regDomain {
A_UINT16 regDmnEnum; /* value from EnumRd table */
A_UINT8 rdCTL;
A_UINT8 maxAntGain;
A_UINT8 dfsMask; /* DFS bitmask for 5Ghz tables */
A_UINT8 flags; /* Requirement flags (AdHoc disallow etc) */
A_UINT16 reserved; /* for alignment */
A_UINT32 pscan; /* Bitmask for passive scan */
A_UINT32 chan11a[BMLEN]; /* 64 bit bitmask for channel/band selection */
A_UINT32 chan11bg[BMLEN];/* 64 bit bitmask for channel/band selection */
} POSTPACK REG_DOMAIN;
#endif /* __REG_DBSCHEMA_H__ */
wlan/include/regulatory/reg_dbvalues.h
+514
View File
@@ -0,0 +1,514 @@
//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2005-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __REG_DBVALUE_H__
#define __REG_DBVALUE_H__
/*
* Numbering from ISO 3166
*/
enum CountryCode {
CTRY_ALBANIA = 8, /* Albania */
CTRY_ALGERIA = 12, /* Algeria */
CTRY_ARGENTINA = 32, /* Argentina */
CTRY_ARMENIA = 51, /* Armenia */
CTRY_ARUBA = 533, /* Aruba */
CTRY_AUSTRALIA = 36, /* Australia (for STA) */
CTRY_AUSTRALIA_AP = 5000, /* Australia (for AP) */
CTRY_AUSTRIA = 40, /* Austria */
CTRY_AZERBAIJAN = 31, /* Azerbaijan */
CTRY_BAHRAIN = 48, /* Bahrain */
CTRY_BANGLADESH = 50, /* Bangladesh */
CTRY_BARBADOS = 52, /* Barbados */
CTRY_BELARUS = 112, /* Belarus */
CTRY_BELGIUM = 56, /* Belgium */
CTRY_BELIZE = 84, /* Belize */
CTRY_BOLIVIA = 68, /* Bolivia */
CTRY_BOSNIA_HERZEGOWANIA = 70, /* Bosnia & Herzegowania */
CTRY_BRAZIL = 76, /* Brazil */
CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */
CTRY_BULGARIA = 100, /* Bulgaria */
CTRY_CAMBODIA = 116, /* Cambodia */
CTRY_CANADA = 124, /* Canada (for STA) */
CTRY_CANADA_AP = 5001, /* Canada (for AP) */
CTRY_CHILE = 152, /* Chile */
CTRY_CHINA = 156, /* People's Republic of China */
CTRY_COLOMBIA = 170, /* Colombia */
CTRY_COSTA_RICA = 188, /* Costa Rica */
CTRY_CROATIA = 191, /* Croatia */
CTRY_CYPRUS = 196,
CTRY_CZECH = 203, /* Czech Republic */
CTRY_DENMARK = 208, /* Denmark */
CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */
CTRY_ECUADOR = 218, /* Ecuador */
CTRY_EGYPT = 818, /* Egypt */
CTRY_EL_SALVADOR = 222, /* El Salvador */
CTRY_ESTONIA = 233, /* Estonia */
CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */
CTRY_FINLAND = 246, /* Finland */
CTRY_FRANCE = 250, /* France */
CTRY_FRANCE2 = 255, /* France2 */
CTRY_GEORGIA = 268, /* Georgia */
CTRY_GERMANY = 276, /* Germany */
CTRY_GREECE = 300, /* Greece */
CTRY_GREENLAND = 304, /* Greenland */
CTRY_GRENADA = 308, /* Grenada */
CTRY_GUAM = 316, /* Guam */
CTRY_GUATEMALA = 320, /* Guatemala */
CTRY_HAITI = 332, /* Haiti */
CTRY_HONDURAS = 340, /* Honduras */
CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */
CTRY_HUNGARY = 348, /* Hungary */
CTRY_ICELAND = 352, /* Iceland */
CTRY_INDIA = 356, /* India */
CTRY_INDONESIA = 360, /* Indonesia */
CTRY_IRAN = 364, /* Iran */
CTRY_IRAQ = 368, /* Iraq */
CTRY_IRELAND = 372, /* Ireland */
CTRY_ISRAEL = 376, /* Israel */
CTRY_ITALY = 380, /* Italy */
CTRY_JAMAICA = 388, /* Jamaica */
CTRY_JAPAN = 392, /* Japan */
CTRY_JAPAN1 = 393, /* Japan (JP1) */
CTRY_JAPAN2 = 394, /* Japan (JP0) */
CTRY_JAPAN3 = 395, /* Japan (JP1-1) */
CTRY_JAPAN4 = 396, /* Japan (JE1) */
CTRY_JAPAN5 = 397, /* Japan (JE2) */
CTRY_JAPAN6 = 399, /* Japan (JP6) */
CTRY_JORDAN = 400, /* Jordan */
CTRY_KAZAKHSTAN = 398, /* Kazakhstan */
CTRY_KENYA = 404, /* Kenya */
CTRY_KOREA_NORTH = 408, /* North Korea */
CTRY_KOREA_ROC = 410, /* South Korea (for STA) */
CTRY_KOREA_ROC2 = 411, /* South Korea */
CTRY_KOREA_ROC3 = 412, /* South Korea (for AP) */
CTRY_KUWAIT = 414, /* Kuwait */
CTRY_LATVIA = 428, /* Latvia */
CTRY_LEBANON = 422, /* Lebanon */
CTRY_LIBYA = 434, /* Libya */
CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */
CTRY_LITHUANIA = 440, /* Lithuania */
CTRY_LUXEMBOURG = 442, /* Luxembourg */
CTRY_MACAU = 446, /* Macau */
CTRY_MACEDONIA = 807, /* the Former Yugoslav Republic of Macedonia */
CTRY_MALAYSIA = 458, /* Malaysia */
CTRY_MALTA = 470, /* Malta */
CTRY_MEXICO = 484, /* Mexico */
CTRY_MONACO = 492, /* Principality of Monaco */
CTRY_MOROCCO = 504, /* Morocco */
CTRY_NEPAL = 524, /* Nepal */
CTRY_NETHERLANDS = 528, /* Netherlands */
CTRY_NETHERLAND_ANTILLES = 530, /* Netherlands-Antilles */
CTRY_NEW_ZEALAND = 554, /* New Zealand */
CTRY_NICARAGUA = 558, /* Nicaragua */
CTRY_NORWAY = 578, /* Norway */
CTRY_OMAN = 512, /* Oman */
CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */
CTRY_PANAMA = 591, /* Panama */
CTRY_PARAGUAY = 600, /* Paraguay */
CTRY_PERU = 604, /* Peru */
CTRY_PHILIPPINES = 608, /* Republic of the Philippines */
CTRY_POLAND = 616, /* Poland */
CTRY_PORTUGAL = 620, /* Portugal */
CTRY_PUERTO_RICO = 630, /* Puerto Rico */
CTRY_QATAR = 634, /* Qatar */
CTRY_ROMANIA = 642, /* Romania */
CTRY_RUSSIA = 643, /* Russia */
CTRY_RWANDA = 646, /* Rwanda */
CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */
CTRY_MONTENEGRO = 891, /* Montenegro */
CTRY_SINGAPORE = 702, /* Singapore */
CTRY_SLOVAKIA = 703, /* Slovak Republic */
CTRY_SLOVENIA = 705, /* Slovenia */
CTRY_SOUTH_AFRICA = 710, /* South Africa */
CTRY_SPAIN = 724, /* Spain */
CTRY_SRILANKA = 144, /* Sri Lanka */
CTRY_SWEDEN = 752, /* Sweden */
CTRY_SWITZERLAND = 756, /* Switzerland */
CTRY_SYRIA = 760, /* Syria */
CTRY_TAIWAN = 158, /* Taiwan */
CTRY_THAILAND = 764, /* Thailand */
CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */
CTRY_TUNISIA = 788, /* Tunisia */
CTRY_TURKEY = 792, /* Turkey */
CTRY_UAE = 784, /* U.A.E. */
CTRY_UKRAINE = 804, /* Ukraine */
CTRY_UNITED_KINGDOM = 826, /* United Kingdom */
CTRY_UNITED_STATES = 840, /* United States (for STA) */
CTRY_UNITED_STATES_AP = 841, /* United States (for AP) */
CTRY_UNITED_STATES_PS = 842, /* United States - public safety */
CTRY_URUGUAY = 858, /* Uruguay */
CTRY_UZBEKISTAN = 860, /* Uzbekistan */
CTRY_VENEZUELA = 862, /* Venezuela */
CTRY_VIET_NAM = 704, /* Viet Nam */
CTRY_YEMEN = 887, /* Yemen */
CTRY_ZIMBABWE = 716 /* Zimbabwe */
};
#define CTRY_DEBUG 0
#define CTRY_DEFAULT 0x1ff
/*
* The following regulatory domain definitions are
* found in the EEPROM. Each regulatory domain
* can operate in either a 5GHz or 2.4GHz wireless mode or
* both 5GHz and 2.4GHz wireless modes.
* In general, the value holds no special
* meaning and is used to decode into either specific
* 2.4GHz or 5GHz wireless mode for that particular
* regulatory domain.
*
* Enumerated Regulatory Domain Information 8 bit values indicate that
* the regdomain is really a pair of unitary regdomains. 12 bit values
* are the real unitary regdomains and are the only ones which have the
* frequency bitmasks and flags set.
*/
enum EnumRd {
NO_ENUMRD = 0x00,
NULL1_WORLD = 0x03, /* For 11b-only countries (no 11a allowed) */
NULL1_ETSIB = 0x07, /* Israel */
NULL1_ETSIC = 0x08,
FCC1_FCCA = 0x10, /* USA */
FCC1_WORLD = 0x11, /* Hong Kong */
FCC2_FCCA = 0x20, /* Canada */
FCC2_WORLD = 0x21, /* Australia & HK */
FCC2_ETSIC = 0x22,
FCC3_FCCA = 0x3A, /* USA & Canada w/5470 band, 11h, DFS enabled */
FCC3_WORLD = 0x3B, /* USA & Canada w/5470 band, 11h, DFS enabled */
FCC4_FCCA = 0x12, /* FCC public safety plus UNII bands */
FCC5_FCCA = 0x13, /* US with no DFS */
FCC5_WORLD = 0x16, /* US with no DFS */
FCC6_FCCA = 0x14, /* Same as FCC2_FCCA but with 5600-5650MHz channels disabled for US & Canada APs */
FCC6_WORLD = 0x23, /* Same as FCC2_FCCA but with 5600-5650MHz channels disabled for Australia APs */
ETSI1_WORLD = 0x37,
ETSI2_WORLD = 0x35, /* Hungary & others */
ETSI3_WORLD = 0x36, /* France & others */
ETSI4_WORLD = 0x30,
ETSI4_ETSIC = 0x38,
ETSI5_WORLD = 0x39,
ETSI6_WORLD = 0x34, /* Bulgaria */
ETSI8_WORLD = 0x3D, /* Russia & Ukraine */
ETSI_RESERVED = 0x33, /* Reserved (Do not used) */
FRANCE_RES = 0x31, /* Legacy France for OEM */
APL6_WORLD = 0x5B, /* Singapore */
APL4_WORLD = 0x42, /* Singapore */
APL3_FCCA = 0x50,
APL_RESERVED = 0x44, /* Reserved (Do not used) */
APL2_WORLD = 0x45, /* Korea */
APL2_APLC = 0x46,
APL3_WORLD = 0x47,
APL2_APLD = 0x49, /* Korea with 2.3G channels */
APL2_FCCA = 0x4D, /* Specific Mobile Customer */
APL1_WORLD = 0x52, /* Latin America */
APL1_FCCA = 0x53,
APL1_ETSIC = 0x55,
APL2_ETSIC = 0x56, /* Venezuela */
APL5_WORLD = 0x58, /* Chile */
APL7_FCCA = 0x5C,
APL8_WORLD = 0x5D,
APL9_WORLD = 0x5E,
APL10_WORLD = 0x5F, /* Korea 5GHz for STA */
MKK5_MKKA = 0x99, /* This is a temporary value. MG and DQ have to give official one */
MKK5_FCCA = 0x9A, /* This is a temporary value. MG and DQ have to give official one */
MKK5_MKKC = 0x88,
MKK11_MKKA = 0xD4,
MKK11_FCCA = 0xD5,
MKK11_MKKC = 0xD7,
/*
* World mode SKUs
*/
WOR0_WORLD = 0x60, /* World0 (WO0 SKU) */
WOR1_WORLD = 0x61, /* World1 (WO1 SKU) */
WOR2_WORLD = 0x62, /* World2 (WO2 SKU) */
WOR3_WORLD = 0x63, /* World3 (WO3 SKU) */
WOR4_WORLD = 0x64, /* World4 (WO4 SKU) */
WOR5_ETSIC = 0x65, /* World5 (WO5 SKU) */
WOR01_WORLD = 0x66, /* World0-1 (WW0-1 SKU) */
WOR02_WORLD = 0x67, /* World0-2 (WW0-2 SKU) */
EU1_WORLD = 0x68, /* Same as World0-2 (WW0-2 SKU), except active scan ch1-13. No ch14 */
WOR9_WORLD = 0x69, /* World9 (WO9 SKU) */
WORA_WORLD = 0x6A, /* WorldA (WOA SKU) */
WORB_WORLD = 0x6B, /* WorldB (WOA SKU) */
WORC_WORLD = 0x6C, /* WorldC (WOA SKU) */
/*
* Regulator domains ending in a number (e.g. APL1,
* MK1, ETSI4, etc) apply to 5GHz channel and power
* information. Regulator domains ending in a letter
* (e.g. APLA, FCCA, etc) apply to 2.4GHz channel and
* power information.
*/
APL1 = 0x0150, /* LAT & Asia */
APL2 = 0x0250, /* LAT & Asia */
APL3 = 0x0350, /* Taiwan */
APL4 = 0x0450, /* Jordan */
APL5 = 0x0550, /* Chile */
APL6 = 0x0650, /* Singapore */
APL7 = 0x0750, /* Taiwan */
APL8 = 0x0850, /* Malaysia */
APL9 = 0x0950, /* Korea */
APL10 = 0x1050, /* Korea 5GHz */
ETSI1 = 0x0130, /* Europe & others */
ETSI2 = 0x0230, /* Europe & others */
ETSI3 = 0x0330, /* Europe & others */
ETSI4 = 0x0430, /* Europe & others */
ETSI5 = 0x0530, /* Europe & others */
ETSI6 = 0x0630, /* Europe & others */
ETSI8 = 0x0830, /* Russia & Ukraine - only by APs */
ETSIB = 0x0B30, /* Israel */
ETSIC = 0x0C30, /* Latin America */
FCC1 = 0x0110, /* US & others */
FCC2 = 0x0120, /* Canada, Australia & New Zealand */
FCC3 = 0x0160, /* US w/new middle band & DFS */
FCC4 = 0x0165,
FCC5 = 0x0180,
FCC6 = 0x0610,
FCCA = 0x0A10,
APLD = 0x0D50, /* South Korea */
MKK1 = 0x0140, /* Japan */
MKK2 = 0x0240, /* Japan Extended */
MKK3 = 0x0340, /* Japan new 5GHz */
MKK4 = 0x0440, /* Japan new 5GHz */
MKK5 = 0x0540, /* Japan new 5GHz */
MKK6 = 0x0640, /* Japan new 5GHz */
MKK7 = 0x0740, /* Japan new 5GHz */
MKK8 = 0x0840, /* Japan new 5GHz */
MKK9 = 0x0940, /* Japan new 5GHz */
MKK10 = 0x1040, /* Japan new 5GHz */
MKK11 = 0x1140, /* Japan new 5GHz */
MKK12 = 0x1240, /* Japan new 5GHz */
MKKA = 0x0A40, /* Japan */
MKKC = 0x0A50,
NULL1 = 0x0198,
WORLD = 0x0199,
DEBUG_REG_DMN = 0x01ff,
UNINIT_REG_DMN = 0x0fff,
};
enum { /* conformance test limits */
FCC = 0x10,
MKK = 0x40,
ETSI = 0x30,
NO_CTL = 0xff,
CTL_11B = 1,
CTL_11G = 2
};
/*
* The following are flags for different requirements per reg domain.
* These requirements are either inhereted from the reg domain pair or
* from the unitary reg domain if the reg domain pair flags value is
* 0
*/
enum {
NO_REQ = 0x00,
DISALLOW_ADHOC_11A = 0x01,
ADHOC_PER_11D = 0x02,
ADHOC_NO_11A = 0x04,
DISALLOW_ADHOC_11G = 0x08
};
/*
* The following describe the bit masks for different passive scan
* capability/requirements per regdomain.
*/
#define NO_PSCAN 0x00000000
#define PSCAN_FCC 0x00000001
#define PSCAN_ETSI 0x00000002
#define PSCAN_MKK 0x00000004
#define PSCAN_ETSIB 0x00000008
#define PSCAN_ETSIC 0x00000010
#define PSCAN_WWR 0x00000020
#define PSCAN_DEFER 0xFFFFFFFF
/* Bit masks for DFS per regdomain */
enum {
NO_DFS = 0x00,
DFS_FCC3 = 0x01,
DFS_ETSI = 0x02,
DFS_MKK = 0x04
};
#define DEF_REGDMN FCC1_FCCA
/*
* The following table is the master list for all different freqeuncy
* bands with the complete matrix of all possible flags and settings
* for each band if it is used in ANY reg domain.
*
* The table of frequency bands is indexed by a bitmask. The ordering
* must be consistent with the enum below. When adding a new
* frequency band, be sure to match the location in the enum with the
* comments
*/
/*
* These frequency values are as per channel tags and regulatory domain
* info. Please update them as database is updated.
*/
#define A_FREQ_MIN 4920
#define A_FREQ_MAX 5825
#define A_CHAN0_FREQ 5000
#define A_CHAN_MAX ((A_FREQ_MAX - A_CHAN0_FREQ)/5)
#define BG_FREQ_MIN 2412
#define BG_FREQ_MAX 2484
#define BG_CHAN0_FREQ 2407
#define BG_CHAN_MIN ((BG_FREQ_MIN - BG_CHAN0_FREQ)/5)
#define BG_CHAN_MAX 14 /* corresponding to 2484 MHz */
#define A_20MHZ_BAND_FREQ_MAX 5000
/*
* 5GHz 11A channel tags
*/
enum {
F1_4920_4980,
F1_5040_5080,
F1_5120_5240,
F1_5180_5240,
F2_5180_5240,
F3_5180_5240,
F4_5180_5240,
F5_5180_5240,
F6_5180_5240,
F7_5180_5240,
F1_5260_5280,
F1_5260_5320,
F2_5260_5320,
F3_5260_5320,
F4_5260_5320,
F5_5260_5320,
F6_5260_5320,
F1_5260_5700,
F1_5280_5320,
F1_5500_5620,
F1_5500_5660,
F1_5500_5700,
F2_5500_5700,
F3_5500_5700,
F4_5500_5700,
F5_5500_5700,
F6_5500_5700,
F7_5500_5700,
F8_5500_5700,
F1_5745_5805,
F2_5745_5805,
F3_5745_5805,
F1_5745_5825,
F2_5745_5825,
F3_5745_5825,
F4_5745_5825,
F5_5745_5825,
W1_4920_4980,
W1_5040_5080,
W1_5170_5230,
W1_5180_5240,
W1_5260_5320,
W1_5745_5825,
W1_5500_5700,
};
/* 2.4 GHz table - for 11b and 11g info */
enum {
BG1_2312_2372,
BG2_2312_2372,
BG1_2412_2472,
BG2_2412_2472,
BG3_2412_2472,
BG4_2412_2472,
BG1_2412_2462,
BG2_2412_2462,
BG1_2432_2442,
BG1_2457_2472,
BG1_2467_2472,
BG1_2484_2484, /* No G */
BG2_2484_2484, /* No G */
BG1_2512_2732,
WBG1_2312_2372,
WBG1_2412_2412,
WBG1_2417_2432,
WBG1_2437_2442,
WBG1_2447_2457,
WBG1_2462_2462,
WBG1_2467_2467,
WBG2_2467_2467,
WBG1_2472_2472,
WBG2_2472_2472,
WBG1_2484_2484, /* No G */
WBG2_2484_2484, /* No G */
};
#endif /* __REG_DBVALUE_H__ */
wlan/include/roaming.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef _ROAMING_H_
#define _ROAMING_H_
/*
* The signal quality could be in terms of either snr or rssi. We should
* have an enum for both of them. For the time being, we are going to move
* it to wmi.h that is shared by both host and the target, since we are
* repartitioning the code to the host
*/
#define SIGNAL_QUALITY_NOISE_FLOOR -96
#define SIGNAL_QUALITY_METRICS_NUM_MAX 2
typedef enum {
SIGNAL_QUALITY_METRICS_SNR = 0,
SIGNAL_QUALITY_METRICS_RSSI,
SIGNAL_QUALITY_METRICS_ALL,
} SIGNAL_QUALITY_METRICS_TYPE;
#endif /* _ROAMING_H_ */
wlan/include/targaddrs.h
+402
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __TARGADDRS_H__
#define __TARGADDRS_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
#if defined(AR6002)
#include "AR6002/addrs.h"
#endif
/*
* AR6K option bits, to enable/disable various features.
* By default, all option bits are 0.
* These bits can be set in LOCAL_SCRATCH register 0.
*/
#define AR6K_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */
#define AR6K_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */
#define AR6K_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */
#define AR6K_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */
#define AR6K_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */
#define AR6K_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */
#define AR6K_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */
#define AR6K_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */
/*
* xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
* host_interest structure. It must match the address of the _host_interest
* symbol (see linker script).
*
* Host Interest is shared between Host and Target in order to coordinate
* between the two, and is intended to remain constant (with additions only
* at the end) across software releases.
*
* All addresses are available here so that it's possible to
* write a single binary that works with all Target Types.
* May be used in assembler code as well as C.
*/
#define AR6002_HOST_INTEREST_ADDRESS 0x00500400
#define AR6003_HOST_INTEREST_ADDRESS 0x00540600
#define MCKINLEY_HOST_INTEREST_ADDRESS 0x00400600
#define HOST_INTEREST_MAX_SIZE 0x100
#if !defined(__ASSEMBLER__)
struct register_dump_s;
struct dbglog_hdr_s;
/*
* These are items that the Host may need to access
* via BMI or via the Diagnostic Window. The position
* of items in this structure must remain constant
* across firmware revisions!
*
* Types for each item must be fixed size across
* target and host platforms.
*
* More items may be added at the end.
*/
PREPACK64 struct host_interest_s {
/*
* Pointer to application-defined area, if any.
* Set by Target application during startup.
*/
A_UINT32 hi_app_host_interest; /* 0x00 */
/* Pointer to register dump area, valid after Target crash. */
A_UINT32 hi_failure_state; /* 0x04 */
/* Pointer to debug logging header */
A_UINT32 hi_dbglog_hdr; /* 0x08 */
/* Indicates whether or not flash is present on Target.
* NB: flash_is_present indicator is here not just
* because it might be of interest to the Host; but
* also because it's set early on by Target's startup
* asm code and we need it to have a special RAM address
* so that it doesn't get reinitialized with the rest
* of data.
*/
A_UINT32 hi_flash_is_present; /* 0x0c */
/*
* General-purpose flag bits, similar to AR6000_OPTION_* flags.
* Can be used by application rather than by OS.
*/
A_UINT32 hi_option_flag; /* 0x10 */
/*
* Boolean that determines whether or not to
* display messages on the serial port.
*/
A_UINT32 hi_serial_enable; /* 0x14 */
/* Start address of DataSet index, if any */
A_UINT32 hi_dset_list_head; /* 0x18 */
/* Override Target application start address */
A_UINT32 hi_app_start; /* 0x1c */
/* Clock and voltage tuning */
A_UINT32 hi_skip_clock_init; /* 0x20 */
A_UINT32 hi_core_clock_setting; /* 0x24 */
A_UINT32 hi_cpu_clock_setting; /* 0x28 */
A_UINT32 hi_system_sleep_setting; /* 0x2c */
A_UINT32 hi_xtal_control_setting; /* 0x30 */
A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */
A_UINT32 hi_clock_info; /* 0x40 */
/*
* Flash configuration overrides, used only
* when firmware is not executing from flash.
* (When using flash, modify the global variables
* with equivalent names.)
*/
A_UINT32 hi_bank0_addr_value; /* 0x44 */
A_UINT32 hi_bank0_read_value; /* 0x48 */
A_UINT32 hi_bank0_write_value; /* 0x4c */
A_UINT32 hi_bank0_config_value; /* 0x50 */
/* Pointer to Board Data */
A_UINT32 hi_board_data; /* 0x54 */
A_UINT32 hi_board_data_initialized; /* 0x58 */
A_UINT32 hi_dset_RAM_index_table; /* 0x5c */
A_UINT32 hi_desired_baud_rate; /* 0x60 */
A_UINT32 hi_dbglog_config; /* 0x64 */
A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */
A_UINT32 hi_mbox_io_block_sz; /* 0x6c */
A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */
A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */
A_UINT32 hi_refclk_hz; /* 0x78 */
A_UINT32 hi_ext_clk_detected; /* 0x7c */
A_UINT32 hi_dbg_uart_txpin; /* 0x80 */
A_UINT32 hi_dbg_uart_rxpin; /* 0x84 */
A_UINT32 hi_hci_uart_baud; /* 0x88 */
A_UINT32 hi_hci_uart_pin_assignments; /* 0x8C */
/* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */
A_UINT32 hi_hci_uart_baud_scale_val; /* 0x90 */
A_UINT32 hi_hci_uart_baud_step_val; /* 0x94 */
A_UINT32 hi_allocram_start; /* 0x98 */
A_UINT32 hi_allocram_sz; /* 0x9c */
A_UINT32 hi_hci_bridge_flags; /* 0xa0 */
A_UINT32 hi_hci_uart_support_pins; /* 0xa4 */
/* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */
A_UINT32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
/* 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
* [31:16]: wakeup timeout in ms
*/
/* Pointer to extended board Data */
A_UINT32 hi_board_ext_data; /* 0xac */
A_UINT32 hi_board_ext_data_config; /* 0xb0 */
/*
* Bit [0] : valid
* Bit[31:16: size
*/
/*
* hi_reset_flag is used to do some stuff when target reset.
* such as restore app_start after warm reset or
* preserve host Interest area, or preserve ROM data, literals etc.
*/
A_UINT32 hi_reset_flag; /* 0xb4 */
/* indicate hi_reset_flag is valid */
A_UINT32 hi_reset_flag_valid; /* 0xb8 */
A_UINT32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */
/* 0xbc - [31:0]: idle timeout in ms
*/
/* ACS flags */
A_UINT32 hi_acs_flags; /* 0xc0 */
A_UINT32 hi_console_flags; /* 0xc4 */
A_UINT32 hi_nvram_state; /* 0xc8 */
A_UINT32 hi_option_flag2; /* 0xcc */
/* If non-zero, override values sent to Host in WMI_READY event. */
A_UINT32 hi_sw_version_override; /* 0xd0 */
A_UINT32 hi_abi_version_override; /* 0xd4 */
/* test applications flags */
A_UINT32 hi_test_apps_related ; /* 0xd8 */
/* location of test script */
A_UINT32 hi_ota_testscript; /* 0xdc */
/* location of CAL data */
A_UINT32 hi_cal_data; /* 0xe0 */
} POSTPACK64;
/* bitmap for hi_test_apps_related */
#define HI_TEST_APPS_TESTSCRIPT_LOADED 0x00000001
#define HI_TEST_APPS_CAL_DATA_AVAIL 0x00000002
/* Bits defined in hi_option_flag */
#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */
#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */
#define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */
#define HI_OPTION_MAC_ADDR_METHOD 0x08 /* MAC addr method 0-locally administred 1-globally unique addrs */
#define HI_OPTION_ENABLE_RFKILL 0x10 /* RFKill Enable Feature*/
#define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */
#define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */
#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */
#define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */
#define HI_OPTION_NUM_DEV_LSB 0x200
#define HI_OPTION_NUM_DEV_MSB 0x800
#define HI_OPTION_DEV_MODE_LSB 0x1000
#define HI_OPTION_DEV_MODE_MSB 0x8000000
#define HI_OPTION_NO_LFT_STBL 0x10000000 /* Disable LowFreq Timer Stabilization */
#define HI_OPTION_SKIP_REG_SCAN 0x20000000 /* Skip regulatory scan */
#define HI_OPTION_INIT_REG_SCAN 0x40000000 /* Do regulatory scan during init before sending WMI ready event to host */
#define HI_OPTION_FW_BRIDGE 0x80000000
#define HI_OPTION_OFFLOAD_AMSDU 0x01
#define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3
/* 2 bits of hi_option_flag are used to represent 3 modes */
#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */
#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */
#define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */
/* 2 bits of hi_option flag are usedto represent 4 submodes */
#define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */
#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */
#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */
#define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */
/* Num dev Mask */
#define HI_OPTION_NUM_DEV_MASK 0x7
#define HI_OPTION_NUM_DEV_SHIFT 0x9
#define HI_OPTION_RF_KILL_SHIFT 0x4
#define HI_OPTION_RF_KILL_MASK 0x1
/* firmware bridging */
#define HI_OPTION_FW_BRIDGE_SHIFT 0x1f
/* Fw Mode/SubMode Mask
|-------------------------------------------------------------------------------|
| SUB | SUB | SUB | SUB | | | | |
| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0] |
| (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) |
|-------------------------------------------------------------------------------|
*/
#define HI_OPTION_FW_MODE_BITS 0x2
#define HI_OPTION_FW_MODE_MASK 0x3
#define HI_OPTION_FW_MODE_SHIFT 0xC
#define HI_OPTION_ALL_FW_MODE_MASK 0xFF
#define HI_OPTION_FW_SUBMODE_BITS 0x2
#define HI_OPTION_FW_SUBMODE_MASK 0x3
#define HI_OPTION_FW_SUBMODE_SHIFT 0x14
#define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00
#define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8
/* hi_reset_flag */
#define HI_RESET_FLAG_PRESERVE_APP_START 0x01 /* preserve App Start address */
#define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02 /* preserve host interest */
#define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 /* preserve ROM data */
#define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08
#define HI_RESET_FLAG_IS_VALID 0x12345678 /* indicate the reset flag is valid */
#define ON_RESET_FLAGS_VALID() \
(HOST_INTEREST->hi_reset_flag_valid == HI_RESET_FLAG_IS_VALID)
#define RESET_FLAGS_VALIDATE() \
(HOST_INTEREST->hi_reset_flag_valid = HI_RESET_FLAG_IS_VALID)
#define RESET_FLAGS_INVALIDATE() \
(HOST_INTEREST->hi_reset_flag_valid = 0)
#define ON_RESET_PRESERVE_APP_START() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_APP_START)
#define ON_RESET_PRESERVE_NVRAM_STATE() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_NVRAM_STATE)
#define ON_RESET_PRESERVE_HOST_INTEREST() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_HOST_INTEREST)
#define ON_RESET_PRESERVE_ROMDATA() \
(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_ROMDATA)
#define HI_ACS_FLAGS_ENABLED (1 << 0) /* ACS is enabled */
#define HI_ACS_FLAGS_USE_WWAN (1 << 1) /* Use physical WWAN device */
#define HI_ACS_FLAGS_TEST_VAP (1 << 2) /* Use test VAP */
/* CONSOLE FLAGS
*
* Bit Range Meaning
* --------- --------------------------------
* 2..0 UART ID (0 = Default)
* 3 Baud Select (0 = 9600, 1 = 115200)
* 30..4 Reserved
* 31 Enable Console
*
* */
#define HI_CONSOLE_FLAGS_ENABLE (1 << 31)
#define HI_CONSOLE_FLAGS_UART_MASK (0x7)
#define HI_CONSOLE_FLAGS_UART_SHIFT 0
#define HI_CONSOLE_FLAGS_BAUD_SELECT (1 << 3)
/*
* Intended for use by Host software, this macro returns the Target RAM
* address of any item in the host_interest structure.
* Example: target_addr = AR6002_HOST_INTEREST_ITEM_ADDRESS(hi_board_data);
*/
#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((unsigned long)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((unsigned long)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item)))
#define MCKINLEY_HOST_INTEREST_ITEM_ADDRESS(item) \
((A_UINT32)&((((struct host_interest_s *)(MCKINLEY_HOST_INTEREST_ADDRESS))->item)))
#define HOST_INTEREST_DBGLOG_IS_ENABLED() \
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG))
#define HOST_INTEREST_PROFILE_IS_ENABLED() \
(HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE)
#define LF_TIMER_STABILIZATION_IS_ENABLED() \
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_NO_LFT_STBL))
#define IS_AMSDU_OFFLAOD_ENABLED() \
((HOST_INTEREST->hi_option_flag2 & HI_OPTION_OFFLOAD_AMSDU))
/* Convert a Target virtual address into a Target physical address */
#define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff)
#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff)
#define MCKINLEY_VTOP(vaddr) (vaddr)
#define TARG_VTOP(TargetType, vaddr) \
(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \
(((TargetType) == TARGET_TYPE_MCKINLEY) ? MCKINLEY_VTOP(vaddr) : 0)))
#define HOST_INTEREST_ITEM_ADDRESS(TargetType, item) \
(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : \
(((TargetType) == TARGET_TYPE_MCKINLEY) ? MCKINLEY_HOST_INTEREST_ITEM_ADDRESS(item) : 0)))
/* override REV2 ROM's app start address */
#define AR6002_REV2_APP_START_OVERRIDE 0x911A00
#define AR6002_REV2_DATASET_PATCH_ADDRESS 0x52d8b0
#define AR6002_REV2_APP_LOAD_ADDRESS 0x502070
#define AR6003_REV2_APP_START_OVERRIDE 0x944C00
#define AR6003_REV2_APP_LOAD_ADDRESS 0x543180
#define AR6003_REV2_BOARD_EXT_DATA_ADDRESS 0x57E500
#define AR6003_REV2_DATASET_PATCH_ADDRESS 0x57e884
#define AR6003_REV2_RAM_RESERVE_SIZE 6912
#define AR6003_REV3_APP_START_OVERRIDE 0x945d20
#define AR6003_REV3_APP_LOAD_ADDRESS 0x545000
#define AR6003_REV3_BOARD_EXT_DATA_ADDRESS 0x542330
#define AR6003_REV3_DATASET_PATCH_ADDRESS 0x57FEC8
#define AR6003_REV3_RAM_RESERVE_SIZE 512
#define AR6003_REV3_RAM_RESERVE_SIZE_TCMD 4352
/* # of A_UINT32 entries in targregs, used by DIAG_FETCH_TARG_REGS */
#define AR6003_FETCH_TARG_REGS_COUNT 64
#define MCKINLEY_FETCH_TARG_REGS_COUNT 64
#endif /* !__ASSEMBLER__ */
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __TARGADDRS_H__ */
wlan/include/testcmd.h
+380
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef TESTCMD_H_
#define TESTCMD_H_
#ifdef __cplusplus
extern "C" {
#endif
#ifdef AR6002_REV2
#define TCMD_MAX_RATES 12
#else
#define TCMD_MAX_RATES 28
#endif
//#define WMI_CMD_ID_SIZE 4
//#define WMI_CMDS_SIZE_MAX 2048
//#define TC_CMDS_GAP 16
// should add up to the same size as buf[WMI_CMDS_SIZE_MAX]
//#define TC_CMDS_SIZE_MAX (WMI_CMDS_SIZE_MAX - sizeof(TC_CMDS_HDR) - WMI_CMD_ID_SIZE - TC_CMDS_GAP)
#define TC_CMDS_SIZE_MAX 256
typedef enum {
ZEROES_PATTERN = 0,
ONES_PATTERN,
REPEATING_10,
PN7_PATTERN,
PN9_PATTERN,
PN15_PATTERN
}TX_DATA_PATTERN;
/* Continous tx
mode : TCMD_CONT_TX_OFF - Disabling continous tx
TCMD_CONT_TX_SINE - Enable continuous unmodulated tx
TCMD_CONT_TX_FRAME- Enable continuous modulated tx
freq : Channel freq in Mhz. (e.g 2412 for channel 1 in 11 g)
dataRate: 0 - 1 Mbps
1 - 2 Mbps
2 - 5.5 Mbps
3 - 11 Mbps
4 - 6 Mbps
5 - 9 Mbps
6 - 12 Mbps
7 - 18 Mbps
8 - 24 Mbps
9 - 36 Mbps
10 - 28 Mbps
11 - 54 Mbps
txPwr: twice the Tx power in dBm, actual dBm values of [5 -11] for unmod Tx,
[5-14] for mod Tx
antenna: 1 - one antenna
2 - two antenna
Note : Enable/disable continuous tx test cmd works only when target is awake.
*/
typedef enum {
TCMD_CONT_TX_OFF = 0,
TCMD_CONT_TX_SINE,
TCMD_CONT_TX_FRAME,
TCMD_CONT_TX_TX99,
TCMD_CONT_TX_TX100,
TCMD_CONT_TX_OFFSETTONE,
} TCMD_CONT_TX_MODE;
typedef enum {
TCMD_WLAN_MODE_NOHT = 0,
TCMD_WLAN_MODE_HT20 = 1,
TCMD_WLAN_MODE_HT40PLUS = 2,
TCMD_WLAN_MODE_HT40MINUS = 3,
TCMD_WLAN_MODE_CCK = 4,
TCMD_WLAN_MODE_MAX,
TCMD_WLAN_MODE_INVALID = TCMD_WLAN_MODE_MAX,
} TCMD_WLAN_MODE;
typedef enum {
TPC_TX_PWR = 0,
TPC_FORCED_GAIN,
TPC_TGT_PWR
} TPC_TYPE;
typedef PREPACK struct {
A_UINT32 testCmdId;
A_UINT32 mode;
A_UINT32 freq;
A_UINT32 dataRate;
A_INT32 txPwr;
A_UINT32 antenna;
A_UINT32 enANI;
A_UINT32 scramblerOff;
A_UINT32 aifsn;
A_UINT16 pktSz;
A_UINT16 txPattern;
A_UINT32 shortGuard;
A_UINT32 numPackets;
A_UINT32 wlanMode;
A_UINT32 tpcm;
} POSTPACK TCMD_CONT_TX;
#define TCMD_TXPATTERN_ZERONE 0x1
#define TCMD_TXPATTERN_ZERONE_DIS_SCRAMBLE 0x2
/* Continuous Rx
act: TCMD_CONT_RX_PROMIS - promiscuous mode (accept all incoming frames)
TCMD_CONT_RX_FILTER - filter mode (accept only frames with dest
address equal specified
mac address (set via act =3)
TCMD_CONT_RX_REPORT off mode (disable cont rx mode and get the
report from the last cont
Rx test)
TCMD_CONT_RX_SETMAC - set MacAddr mode (sets the MAC address for the
target. This Overrides
the default MAC address.)
*/
typedef enum {
TCMD_CONT_RX_PROMIS =0,
TCMD_CONT_RX_FILTER,
TCMD_CONT_RX_REPORT,
TCMD_CONT_RX_SETMAC,
TCMD_CONT_RX_SET_ANT_SWITCH_TABLE,
TC_CMD_RESP,
} TCMD_CONT_RX_ACT;
typedef PREPACK struct {
A_UINT32 testCmdId;
A_UINT32 act;
A_UINT32 enANI;
PREPACK union {
struct PREPACK TCMD_CONT_RX_PARA {
A_UINT32 freq;
A_UINT32 antenna;
A_UINT32 wlanMode;
} POSTPACK para;
struct PREPACK TCMD_CONT_RX_REPORT {
A_UINT32 totalPkt;
A_INT32 rssiInDBm;
A_UINT32 crcErrPkt;
A_UINT32 secErrPkt;
A_UINT16 rateCnt[TCMD_MAX_RATES];
A_UINT16 rateCntShortGuard[TCMD_MAX_RATES];
} POSTPACK report;
struct PREPACK TCMD_CONT_RX_MAC {
A_UCHAR addr[ATH_MAC_LEN];
A_UCHAR btaddr[ATH_MAC_LEN];
A_UINT16 regDmn[2];
A_UINT32 otpWriteFlag;
} POSTPACK mac;
struct PREPACK TCMD_CONT_RX_ANT_SWITCH_TABLE {
A_UINT32 antswitch1;
A_UINT32 antswitch2;
}POSTPACK antswitchtable;
} POSTPACK u;
} POSTPACK TCMD_CONT_RX;
/* Force sleep/wake test cmd
mode: TCMD_PM_WAKEUP - Wakeup the target
TCMD_PM_SLEEP - Force the target to sleep.
*/
typedef enum {
TCMD_PM_WAKEUP = 1, /* be consistent with target */
TCMD_PM_SLEEP,
TCMD_PM_DEEPSLEEP
} TCMD_PM_MODE;
typedef PREPACK struct {
A_UINT32 testCmdId;
A_UINT32 mode;
} POSTPACK TCMD_PM;
typedef enum {
TC_CMDS_VERSION_RESERVED=0,
TC_CMDS_VERSION_MDK,
TC_CMDS_VERSION_TS,
TC_CMDS_VERSION_LAST,
} TC_CMDS_VERSION;
typedef enum {
TC_CMDS_TS =0,
TC_CMDS_CAL,
TC_CMDS_TPCCAL = TC_CMDS_CAL,
TC_CMDS_TPCCAL_WITH_OTPWRITE,
TC_CMDS_OTPDUMP,
TC_CMDS_OTPSTREAMWRITE,
TC_CMDS_EFUSEDUMP,
TC_CMDS_EFUSEWRITE,
TC_CMDS_READTHERMAL,
TC_CMDS_PM_CAL,
TC_CMDS_PSAT_CAL,
TC_CMDS_PSAT_CAL_RESULT,
TC_CMDS_CAL_PWRS,
TC_CMDS_WRITE_CAL_2_OTP,
TC_CMDS_CHAR_PSAT,
TC_CMDS_CHAR_PSAT_RESULT,
TC_CMDS_PM_CAL_RESULT,
TC_CMDS_SINIT_WAIT,
TC_CMDS_SINIT_LOAD_AUTO,
TC_CMDS_COUNT
} TC_CMDS_ACT;
typedef PREPACK struct {
A_UINT32 testCmdId;
A_UINT32 act;
PREPACK union {
A_UINT32 enANI; // to be identical to CONT_RX struct
struct PREPACK {
A_UINT16 length;
A_UINT8 version;
A_UINT8 bufLen;
} POSTPACK parm;
} POSTPACK u;
} POSTPACK TC_CMDS_HDR;
typedef PREPACK struct {
TC_CMDS_HDR hdr;
A_UINT8 buf[TC_CMDS_SIZE_MAX];
} POSTPACK TC_CMDS;
typedef PREPACK struct {
A_UINT32 testCmdId;
A_UINT32 regAddr;
A_UINT32 val;
A_UINT16 flag;
} POSTPACK TCMD_SET_REG;
typedef enum {
TCMD_CONT_TX_ID,
TCMD_CONT_RX_ID,
TCMD_PM_ID,
TC_CMDS_ID,
TCMD_SET_REG_ID,
/*For synergy purpose we added the following tcmd id but these
tcmd's will not go to the firmware instead we will write values
to the NV area */
TCMD_NIC_MAC = 100,
TCMD_CAL_FILE_INDEX = 101,
} TCMD_ID;
typedef PREPACK struct
{
A_UINT32 testCmdId;
A_UINT8 mac_address[ATH_MAC_LEN];
} POSTPACK TCMD_NIC_MAC_S;
typedef PREPACK struct
{
A_UINT32 testCmdId;
A_UINT32 cal_file_index;
} POSTPACK TCMD_CAL_FILE_INDEX_S;
typedef PREPACK union {
TCMD_CONT_TX contTx;
TCMD_CONT_RX contRx;
TCMD_PM pm;
// New test cmds from ART/MDK ...
TC_CMDS tcCmds;
TCMD_SET_REG setReg;
} POSTPACK TEST_CMD;
typedef enum {
TC_MSG_RESERVED,
TC_MSG_PSAT_CAL_RESULTS,
TC_MSG_CAL_POWER,
TC_MSG_CHAR_PSAT_RESULTS,
TC_MSG_PM_CAL_RESULTS,
TC_MSG_PSAT_CAL_ACK,
TC_MSG_COUNT
} TC_MSG_ID;
typedef PREPACK struct {
A_INT8 olpcGainDelta_diff;
A_INT8 olpcGainDelta_abs;
A_UINT8 thermCalVal;
A_UINT8 numTryBF;
A_UINT32 cmac_olpc;
A_UINT32 cmac_psat;
A_UINT16 cmac_olpc_pcdac;
A_UINT16 cmac_psat_pcdac;
A_INT16 lineSlope;
A_INT16 lineVariance;
A_UINT16 psatParm;
A_UINT8 reserved[2];
} POSTPACK OLPCGAIN_THERM_DUPLET;
#if !defined(WHAL_NUM_11G_CAL_PIERS_EXT)
#define WHAL_NUM_11G_CAL_PIERS_EXT 16
#define WHAL_NUM_11A_CAL_PIERS_EXT 32
#endif
#define PSAT_WHAL_NUM_11G_CAL_PIERS_MAX 3
#define PSAT_WHAL_NUM_11A_CAL_PIERS_MAX 5
typedef PREPACK struct {
OLPCGAIN_THERM_DUPLET olpcGainTherm2G[PSAT_WHAL_NUM_11G_CAL_PIERS_MAX];
OLPCGAIN_THERM_DUPLET olpcGainTherm5G[PSAT_WHAL_NUM_11A_CAL_PIERS_MAX];
} POSTPACK PSAT_CAL_RESULTS;
#define _MAX_TX_GAIN_ENTRIES 32
typedef PREPACK struct {
A_UINT32 cmac_i[_MAX_TX_GAIN_ENTRIES];
A_UINT8 pcdac[_MAX_TX_GAIN_ENTRIES];
A_UINT8 freq;
A_UINT8 an_txrf3_rdiv2g;
A_UINT8 an_txrf3_pdpredist2g;
A_UINT8 an_rxtx2_mxrgain;
A_UINT8 an_rxrf_bias1_pwd_ic25mxr2gh;
A_UINT8 an_bias2_pwd_ic25rxrf;
A_UINT8 an_bb1_i2v_curr2x;
A_UINT8 an_txrf3_capdiv2g;
// A_UINT32 cmac_q[_MAX_TX_GAIN_ENTRIES];
} POSTPACK CHAR_PSAT_RESULTS;
typedef PREPACK struct {
A_INT16 txPwr2G_t10[WHAL_NUM_11G_CAL_PIERS_EXT];
A_INT16 txPwr5G_t10[WHAL_NUM_11A_CAL_PIERS_EXT];
} POSTPACK CAL_TXPWR;
typedef PREPACK struct {
A_UINT8 thermCalVal;
A_UINT8 future[3];
} POSTPACK PM_CAL_RESULTS;
typedef PREPACK struct {
TC_MSG_ID msgId;
PREPACK union {
PSAT_CAL_RESULTS psatCalResults;
CAL_TXPWR txPwrs;
CHAR_PSAT_RESULTS psatCharResults;
PM_CAL_RESULTS pmCalResults;
} POSTPACK msg;
} POSTPACK TC_MSG;
typedef struct _psat_sweep_table {
A_UINT8 an_txrf3_rdiv2g; // [0,3] _RDIV2G_MIN, _RDIV2G_MAX
A_UINT8 an_txrf3_pdpredist2g; // [0,1] _PDPREDIST2G_MIN, _PDPREDIST2G_MAX
A_UINT8 an_rxtx2_mxrgain; // [0,3] _MXRGAIN_MIN, _MXRGAIN_MAX
A_UINT8 an_rxrf_bias1_pwd_ic25mxr2gh; // [0,3] _PWD_IC25MX2GH_MIN, _PWD_IC25MXRGH_MAX
A_UINT8 an_bias2_pwd_ic25rxrf; // [0,3] _PWD_IC25RXRF_MIN, _PWD_RC25RXRF_MAX
A_UINT8 an_bb1_i2v_curr2x; // [0,1] _I2V_CURR2X_MIN, _I2V_CURR2X_MAX
A_UINT8 an_txrf3_capdiv2g; // [0,15] _CAPDIV2G_MIN, _CAPDIV2G_MAX
A_INT8 olpcPsatCmacDelta; // olpcPsatCmacDelta
A_UINT16 psatParm;
A_UINT16 padding2;
} PSAT_SWEEP_TABLE;
#define NUM_PSAT_CHAR_PARMS 7
#ifdef __cplusplus
}
#endif
#endif /* TESTCMD_H_ */
wlan/include/wlan_defs.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __WLAN_DEFS_H__
#define __WLAN_DEFS_H__
/*
* This file contains WLAN definitions that may be used across both
* Host and Target software.
*/
typedef enum {
MODE_11A = 0, /* 11a Mode */
MODE_11G = 1, /* 11b/g Mode */
MODE_11B = 2, /* 11b Mode */
MODE_11GONLY = 3, /* 11g only Mode */
#ifdef SUPPORT_11N
MODE_11NA_HT20 = 4, /* 11a HT20 mode */
MODE_11NG_HT20 = 5, /* 11g HT20 mode */
MODE_11NA_HT40 = 6, /* 11a HT40 mode */
MODE_11NG_HT40 = 7, /* 11g HT40 mode */
MODE_UNKNOWN = 8,
MODE_MAX = 8
#else
MODE_UNKNOWN = 4,
MODE_MAX = 4
#endif
} WLAN_PHY_MODE;
typedef enum {
WLAN_11A_CAPABILITY = 1,
WLAN_11G_CAPABILITY = 2,
WLAN_11AG_CAPABILITY = 3,
}WLAN_CAPABILITY;
#ifdef SUPPORT_11N
#ifdef SUPPORT_2SS
typedef A_UINT64 A_RATEMASK;
#else
typedef unsigned long A_RATEMASK;
#endif /* SUPPORT_2SS */
#else
typedef unsigned short A_RATEMASK;
#endif /* SUPPORT_11N */
#ifdef SUPPORT_11N
#define IS_MODE_11A(mode) (((mode) == MODE_11A) || \
((mode) == MODE_11NA_HT20) || \
((mode) == MODE_11NA_HT40))
#define IS_MODE_11B(mode) ((mode) == MODE_11B)
#define IS_MODE_11G(mode) (((mode) == MODE_11G) || \
((mode) == MODE_11GONLY) || \
((mode) == MODE_11NG_HT20) || \
((mode) == MODE_11NG_HT40))
#define IS_MODE_11GN(mode) (((mode) == MODE_11NG_HT20) || \
((mode) == MODE_11NG_HT40))
#define IS_MODE_11GONLY(mode) ((mode) == MODE_11GONLY)
#define IS_MODE_11AN(mode) (((mode) == MODE_11NA_HT20) || \
((mode) == MODE_11NA_HT40))
#define IS_MODE_11N(mode) ((IS_MODE_11GN(mode)) || (IS_MODE_11AN(mode)))
#else
#define IS_MODE_11A(mode) ((mode) == MODE_11A)
#define IS_MODE_11B(mode) ((mode) == MODE_11B)
#define IS_MODE_11G(mode) (((mode) == MODE_11G) || \
((mode) == MODE_11GONLY))
#define IS_MODE_11GONLY(mode) ((mode) == MODE_11GONLY)
#endif /* SUPPORT_11N */
#endif /* __WLANDEFS_H__ */
wlan/include/wlan_dset.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2007-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __WLAN_DSET_H__
#define __WLAN_DSET_H__
typedef PREPACK struct wow_config_dset {
A_UINT8 valid_dset;
A_UINT8 gpio_enable;
A_UINT16 gpio_pin;
} POSTPACK WOW_CONFIG_DSET;
#endif
wlan/include/wmi.h
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wlan/include/wmi_thin.h
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//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
/*
* This file contains the definitions of the WMI protocol specified in the
* Wireless Module Interface (WMI). It includes definitions of all the
* commands and events. Commands are messages from the host to the WM.
* Events and Replies are messages from the WM to the host.
*
* Ownership of correctness in regards to WMI commands
* belongs to the host driver and the WM is not required to validate
* parameters for value, proper range, or any other checking.
*
*/
#ifndef _WMI_THIN_H_
#define _WMI_THIN_H_
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
WMI_THIN_CONFIG_CMDID = 0x8000, // WMI_THIN_RESERVED_START
WMI_THIN_SET_MIB_CMDID,
WMI_THIN_GET_MIB_CMDID,
WMI_THIN_JOIN_CMDID,
WMI_THIN_CONNECT_CMDID,
WMI_THIN_RESET_CMDID,
/* add new CMDID's here */
WMI_THIN_RESERVED_END_CMDID = 0x8fff // WMI_THIN_RESERVED_END
} WMI_THIN_COMMAND_ID;
typedef enum{
TEMPLATE_FRM_FIRST = 0,
TEMPLATE_FRM_PROBE_REQ =TEMPLATE_FRM_FIRST,
TEMPLATE_FRM_BEACON,
TEMPLATE_FRM_PROBE_RESP,
TEMPLATE_FRM_NULL,
TEMPLATE_FRM_QOS_NULL,
TEMPLATE_FRM_PSPOLL,
TEMPLATE_FRM_MAX
}WMI_TEMPLATE_FRM_TYPE;
/* TEMPLATE_FRM_LEN... represent the maximum allowable
* data lengths (bytes) for each frame type */
#define TEMPLATE_FRM_LEN_PROBE_REQ (256) /* Symbian dictates a minimum of 256 for these 3 frame types */
#define TEMPLATE_FRM_LEN_BEACON (256)
#define TEMPLATE_FRM_LEN_PROBE_RESP (256)
#define TEMPLATE_FRM_LEN_NULL (32)
#define TEMPLATE_FRM_LEN_QOS_NULL (32)
#define TEMPLATE_FRM_LEN_PSPOLL (32)
#define TEMPLATE_FRM_LEN_SUM (TEMPLATE_FRM_LEN_PROBE_REQ + TEMPLATE_FRM_LEN_BEACON + TEMPLATE_FRM_LEN_PROBE_RESP + \
TEMPLATE_FRM_LEN_NULL + TEMPLATE_FRM_LEN_QOS_NULL + TEMPLATE_FRM_LEN_PSPOLL)
/* MAC Header Build Rules */
/* These values allow the host to configure the
* target code that is responsible for constructing
* the MAC header. In cases where the MAC header
* is provided by the host framework, the target
* has a diminished responsibility over what fields
* it must write. This will vary from framework to framework.
* Symbian requires different behavior from MAC80211 which
* requires different behavior from MS Native Wifi. */
#define WMI_WRT_VER_TYPE 0x00000001
#define WMI_WRT_DURATION 0x00000002
#define WMI_WRT_DIRECTION 0x00000004
#define WMI_WRT_POWER 0x00000008
#define WMI_WRT_WEP 0x00000010
#define WMI_WRT_MORE 0x00000020
#define WMI_WRT_BSSID 0x00000040
#define WMI_WRT_QOS 0x00000080
#define WMI_WRT_SEQNO 0x00000100
#define WMI_GUARD_TX 0x00000200 /* prevents TX ops that are not allowed for a current state */
#define WMI_WRT_DEFAULT_CONFIG (WMI_WRT_VER_TYPE | WMI_WRT_DURATION | WMI_WRT_DIRECTION | \
WMI_WRT_POWER | WMI_WRT_MORE | WMI_WRT_WEP | WMI_WRT_BSSID | \
WMI_WRT_QOS | WMI_WRT_SEQNO | WMI_GUARD_TX)
/* WMI_THIN_CONFIG_TXCOMPLETE -- Used to configure the params and content for
* TX Complete messages the will come from the Target. these messages are
* disabled by default but can be enabled using this structure and the
* WMI_THIN_CONFIG_CMDID. */
typedef PREPACK struct {
A_UINT8 version; /* the versioned type of messages to use or 0 to disable */
A_UINT8 countThreshold; /* msg count threshold triggering a tx complete message */
A_UINT16 timeThreshold; /* timeout interval in MSEC triggering a tx complete message */
} POSTPACK WMI_THIN_CONFIG_TXCOMPLETE;
/* WMI_THIN_CONFIG_DECRYPT_ERR -- Used to configure behavior for received frames
* that have decryption errors. The default behavior is to discard the frame
* without notification. Alternately, the MAC Header is forwarded to the host
* with the failed status. */
typedef PREPACK struct {
A_UINT8 enable; /* 1 == send decrypt errors to the host, 0 == don't */
A_UINT8 reserved[3]; /* align padding */
} POSTPACK WMI_THIN_CONFIG_DECRYPT_ERR;
/* WMI_THIN_CONFIG_TX_MAC_RULES -- Used to configure behavior for transmitted
* frames that require partial MAC header construction. These rules
* are used by the target to indicate which fields need to be written. */
typedef PREPACK struct {
A_UINT32 rules; /* combination of WMI_WRT_... values */
} POSTPACK WMI_THIN_CONFIG_TX_MAC_RULES;
/* WMI_THIN_CONFIG_RX_FILTER_RULES -- Used to configure behavior for received
* frames as to which frames should get forwarded to the host and which
* should get processed internally. */
typedef PREPACK struct {
A_UINT32 rules; /* combination of WMI_FILT_... values */
} POSTPACK WMI_THIN_CONFIG_RX_FILTER_RULES;
/* WMI_THIN_CONFIG_CIPHER_ENCAP -- Used to configure behavior for both
* TX and RX frames regarding security cipher encapsulation. The host may specify
* whether or not the firmware is responsible for cipher
* encapsulation. If the firmware is responsible it will add the security header
* and trailer for TX frames and remove the header and trailer for Rx frames. Also,
* the firmware will examine the resource counter if any and behave appropriately when
* a bad value is detected. If the host indicates responsibility for encapsulation
* then it is responsible for all aspects of encapsulation, however the device will
* still perform the encryption and decryption of the frame payload if a key has
* been provided. */
typedef PREPACK struct {
A_UINT8 enable; /* enables/disables firmware cipher encapsulation */
A_UINT8 reserved[3]; /* align padding */
} POSTPACK WMI_THIN_CONFIG_CIPHER_ENCAP;
/* WMI_THIN_CONFIG_CMD -- Used to contain some combination of the above
* WMI_THIN_CONFIG_... structures. The actual combination is indicated
* by the value of cfgField. Each bit in this field corresponds to
* one of the above structures. */
typedef PREPACK struct {
#define WMI_THIN_CFG_TXCOMP 0x00000001
#define WMI_THIN_CFG_DECRYPT 0x00000002
#define WMI_THIN_UNUSED1 0x00000004 /* used to be WMI_THIN_CFG_MAC_RULES */
#define WMI_THIN_CFG_FILTER_RULES 0x00000008
#define WMI_THIN_CFG_CIPHER_ENCAP 0x00000010
A_UINT32 cfgField; /* combination of WMI_THIN_CFG_... describes contents of config command */
A_UINT16 length; /* length in bytes of appended sub-commands */
A_UINT8 reserved[2]; /* align padding */
} POSTPACK WMI_THIN_CONFIG_CMD;
/* MIB Access Identifiers tailored for Symbian. */
enum {
MIB_ID_STA_MAC = 1, // [READONLY]
MIB_ID_RX_LIFE_TIME, // [NOT IMPLEMENTED]
MIB_ID_SLOT_TIME, // [READ/WRITE]
MIB_ID_RTS_THRESHOLD, // [READ/WRITE]
MIB_ID_CTS_TO_SELF, // [READ/WRITE]
MIB_ID_TEMPLATE_FRAME, // [WRITE ONLY]
MIB_ID_RXFRAME_FILTER, // [READ/WRITE]
MIB_ID_BEACON_FILTER_TABLE, // [WRITE ONLY]
MIB_ID_BEACON_FILTER, // [READ/WRITE]
MIB_ID_BEACON_LOST_COUNT, // [WRITE ONLY]
MIB_ID_RSSI_THRESHOLD, // [WRITE ONLY]
MIB_ID_HT_CAP, // [NOT IMPLEMENTED]
MIB_ID_HT_OP, // [NOT IMPLEMENTED]
MIB_ID_HT_2ND_BEACON, // [NOT IMPLEMENTED]
MIB_ID_HT_BLOCK_ACK, // [NOT IMPLEMENTED]
MIB_ID_PREAMBLE, // [READ/WRITE]
/*MIB_ID_GROUP_ADDR_TABLE,*/
/*MIB_ID_WEP_DEFAULT_KEY_ID */ // satisfied by wmi_addKey_cmd()
/*MIB_ID_TX_POWER */
/*MIB_ID_ARP_IP_TABLE */
/*MIB_ID_SLEEP_MODE */
/*MIB_ID_WAKE_INTERVAL*/
/*MIB_ID_STAT_TABLE*/
/*MIB_ID_IBSS_PWR_SAVE*/
/*MIB_ID_COUNTERS_TABLE*/
/*MIB_ID_ETHERTYPE_FILTER*/
/*MIB_ID_BC_UDP_FILTER*/
};
typedef PREPACK struct {
A_UINT8 addr[ATH_MAC_LEN];
} POSTPACK WMI_THIN_MIB_STA_MAC;
typedef PREPACK struct {
A_UINT32 time; // units == msec
} POSTPACK WMI_THIN_MIB_RX_LIFE_TIME;
typedef PREPACK struct {
A_UINT8 enable; //1 = on, 0 = off
} POSTPACK WMI_THIN_MIB_CTS_TO_SELF;
typedef PREPACK struct {
A_UINT32 time; // units == usec
} POSTPACK WMI_THIN_MIB_SLOT_TIME;
typedef PREPACK struct {
A_UINT16 length; //units == bytes
} POSTPACK WMI_THIN_MIB_RTS_THRESHOLD;
typedef PREPACK struct {
A_UINT8 type; // type of frame
A_UINT8 rate; // tx rate to be used (one of WMI_BIT_RATE)
A_UINT16 length; // num bytes following this structure as the template data
} POSTPACK WMI_THIN_MIB_TEMPLATE_FRAME;
typedef PREPACK struct {
#define FRAME_FILTER_PROMISCUOUS 0x00000001
#define FRAME_FILTER_BSSID 0x00000002
A_UINT32 filterMask;
} POSTPACK WMI_THIN_MIB_RXFRAME_FILTER;
#define IE_FILTER_TREATMENT_CHANGE 1
#define IE_FILTER_TREATMENT_APPEAR 2
typedef PREPACK struct {
A_UINT8 ie;
A_UINT8 treatment;
} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE;
typedef PREPACK struct {
A_UINT8 ie;
A_UINT8 treatment;
A_UINT8 oui[3];
A_UINT8 type;
A_UINT16 version;
} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE_OUI;
typedef PREPACK struct {
A_UINT16 numElements;
A_UINT8 entrySize; // sizeof(WMI_THIN_MIB_BEACON_FILTER_TABLE) on host cpu may be 2 may be 4
A_UINT8 reserved;
} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE_HEADER;
typedef PREPACK struct {
A_UINT32 count; /* num beacons between deliveries */
A_UINT8 enable;
A_UINT8 reserved[3];
} POSTPACK WMI_THIN_MIB_BEACON_FILTER;
typedef PREPACK struct {
A_UINT32 count; /* num consec lost beacons after which send event */
} POSTPACK WMI_THIN_MIB_BEACON_LOST_COUNT;
typedef PREPACK struct {
A_UINT8 rssi; /* the low threshold which can trigger an event warning */
A_UINT8 tolerance; /* the range above and below the threshold to prevent event flooding to the host. */
A_UINT8 count; /* the sample count of consecutive frames necessary to trigger an event. */
A_UINT8 reserved[1]; /* padding */
} POSTPACK WMI_THIN_MIB_RSSI_THRESHOLD;
typedef PREPACK struct {
A_UINT32 cap;
A_UINT32 rxRateField;
A_UINT32 beamForming;
A_UINT8 addr[ATH_MAC_LEN];
A_UINT8 enable;
A_UINT8 stbc;
A_UINT8 maxAMPDU;
A_UINT8 msduSpacing;
A_UINT8 mcsFeedback;
A_UINT8 antennaSelCap;
} POSTPACK WMI_THIN_MIB_HT_CAP;
typedef PREPACK struct {
A_UINT32 infoField;
A_UINT32 basicRateField;
A_UINT8 protection;
A_UINT8 secondChanneloffset;
A_UINT8 channelWidth;
A_UINT8 reserved;
} POSTPACK WMI_THIN_MIB_HT_OP;
typedef PREPACK struct {
#define SECOND_BEACON_PRIMARY 1
#define SECOND_BEACON_EITHER 2
#define SECOND_BEACON_SECONDARY 3
A_UINT8 cfg;
A_UINT8 reserved[3]; /* padding */
} POSTPACK WMI_THIN_MIB_HT_2ND_BEACON;
typedef PREPACK struct {
A_UINT8 txTIDField;
A_UINT8 rxTIDField;
A_UINT8 reserved[2]; /* padding */
} POSTPACK WMI_THIN_MIB_HT_BLOCK_ACK;
typedef PREPACK struct {
A_UINT8 enableLong; // 1 == long preamble, 0 == short preamble
A_UINT8 reserved[3];
} POSTPACK WMI_THIN_MIB_PREAMBLE;
typedef PREPACK struct {
A_UINT16 length; /* the length in bytes of the appended MIB data */
A_UINT8 mibID; /* the ID of the MIB element being set */
A_UINT8 reserved; /* align padding */
} POSTPACK WMI_THIN_SET_MIB_CMD;
typedef PREPACK struct {
A_UINT8 mibID; /* the ID of the MIB element being set */
A_UINT8 reserved[3]; /* align padding */
} POSTPACK WMI_THIN_GET_MIB_CMD;
typedef PREPACK struct {
A_UINT32 basicRateMask; /* bit mask of basic rates */
A_UINT32 beaconIntval; /* TUs */
A_UINT16 atimWindow; /* TUs */
A_UINT16 channel; /* frequency in Mhz */
A_UINT8 networkType; /* INFRA_NETWORK | ADHOC_NETWORK */
A_UINT8 ssidLength; /* 0 - 32 */
A_UINT8 probe; /* != 0 : issue probe req at start */
A_UINT8 reserved; /* alignment */
A_UCHAR ssid[WMI_MAX_SSID_LEN];
A_UINT8 bssid[ATH_MAC_LEN];
} POSTPACK WMI_THIN_JOIN_CMD;
typedef PREPACK struct {
A_UINT16 dtim; /* dtim interval in num beacons */
A_UINT16 aid; /* 80211 association ID from Assoc resp */
} POSTPACK WMI_THIN_CONNECT_CMD;
typedef PREPACK struct {
A_UINT8 reserved[4];
} POSTPACK WMI_THIN_RESET_CMD;
typedef enum {
WMI_THIN_EVENTID_RESERVED_START = 0x8000,
WMI_THIN_GET_MIB_EVENTID,
WMI_THIN_JOIN_EVENTID,
/* Add new THIN EVENTID's here */
WMI_THIN_EVENTID_RESERVED_END = 0x8fff
} WMI_THIN_EVENT_ID;
/* Possible values for WMI_THIN_JOIN_EVENT.result */
typedef enum {
WMI_THIN_JOIN_RES_SUCCESS = 0, // device has joined the network
WMI_THIN_JOIN_RES_FAIL, // device failed for unspecified reason
WMI_THIN_JOIN_RES_TIMEOUT, // device failed due to no beacon rx in time limit
WMI_THIN_JOIN_RES_BAD_PARAM, // device failed due to bad cmd param.
WMI_THIN_JOIN_RES_IBSS_START, // device started new IBSS network.
}WMI_THIN_JOIN_RESULT;
typedef PREPACK struct {
A_UINT8 result; /* the result of the join cmd. one of WMI_THIN_JOIN_RESULT */
A_UINT8 reserved[3]; /* alignment */
} POSTPACK WMI_THIN_JOIN_EVENT;
#ifdef __cplusplus
}
#endif
#endif /* _WMI_THIN_H_ */
wlan/include/wmix.h
+283
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@@ -0,0 +1,283 @@
//------------------------------------------------------------------------------
// ISC License (ISC)
//
// Copyright (c) 2004-2010, The Linux Foundation
// All rights reserved.
// Software was previously licensed under ISC license by Qualcomm Atheros, Inc.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
/*
* This file contains extensions of the WMI protocol specified in the
* Wireless Module Interface (WMI). It includes definitions of all
* extended commands and events. Extensions include useful commands
* that are not directly related to wireless activities. They may
* be hardware-specific, and they might not be supported on all
* implementations.
*
* Extended WMIX commands are encapsulated in a WMI message with
* cmd=WMI_EXTENSION_CMD.
*/
#ifndef _WMIX_H_
#define _WMIX_H_
#ifdef __cplusplus
extern "C" {
#endif
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
#include "dbglog.h"
/*
* Extended WMI commands are those that are needed during wireless
* operation, but which are not really wireless commands. This allows,
* for instance, platform-specific commands. Extended WMI commands are
* embedded in a WMI command message with WMI_COMMAND_ID=WMI_EXTENSION_CMDID.
* Extended WMI events are similarly embedded in a WMI event message with
* WMI_EVENT_ID=WMI_EXTENSION_EVENTID.
*/
typedef PREPACK struct {
A_UINT32 commandId;
} POSTPACK WMIX_CMD_HDR;
typedef enum {
WMIX_DSETOPEN_REPLY_CMDID = 0x2001,
WMIX_DSETDATA_REPLY_CMDID,
WMIX_GPIO_OUTPUT_SET_CMDID,
WMIX_GPIO_INPUT_GET_CMDID,
WMIX_GPIO_REGISTER_SET_CMDID,
WMIX_GPIO_REGISTER_GET_CMDID,
WMIX_GPIO_INTR_ACK_CMDID,
WMIX_HB_CHALLENGE_RESP_CMDID,
WMIX_DBGLOG_CFG_MODULE_CMDID,
WMIX_PROF_CFG_CMDID, /* 0x200a */
WMIX_PROF_ADDR_SET_CMDID,
WMIX_PROF_START_CMDID,
WMIX_PROF_STOP_CMDID,
WMIX_PROF_COUNT_GET_CMDID,
} WMIX_COMMAND_ID;
typedef enum {
WMIX_DSETOPENREQ_EVENTID = 0x3001,
WMIX_DSETCLOSE_EVENTID,
WMIX_DSETDATAREQ_EVENTID,
WMIX_GPIO_INTR_EVENTID,
WMIX_GPIO_DATA_EVENTID,
WMIX_GPIO_ACK_EVENTID,
WMIX_HB_CHALLENGE_RESP_EVENTID,
WMIX_DBGLOG_EVENTID,
WMIX_PROF_COUNT_EVENTID,
} WMIX_EVENT_ID;
/*
* =============DataSet support=================
*/
/*
* WMIX_DSETOPENREQ_EVENTID
* DataSet Open Request Event
*/
typedef PREPACK struct {
A_UINT32 dset_id;
A_UINT32 targ_dset_handle; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */
} POSTPACK WMIX_DSETOPENREQ_EVENT;
/*
* WMIX_DSETCLOSE_EVENTID
* DataSet Close Event
*/
typedef PREPACK struct {
A_UINT32 access_cookie;
} POSTPACK WMIX_DSETCLOSE_EVENT;
/*
* WMIX_DSETDATAREQ_EVENTID
* DataSet Data Request Event
*/
typedef PREPACK struct {
A_UINT32 access_cookie;
A_UINT32 offset;
A_UINT32 length;
A_UINT32 targ_buf; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_fn; /* echo'ed, not used by Host, */
A_UINT32 targ_reply_arg; /* echo'ed, not used by Host, */
} POSTPACK WMIX_DSETDATAREQ_EVENT;
typedef PREPACK struct {
A_UINT32 status;
A_UINT32 targ_dset_handle;
A_UINT32 targ_reply_fn;
A_UINT32 targ_reply_arg;
A_UINT32 access_cookie;
A_UINT32 size;
A_UINT32 version;
} POSTPACK WMIX_DSETOPEN_REPLY_CMD;
typedef PREPACK struct {
A_UINT32 status;
A_UINT32 targ_buf;
A_UINT32 targ_reply_fn;
A_UINT32 targ_reply_arg;
A_UINT32 length;
A_UINT8 buf[1];
} POSTPACK WMIX_DSETDATA_REPLY_CMD;
/*
* =============GPIO support=================
* NB: Some of the WMIX APIs use a 32-bit mask. On Targets that support
* more than 32 GPIO pins, those APIs only support the first 32 GPIO pins.
*/
#include "gpio.h"
/*
* Set GPIO pin output state.
* In order for output to be driven, a pin must be enabled for output.
* This can be done during initialization through the GPIO Configuration
* DataSet, or during operation with the enable_mask.
*
* If a request is made to simultaneously set/clear or set/disable or
* clear/disable or disable/enable, results are undefined.
*/
typedef PREPACK struct {
A_UINT32 set_mask; /* pins to set */
A_UINT32 clear_mask; /* pins to clear */
A_UINT32 enable_mask; /* pins to enable for output */
A_UINT32 disable_mask; /* pins to disable/tristate */
} POSTPACK WMIX_GPIO_OUTPUT_SET_CMD;
/*
* Set a GPIO register. For debug/exceptional cases.
* Values for gpioreg_id are GPIO_ID_*, defined in a
* platform-dependent header, gpio.h.
*/
typedef PREPACK struct {
A_UINT32 gpioreg_id; /* GPIO register ID */
A_UINT32 value; /* value to write */
} POSTPACK WMIX_GPIO_REGISTER_SET_CMD;
/* Get a GPIO register. For debug/exceptional cases. */
typedef PREPACK struct {
A_UINT32 gpioreg_id; /* GPIO register to read */
} POSTPACK WMIX_GPIO_REGISTER_GET_CMD;
/*
* Host acknowledges and re-arms GPIO interrupts. A single
* message should be used to acknowledge all interrupts that
* were delivered in an earlier WMIX_GPIO_INTR_EVENT message.
*/
typedef PREPACK struct {
A_UINT32 ack_mask; /* interrupts to acknowledge */
} POSTPACK WMIX_GPIO_INTR_ACK_CMD;
/*
* Target informs Host of GPIO interrupts that have ocurred since the
* last WMIX_GIPO_INTR_ACK_CMD was received. Additional information --
* the current GPIO input values is provided -- in order to support
* use of a GPIO interrupt as a Data Valid signal for other GPIO pins.
*/
typedef PREPACK struct {
A_UINT32 intr_mask; /* pending GPIO interrupts */
A_UINT32 input_values; /* recent GPIO input values */
} POSTPACK WMIX_GPIO_INTR_EVENT;
/*
* Target responds to Host's earlier WMIX_GPIO_INPUT_GET_CMDID request
* using a GPIO_DATA_EVENT with
* value set to the mask of GPIO pin inputs and
* reg_id set to GPIO_ID_NONE
*
*
* Target responds to Hosts's earlier WMIX_GPIO_REGISTER_GET_CMDID request
* using a GPIO_DATA_EVENT with
* value set to the value of the requested register and
* reg_id identifying the register (reflects the original request)
* NB: reg_id supports the future possibility of unsolicited
* WMIX_GPIO_DATA_EVENTs (for polling GPIO input), and it may
* simplify Host GPIO support.
*/
typedef PREPACK struct {
A_UINT32 value;
A_UINT32 reg_id;
} POSTPACK WMIX_GPIO_DATA_EVENT;
/*
* =============Error Detection support=================
*/
/*
* WMIX_HB_CHALLENGE_RESP_CMDID
* Heartbeat Challenge Response command
*/
typedef PREPACK struct {
A_UINT32 cookie;
A_UINT32 source;
} POSTPACK WMIX_HB_CHALLENGE_RESP_CMD;
/*
* WMIX_HB_CHALLENGE_RESP_EVENTID
* Heartbeat Challenge Response Event
*/
#define WMIX_HB_CHALLENGE_RESP_EVENT WMIX_HB_CHALLENGE_RESP_CMD
typedef PREPACK struct {
struct dbglog_config_s config;
} POSTPACK WMIX_DBGLOG_CFG_MODULE_CMD;
/*
* =============Target Profiling support=================
*/
typedef PREPACK struct {
A_UINT32 period; /* Time (in 30.5us ticks) between samples */
A_UINT32 nbins;
} POSTPACK WMIX_PROF_CFG_CMD;
typedef PREPACK struct {
A_UINT32 addr;
} POSTPACK WMIX_PROF_ADDR_SET_CMD;
/*
* Target responds to Hosts's earlier WMIX_PROF_COUNT_GET_CMDID request
* using a WMIX_PROF_COUNT_EVENT with
* addr set to the next address
* count set to the corresponding count
*/
typedef PREPACK struct {
A_UINT32 addr;
A_UINT32 count;
} POSTPACK WMIX_PROF_COUNT_EVENT;
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#ifdef __cplusplus
}
#endif
#endif /* _WMIX_H_ */