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2024-09-09 08:52:07 +00:00
commit f9cc65cfda
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kernel/include/media/Kbuild
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header-y += tavarua.h
header-y += radio-iris-commands.h
header-y += msm_camera.h
header-y += vcap_fmt.h
header-y += msm_isp.h
header-y += msm_gemini.h
header-y += msm_gestures.h
header-y += msm_mercury.h
header-y += msm_jpeg.h
header-y += msm_media_info.h
header-y += msm_vidc.h
header-y += msmb_camera.h
header-y += msm_cam_sensor.h
header-y += msmb_isp.h
header-y += msmb_ispif.h
header-y += msmb_generic_buf_mgr.h
header-y += msmb_pproc.h
kernel/include/media/adp1653.h
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/*
* include/media/adp1653.h
*
* Copyright (C) 2008--2011 Nokia Corporation
*
* Contact: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
*
* Contributors:
* Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
* Tuukka Toivonen <tuukkat76@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#ifndef ADP1653_H
#define ADP1653_H
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <linux/videodev2.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-subdev.h>
#define ADP1653_NAME "adp1653"
#define ADP1653_I2C_ADDR (0x60 >> 1)
/* Register definitions */
#define ADP1653_REG_OUT_SEL 0x00
#define ADP1653_REG_OUT_SEL_HPLED_TORCH_MIN 0x01
#define ADP1653_REG_OUT_SEL_HPLED_TORCH_MAX 0x0b
#define ADP1653_REG_OUT_SEL_HPLED_FLASH_MIN 0x0c
#define ADP1653_REG_OUT_SEL_HPLED_FLASH_MAX 0x1f
#define ADP1653_REG_OUT_SEL_HPLED_SHIFT 3
#define ADP1653_REG_OUT_SEL_ILED_MAX 0x07
#define ADP1653_REG_OUT_SEL_ILED_SHIFT 0
#define ADP1653_REG_CONFIG 0x01
#define ADP1653_REG_CONFIG_TMR_CFG (1 << 4)
#define ADP1653_REG_CONFIG_TMR_SET_MAX 0x0f
#define ADP1653_REG_CONFIG_TMR_SET_SHIFT 0
#define ADP1653_REG_SW_STROBE 0x02
#define ADP1653_REG_SW_STROBE_SW_STROBE (1 << 0)
#define ADP1653_REG_FAULT 0x03
#define ADP1653_REG_FAULT_FLT_SCP (1 << 3)
#define ADP1653_REG_FAULT_FLT_OT (1 << 2)
#define ADP1653_REG_FAULT_FLT_TMR (1 << 1)
#define ADP1653_REG_FAULT_FLT_OV (1 << 0)
#define ADP1653_INDICATOR_INTENSITY_MIN 0
#define ADP1653_INDICATOR_INTENSITY_STEP 2500
#define ADP1653_INDICATOR_INTENSITY_MAX \
(ADP1653_REG_OUT_SEL_ILED_MAX * ADP1653_INDICATOR_INTENSITY_STEP)
#define ADP1653_INDICATOR_INTENSITY_uA_TO_REG(a) \
((a) / ADP1653_INDICATOR_INTENSITY_STEP)
#define ADP1653_INDICATOR_INTENSITY_REG_TO_uA(a) \
((a) * ADP1653_INDICATOR_INTENSITY_STEP)
#define ADP1653_FLASH_INTENSITY_BASE 35
#define ADP1653_FLASH_INTENSITY_STEP 15
#define ADP1653_FLASH_INTENSITY_MIN \
(ADP1653_FLASH_INTENSITY_BASE \
+ ADP1653_REG_OUT_SEL_HPLED_FLASH_MIN * ADP1653_FLASH_INTENSITY_STEP)
#define ADP1653_FLASH_INTENSITY_MAX \
(ADP1653_FLASH_INTENSITY_MIN + \
(ADP1653_REG_OUT_SEL_HPLED_FLASH_MAX - \
ADP1653_REG_OUT_SEL_HPLED_FLASH_MIN + 1) * \
ADP1653_FLASH_INTENSITY_STEP)
#define ADP1653_FLASH_INTENSITY_mA_TO_REG(a) \
((a) < ADP1653_FLASH_INTENSITY_BASE ? 0 : \
(((a) - ADP1653_FLASH_INTENSITY_BASE) / ADP1653_FLASH_INTENSITY_STEP))
#define ADP1653_FLASH_INTENSITY_REG_TO_mA(a) \
((a) * ADP1653_FLASH_INTENSITY_STEP + ADP1653_FLASH_INTENSITY_BASE)
#define ADP1653_TORCH_INTENSITY_MIN \
(ADP1653_FLASH_INTENSITY_BASE \
+ ADP1653_REG_OUT_SEL_HPLED_TORCH_MIN * ADP1653_FLASH_INTENSITY_STEP)
#define ADP1653_TORCH_INTENSITY_MAX \
(ADP1653_TORCH_INTENSITY_MIN + \
(ADP1653_REG_OUT_SEL_HPLED_TORCH_MAX - \
ADP1653_REG_OUT_SEL_HPLED_TORCH_MIN + 1) * \
ADP1653_FLASH_INTENSITY_STEP)
struct adp1653_platform_data {
int (*power)(struct v4l2_subdev *sd, int on);
u32 max_flash_timeout; /* flash light timeout in us */
u32 max_flash_intensity; /* led intensity, flash mode */
u32 max_torch_intensity; /* led intensity, torch mode */
u32 max_indicator_intensity; /* indicator led intensity */
};
#define to_adp1653_flash(sd) container_of(sd, struct adp1653_flash, subdev)
struct adp1653_flash {
struct v4l2_subdev subdev;
struct adp1653_platform_data *platform_data;
struct v4l2_ctrl_handler ctrls;
struct v4l2_ctrl *led_mode;
struct v4l2_ctrl *flash_timeout;
struct v4l2_ctrl *flash_intensity;
struct v4l2_ctrl *torch_intensity;
struct v4l2_ctrl *indicator_intensity;
struct mutex power_lock;
int power_count;
int fault;
};
#endif /* ADP1653_H */
kernel/include/media/adv7183.h
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/*
* adv7183.h - definition for adv7183 inputs and outputs
*
* Copyright (c) 2011 Analog Devices Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _ADV7183_H_
#define _ADV7183_H_
/* ADV7183 HW inputs */
#define ADV7183_COMPOSITE0 0 /* CVBS in on AIN1 */
#define ADV7183_COMPOSITE1 1 /* CVBS in on AIN2 */
#define ADV7183_COMPOSITE2 2 /* CVBS in on AIN3 */
#define ADV7183_COMPOSITE3 3 /* CVBS in on AIN4 */
#define ADV7183_COMPOSITE4 4 /* CVBS in on AIN5 */
#define ADV7183_COMPOSITE5 5 /* CVBS in on AIN6 */
#define ADV7183_COMPOSITE6 6 /* CVBS in on AIN7 */
#define ADV7183_COMPOSITE7 7 /* CVBS in on AIN8 */
#define ADV7183_COMPOSITE8 8 /* CVBS in on AIN9 */
#define ADV7183_COMPOSITE9 9 /* CVBS in on AIN10 */
#define ADV7183_COMPOSITE10 10 /* CVBS in on AIN11 */
#define ADV7183_SVIDEO0 11 /* Y on AIN1, C on AIN4 */
#define ADV7183_SVIDEO1 12 /* Y on AIN2, C on AIN5 */
#define ADV7183_SVIDEO2 13 /* Y on AIN3, C on AIN6 */
#define ADV7183_COMPONENT0 14 /* Y on AIN1, Pr on AIN4, Pb on AIN5 */
#define ADV7183_COMPONENT1 15 /* Y on AIN2, Pr on AIN3, Pb on AIN6 */
/* ADV7183 HW outputs */
#define ADV7183_8BIT_OUT 0
#define ADV7183_16BIT_OUT 1
#endif
kernel/include/media/adv7343.h
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/*
* ADV7343 header file
*
* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed .as is. WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef ADV7343_H
#define ADV7343_H
#define ADV7343_COMPOSITE_ID (0)
#define ADV7343_COMPONENT_ID (1)
#define ADV7343_SVIDEO_ID (2)
#endif /* End of #ifndef ADV7343_H */
kernel/include/media/ak881x.h
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/*
* Header for AK8813 / AK8814 TV-ecoders from Asahi Kasei Microsystems Co., Ltd. (AKM)
*
* Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef AK881X_H
#define AK881X_H
#define AK881X_IF_MODE_MASK (3 << 0)
#define AK881X_IF_MODE_BT656 (0 << 0)
#define AK881X_IF_MODE_MASTER (1 << 0)
#define AK881X_IF_MODE_SLAVE (2 << 0)
#define AK881X_FIELD (1 << 2)
#define AK881X_COMPONENT (1 << 3)
struct ak881x_pdata {
unsigned long flags;
};
#endif
kernel/include/media/as3645a.h
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/*
* include/media/as3645a.h
*
* Copyright (C) 2008-2011 Nokia Corporation
*
* Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#ifndef __AS3645A_H__
#define __AS3645A_H__
#include <media/v4l2-subdev.h>
#define AS3645A_NAME "as3645a"
#define AS3645A_I2C_ADDR (0x60 >> 1) /* W:0x60, R:0x61 */
#define AS3645A_FLASH_TIMEOUT_MIN 100000 /* us */
#define AS3645A_FLASH_TIMEOUT_MAX 850000
#define AS3645A_FLASH_TIMEOUT_STEP 50000
#define AS3645A_FLASH_INTENSITY_MIN 200 /* mA */
#define AS3645A_FLASH_INTENSITY_MAX_1LED 500
#define AS3645A_FLASH_INTENSITY_MAX_2LEDS 400
#define AS3645A_FLASH_INTENSITY_STEP 20
#define AS3645A_TORCH_INTENSITY_MIN 20 /* mA */
#define AS3645A_TORCH_INTENSITY_MAX 160
#define AS3645A_TORCH_INTENSITY_STEP 20
#define AS3645A_INDICATOR_INTENSITY_MIN 0 /* uA */
#define AS3645A_INDICATOR_INTENSITY_MAX 10000
#define AS3645A_INDICATOR_INTENSITY_STEP 2500
/*
* as3645a_platform_data - Flash controller platform data
* @set_power: Set power callback
* @vref: VREF offset (0=0V, 1=+0.3V, 2=-0.3V, 3=+0.6V)
* @peak: Inductor peak current limit (0=1.25A, 1=1.5A, 2=1.75A, 3=2.0A)
* @ext_strobe: True if external flash strobe can be used
* @flash_max_current: Max flash current (mA, <= AS3645A_FLASH_INTENSITY_MAX)
* @torch_max_current: Max torch current (mA, >= AS3645A_TORCH_INTENSITY_MAX)
* @timeout_max: Max flash timeout (us, <= AS3645A_FLASH_TIMEOUT_MAX)
*/
struct as3645a_platform_data {
int (*set_power)(struct v4l2_subdev *subdev, int on);
unsigned int vref;
unsigned int peak;
bool ext_strobe;
/* Flash and torch currents and timeout limits */
unsigned int flash_max_current;
unsigned int torch_max_current;
unsigned int timeout_max;
};
#endif /* __AS3645A_H__ */
kernel/include/media/atmel-isi.h
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/*
* Register definitions for the Atmel Image Sensor Interface.
*
* Copyright (C) 2011 Atmel Corporation
* Josh Wu, <josh.wu@atmel.com>
*
* Based on previous work by Lars Haring, <lars.haring@atmel.com>
* and Sedji Gaouaou
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ATMEL_ISI_H__
#define __ATMEL_ISI_H__
#include <linux/types.h>
/* ISI_V2 register offsets */
#define ISI_CFG1 0x0000
#define ISI_CFG2 0x0004
#define ISI_PSIZE 0x0008
#define ISI_PDECF 0x000c
#define ISI_Y2R_SET0 0x0010
#define ISI_Y2R_SET1 0x0014
#define ISI_R2Y_SET0 0x0018
#define ISI_R2Y_SET1 0x001C
#define ISI_R2Y_SET2 0x0020
#define ISI_CTRL 0x0024
#define ISI_STATUS 0x0028
#define ISI_INTEN 0x002C
#define ISI_INTDIS 0x0030
#define ISI_INTMASK 0x0034
#define ISI_DMA_CHER 0x0038
#define ISI_DMA_CHDR 0x003C
#define ISI_DMA_CHSR 0x0040
#define ISI_DMA_P_ADDR 0x0044
#define ISI_DMA_P_CTRL 0x0048
#define ISI_DMA_P_DSCR 0x004C
#define ISI_DMA_C_ADDR 0x0050
#define ISI_DMA_C_CTRL 0x0054
#define ISI_DMA_C_DSCR 0x0058
/* Bitfields in CFG1 */
#define ISI_CFG1_HSYNC_POL_ACTIVE_LOW (1 << 2)
#define ISI_CFG1_VSYNC_POL_ACTIVE_LOW (1 << 3)
#define ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING (1 << 4)
#define ISI_CFG1_EMB_SYNC (1 << 6)
#define ISI_CFG1_CRC_SYNC (1 << 7)
/* Constants for FRATE(ISI_V2) */
#define ISI_CFG1_FRATE_CAPTURE_ALL (0 << 8)
#define ISI_CFG1_FRATE_DIV_2 (1 << 8)
#define ISI_CFG1_FRATE_DIV_3 (2 << 8)
#define ISI_CFG1_FRATE_DIV_4 (3 << 8)
#define ISI_CFG1_FRATE_DIV_5 (4 << 8)
#define ISI_CFG1_FRATE_DIV_6 (5 << 8)
#define ISI_CFG1_FRATE_DIV_7 (6 << 8)
#define ISI_CFG1_FRATE_DIV_8 (7 << 8)
#define ISI_CFG1_DISCR (1 << 11)
#define ISI_CFG1_FULL_MODE (1 << 12)
/* Bitfields in CFG2 */
#define ISI_CFG2_GRAYSCALE (1 << 13)
/* Constants for YCC_SWAP(ISI_V2) */
#define ISI_CFG2_YCC_SWAP_DEFAULT (0 << 28)
#define ISI_CFG2_YCC_SWAP_MODE_1 (1 << 28)
#define ISI_CFG2_YCC_SWAP_MODE_2 (2 << 28)
#define ISI_CFG2_YCC_SWAP_MODE_3 (3 << 28)
#define ISI_CFG2_IM_VSIZE_OFFSET 0
#define ISI_CFG2_IM_HSIZE_OFFSET 16
#define ISI_CFG2_IM_VSIZE_MASK (0x7FF << ISI_CFG2_IM_VSIZE_OFFSET)
#define ISI_CFG2_IM_HSIZE_MASK (0x7FF << ISI_CFG2_IM_HSIZE_OFFSET)
/* Bitfields in CTRL */
/* Also using in SR(ISI_V2) */
#define ISI_CTRL_EN (1 << 0)
#define ISI_CTRL_CDC (1 << 8)
/* Also using in SR/IER/IDR/IMR(ISI_V2) */
#define ISI_CTRL_DIS (1 << 1)
#define ISI_CTRL_SRST (1 << 2)
/* Bitfields in SR */
#define ISI_SR_SIP (1 << 19)
/* Also using in SR/IER/IDR/IMR */
#define ISI_SR_VSYNC (1 << 10)
#define ISI_SR_PXFR_DONE (1 << 16)
#define ISI_SR_CXFR_DONE (1 << 17)
#define ISI_SR_P_OVR (1 << 24)
#define ISI_SR_C_OVR (1 << 25)
#define ISI_SR_CRC_ERR (1 << 26)
#define ISI_SR_FR_OVR (1 << 27)
/* Bitfields in DMA_C_CTRL & in DMA_P_CTRL */
#define ISI_DMA_CTRL_FETCH (1 << 0)
#define ISI_DMA_CTRL_WB (1 << 1)
#define ISI_DMA_CTRL_IEN (1 << 2)
#define ISI_DMA_CTRL_DONE (1 << 3)
/* Bitfields in DMA_CHSR/CHER/CHDR */
#define ISI_DMA_CHSR_P_CH (1 << 0)
#define ISI_DMA_CHSR_C_CH (1 << 1)
/* Definition for isi_platform_data */
#define ISI_DATAWIDTH_8 0x01
#define ISI_DATAWIDTH_10 0x02
struct isi_platform_data {
u8 has_emb_sync;
u8 emb_crc_sync;
u8 hsync_act_low;
u8 vsync_act_low;
u8 pclk_act_falling;
u8 full_mode;
u32 data_width_flags;
/* Using for ISI_CFG1 */
u32 frate;
/* Using for ISI_MCK */
u32 mck_hz;
};
#endif /* __ATMEL_ISI_H__ */
kernel/include/media/blackfin/bfin_capture.h
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#ifndef _BFIN_CAPTURE_H_
#define _BFIN_CAPTURE_H_
#include <linux/i2c.h>
struct v4l2_input;
struct ppi_info;
struct bcap_route {
u32 input;
u32 output;
};
struct bfin_capture_config {
/* card name */
char *card_name;
/* inputs available at the sub device */
struct v4l2_input *inputs;
/* number of inputs supported */
int num_inputs;
/* routing information for each input */
struct bcap_route *routes;
/* i2c bus adapter no */
int i2c_adapter_id;
/* i2c subdevice board info */
struct i2c_board_info board_info;
/* ppi board info */
const struct ppi_info *ppi_info;
/* ppi control */
unsigned long ppi_control;
/* ppi interrupt mask */
u32 int_mask;
/* horizontal blanking clocks */
int blank_clocks;
};
#endif
kernel/include/media/blackfin/ppi.h
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/*
* Analog Devices PPI header file
*
* Copyright (c) 2011 Analog Devices Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _PPI_H_
#define _PPI_H_
#include <linux/interrupt.h>
#ifdef EPPI_EN
#define PORT_EN EPPI_EN
#define DMA32 0
#define PACK_EN PACKEN
#endif
struct ppi_if;
struct ppi_params {
int width;
int height;
int bpp;
unsigned long ppi_control;
u32 int_mask;
int blank_clocks;
};
struct ppi_ops {
int (*attach_irq)(struct ppi_if *ppi, irq_handler_t handler);
void (*detach_irq)(struct ppi_if *ppi);
int (*start)(struct ppi_if *ppi);
int (*stop)(struct ppi_if *ppi);
int (*set_params)(struct ppi_if *ppi, struct ppi_params *params);
void (*update_addr)(struct ppi_if *ppi, unsigned long addr);
};
enum ppi_type {
PPI_TYPE_PPI,
PPI_TYPE_EPPI,
};
struct ppi_info {
enum ppi_type type;
int dma_ch;
int irq_err;
void __iomem *base;
const unsigned short *pin_req;
};
struct ppi_if {
unsigned long ppi_control;
const struct ppi_ops *ops;
const struct ppi_info *info;
bool err_int;
void *priv;
};
struct ppi_if *ppi_create_instance(const struct ppi_info *info);
void ppi_delete_instance(struct ppi_if *ppi);
#endif
kernel/include/media/bt819.h
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/*
bt819.h - bt819 notifications
Copyright (C) 2009 Hans Verkuil (hverkuil@xs4all.nl)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _BT819_H_
#define _BT819_H_
#include <linux/ioctl.h>
/* v4l2_device notifications. */
/* Needed to reset the FIFO buffer when changing the input
or the video standard.
Note: these ioctls that internal to the kernel and are never called
from userspace. */
#define BT819_FIFO_RESET_LOW _IO('b', 0)
#define BT819_FIFO_RESET_HIGH _IO('b', 1)
#endif
kernel/include/media/cs5345.h
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/*
cs5345.h - definition for cs5345 inputs and outputs
Copyright (C) 2007 Hans Verkuil (hverkuil@xs4all.nl)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _CS5345_H_
#define _CS5345_H_
/* CS5345 HW inputs */
#define CS5345_IN_MIC 0
#define CS5345_IN_1 1
#define CS5345_IN_2 2
#define CS5345_IN_3 3
#define CS5345_IN_4 4
#define CS5345_IN_5 5
#define CS5345_IN_6 6
#define CS5345_MCLK_1 0x00
#define CS5345_MCLK_1_5 0x10
#define CS5345_MCLK_2 0x20
#define CS5345_MCLK_3 0x30
#define CS5345_MCLK_4 0x40
#endif
kernel/include/media/cs53l32a.h
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/*
cs53l32a.h - definition for cs53l32a inputs and outputs
Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _CS53L32A_H_
#define _CS53L32A_H_
/* There are 2 physical inputs, but the second input can be
placed in two modes, the first mode bypasses the PGA (gain),
the second goes through the PGA. Hence there are three
possible inputs to choose from. */
/* CS53L32A HW inputs */
#define CS53L32A_IN0 0
#define CS53L32A_IN1 1
#define CS53L32A_IN2 2
#endif
kernel/include/media/cx2341x.h
+295
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/*
cx23415/6/8 header containing common defines.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef CX2341X_H
#define CX2341X_H
#include <media/v4l2-ctrls.h>
enum cx2341x_port {
CX2341X_PORT_MEMORY = 0,
CX2341X_PORT_STREAMING = 1,
CX2341X_PORT_SERIAL = 2
};
enum cx2341x_cap {
CX2341X_CAP_HAS_SLICED_VBI = 1 << 0,
CX2341X_CAP_HAS_TS = 1 << 1,
CX2341X_CAP_HAS_AC3 = 1 << 2,
};
struct cx2341x_mpeg_params {
/* misc */
u32 capabilities;
enum cx2341x_port port;
u16 width;
u16 height;
u16 is_50hz;
/* stream */
enum v4l2_mpeg_stream_type stream_type;
enum v4l2_mpeg_stream_vbi_fmt stream_vbi_fmt;
u16 stream_insert_nav_packets;
/* audio */
enum v4l2_mpeg_audio_sampling_freq audio_sampling_freq;
enum v4l2_mpeg_audio_encoding audio_encoding;
enum v4l2_mpeg_audio_l2_bitrate audio_l2_bitrate;
enum v4l2_mpeg_audio_ac3_bitrate audio_ac3_bitrate;
enum v4l2_mpeg_audio_mode audio_mode;
enum v4l2_mpeg_audio_mode_extension audio_mode_extension;
enum v4l2_mpeg_audio_emphasis audio_emphasis;
enum v4l2_mpeg_audio_crc audio_crc;
u32 audio_properties;
u16 audio_mute;
/* video */
enum v4l2_mpeg_video_encoding video_encoding;
enum v4l2_mpeg_video_aspect video_aspect;
u16 video_b_frames;
u16 video_gop_size;
u16 video_gop_closure;
enum v4l2_mpeg_video_bitrate_mode video_bitrate_mode;
u32 video_bitrate;
u32 video_bitrate_peak;
u16 video_temporal_decimation;
u16 video_mute;
u32 video_mute_yuv;
/* encoding filters */
enum v4l2_mpeg_cx2341x_video_spatial_filter_mode video_spatial_filter_mode;
u16 video_spatial_filter;
enum v4l2_mpeg_cx2341x_video_luma_spatial_filter_type video_luma_spatial_filter_type;
enum v4l2_mpeg_cx2341x_video_chroma_spatial_filter_type video_chroma_spatial_filter_type;
enum v4l2_mpeg_cx2341x_video_temporal_filter_mode video_temporal_filter_mode;
u16 video_temporal_filter;
enum v4l2_mpeg_cx2341x_video_median_filter_type video_median_filter_type;
u16 video_luma_median_filter_top;
u16 video_luma_median_filter_bottom;
u16 video_chroma_median_filter_top;
u16 video_chroma_median_filter_bottom;
};
#define CX2341X_MBOX_MAX_DATA 16
extern const u32 cx2341x_mpeg_ctrls[];
typedef int (*cx2341x_mbox_func)(void *priv, u32 cmd, int in, int out,
u32 data[CX2341X_MBOX_MAX_DATA]);
int cx2341x_update(void *priv, cx2341x_mbox_func func,
const struct cx2341x_mpeg_params *old,
const struct cx2341x_mpeg_params *new);
int cx2341x_ctrl_query(const struct cx2341x_mpeg_params *params,
struct v4l2_queryctrl *qctrl);
const char * const *cx2341x_ctrl_get_menu(const struct cx2341x_mpeg_params *p, u32 id);
int cx2341x_ext_ctrls(struct cx2341x_mpeg_params *params, int busy,
struct v4l2_ext_controls *ctrls, unsigned int cmd);
void cx2341x_fill_defaults(struct cx2341x_mpeg_params *p);
void cx2341x_log_status(const struct cx2341x_mpeg_params *p, const char *prefix);
struct cx2341x_handler;
struct cx2341x_handler_ops {
/* needed for the video clock freq */
int (*s_audio_sampling_freq)(struct cx2341x_handler *hdl, u32 val);
/* needed for dualwatch */
int (*s_audio_mode)(struct cx2341x_handler *hdl, u32 val);
/* needed for setting up the video resolution */
int (*s_video_encoding)(struct cx2341x_handler *hdl, u32 val);
/* needed for setting up the sliced vbi insertion data structures */
int (*s_stream_vbi_fmt)(struct cx2341x_handler *hdl, u32 val);
};
struct cx2341x_handler {
u32 capabilities;
enum cx2341x_port port;
u16 width;
u16 height;
u16 is_50hz;
u32 audio_properties;
struct v4l2_ctrl_handler hdl;
void *priv;
cx2341x_mbox_func func;
const struct cx2341x_handler_ops *ops;
struct v4l2_ctrl *stream_vbi_fmt;
struct {
/* audio cluster */
struct v4l2_ctrl *audio_sampling_freq;
struct v4l2_ctrl *audio_encoding;
struct v4l2_ctrl *audio_l2_bitrate;
struct v4l2_ctrl *audio_mode;
struct v4l2_ctrl *audio_mode_extension;
struct v4l2_ctrl *audio_emphasis;
struct v4l2_ctrl *audio_crc;
struct v4l2_ctrl *audio_ac3_bitrate;
};
struct {
/* video gop cluster */
struct v4l2_ctrl *video_b_frames;
struct v4l2_ctrl *video_gop_size;
};
struct {
/* stream type cluster */
struct v4l2_ctrl *stream_type;
struct v4l2_ctrl *video_encoding;
struct v4l2_ctrl *video_bitrate_mode;
struct v4l2_ctrl *video_bitrate;
struct v4l2_ctrl *video_bitrate_peak;
};
struct {
/* video mute cluster */
struct v4l2_ctrl *video_mute;
struct v4l2_ctrl *video_mute_yuv;
};
struct {
/* video filter mode cluster */
struct v4l2_ctrl *video_spatial_filter_mode;
struct v4l2_ctrl *video_temporal_filter_mode;
struct v4l2_ctrl *video_median_filter_type;
};
struct {
/* video filter type cluster */
struct v4l2_ctrl *video_luma_spatial_filter_type;
struct v4l2_ctrl *video_chroma_spatial_filter_type;
};
struct {
/* video filter cluster */
struct v4l2_ctrl *video_spatial_filter;
struct v4l2_ctrl *video_temporal_filter;
};
struct {
/* video median cluster */
struct v4l2_ctrl *video_luma_median_filter_top;
struct v4l2_ctrl *video_luma_median_filter_bottom;
struct v4l2_ctrl *video_chroma_median_filter_top;
struct v4l2_ctrl *video_chroma_median_filter_bottom;
};
};
int cx2341x_handler_init(struct cx2341x_handler *cxhdl,
unsigned nr_of_controls_hint);
void cx2341x_handler_set_50hz(struct cx2341x_handler *cxhdl, int is_50hz);
int cx2341x_handler_setup(struct cx2341x_handler *cxhdl);
void cx2341x_handler_set_busy(struct cx2341x_handler *cxhdl, int busy);
/* Firmware names */
#define CX2341X_FIRM_ENC_FILENAME "v4l-cx2341x-enc.fw"
/* Decoder firmware for the cx23415 only */
#define CX2341X_FIRM_DEC_FILENAME "v4l-cx2341x-dec.fw"
/* Firmware API commands */
/* MPEG decoder API, specific to the cx23415 */
#define CX2341X_DEC_PING_FW 0x00
#define CX2341X_DEC_START_PLAYBACK 0x01
#define CX2341X_DEC_STOP_PLAYBACK 0x02
#define CX2341X_DEC_SET_PLAYBACK_SPEED 0x03
#define CX2341X_DEC_STEP_VIDEO 0x05
#define CX2341X_DEC_SET_DMA_BLOCK_SIZE 0x08
#define CX2341X_DEC_GET_XFER_INFO 0x09
#define CX2341X_DEC_GET_DMA_STATUS 0x0a
#define CX2341X_DEC_SCHED_DMA_FROM_HOST 0x0b
#define CX2341X_DEC_PAUSE_PLAYBACK 0x0d
#define CX2341X_DEC_HALT_FW 0x0e
#define CX2341X_DEC_SET_STANDARD 0x10
#define CX2341X_DEC_GET_VERSION 0x11
#define CX2341X_DEC_SET_STREAM_INPUT 0x14
#define CX2341X_DEC_GET_TIMING_INFO 0x15
#define CX2341X_DEC_SET_AUDIO_MODE 0x16
#define CX2341X_DEC_SET_EVENT_NOTIFICATION 0x17
#define CX2341X_DEC_SET_DISPLAY_BUFFERS 0x18
#define CX2341X_DEC_EXTRACT_VBI 0x19
#define CX2341X_DEC_SET_DECODER_SOURCE 0x1a
#define CX2341X_DEC_SET_PREBUFFERING 0x1e
/* MPEG encoder API */
#define CX2341X_ENC_PING_FW 0x80
#define CX2341X_ENC_START_CAPTURE 0x81
#define CX2341X_ENC_STOP_CAPTURE 0x82
#define CX2341X_ENC_SET_AUDIO_ID 0x89
#define CX2341X_ENC_SET_VIDEO_ID 0x8b
#define CX2341X_ENC_SET_PCR_ID 0x8d
#define CX2341X_ENC_SET_FRAME_RATE 0x8f
#define CX2341X_ENC_SET_FRAME_SIZE 0x91
#define CX2341X_ENC_SET_BIT_RATE 0x95
#define CX2341X_ENC_SET_GOP_PROPERTIES 0x97
#define CX2341X_ENC_SET_ASPECT_RATIO 0x99
#define CX2341X_ENC_SET_DNR_FILTER_MODE 0x9b
#define CX2341X_ENC_SET_DNR_FILTER_PROPS 0x9d
#define CX2341X_ENC_SET_CORING_LEVELS 0x9f
#define CX2341X_ENC_SET_SPATIAL_FILTER_TYPE 0xa1
#define CX2341X_ENC_SET_VBI_LINE 0xb7
#define CX2341X_ENC_SET_STREAM_TYPE 0xb9
#define CX2341X_ENC_SET_OUTPUT_PORT 0xbb
#define CX2341X_ENC_SET_AUDIO_PROPERTIES 0xbd
#define CX2341X_ENC_HALT_FW 0xc3
#define CX2341X_ENC_GET_VERSION 0xc4
#define CX2341X_ENC_SET_GOP_CLOSURE 0xc5
#define CX2341X_ENC_GET_SEQ_END 0xc6
#define CX2341X_ENC_SET_PGM_INDEX_INFO 0xc7
#define CX2341X_ENC_SET_VBI_CONFIG 0xc8
#define CX2341X_ENC_SET_DMA_BLOCK_SIZE 0xc9
#define CX2341X_ENC_GET_PREV_DMA_INFO_MB_10 0xca
#define CX2341X_ENC_GET_PREV_DMA_INFO_MB_9 0xcb
#define CX2341X_ENC_SCHED_DMA_TO_HOST 0xcc
#define CX2341X_ENC_INITIALIZE_INPUT 0xcd
#define CX2341X_ENC_SET_FRAME_DROP_RATE 0xd0
#define CX2341X_ENC_PAUSE_ENCODER 0xd2
#define CX2341X_ENC_REFRESH_INPUT 0xd3
#define CX2341X_ENC_SET_COPYRIGHT 0xd4
#define CX2341X_ENC_SET_EVENT_NOTIFICATION 0xd5
#define CX2341X_ENC_SET_NUM_VSYNC_LINES 0xd6
#define CX2341X_ENC_SET_PLACEHOLDER 0xd7
#define CX2341X_ENC_MUTE_VIDEO 0xd9
#define CX2341X_ENC_MUTE_AUDIO 0xda
#define CX2341X_ENC_SET_VERT_CROP_LINE 0xdb
#define CX2341X_ENC_MISC 0xdc
/* OSD API, specific to the cx23415 */
#define CX2341X_OSD_GET_FRAMEBUFFER 0x41
#define CX2341X_OSD_GET_PIXEL_FORMAT 0x42
#define CX2341X_OSD_SET_PIXEL_FORMAT 0x43
#define CX2341X_OSD_GET_STATE 0x44
#define CX2341X_OSD_SET_STATE 0x45
#define CX2341X_OSD_GET_OSD_COORDS 0x46
#define CX2341X_OSD_SET_OSD_COORDS 0x47
#define CX2341X_OSD_GET_SCREEN_COORDS 0x48
#define CX2341X_OSD_SET_SCREEN_COORDS 0x49
#define CX2341X_OSD_GET_GLOBAL_ALPHA 0x4a
#define CX2341X_OSD_SET_GLOBAL_ALPHA 0x4b
#define CX2341X_OSD_SET_BLEND_COORDS 0x4c
#define CX2341X_OSD_GET_FLICKER_STATE 0x4f
#define CX2341X_OSD_SET_FLICKER_STATE 0x50
#define CX2341X_OSD_BLT_COPY 0x52
#define CX2341X_OSD_BLT_FILL 0x53
#define CX2341X_OSD_BLT_TEXT 0x54
#define CX2341X_OSD_SET_FRAMEBUFFER_WINDOW 0x56
#define CX2341X_OSD_SET_CHROMA_KEY 0x60
#define CX2341X_OSD_GET_ALPHA_CONTENT_INDEX 0x61
#define CX2341X_OSD_SET_ALPHA_CONTENT_INDEX 0x62
#endif /* CX2341X_H */
kernel/include/media/cx25840.h
+188
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/*
cx25840.h - definition for cx25840/1/2/3 inputs
Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _CX25840_H_
#define _CX25840_H_
/* Note that the cx25840 driver requires that the bridge driver calls the
v4l2_subdev's init operation in order to load the driver's firmware.
Without this the audio standard detection will fail and you will
only get mono.
Since loading the firmware is often problematic when the driver is
compiled into the kernel I recommend postponing calling this function
until the first open of the video device. Another reason for
postponing it is that loading this firmware takes a long time (seconds)
due to the slow i2c bus speed. So it will speed up the boot process if
you can avoid loading the fw as long as the video device isn't used. */
enum cx25840_video_input {
/* Composite video inputs In1-In8 */
CX25840_COMPOSITE1 = 1,
CX25840_COMPOSITE2,
CX25840_COMPOSITE3,
CX25840_COMPOSITE4,
CX25840_COMPOSITE5,
CX25840_COMPOSITE6,
CX25840_COMPOSITE7,
CX25840_COMPOSITE8,
/* S-Video inputs consist of one luma input (In1-In8) ORed with one
chroma input (In5-In8) */
CX25840_SVIDEO_LUMA1 = 0x10,
CX25840_SVIDEO_LUMA2 = 0x20,
CX25840_SVIDEO_LUMA3 = 0x30,
CX25840_SVIDEO_LUMA4 = 0x40,
CX25840_SVIDEO_LUMA5 = 0x50,
CX25840_SVIDEO_LUMA6 = 0x60,
CX25840_SVIDEO_LUMA7 = 0x70,
CX25840_SVIDEO_LUMA8 = 0x80,
CX25840_SVIDEO_CHROMA4 = 0x400,
CX25840_SVIDEO_CHROMA5 = 0x500,
CX25840_SVIDEO_CHROMA6 = 0x600,
CX25840_SVIDEO_CHROMA7 = 0x700,
CX25840_SVIDEO_CHROMA8 = 0x800,
/* S-Video aliases for common luma/chroma combinations */
CX25840_SVIDEO1 = 0x510,
CX25840_SVIDEO2 = 0x620,
CX25840_SVIDEO3 = 0x730,
CX25840_SVIDEO4 = 0x840,
/* Allow frames to specify specific input configurations */
CX25840_VIN1_CH1 = 0x80000000,
CX25840_VIN2_CH1 = 0x80000001,
CX25840_VIN3_CH1 = 0x80000002,
CX25840_VIN4_CH1 = 0x80000003,
CX25840_VIN5_CH1 = 0x80000004,
CX25840_VIN6_CH1 = 0x80000005,
CX25840_VIN7_CH1 = 0x80000006,
CX25840_VIN8_CH1 = 0x80000007,
CX25840_VIN4_CH2 = 0x80000000,
CX25840_VIN5_CH2 = 0x80000010,
CX25840_VIN6_CH2 = 0x80000020,
CX25840_NONE_CH2 = 0x80000030,
CX25840_VIN7_CH3 = 0x80000000,
CX25840_VIN8_CH3 = 0x80000040,
CX25840_NONE0_CH3 = 0x80000080,
CX25840_NONE1_CH3 = 0x800000c0,
CX25840_SVIDEO_ON = 0x80000100,
CX25840_COMPONENT_ON = 0x80000200,
CX25840_DIF_ON = 0x80000400,
};
enum cx25840_audio_input {
/* Audio inputs: serial or In4-In8 */
CX25840_AUDIO_SERIAL,
CX25840_AUDIO4 = 4,
CX25840_AUDIO5,
CX25840_AUDIO6,
CX25840_AUDIO7,
CX25840_AUDIO8,
};
enum cx25840_io_pin {
CX25840_PIN_DVALID_PRGM0 = 0,
CX25840_PIN_FIELD_PRGM1,
CX25840_PIN_HRESET_PRGM2,
CX25840_PIN_VRESET_HCTL_PRGM3,
CX25840_PIN_IRQ_N_PRGM4,
CX25840_PIN_IR_TX_PRGM6,
CX25840_PIN_IR_RX_PRGM5,
CX25840_PIN_GPIO0_PRGM8,
CX25840_PIN_GPIO1_PRGM9,
CX25840_PIN_SA_SDIN, /* Alternate GP Input only */
CX25840_PIN_SA_SDOUT, /* Alternate GP Input only */
CX25840_PIN_PLL_CLK_PRGM7,
CX25840_PIN_CHIP_SEL_VIPCLK, /* Output only */
};
enum cx25840_io_pad {
/* Output pads */
CX25840_PAD_DEFAULT = 0,
CX25840_PAD_ACTIVE,
CX25840_PAD_VACTIVE,
CX25840_PAD_CBFLAG,
CX25840_PAD_VID_DATA_EXT0,
CX25840_PAD_VID_DATA_EXT1,
CX25840_PAD_GPO0,
CX25840_PAD_GPO1,
CX25840_PAD_GPO2,
CX25840_PAD_GPO3,
CX25840_PAD_IRQ_N,
CX25840_PAD_AC_SYNC,
CX25840_PAD_AC_SDOUT,
CX25840_PAD_PLL_CLK,
CX25840_PAD_VRESET,
CX25840_PAD_RESERVED,
/* Pads for PLL_CLK output only */
CX25840_PAD_XTI_X5_DLL,
CX25840_PAD_AUX_PLL,
CX25840_PAD_VID_PLL,
CX25840_PAD_XTI,
/* Input Pads */
CX25840_PAD_GPI0,
CX25840_PAD_GPI1,
CX25840_PAD_GPI2,
CX25840_PAD_GPI3,
};
enum cx25840_io_pin_strength {
CX25840_PIN_DRIVE_MEDIUM = 0,
CX25840_PIN_DRIVE_SLOW,
CX25840_PIN_DRIVE_FAST,
};
enum cx23885_io_pin {
CX23885_PIN_IR_RX_GPIO19,
CX23885_PIN_IR_TX_GPIO20,
CX23885_PIN_I2S_SDAT_GPIO21,
CX23885_PIN_I2S_WCLK_GPIO22,
CX23885_PIN_I2S_BCLK_GPIO23,
CX23885_PIN_IRQ_N_GPIO16,
};
enum cx23885_io_pad {
CX23885_PAD_IR_RX,
CX23885_PAD_GPIO19,
CX23885_PAD_IR_TX,
CX23885_PAD_GPIO20,
CX23885_PAD_I2S_SDAT,
CX23885_PAD_GPIO21,
CX23885_PAD_I2S_WCLK,
CX23885_PAD_GPIO22,
CX23885_PAD_I2S_BCLK,
CX23885_PAD_GPIO23,
CX23885_PAD_IRQ_N,
CX23885_PAD_GPIO16,
};
/* pvr150_workaround activates a workaround for a hardware bug that is
present in Hauppauge PVR-150 (and possibly PVR-500) cards that have
certain NTSC tuners (tveeprom tuner model numbers 85, 99 and 112). The
audio autodetect fails on some channels for these models and the workaround
is to select the audio standard explicitly. Many thanks to Hauppauge for
providing this information.
This platform data only needs to be supplied by the ivtv driver. */
struct cx25840_platform_data {
int pvr150_workaround;
};
#endif
kernel/include/media/davinci/ccdc_types.h
+43
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/*
* Copyright (C) 2008-2009 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
**************************************************************************/
#ifndef _CCDC_TYPES_H
#define _CCDC_TYPES_H
enum ccdc_pixfmt {
CCDC_PIXFMT_RAW,
CCDC_PIXFMT_YCBCR_16BIT,
CCDC_PIXFMT_YCBCR_8BIT
};
enum ccdc_frmfmt {
CCDC_FRMFMT_PROGRESSIVE,
CCDC_FRMFMT_INTERLACED
};
/* PIXEL ORDER IN MEMORY from LSB to MSB */
/* only applicable for 8-bit input mode */
enum ccdc_pixorder {
CCDC_PIXORDER_YCBYCR,
CCDC_PIXORDER_CBYCRY,
};
enum ccdc_buftype {
CCDC_BUFTYPE_FLD_INTERLEAVED,
CCDC_BUFTYPE_FLD_SEPARATED
};
#endif
kernel/include/media/davinci/dm355_ccdc.h
+321
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/*
* Copyright (C) 2005-2009 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _DM355_CCDC_H
#define _DM355_CCDC_H
#include <media/davinci/ccdc_types.h>
#include <media/davinci/vpfe_types.h>
/* enum for No of pixel per line to be avg. in Black Clamping */
enum ccdc_sample_length {
CCDC_SAMPLE_1PIXELS,
CCDC_SAMPLE_2PIXELS,
CCDC_SAMPLE_4PIXELS,
CCDC_SAMPLE_8PIXELS,
CCDC_SAMPLE_16PIXELS
};
/* enum for No of lines in Black Clamping */
enum ccdc_sample_line {
CCDC_SAMPLE_1LINES,
CCDC_SAMPLE_2LINES,
CCDC_SAMPLE_4LINES,
CCDC_SAMPLE_8LINES,
CCDC_SAMPLE_16LINES
};
/* enum for Alaw gama width */
enum ccdc_gamma_width {
CCDC_GAMMA_BITS_13_4,
CCDC_GAMMA_BITS_12_3,
CCDC_GAMMA_BITS_11_2,
CCDC_GAMMA_BITS_10_1,
CCDC_GAMMA_BITS_09_0
};
enum ccdc_colpats {
CCDC_RED,
CCDC_GREEN_RED,
CCDC_GREEN_BLUE,
CCDC_BLUE
};
struct ccdc_col_pat {
enum ccdc_colpats olop;
enum ccdc_colpats olep;
enum ccdc_colpats elop;
enum ccdc_colpats elep;
};
enum ccdc_datasft {
CCDC_DATA_NO_SHIFT,
CCDC_DATA_SHIFT_1BIT,
CCDC_DATA_SHIFT_2BIT,
CCDC_DATA_SHIFT_3BIT,
CCDC_DATA_SHIFT_4BIT,
CCDC_DATA_SHIFT_5BIT,
CCDC_DATA_SHIFT_6BIT
};
enum ccdc_data_size {
CCDC_DATA_16BITS,
CCDC_DATA_15BITS,
CCDC_DATA_14BITS,
CCDC_DATA_13BITS,
CCDC_DATA_12BITS,
CCDC_DATA_11BITS,
CCDC_DATA_10BITS,
CCDC_DATA_8BITS
};
enum ccdc_mfilt1 {
CCDC_NO_MEDIAN_FILTER1,
CCDC_AVERAGE_FILTER1,
CCDC_MEDIAN_FILTER1
};
enum ccdc_mfilt2 {
CCDC_NO_MEDIAN_FILTER2,
CCDC_AVERAGE_FILTER2,
CCDC_MEDIAN_FILTER2
};
/* structure for ALaw */
struct ccdc_a_law {
/* Enable/disable A-Law */
unsigned char enable;
/* Gama Width Input */
enum ccdc_gamma_width gama_wd;
};
/* structure for Black Clamping */
struct ccdc_black_clamp {
/* only if bClampEnable is TRUE */
unsigned char b_clamp_enable;
/* only if bClampEnable is TRUE */
enum ccdc_sample_length sample_pixel;
/* only if bClampEnable is TRUE */
enum ccdc_sample_line sample_ln;
/* only if bClampEnable is TRUE */
unsigned short start_pixel;
/* only if bClampEnable is FALSE */
unsigned short sgain;
unsigned short dc_sub;
};
/* structure for Black Level Compensation */
struct ccdc_black_compensation {
/* Constant value to subtract from Red component */
unsigned char r;
/* Constant value to subtract from Gr component */
unsigned char gr;
/* Constant value to subtract from Blue component */
unsigned char b;
/* Constant value to subtract from Gb component */
unsigned char gb;
};
struct ccdc_float {
int integer;
unsigned int decimal;
};
#define CCDC_CSC_COEFF_TABLE_SIZE 16
/* structure for color space converter */
struct ccdc_csc {
unsigned char enable;
/*
* S8Q5. Use 2 decimal precision, user values range from -3.00 to 3.99.
* example - to use 1.03, set integer part as 1, and decimal part as 3
* to use -1.03, set integer part as -1 and decimal part as 3
*/
struct ccdc_float coeff[CCDC_CSC_COEFF_TABLE_SIZE];
};
/* Structures for Vertical Defect Correction*/
enum ccdc_vdf_csl {
CCDC_VDF_NORMAL,
CCDC_VDF_HORZ_INTERPOL_SAT,
CCDC_VDF_HORZ_INTERPOL
};
enum ccdc_vdf_cuda {
CCDC_VDF_WHOLE_LINE_CORRECT,
CCDC_VDF_UPPER_DISABLE
};
enum ccdc_dfc_mwr {
CCDC_DFC_MWR_WRITE_COMPLETE,
CCDC_DFC_WRITE_REG
};
enum ccdc_dfc_mrd {
CCDC_DFC_READ_COMPLETE,
CCDC_DFC_READ_REG
};
enum ccdc_dfc_ma_rst {
CCDC_DFC_INCR_ADDR,
CCDC_DFC_CLR_ADDR
};
enum ccdc_dfc_mclr {
CCDC_DFC_CLEAR_COMPLETE,
CCDC_DFC_CLEAR
};
struct ccdc_dft_corr_ctl {
enum ccdc_vdf_csl vdfcsl;
enum ccdc_vdf_cuda vdfcuda;
unsigned int vdflsft;
};
struct ccdc_dft_corr_mem_ctl {
enum ccdc_dfc_mwr dfcmwr;
enum ccdc_dfc_mrd dfcmrd;
enum ccdc_dfc_ma_rst dfcmarst;
enum ccdc_dfc_mclr dfcmclr;
};
#define CCDC_DFT_TABLE_SIZE 16
/*
* Main Structure for vertical defect correction. Vertical defect
* correction can correct up to 16 defects if defects less than 16
* then pad the rest with 0
*/
struct ccdc_vertical_dft {
unsigned char ver_dft_en;
unsigned char gen_dft_en;
unsigned int saturation_ctl;
struct ccdc_dft_corr_ctl dft_corr_ctl;
struct ccdc_dft_corr_mem_ctl dft_corr_mem_ctl;
int table_size;
unsigned int dft_corr_horz[CCDC_DFT_TABLE_SIZE];
unsigned int dft_corr_vert[CCDC_DFT_TABLE_SIZE];
unsigned int dft_corr_sub1[CCDC_DFT_TABLE_SIZE];
unsigned int dft_corr_sub2[CCDC_DFT_TABLE_SIZE];
unsigned int dft_corr_sub3[CCDC_DFT_TABLE_SIZE];
};
struct ccdc_data_offset {
unsigned char horz_offset;
unsigned char vert_offset;
};
/*
* Structure for CCDC configuration parameters for raw capture mode passed
* by application
*/
struct ccdc_config_params_raw {
/* data shift to be applied before storing */
enum ccdc_datasft datasft;
/* data size value from 8 to 16 bits */
enum ccdc_data_size data_sz;
/* median filter for sdram */
enum ccdc_mfilt1 mfilt1;
enum ccdc_mfilt2 mfilt2;
/* low pass filter enable/disable */
unsigned char lpf_enable;
/* Threshold of median filter */
int med_filt_thres;
/*
* horz and vertical data offset. Appliable for defect correction
* and lsc
*/
struct ccdc_data_offset data_offset;
/* Structure for Optional A-Law */
struct ccdc_a_law alaw;
/* Structure for Optical Black Clamp */
struct ccdc_black_clamp blk_clamp;
/* Structure for Black Compensation */
struct ccdc_black_compensation blk_comp;
/* struture for vertical Defect Correction Module Configuration */
struct ccdc_vertical_dft vertical_dft;
/* structure for color space converter Module Configuration */
struct ccdc_csc csc;
/* color patters for bayer capture */
struct ccdc_col_pat col_pat_field0;
struct ccdc_col_pat col_pat_field1;
};
#ifdef __KERNEL__
#include <linux/io.h>
#define CCDC_WIN_PAL {0, 0, 720, 576}
#define CCDC_WIN_VGA {0, 0, 640, 480}
struct ccdc_params_ycbcr {
/* pixel format */
enum ccdc_pixfmt pix_fmt;
/* progressive or interlaced frame */
enum ccdc_frmfmt frm_fmt;
/* video window */
struct v4l2_rect win;
/* field id polarity */
enum vpfe_pin_pol fid_pol;
/* vertical sync polarity */
enum vpfe_pin_pol vd_pol;
/* horizontal sync polarity */
enum vpfe_pin_pol hd_pol;
/* enable BT.656 embedded sync mode */
int bt656_enable;
/* cb:y:cr:y or y:cb:y:cr in memory */
enum ccdc_pixorder pix_order;
/* interleaved or separated fields */
enum ccdc_buftype buf_type;
};
/* Gain applied to Raw Bayer data */
struct ccdc_gain {
unsigned short r_ye;
unsigned short gr_cy;
unsigned short gb_g;
unsigned short b_mg;
};
/* Structure for CCDC configuration parameters for raw capture mode */
struct ccdc_params_raw {
/* pixel format */
enum ccdc_pixfmt pix_fmt;
/* progressive or interlaced frame */
enum ccdc_frmfmt frm_fmt;
/* video window */
struct v4l2_rect win;
/* field id polarity */
enum vpfe_pin_pol fid_pol;
/* vertical sync polarity */
enum vpfe_pin_pol vd_pol;
/* horizontal sync polarity */
enum vpfe_pin_pol hd_pol;
/* interleaved or separated fields */
enum ccdc_buftype buf_type;
/* Gain values */
struct ccdc_gain gain;
/* offset */
unsigned int ccdc_offset;
/* horizontal flip enable */
unsigned char horz_flip_enable;
/*
* enable to store the image in inverse order in memory
* (bottom to top)
*/
unsigned char image_invert_enable;
/* Configurable part of raw data */
struct ccdc_config_params_raw config_params;
};
#endif
#endif /* DM355_CCDC_H */
kernel/include/media/davinci/dm644x_ccdc.h
+184
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/*
* Copyright (C) 2006-2009 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _DM644X_CCDC_H
#define _DM644X_CCDC_H
#include <media/davinci/ccdc_types.h>
#include <media/davinci/vpfe_types.h>
/* enum for No of pixel per line to be avg. in Black Clamping*/
enum ccdc_sample_length {
CCDC_SAMPLE_1PIXELS,
CCDC_SAMPLE_2PIXELS,
CCDC_SAMPLE_4PIXELS,
CCDC_SAMPLE_8PIXELS,
CCDC_SAMPLE_16PIXELS
};
/* enum for No of lines in Black Clamping */
enum ccdc_sample_line {
CCDC_SAMPLE_1LINES,
CCDC_SAMPLE_2LINES,
CCDC_SAMPLE_4LINES,
CCDC_SAMPLE_8LINES,
CCDC_SAMPLE_16LINES
};
/* enum for Alaw gama width */
enum ccdc_gama_width {
CCDC_GAMMA_BITS_15_6,
CCDC_GAMMA_BITS_14_5,
CCDC_GAMMA_BITS_13_4,
CCDC_GAMMA_BITS_12_3,
CCDC_GAMMA_BITS_11_2,
CCDC_GAMMA_BITS_10_1,
CCDC_GAMMA_BITS_09_0
};
enum ccdc_data_size {
CCDC_DATA_16BITS,
CCDC_DATA_15BITS,
CCDC_DATA_14BITS,
CCDC_DATA_13BITS,
CCDC_DATA_12BITS,
CCDC_DATA_11BITS,
CCDC_DATA_10BITS,
CCDC_DATA_8BITS
};
/* structure for ALaw */
struct ccdc_a_law {
/* Enable/disable A-Law */
unsigned char enable;
/* Gama Width Input */
enum ccdc_gama_width gama_wd;
};
/* structure for Black Clamping */
struct ccdc_black_clamp {
unsigned char enable;
/* only if bClampEnable is TRUE */
enum ccdc_sample_length sample_pixel;
/* only if bClampEnable is TRUE */
enum ccdc_sample_line sample_ln;
/* only if bClampEnable is TRUE */
unsigned short start_pixel;
/* only if bClampEnable is TRUE */
unsigned short sgain;
/* only if bClampEnable is FALSE */
unsigned short dc_sub;
};
/* structure for Black Level Compensation */
struct ccdc_black_compensation {
/* Constant value to subtract from Red component */
char r;
/* Constant value to subtract from Gr component */
char gr;
/* Constant value to subtract from Blue component */
char b;
/* Constant value to subtract from Gb component */
char gb;
};
/* structure for fault pixel correction */
struct ccdc_fault_pixel {
/* Enable or Disable fault pixel correction */
unsigned char enable;
/* Number of fault pixel */
unsigned short fp_num;
/* Address of fault pixel table */
unsigned int fpc_table_addr;
};
/* Structure for CCDC configuration parameters for raw capture mode passed
* by application
*/
struct ccdc_config_params_raw {
/* data size value from 8 to 16 bits */
enum ccdc_data_size data_sz;
/* Structure for Optional A-Law */
struct ccdc_a_law alaw;
/* Structure for Optical Black Clamp */
struct ccdc_black_clamp blk_clamp;
/* Structure for Black Compensation */
struct ccdc_black_compensation blk_comp;
/* Structure for Fault Pixel Module Configuration */
struct ccdc_fault_pixel fault_pxl;
};
#ifdef __KERNEL__
#include <linux/io.h>
/* Define to enable/disable video port */
#define FP_NUM_BYTES 4
/* Define for extra pixel/line and extra lines/frame */
#define NUM_EXTRAPIXELS 8
#define NUM_EXTRALINES 8
/* settings for commonly used video formats */
#define CCDC_WIN_PAL {0, 0, 720, 576}
/* ntsc square pixel */
#define CCDC_WIN_VGA {0, 0, (640 + NUM_EXTRAPIXELS), (480 + NUM_EXTRALINES)}
/* Structure for CCDC configuration parameters for raw capture mode */
struct ccdc_params_raw {
/* pixel format */
enum ccdc_pixfmt pix_fmt;
/* progressive or interlaced frame */
enum ccdc_frmfmt frm_fmt;
/* video window */
struct v4l2_rect win;
/* field id polarity */
enum vpfe_pin_pol fid_pol;
/* vertical sync polarity */
enum vpfe_pin_pol vd_pol;
/* horizontal sync polarity */
enum vpfe_pin_pol hd_pol;
/* interleaved or separated fields */
enum ccdc_buftype buf_type;
/*
* enable to store the image in inverse
* order in memory(bottom to top)
*/
unsigned char image_invert_enable;
/* configurable paramaters */
struct ccdc_config_params_raw config_params;
};
struct ccdc_params_ycbcr {
/* pixel format */
enum ccdc_pixfmt pix_fmt;
/* progressive or interlaced frame */
enum ccdc_frmfmt frm_fmt;
/* video window */
struct v4l2_rect win;
/* field id polarity */
enum vpfe_pin_pol fid_pol;
/* vertical sync polarity */
enum vpfe_pin_pol vd_pol;
/* horizontal sync polarity */
enum vpfe_pin_pol hd_pol;
/* enable BT.656 embedded sync mode */
int bt656_enable;
/* cb:y:cr:y or y:cb:y:cr in memory */
enum ccdc_pixorder pix_order;
/* interleaved or separated fields */
enum ccdc_buftype buf_type;
};
#endif
#endif /* _DM644X_CCDC_H */
kernel/include/media/davinci/isif.h
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/*
* Copyright (C) 2008-2009 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* isif header file
*/
#ifndef _ISIF_H
#define _ISIF_H
#include <media/davinci/ccdc_types.h>
#include <media/davinci/vpfe_types.h>
/* isif float type S8Q8/U8Q8 */
struct isif_float_8 {
/* 8 bit integer part */
__u8 integer;
/* 8 bit decimal part */
__u8 decimal;
};
/* isif float type U16Q16/S16Q16 */
struct isif_float_16 {
/* 16 bit integer part */
__u16 integer;
/* 16 bit decimal part */
__u16 decimal;
};
/************************************************************************
* Vertical Defect Correction parameters
***********************************************************************/
/* Defect Correction (DFC) table entry */
struct isif_vdfc_entry {
/* vertical position of defect */
__u16 pos_vert;
/* horizontal position of defect */
__u16 pos_horz;
/*
* Defect level of Vertical line defect position. This is subtracted
* from the data at the defect position
*/
__u8 level_at_pos;
/*
* Defect level of the pixels upper than the vertical line defect.
* This is subtracted from the data
*/
__u8 level_up_pixels;
/*
* Defect level of the pixels lower than the vertical line defect.
* This is subtracted from the data
*/
__u8 level_low_pixels;
};
#define ISIF_VDFC_TABLE_SIZE 8
struct isif_dfc {
/* enable vertical defect correction */
__u8 en;
/* Defect level subtraction. Just fed through if saturating */
#define ISIF_VDFC_NORMAL 0
/*
* Defect level subtraction. Horizontal interpolation ((i-2)+(i+2))/2
* if data saturating
*/
#define ISIF_VDFC_HORZ_INTERPOL_IF_SAT 1
/* Horizontal interpolation (((i-2)+(i+2))/2) */
#define ISIF_VDFC_HORZ_INTERPOL 2
/* one of the vertical defect correction modes above */
__u8 corr_mode;
/* 0 - whole line corrected, 1 - not pixels upper than the defect */
__u8 corr_whole_line;
#define ISIF_VDFC_NO_SHIFT 0
#define ISIF_VDFC_SHIFT_1 1
#define ISIF_VDFC_SHIFT_2 2
#define ISIF_VDFC_SHIFT_3 3
#define ISIF_VDFC_SHIFT_4 4
/*
* defect level shift value. level_at_pos, level_upper_pos,
* and level_lower_pos can be shifted up by this value. Choose
* one of the values above
*/
__u8 def_level_shift;
/* defect saturation level */
__u16 def_sat_level;
/* number of vertical defects. Max is ISIF_VDFC_TABLE_SIZE */
__u16 num_vdefects;
/* VDFC table ptr */
struct isif_vdfc_entry table[ISIF_VDFC_TABLE_SIZE];
};
struct isif_horz_bclamp {
/* Horizontal clamp disabled. Only vertical clamp value is subtracted */
#define ISIF_HORZ_BC_DISABLE 0
/*
* Horizontal clamp value is calculated and subtracted from image data
* along with vertical clamp value
*/
#define ISIF_HORZ_BC_CLAMP_CALC_ENABLED 1
/*
* Horizontal clamp value calculated from previous image is subtracted
* from image data along with vertical clamp value.
*/
#define ISIF_HORZ_BC_CLAMP_NOT_UPDATED 2
/* horizontal clamp mode. One of the values above */
__u8 mode;
/*
* pixel value limit enable.
* 0 - limit disabled
* 1 - pixel value limited to 1023
*/
__u8 clamp_pix_limit;
/* Select Most left window for bc calculation */
#define ISIF_SEL_MOST_LEFT_WIN 0
/* Select Most right window for bc calculation */
#define ISIF_SEL_MOST_RIGHT_WIN 1
/* Select most left or right window for clamp val calculation */
__u8 base_win_sel_calc;
/* Window count per color for calculation. range 1-32 */
__u8 win_count_calc;
/* Window start position - horizontal for calculation. 0 - 8191 */
__u16 win_start_h_calc;
/* Window start position - vertical for calculation 0 - 8191 */
__u16 win_start_v_calc;
#define ISIF_HORZ_BC_SZ_H_2PIXELS 0
#define ISIF_HORZ_BC_SZ_H_4PIXELS 1
#define ISIF_HORZ_BC_SZ_H_8PIXELS 2
#define ISIF_HORZ_BC_SZ_H_16PIXELS 3
/* Width of the sample window in pixels for calculation */
__u8 win_h_sz_calc;
#define ISIF_HORZ_BC_SZ_V_32PIXELS 0
#define ISIF_HORZ_BC_SZ_V_64PIXELS 1
#define ISIF_HORZ_BC_SZ_V_128PIXELS 2
#define ISIF_HORZ_BC_SZ_V_256PIXELS 3
/* Height of the sample window in pixels for calculation */
__u8 win_v_sz_calc;
};
/************************************************************************
* Black Clamp parameters
***********************************************************************/
struct isif_vert_bclamp {
/* Reset value used is the clamp value calculated */
#define ISIF_VERT_BC_USE_HORZ_CLAMP_VAL 0
/* Reset value used is reset_clamp_val configured */
#define ISIF_VERT_BC_USE_CONFIG_CLAMP_VAL 1
/* No update, previous image value is used */
#define ISIF_VERT_BC_NO_UPDATE 2
/*
* Reset value selector for vertical clamp calculation. Use one of
* the above values
*/
__u8 reset_val_sel;
/* U8Q8. Line average coefficient used in vertical clamp calculation */
__u8 line_ave_coef;
/* Height of the optical black region for calculation */
__u16 ob_v_sz_calc;
/* Optical black region start position - horizontal. 0 - 8191 */
__u16 ob_start_h;
/* Optical black region start position - vertical 0 - 8191 */
__u16 ob_start_v;
};
struct isif_black_clamp {
/*
* This offset value is added irrespective of the clamp enable status.
* S13
*/
__u16 dc_offset;
/*
* Enable black/digital clamp value to be subtracted from the image data
*/
__u8 en;
/*
* black clamp mode. same/separate clamp for 4 colors
* 0 - disable - same clamp value for all colors
* 1 - clamp value calculated separately for all colors
*/
__u8 bc_mode_color;
/* Vrtical start position for bc subtraction */
__u16 vert_start_sub;
/* Black clamp for horizontal direction */
struct isif_horz_bclamp horz;
/* Black clamp for vertical direction */
struct isif_vert_bclamp vert;
};
/*************************************************************************
** Color Space Conversion (CSC)
*************************************************************************/
#define ISIF_CSC_NUM_COEFF 16
struct isif_color_space_conv {
/* Enable color space conversion */
__u8 en;
/*
* csc coeffient table. S8Q5, M00 at index 0, M01 at index 1, and
* so forth
*/
struct isif_float_8 coeff[ISIF_CSC_NUM_COEFF];
};
/*************************************************************************
** Black Compensation parameters
*************************************************************************/
struct isif_black_comp {
/* Comp for Red */
__s8 r_comp;
/* Comp for Gr */
__s8 gr_comp;
/* Comp for Blue */
__s8 b_comp;
/* Comp for Gb */
__s8 gb_comp;
};
/*************************************************************************
** Gain parameters
*************************************************************************/
struct isif_gain {
/* Gain for Red or ye */
struct isif_float_16 r_ye;
/* Gain for Gr or cy */
struct isif_float_16 gr_cy;
/* Gain for Gb or g */
struct isif_float_16 gb_g;
/* Gain for Blue or mg */
struct isif_float_16 b_mg;
};
#define ISIF_LINEAR_TAB_SIZE 192
/*************************************************************************
** Linearization parameters
*************************************************************************/
struct isif_linearize {
/* Enable or Disable linearization of data */
__u8 en;
/* Shift value applied */
__u8 corr_shft;
/* scale factor applied U11Q10 */
struct isif_float_16 scale_fact;
/* Size of the linear table */
__u16 table[ISIF_LINEAR_TAB_SIZE];
};
/* Color patterns */
#define ISIF_RED 0
#define ISIF_GREEN_RED 1
#define ISIF_GREEN_BLUE 2
#define ISIF_BLUE 3
struct isif_col_pat {
__u8 olop;
__u8 olep;
__u8 elop;
__u8 elep;
};
/*************************************************************************
** Data formatter parameters
*************************************************************************/
struct isif_fmtplen {
/*
* number of program entries for SET0, range 1 - 16
* when fmtmode is ISIF_SPLIT, 1 - 8 when fmtmode is
* ISIF_COMBINE
*/
__u16 plen0;
/*
* number of program entries for SET1, range 1 - 16
* when fmtmode is ISIF_SPLIT, 1 - 8 when fmtmode is
* ISIF_COMBINE
*/
__u16 plen1;
/**
* number of program entries for SET2, range 1 - 16
* when fmtmode is ISIF_SPLIT, 1 - 8 when fmtmode is
* ISIF_COMBINE
*/
__u16 plen2;
/**
* number of program entries for SET3, range 1 - 16
* when fmtmode is ISIF_SPLIT, 1 - 8 when fmtmode is
* ISIF_COMBINE
*/
__u16 plen3;
};
struct isif_fmt_cfg {
#define ISIF_SPLIT 0
#define ISIF_COMBINE 1
/* Split or combine or line alternate */
__u8 fmtmode;
/* enable or disable line alternating mode */
__u8 ln_alter_en;
#define ISIF_1LINE 0
#define ISIF_2LINES 1
#define ISIF_3LINES 2
#define ISIF_4LINES 3
/* Split/combine line number */
__u8 lnum;
/* Address increment Range 1 - 16 */
__u8 addrinc;
};
struct isif_fmt_addr_ptr {
/* Initial address */
__u32 init_addr;
/* output line number */
#define ISIF_1STLINE 0
#define ISIF_2NDLINE 1
#define ISIF_3RDLINE 2
#define ISIF_4THLINE 3
__u8 out_line;
};
struct isif_fmtpgm_ap {
/* program address pointer */
__u8 pgm_aptr;
/* program address increment or decrement */
__u8 pgmupdt;
};
struct isif_data_formatter {
/* Enable/Disable data formatter */
__u8 en;
/* data formatter configuration */
struct isif_fmt_cfg cfg;
/* Formatter program entries length */
struct isif_fmtplen plen;
/* first pixel in a line fed to formatter */
__u16 fmtrlen;
/* HD interval for output line. Only valid when split line */
__u16 fmthcnt;
/* formatter address pointers */
struct isif_fmt_addr_ptr fmtaddr_ptr[16];
/* program enable/disable */
__u8 pgm_en[32];
/* program address pointers */
struct isif_fmtpgm_ap fmtpgm_ap[32];
};
struct isif_df_csc {
/* Color Space Conversion confguration, 0 - csc, 1 - df */
__u8 df_or_csc;
/* csc configuration valid if df_or_csc is 0 */
struct isif_color_space_conv csc;
/* data formatter configuration valid if df_or_csc is 1 */
struct isif_data_formatter df;
/* start pixel in a line at the input */
__u32 start_pix;
/* number of pixels in input line */
__u32 num_pixels;
/* start line at the input */
__u32 start_line;
/* number of lines at the input */
__u32 num_lines;
};
struct isif_gain_offsets_adj {
/* Gain adjustment per color */
struct isif_gain gain;
/* Offset adjustment */
__u16 offset;
/* Enable or Disable Gain adjustment for SDRAM data */
__u8 gain_sdram_en;
/* Enable or Disable Gain adjustment for IPIPE data */
__u8 gain_ipipe_en;
/* Enable or Disable Gain adjustment for H3A data */
__u8 gain_h3a_en;
/* Enable or Disable Gain adjustment for SDRAM data */
__u8 offset_sdram_en;
/* Enable or Disable Gain adjustment for IPIPE data */
__u8 offset_ipipe_en;
/* Enable or Disable Gain adjustment for H3A data */
__u8 offset_h3a_en;
};
struct isif_cul {
/* Horizontal Cull pattern for odd lines */
__u8 hcpat_odd;
/* Horizontal Cull pattern for even lines */
__u8 hcpat_even;
/* Vertical Cull pattern */
__u8 vcpat;
/* Enable or disable lpf. Apply when cull is enabled */
__u8 en_lpf;
};
struct isif_compress {
#define ISIF_ALAW 0
#define ISIF_DPCM 1
#define ISIF_NO_COMPRESSION 2
/* Compression Algorithm used */
__u8 alg;
/* Choose Predictor1 for DPCM compression */
#define ISIF_DPCM_PRED1 0
/* Choose Predictor2 for DPCM compression */
#define ISIF_DPCM_PRED2 1
/* Predictor for DPCM compression */
__u8 pred;
};
/* all the stuff in this struct will be provided by userland */
struct isif_config_params_raw {
/* Linearization parameters for image sensor data input */
struct isif_linearize linearize;
/* Data formatter or CSC */
struct isif_df_csc df_csc;
/* Defect Pixel Correction (DFC) confguration */
struct isif_dfc dfc;
/* Black/Digital Clamp configuration */
struct isif_black_clamp bclamp;
/* Gain, offset adjustments */
struct isif_gain_offsets_adj gain_offset;
/* Culling */
struct isif_cul culling;
/* A-Law and DPCM compression options */
struct isif_compress compress;
/* horizontal offset for Gain/LSC/DFC */
__u16 horz_offset;
/* vertical offset for Gain/LSC/DFC */
__u16 vert_offset;
/* color pattern for field 0 */
struct isif_col_pat col_pat_field0;
/* color pattern for field 1 */
struct isif_col_pat col_pat_field1;
#define ISIF_NO_SHIFT 0
#define ISIF_1BIT_SHIFT 1
#define ISIF_2BIT_SHIFT 2
#define ISIF_3BIT_SHIFT 3
#define ISIF_4BIT_SHIFT 4
#define ISIF_5BIT_SHIFT 5
#define ISIF_6BIT_SHIFT 6
/* Data shift applied before storing to SDRAM */
__u8 data_shift;
/* enable input test pattern generation */
__u8 test_pat_gen;
};
#ifdef __KERNEL__
struct isif_ycbcr_config {
/* isif pixel format */
enum ccdc_pixfmt pix_fmt;
/* isif frame format */
enum ccdc_frmfmt frm_fmt;
/* ISIF crop window */
struct v4l2_rect win;
/* field polarity */
enum vpfe_pin_pol fid_pol;
/* interface VD polarity */
enum vpfe_pin_pol vd_pol;
/* interface HD polarity */
enum vpfe_pin_pol hd_pol;
/* isif pix order. Only used for ycbcr capture */
enum ccdc_pixorder pix_order;
/* isif buffer type. Only used for ycbcr capture */
enum ccdc_buftype buf_type;
};
/* MSB of image data connected to sensor port */
enum isif_data_msb {
ISIF_BIT_MSB_15,
ISIF_BIT_MSB_14,
ISIF_BIT_MSB_13,
ISIF_BIT_MSB_12,
ISIF_BIT_MSB_11,
ISIF_BIT_MSB_10,
ISIF_BIT_MSB_9,
ISIF_BIT_MSB_8,
ISIF_BIT_MSB_7
};
enum isif_cfa_pattern {
ISIF_CFA_PAT_MOSAIC,
ISIF_CFA_PAT_STRIPE
};
struct isif_params_raw {
/* isif pixel format */
enum ccdc_pixfmt pix_fmt;
/* isif frame format */
enum ccdc_frmfmt frm_fmt;
/* video window */
struct v4l2_rect win;
/* field polarity */
enum vpfe_pin_pol fid_pol;
/* interface VD polarity */
enum vpfe_pin_pol vd_pol;
/* interface HD polarity */
enum vpfe_pin_pol hd_pol;
/* buffer type. Applicable for interlaced mode */
enum ccdc_buftype buf_type;
/* Gain values */
struct isif_gain gain;
/* cfa pattern */
enum isif_cfa_pattern cfa_pat;
/* Data MSB position */
enum isif_data_msb data_msb;
/* Enable horizontal flip */
unsigned char horz_flip_en;
/* Enable image invert vertically */
unsigned char image_invert_en;
/* all the userland defined stuff*/
struct isif_config_params_raw config_params;
};
enum isif_data_pack {
ISIF_PACK_16BIT,
ISIF_PACK_12BIT,
ISIF_PACK_8BIT
};
#define ISIF_WIN_NTSC {0, 0, 720, 480}
#define ISIF_WIN_VGA {0, 0, 640, 480}
#endif
#endif
kernel/include/media/davinci/vpbe.h
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/*
* Copyright (C) 2010 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation version 2.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _VPBE_H
#define _VPBE_H
#include <linux/videodev2.h>
#include <linux/i2c.h>
#include <media/v4l2-dev.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-device.h>
#include <media/davinci/vpbe_osd.h>
#include <media/davinci/vpbe_venc.h>
#include <media/davinci/vpbe_types.h>
/* OSD configuration info */
struct osd_config_info {
char module_name[32];
};
struct vpbe_output {
struct v4l2_output output;
/*
* If output capabilities include dv_preset, list supported presets
* below
*/
char *subdev_name;
/*
* defualt_mode identifies the default timings set at the venc or
* external encoder.
*/
char *default_mode;
/*
* Fields below are used for supporting multiple modes. For example,
* LCD panel might support different modes and they are listed here.
* Similarly for supporting external encoders, lcd controller port
* requires a set of non-standard timing values to be listed here for
* each supported mode since venc is used in non-standard timing mode
* for interfacing with external encoder similar to configuring lcd
* panel timings
*/
unsigned int num_modes;
struct vpbe_enc_mode_info *modes;
/*
* Bus configuration goes here for external encoders. Some encoders
* may require multiple interface types for each of the output. For
* example, SD modes would use YCC8 where as HD mode would use YCC16.
* Not sure if this is needed on a per mode basis instead of per
* output basis. If per mode is needed, we may have to move this to
* mode_info structure
*/
enum v4l2_mbus_pixelcode if_params;
};
/* encoder configuration info */
struct encoder_config_info {
char module_name[32];
/* Is this an i2c device ? */
unsigned int is_i2c:1;
/* i2c subdevice board info */
struct i2c_board_info board_info;
};
/*amplifier configuration info */
struct amp_config_info {
char module_name[32];
/* Is this an i2c device ? */
unsigned int is_i2c:1;
/* i2c subdevice board info */
struct i2c_board_info board_info;
};
/* structure for defining vpbe display subsystem components */
struct vpbe_config {
char module_name[32];
/* i2c bus adapter no */
int i2c_adapter_id;
struct osd_config_info osd;
struct encoder_config_info venc;
/* external encoder information goes here */
int num_ext_encoders;
struct encoder_config_info *ext_encoders;
/* amplifier information goes here */
struct amp_config_info *amp;
int num_outputs;
/* Order is venc outputs followed by LCD and then external encoders */
struct vpbe_output *outputs;
};
struct vpbe_device;
struct vpbe_device_ops {
/* crop cap for the display */
int (*g_cropcap)(struct vpbe_device *vpbe_dev,
struct v4l2_cropcap *cropcap);
/* Enumerate the outputs */
int (*enum_outputs)(struct vpbe_device *vpbe_dev,
struct v4l2_output *output);
/* Set output to the given index */
int (*set_output)(struct vpbe_device *vpbe_dev,
int index);
/* Get current output */
unsigned int (*get_output)(struct vpbe_device *vpbe_dev);
/* Set DV preset at current output */
int (*s_dv_preset)(struct vpbe_device *vpbe_dev,
struct v4l2_dv_preset *dv_preset);
/* Get DV presets supported at the output */
int (*g_dv_preset)(struct vpbe_device *vpbe_dev,
struct v4l2_dv_preset *dv_preset);
/* Enumerate the DV Presets supported at the output */
int (*enum_dv_presets)(struct vpbe_device *vpbe_dev,
struct v4l2_dv_enum_preset *preset_info);
/* Set std at the output */
int (*s_std)(struct vpbe_device *vpbe_dev, v4l2_std_id *std_id);
/* Get the current std at the output */
int (*g_std)(struct vpbe_device *vpbe_dev, v4l2_std_id *std_id);
/* initialize the device */
int (*initialize)(struct device *dev, struct vpbe_device *vpbe_dev);
/* De-initialize the device */
void (*deinitialize)(struct device *dev, struct vpbe_device *vpbe_dev);
/* Get the current mode info */
int (*get_mode_info)(struct vpbe_device *vpbe_dev,
struct vpbe_enc_mode_info*);
/*
* Set the current mode in the encoder. Alternate way of setting
* standard or DV preset or custom timings in the encoder
*/
int (*set_mode)(struct vpbe_device *vpbe_dev,
struct vpbe_enc_mode_info*);
/* Power management operations */
int (*suspend)(struct vpbe_device *vpbe_dev);
int (*resume)(struct vpbe_device *vpbe_dev);
};
/* struct for vpbe device */
struct vpbe_device {
/* V4l2 device */
struct v4l2_device v4l2_dev;
/* vpbe dispay controller cfg */
struct vpbe_config *cfg;
/* parent device */
struct device *pdev;
/* external encoder v4l2 sub devices */
struct v4l2_subdev **encoders;
/* current encoder index */
int current_sd_index;
/* external amplifier v4l2 subdevice */
struct v4l2_subdev *amp;
struct mutex lock;
/* device initialized */
int initialized;
/* vpbe dac clock */
struct clk *dac_clk;
/* osd_device pointer */
struct osd_state *osd_device;
/* venc device pointer */
struct venc_platform_data *venc_device;
/*
* fields below are accessed by users of vpbe_device. Not the
* ones above
*/
/* current output */
int current_out_index;
/* lock used by caller to do atomic operation on vpbe device */
/* current timings set in the controller */
struct vpbe_enc_mode_info current_timings;
/* venc sub device */
struct v4l2_subdev *venc;
/* device operations below */
struct vpbe_device_ops ops;
};
#endif
kernel/include/media/davinci/vpbe_display.h
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/*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef VPBE_DISPLAY_H
#define VPBE_DISPLAY_H
/* Header files */
#include <linux/videodev2.h>
#include <media/v4l2-common.h>
#include <media/videobuf-dma-contig.h>
#include <media/davinci/vpbe_types.h>
#include <media/davinci/vpbe_osd.h>
#include <media/davinci/vpbe.h>
#define VPBE_DISPLAY_MAX_DEVICES 2
enum vpbe_display_device_id {
VPBE_DISPLAY_DEVICE_0,
VPBE_DISPLAY_DEVICE_1
};
#define VPBE_DISPLAY_DRV_NAME "vpbe-display"
#define VPBE_DISPLAY_MAJOR_RELEASE 1
#define VPBE_DISPLAY_MINOR_RELEASE 0
#define VPBE_DISPLAY_BUILD 1
#define VPBE_DISPLAY_VERSION_CODE ((VPBE_DISPLAY_MAJOR_RELEASE << 16) | \
(VPBE_DISPLAY_MINOR_RELEASE << 8) | \
VPBE_DISPLAY_BUILD)
#define VPBE_DISPLAY_VALID_FIELD(field) ((V4L2_FIELD_NONE == field) || \
(V4L2_FIELD_ANY == field) || (V4L2_FIELD_INTERLACED == field))
/* Exp ratio numerator and denominator constants */
#define VPBE_DISPLAY_H_EXP_RATIO_N 9
#define VPBE_DISPLAY_H_EXP_RATIO_D 8
#define VPBE_DISPLAY_V_EXP_RATIO_N 6
#define VPBE_DISPLAY_V_EXP_RATIO_D 5
/* Zoom multiplication factor */
#define VPBE_DISPLAY_ZOOM_4X 4
#define VPBE_DISPLAY_ZOOM_2X 2
/* Structures */
struct display_layer_info {
int enable;
/* Layer ID used by Display Manager */
enum osd_layer id;
struct osd_layer_config config;
enum osd_zoom_factor h_zoom;
enum osd_zoom_factor v_zoom;
enum osd_h_exp_ratio h_exp;
enum osd_v_exp_ratio v_exp;
};
/* vpbe display object structure */
struct vpbe_layer {
/* number of buffers in fbuffers */
unsigned int numbuffers;
/* Pointer to the vpbe_display */
struct vpbe_display *disp_dev;
/* Pointer pointing to current v4l2_buffer */
struct videobuf_buffer *cur_frm;
/* Pointer pointing to next v4l2_buffer */
struct videobuf_buffer *next_frm;
/* videobuf specific parameters
* Buffer queue used in video-buf
*/
struct videobuf_queue buffer_queue;
/* Queue of filled frames */
struct list_head dma_queue;
/* Used in video-buf */
spinlock_t irqlock;
/* V4l2 specific parameters */
/* Identifies video device for this layer */
struct video_device video_dev;
/* This field keeps track of type of buffer exchange mechanism user
* has selected
*/
enum v4l2_memory memory;
/* Used to keep track of state of the priority */
struct v4l2_prio_state prio;
/* Used to store pixel format */
struct v4l2_pix_format pix_fmt;
enum v4l2_field buf_field;
/* Video layer configuration params */
struct display_layer_info layer_info;
/* vpbe specific parameters
* enable window for display
*/
unsigned char window_enable;
/* number of open instances of the layer */
unsigned int usrs;
/* number of users performing IO */
unsigned int io_usrs;
/* Indicates id of the field which is being displayed */
unsigned int field_id;
/* Indicates whether streaming started */
unsigned char started;
/* Identifies device object */
enum vpbe_display_device_id device_id;
/* facilitation of ioctl ops lock by v4l2*/
struct mutex opslock;
u8 layer_first_int;
};
/* vpbe device structure */
struct vpbe_display {
/* layer specific parameters */
/* lock for isr updates to buf layers*/
spinlock_t dma_queue_lock;
/* C-Plane offset from start of y-plane */
unsigned int cbcr_ofst;
struct vpbe_layer *dev[VPBE_DISPLAY_MAX_DEVICES];
struct vpbe_device *vpbe_dev;
struct osd_state *osd_device;
};
/* File handle structure */
struct vpbe_fh {
/* vpbe device structure */
struct vpbe_display *disp_dev;
/* pointer to layer object for opened device */
struct vpbe_layer *layer;
/* Indicates whether this file handle is doing IO */
unsigned char io_allowed;
/* Used to keep track priority of this instance */
enum v4l2_priority prio;
};
struct buf_config_params {
unsigned char min_numbuffers;
unsigned char numbuffers[VPBE_DISPLAY_MAX_DEVICES];
unsigned int min_bufsize[VPBE_DISPLAY_MAX_DEVICES];
unsigned int layer_bufsize[VPBE_DISPLAY_MAX_DEVICES];
};
#endif /* VPBE_DISPLAY_H */
kernel/include/media/davinci/vpbe_osd.h
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/*
* Copyright (C) 2007-2009 Texas Instruments Inc
* Copyright (C) 2007 MontaVista Software, Inc.
*
* Andy Lowe (alowe@mvista.com), MontaVista Software
* - Initial version
* Murali Karicheri (mkaricheri@gmail.com), Texas Instruments Ltd.
* - ported to sub device interface
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation version 2..
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef _OSD_H
#define _OSD_H
#include <media/davinci/vpbe_types.h>
#define VPBE_OSD_SUBDEV_NAME "vpbe-osd"
/**
* enum osd_layer
* @WIN_OSD0: On-Screen Display Window 0
* @WIN_VID0: Video Window 0
* @WIN_OSD1: On-Screen Display Window 1
* @WIN_VID1: Video Window 1
*
* Description:
* An enumeration of the osd display layers.
*/
enum osd_layer {
WIN_OSD0,
WIN_VID0,
WIN_OSD1,
WIN_VID1,
};
/**
* enum osd_win_layer
* @OSDWIN_OSD0: On-Screen Display Window 0
* @OSDWIN_OSD1: On-Screen Display Window 1
*
* Description:
* An enumeration of the OSD Window layers.
*/
enum osd_win_layer {
OSDWIN_OSD0,
OSDWIN_OSD1,
};
/**
* enum osd_pix_format
* @PIXFMT_1BPP: 1-bit-per-pixel bitmap
* @PIXFMT_2BPP: 2-bits-per-pixel bitmap
* @PIXFMT_4BPP: 4-bits-per-pixel bitmap
* @PIXFMT_8BPP: 8-bits-per-pixel bitmap
* @PIXFMT_RGB565: 16-bits-per-pixel RGB565
* @PIXFMT_YCbCrI: YUV 4:2:2
* @PIXFMT_RGB888: 24-bits-per-pixel RGB888
* @PIXFMT_YCrCbI: YUV 4:2:2 with chroma swap
* @PIXFMT_NV12: YUV 4:2:0 planar
* @PIXFMT_OSD_ATTR: OSD Attribute Window pixel format (4bpp)
*
* Description:
* An enumeration of the DaVinci pixel formats.
*/
enum osd_pix_format {
PIXFMT_1BPP = 0,
PIXFMT_2BPP,
PIXFMT_4BPP,
PIXFMT_8BPP,
PIXFMT_RGB565,
PIXFMT_YCbCrI,
PIXFMT_RGB888,
PIXFMT_YCrCbI,
PIXFMT_NV12,
PIXFMT_OSD_ATTR,
};
/**
* enum osd_h_exp_ratio
* @H_EXP_OFF: no expansion (1/1)
* @H_EXP_9_OVER_8: 9/8 expansion ratio
* @H_EXP_3_OVER_2: 3/2 expansion ratio
*
* Description:
* An enumeration of the available horizontal expansion ratios.
*/
enum osd_h_exp_ratio {
H_EXP_OFF,
H_EXP_9_OVER_8,
H_EXP_3_OVER_2,
};
/**
* enum osd_v_exp_ratio
* @V_EXP_OFF: no expansion (1/1)
* @V_EXP_6_OVER_5: 6/5 expansion ratio
*
* Description:
* An enumeration of the available vertical expansion ratios.
*/
enum osd_v_exp_ratio {
V_EXP_OFF,
V_EXP_6_OVER_5,
};
/**
* enum osd_zoom_factor
* @ZOOM_X1: no zoom (x1)
* @ZOOM_X2: x2 zoom
* @ZOOM_X4: x4 zoom
*
* Description:
* An enumeration of the available zoom factors.
*/
enum osd_zoom_factor {
ZOOM_X1,
ZOOM_X2,
ZOOM_X4,
};
/**
* enum osd_clut
* @ROM_CLUT: ROM CLUT
* @RAM_CLUT: RAM CLUT
*
* Description:
* An enumeration of the available Color Lookup Tables (CLUTs).
*/
enum osd_clut {
ROM_CLUT,
RAM_CLUT,
};
/**
* enum osd_rom_clut
* @ROM_CLUT0: Macintosh CLUT
* @ROM_CLUT1: CLUT from DM270 and prior devices
*
* Description:
* An enumeration of the ROM Color Lookup Table (CLUT) options.
*/
enum osd_rom_clut {
ROM_CLUT0,
ROM_CLUT1,
};
/**
* enum osd_blending_factor
* @OSD_0_VID_8: OSD pixels are fully transparent
* @OSD_1_VID_7: OSD pixels contribute 1/8, video pixels contribute 7/8
* @OSD_2_VID_6: OSD pixels contribute 2/8, video pixels contribute 6/8
* @OSD_3_VID_5: OSD pixels contribute 3/8, video pixels contribute 5/8
* @OSD_4_VID_4: OSD pixels contribute 4/8, video pixels contribute 4/8
* @OSD_5_VID_3: OSD pixels contribute 5/8, video pixels contribute 3/8
* @OSD_6_VID_2: OSD pixels contribute 6/8, video pixels contribute 2/8
* @OSD_8_VID_0: OSD pixels are fully opaque
*
* Description:
* An enumeration of the DaVinci pixel blending factor options.
*/
enum osd_blending_factor {
OSD_0_VID_8,
OSD_1_VID_7,
OSD_2_VID_6,
OSD_3_VID_5,
OSD_4_VID_4,
OSD_5_VID_3,
OSD_6_VID_2,
OSD_8_VID_0,
};
/**
* enum osd_blink_interval
* @BLINK_X1: blink interval is 1 vertical refresh cycle
* @BLINK_X2: blink interval is 2 vertical refresh cycles
* @BLINK_X3: blink interval is 3 vertical refresh cycles
* @BLINK_X4: blink interval is 4 vertical refresh cycles
*
* Description:
* An enumeration of the DaVinci pixel blinking interval options.
*/
enum osd_blink_interval {
BLINK_X1,
BLINK_X2,
BLINK_X3,
BLINK_X4,
};
/**
* enum osd_cursor_h_width
* @H_WIDTH_1: horizontal line width is 1 pixel
* @H_WIDTH_4: horizontal line width is 4 pixels
* @H_WIDTH_8: horizontal line width is 8 pixels
* @H_WIDTH_12: horizontal line width is 12 pixels
* @H_WIDTH_16: horizontal line width is 16 pixels
* @H_WIDTH_20: horizontal line width is 20 pixels
* @H_WIDTH_24: horizontal line width is 24 pixels
* @H_WIDTH_28: horizontal line width is 28 pixels
*/
enum osd_cursor_h_width {
H_WIDTH_1,
H_WIDTH_4,
H_WIDTH_8,
H_WIDTH_12,
H_WIDTH_16,
H_WIDTH_20,
H_WIDTH_24,
H_WIDTH_28,
};
/**
* enum davinci_cursor_v_width
* @V_WIDTH_1: vertical line width is 1 line
* @V_WIDTH_2: vertical line width is 2 lines
* @V_WIDTH_4: vertical line width is 4 lines
* @V_WIDTH_6: vertical line width is 6 lines
* @V_WIDTH_8: vertical line width is 8 lines
* @V_WIDTH_10: vertical line width is 10 lines
* @V_WIDTH_12: vertical line width is 12 lines
* @V_WIDTH_14: vertical line width is 14 lines
*/
enum osd_cursor_v_width {
V_WIDTH_1,
V_WIDTH_2,
V_WIDTH_4,
V_WIDTH_6,
V_WIDTH_8,
V_WIDTH_10,
V_WIDTH_12,
V_WIDTH_14,
};
/**
* struct osd_cursor_config
* @xsize: horizontal size in pixels
* @ysize: vertical size in lines
* @xpos: horizontal offset in pixels from the left edge of the display
* @ypos: vertical offset in lines from the top of the display
* @interlaced: Non-zero if the display is interlaced, or zero otherwise
* @h_width: horizontal line width
* @v_width: vertical line width
* @clut: the CLUT selector (ROM or RAM) for the cursor color
* @clut_index: an index into the CLUT for the cursor color
*
* Description:
* A structure describing the configuration parameters of the hardware
* rectangular cursor.
*/
struct osd_cursor_config {
unsigned xsize;
unsigned ysize;
unsigned xpos;
unsigned ypos;
int interlaced;
enum osd_cursor_h_width h_width;
enum osd_cursor_v_width v_width;
enum osd_clut clut;
unsigned char clut_index;
};
/**
* struct osd_layer_config
* @pixfmt: pixel format
* @line_length: offset in bytes between start of each line in memory
* @xsize: number of horizontal pixels displayed per line
* @ysize: number of lines displayed
* @xpos: horizontal offset in pixels from the left edge of the display
* @ypos: vertical offset in lines from the top of the display
* @interlaced: Non-zero if the display is interlaced, or zero otherwise
*
* Description:
* A structure describing the configuration parameters of an On-Screen Display
* (OSD) or video layer related to how the image is stored in memory.
* @line_length must be a multiple of the cache line size (32 bytes).
*/
struct osd_layer_config {
enum osd_pix_format pixfmt;
unsigned line_length;
unsigned xsize;
unsigned ysize;
unsigned xpos;
unsigned ypos;
int interlaced;
};
/* parameters that apply on a per-window (OSD or video) basis */
struct osd_window_state {
int is_allocated;
int is_enabled;
unsigned long fb_base_phys;
enum osd_zoom_factor h_zoom;
enum osd_zoom_factor v_zoom;
struct osd_layer_config lconfig;
};
/* parameters that apply on a per-OSD-window basis */
struct osd_osdwin_state {
enum osd_clut clut;
enum osd_blending_factor blend;
int colorkey_blending;
unsigned colorkey;
int rec601_attenuation;
/* index is pixel value */
unsigned char palette_map[16];
};
/* hardware rectangular cursor parameters */
struct osd_cursor_state {
int is_enabled;
struct osd_cursor_config config;
};
struct osd_state;
struct vpbe_osd_ops {
int (*initialize)(struct osd_state *sd);
int (*request_layer)(struct osd_state *sd, enum osd_layer layer);
void (*release_layer)(struct osd_state *sd, enum osd_layer layer);
int (*enable_layer)(struct osd_state *sd, enum osd_layer layer,
int otherwin);
void (*disable_layer)(struct osd_state *sd, enum osd_layer layer);
int (*set_layer_config)(struct osd_state *sd, enum osd_layer layer,
struct osd_layer_config *lconfig);
void (*get_layer_config)(struct osd_state *sd, enum osd_layer layer,
struct osd_layer_config *lconfig);
void (*start_layer)(struct osd_state *sd, enum osd_layer layer,
unsigned long fb_base_phys,
unsigned long cbcr_ofst);
void (*set_left_margin)(struct osd_state *sd, u32 val);
void (*set_top_margin)(struct osd_state *sd, u32 val);
void (*set_interpolation_filter)(struct osd_state *sd, int filter);
int (*set_vid_expansion)(struct osd_state *sd,
enum osd_h_exp_ratio h_exp,
enum osd_v_exp_ratio v_exp);
void (*get_vid_expansion)(struct osd_state *sd,
enum osd_h_exp_ratio *h_exp,
enum osd_v_exp_ratio *v_exp);
void (*set_zoom)(struct osd_state *sd, enum osd_layer layer,
enum osd_zoom_factor h_zoom,
enum osd_zoom_factor v_zoom);
};
struct osd_state {
enum vpbe_version vpbe_type;
spinlock_t lock;
struct device *dev;
dma_addr_t osd_base_phys;
unsigned long osd_base;
unsigned long osd_size;
/* 1-->the isr will toggle the VID0 ping-pong buffer */
int pingpong;
int interpolation_filter;
int field_inversion;
enum osd_h_exp_ratio osd_h_exp;
enum osd_v_exp_ratio osd_v_exp;
enum osd_h_exp_ratio vid_h_exp;
enum osd_v_exp_ratio vid_v_exp;
enum osd_clut backg_clut;
unsigned backg_clut_index;
enum osd_rom_clut rom_clut;
int is_blinking;
/* attribute window blinking enabled */
enum osd_blink_interval blink;
/* YCbCrI or YCrCbI */
enum osd_pix_format yc_pixfmt;
/* columns are Y, Cb, Cr */
unsigned char clut_ram[256][3];
struct osd_cursor_state cursor;
/* OSD0, VID0, OSD1, VID1 */
struct osd_window_state win[4];
/* OSD0, OSD1 */
struct osd_osdwin_state osdwin[2];
/* OSD device Operations */
struct vpbe_osd_ops ops;
};
struct osd_platform_data {
enum vpbe_version vpbe_type;
int field_inv_wa_enable;
};
#endif
kernel/include/media/davinci/vpbe_types.h
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/*
* Copyright (C) 2010 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation version 2.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _VPBE_TYPES_H
#define _VPBE_TYPES_H
enum vpbe_version {
VPBE_VERSION_1 = 1,
VPBE_VERSION_2,
VPBE_VERSION_3,
};
/* vpbe_timing_type - Timing types used in vpbe device */
enum vpbe_enc_timings_type {
VPBE_ENC_STD = 0x1,
VPBE_ENC_DV_PRESET = 0x2,
VPBE_ENC_CUSTOM_TIMINGS = 0x4,
/* Used when set timings through FB device interface */
VPBE_ENC_TIMINGS_INVALID = 0x8,
};
union vpbe_timings {
v4l2_std_id std_id;
unsigned int dv_preset;
};
/*
* struct vpbe_enc_mode_info
* @name: ptr to name string of the standard, "NTSC", "PAL" etc
* @std: standard or non-standard mode. 1 - standard, 0 - nonstandard
* @interlaced: 1 - interlaced, 0 - non interlaced/progressive
* @xres: x or horizontal resolution of the display
* @yres: y or vertical resolution of the display
* @fps: frame per second
* @left_margin: left margin of the display
* @right_margin: right margin of the display
* @upper_margin: upper margin of the display
* @lower_margin: lower margin of the display
* @hsync_len: h-sync length
* @vsync_len: v-sync length
* @flags: bit field: bit usage is documented below
*
* Description:
* Structure holding timing and resolution information of a standard.
* Used by vpbe_device to set required non-standard timing in the
* venc when lcd controller output is connected to a external encoder.
* A table of timings is maintained in vpbe device to set this in
* venc when external encoder is connected to lcd controller output.
* Encoder may provide a g_dv_timings() API to override these values
* as needed.
*
* Notes
* ------
* if_type should be used only by encoder manager and encoder.
* flags usage
* b0 (LSB) - hsync polarity, 0 - negative, 1 - positive
* b1 - vsync polarity, 0 - negative, 1 - positive
* b2 - field id polarity, 0 - negative, 1 - positive
*/
struct vpbe_enc_mode_info {
unsigned char *name;
enum vpbe_enc_timings_type timings_type;
union vpbe_timings timings;
unsigned int interlaced;
unsigned int xres;
unsigned int yres;
struct v4l2_fract aspect;
struct v4l2_fract fps;
unsigned int left_margin;
unsigned int right_margin;
unsigned int upper_margin;
unsigned int lower_margin;
unsigned int hsync_len;
unsigned int vsync_len;
unsigned int flags;
};
#endif
kernel/include/media/davinci/vpbe_venc.h
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/*
* Copyright (C) 2010 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation version 2.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _VPBE_VENC_H
#define _VPBE_VENC_H
#include <media/v4l2-subdev.h>
#include <media/davinci/vpbe_types.h>
#define VPBE_VENC_SUBDEV_NAME "vpbe-venc"
/* venc events */
#define VENC_END_OF_FRAME BIT(0)
#define VENC_FIRST_FIELD BIT(1)
#define VENC_SECOND_FIELD BIT(2)
struct venc_platform_data {
enum vpbe_version venc_type;
int (*setup_pinmux)(enum v4l2_mbus_pixelcode if_type,
int field);
int (*setup_clock)(enum vpbe_enc_timings_type type,
unsigned int mode);
int (*setup_if_config)(enum v4l2_mbus_pixelcode pixcode);
/* Number of LCD outputs supported */
int num_lcd_outputs;
struct vpbe_if_params *lcd_if_params;
};
enum venc_ioctls {
VENC_GET_FLD = 1,
};
/* exported functions */
struct v4l2_subdev *venc_sub_dev_init(struct v4l2_device *v4l2_dev,
const char *venc_name);
#endif
kernel/include/media/davinci/vpfe_capture.h
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/*
* Copyright (C) 2008-2009 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _VPFE_CAPTURE_H
#define _VPFE_CAPTURE_H
#ifdef __KERNEL__
/* Header files */
#include <media/v4l2-dev.h>
#include <linux/videodev2.h>
#include <linux/clk.h>
#include <linux/i2c.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-device.h>
#include <media/videobuf-dma-contig.h>
#include <media/davinci/vpfe_types.h>
#define VPFE_CAPTURE_NUM_DECODERS 5
/* Macros */
#define VPFE_MAJOR_RELEASE 0
#define VPFE_MINOR_RELEASE 0
#define VPFE_BUILD 1
#define VPFE_CAPTURE_VERSION_CODE ((VPFE_MAJOR_RELEASE << 16) | \
(VPFE_MINOR_RELEASE << 8) | \
VPFE_BUILD)
#define CAPTURE_DRV_NAME "vpfe-capture"
struct vpfe_pixel_format {
struct v4l2_fmtdesc fmtdesc;
/* bytes per pixel */
int bpp;
};
struct vpfe_std_info {
int active_pixels;
int active_lines;
/* current frame format */
int frame_format;
};
struct vpfe_route {
u32 input;
u32 output;
};
struct vpfe_subdev_info {
/* Sub device name */
char name[32];
/* Sub device group id */
int grp_id;
/* Number of inputs supported */
int num_inputs;
/* inputs available at the sub device */
struct v4l2_input *inputs;
/* Sub dev routing information for each input */
struct vpfe_route *routes;
/* check if sub dev supports routing */
int can_route;
/* ccdc bus/interface configuration */
struct vpfe_hw_if_param ccdc_if_params;
/* i2c subdevice board info */
struct i2c_board_info board_info;
};
struct vpfe_config {
/* Number of sub devices connected to vpfe */
int num_subdevs;
/* i2c bus adapter no */
int i2c_adapter_id;
/* information about each subdev */
struct vpfe_subdev_info *sub_devs;
/* evm card info */
char *card_name;
/* ccdc name */
char *ccdc;
/* vpfe clock */
struct clk *vpssclk;
struct clk *slaveclk;
/* Function for Clearing the interrupt */
void (*clr_intr)(int vdint);
};
struct vpfe_device {
/* V4l2 specific parameters */
/* Identifies video device for this channel */
struct video_device *video_dev;
/* sub devices */
struct v4l2_subdev **sd;
/* vpfe cfg */
struct vpfe_config *cfg;
/* V4l2 device */
struct v4l2_device v4l2_dev;
/* parent device */
struct device *pdev;
/* Used to keep track of state of the priority */
struct v4l2_prio_state prio;
/* number of open instances of the channel */
u32 usrs;
/* Indicates id of the field which is being displayed */
u32 field_id;
/* flag to indicate whether decoder is initialized */
u8 initialized;
/* current interface type */
struct vpfe_hw_if_param vpfe_if_params;
/* ptr to currently selected sub device */
struct vpfe_subdev_info *current_subdev;
/* current input at the sub device */
int current_input;
/* Keeps track of the information about the standard */
struct vpfe_std_info std_info;
/* std index into std table */
int std_index;
/* CCDC IRQs used when CCDC/ISIF output to SDRAM */
unsigned int ccdc_irq0;
unsigned int ccdc_irq1;
/* number of buffers in fbuffers */
u32 numbuffers;
/* List of buffer pointers for storing frames */
u8 *fbuffers[VIDEO_MAX_FRAME];
/* Pointer pointing to current v4l2_buffer */
struct videobuf_buffer *cur_frm;
/* Pointer pointing to next v4l2_buffer */
struct videobuf_buffer *next_frm;
/*
* This field keeps track of type of buffer exchange mechanism
* user has selected
*/
enum v4l2_memory memory;
/* Used to store pixel format */
struct v4l2_format fmt;
/*
* used when IMP is chained to store the crop window which
* is different from the image window
*/
struct v4l2_rect crop;
/* Buffer queue used in video-buf */
struct videobuf_queue buffer_queue;
/* Queue of filled frames */
struct list_head dma_queue;
/* Used in video-buf */
spinlock_t irqlock;
/* IRQ lock for DMA queue */
spinlock_t dma_queue_lock;
/* lock used to access this structure */
struct mutex lock;
/* number of users performing IO */
u32 io_usrs;
/* Indicates whether streaming started */
u8 started;
/*
* offset where second field starts from the starting of the
* buffer for field separated YCbCr formats
*/
u32 field_off;
};
/* File handle structure */
struct vpfe_fh {
struct vpfe_device *vpfe_dev;
/* Indicates whether this file handle is doing IO */
u8 io_allowed;
/* Used to keep track priority of this instance */
enum v4l2_priority prio;
};
struct vpfe_config_params {
u8 min_numbuffers;
u8 numbuffers;
u32 min_bufsize;
u32 device_bufsize;
};
#endif /* End of __KERNEL__ */
/**
* VPFE_CMD_S_CCDC_RAW_PARAMS - EXPERIMENTAL IOCTL to set raw capture params
* This can be used to configure modules such as defect pixel correction,
* color space conversion, culling etc. This is an experimental ioctl that
* will change in future kernels. So use this ioctl with care !
* TODO: This is to be split into multiple ioctls and also explore the
* possibility of extending the v4l2 api to include this
**/
#define VPFE_CMD_S_CCDC_RAW_PARAMS _IOW('V', BASE_VIDIOC_PRIVATE + 1, \
void *)
#endif /* _DAVINCI_VPFE_H */
kernel/include/media/davinci/vpfe_types.h
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/*
* Copyright (C) 2008-2009 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option)any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _VPFE_TYPES_H
#define _VPFE_TYPES_H
#ifdef __KERNEL__
enum vpfe_pin_pol {
VPFE_PINPOL_POSITIVE,
VPFE_PINPOL_NEGATIVE
};
enum vpfe_hw_if_type {
/* BT656 - 8 bit */
VPFE_BT656,
/* BT1120 - 16 bit */
VPFE_BT1120,
/* Raw Bayer */
VPFE_RAW_BAYER,
/* YCbCr - 8 bit with external sync */
VPFE_YCBCR_SYNC_8,
/* YCbCr - 16 bit with external sync */
VPFE_YCBCR_SYNC_16,
/* BT656 - 10 bit */
VPFE_BT656_10BIT
};
/* interface description */
struct vpfe_hw_if_param {
enum vpfe_hw_if_type if_type;
enum vpfe_pin_pol hdpol;
enum vpfe_pin_pol vdpol;
};
#endif
#endif
kernel/include/media/davinci/vpif_types.h
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/*
* Copyright (C) 2011 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation version 2.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _VPIF_TYPES_H
#define _VPIF_TYPES_H
#include <linux/i2c.h>
#define VPIF_CAPTURE_MAX_CHANNELS 2
enum vpif_if_type {
VPIF_IF_BT656,
VPIF_IF_BT1120,
VPIF_IF_RAW_BAYER
};
struct vpif_interface {
enum vpif_if_type if_type;
unsigned hd_pol:1;
unsigned vd_pol:1;
unsigned fid_pol:1;
};
struct vpif_subdev_info {
const char *name;
struct i2c_board_info board_info;
u32 input;
u32 output;
unsigned can_route:1;
struct vpif_interface vpif_if;
};
struct vpif_display_config {
int (*set_clock)(int, int);
struct vpif_subdev_info *subdevinfo;
int subdev_count;
const char **output;
int output_count;
const char *card_name;
};
struct vpif_input {
struct v4l2_input input;
const char *subdev_name;
};
struct vpif_capture_chan_config {
const struct vpif_input *inputs;
int input_count;
};
struct vpif_capture_config {
int (*setup_input_channel_mode)(int);
int (*setup_input_path)(int, const char *);
struct vpif_capture_chan_config chan_config[VPIF_CAPTURE_MAX_CHANNELS];
struct vpif_subdev_info *subdev_info;
int subdev_count;
const char *card_name;
};
#endif /* _VPIF_TYPES_H */
kernel/include/media/davinci/vpss.h
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/*
* Copyright (C) 2009 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* vpss - video processing subsystem module header file.
*
* Include this header file if a driver needs to configure vpss system
* module. It exports a set of library functions for video drivers to
* configure vpss system module functions such as clock enable/disable,
* vpss interrupt mux to arm, and other common vpss system module
* functions.
*/
#ifndef _VPSS_H
#define _VPSS_H
/* selector for ccdc input selection on DM355 */
enum vpss_ccdc_source_sel {
VPSS_CCDCIN,
VPSS_HSSIIN,
VPSS_PGLPBK, /* for DM365 only */
VPSS_CCDCPG /* for DM365 only */
};
struct vpss_sync_pol {
unsigned int ccdpg_hdpol:1;
unsigned int ccdpg_vdpol:1;
};
struct vpss_pg_frame_size {
short hlpfr;
short pplen;
};
/* Used for enable/disable VPSS Clock */
enum vpss_clock_sel {
/* DM355/DM365 */
VPSS_CCDC_CLOCK,
VPSS_IPIPE_CLOCK,
VPSS_H3A_CLOCK,
VPSS_CFALD_CLOCK,
/*
* When using VPSS_VENC_CLOCK_SEL in vpss_enable_clock() api
* following applies:-
* en = 0 selects ENC_CLK
* en = 1 selects ENC_CLK/2
*/
VPSS_VENC_CLOCK_SEL,
VPSS_VPBE_CLOCK,
/* DM365 only clocks */
VPSS_IPIPEIF_CLOCK,
VPSS_RSZ_CLOCK,
VPSS_BL_CLOCK,
/*
* When using VPSS_PCLK_INTERNAL in vpss_enable_clock() api
* following applies:-
* en = 0 disable internal PCLK
* en = 1 enables internal PCLK
*/
VPSS_PCLK_INTERNAL,
/*
* When using VPSS_PSYNC_CLOCK_SEL in vpss_enable_clock() api
* following applies:-
* en = 0 enables MMR clock
* en = 1 enables VPSS clock
*/
VPSS_PSYNC_CLOCK_SEL,
VPSS_LDC_CLOCK_SEL,
VPSS_OSD_CLOCK_SEL,
VPSS_FDIF_CLOCK,
VPSS_LDC_CLOCK
};
/* select input to ccdc on dm355 */
int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel);
/* enable/disable a vpss clock, 0 - success, -1 - failure */
int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en);
/* set sync polarity, only for DM365*/
void dm365_vpss_set_sync_pol(struct vpss_sync_pol);
/* set the PG_FRAME_SIZE register, only for DM365 */
void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size);
/* wbl reset for dm644x */
enum vpss_wbl_sel {
VPSS_PCR_AEW_WBL_0 = 16,
VPSS_PCR_AF_WBL_0,
VPSS_PCR_RSZ4_WBL_0,
VPSS_PCR_RSZ3_WBL_0,
VPSS_PCR_RSZ2_WBL_0,
VPSS_PCR_RSZ1_WBL_0,
VPSS_PCR_PREV_WBL_0,
VPSS_PCR_CCDC_WBL_O,
};
/* clear wbl overflow flag for DM6446 */
int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel);
#endif
kernel/include/media/gpio-ir-recv.h
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/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __GPIO_IR_RECV_H__
#define __GPIO_IR_RECV_H__
struct gpio_ir_recv_platform_data {
int gpio_nr;
bool active_low;
bool can_wakeup;
u32 swfi_latency;
};
#endif /* __GPIO_IR_RECV_H__ */
kernel/include/media/i2c-addr.h
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/*
* V4L I2C address list
*
*
* Copyright (C) 2006 Mauro Carvalho Chehab <mchehab@infradead.org>
* Based on a previous mapping by
* Ralph Metzler (rjkm@thp.uni-koeln.de)
* Gerd Knorr <kraxel@goldbach.in-berlin.de>
*
*/
/* bttv address list */
#define I2C_ADDR_TSA5522 0xc2
#define I2C_ADDR_TDA7432 0x8a
#define I2C_ADDR_TDA8425 0x82
#define I2C_ADDR_TDA9840 0x84
#define I2C_ADDR_TDA9850 0xb6 /* also used by 9855,9873 */
#define I2C_ADDR_TDA9874 0xb0 /* also used by 9875 */
#define I2C_ADDR_TDA9875 0xb0
#define I2C_ADDR_HAUPEE 0xa0
#define I2C_ADDR_STBEE 0xae
#define I2C_ADDR_VHX 0xc0
#define I2C_ADDR_MSP3400 0x80
#define I2C_ADDR_MSP3400_ALT 0x88
#define I2C_ADDR_TEA6300 0x80 /* also used by 6320 */
#define I2C_ADDR_DPL3518 0x84
#define I2C_ADDR_TDA9887 0x86
/*
* i2c bus addresses for the chips supported by tvaudio.c
*/
#define I2C_ADDR_TDA8425 0x82
#define I2C_ADDR_TDA9840 0x84 /* also used by TA8874Z */
#define I2C_ADDR_TDA985x_L 0xb4 /* also used by 9873 */
#define I2C_ADDR_TDA985x_H 0xb6
#define I2C_ADDR_TDA9874 0xb0 /* also used by 9875 */
#define I2C_ADDR_TEA6300 0x80 /* also used by 6320 */
#define I2C_ADDR_TEA6420 0x98
#define I2C_ADDR_PIC16C54 0x96 /* PV951 */
kernel/include/media/ir-kbd-i2c.h
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#ifndef _IR_I2C
#define _IR_I2C
#include <media/rc-core.h>
#define DEFAULT_POLLING_INTERVAL 100 /* ms */
struct IR_i2c;
struct IR_i2c {
char *ir_codes;
struct i2c_client *c;
struct rc_dev *rc;
/* Used to avoid fast repeating */
unsigned char old;
u32 polling_interval; /* in ms */
struct delayed_work work;
char name[32];
char phys[32];
int (*get_key)(struct IR_i2c*, u32*, u32*);
};
enum ir_kbd_get_key_fn {
IR_KBD_GET_KEY_CUSTOM = 0,
IR_KBD_GET_KEY_PIXELVIEW,
IR_KBD_GET_KEY_HAUP,
IR_KBD_GET_KEY_KNC1,
IR_KBD_GET_KEY_FUSIONHDTV,
IR_KBD_GET_KEY_HAUP_XVR,
IR_KBD_GET_KEY_AVERMEDIA_CARDBUS,
};
/* Can be passed when instantiating an ir_video i2c device */
struct IR_i2c_init_data {
char *ir_codes;
const char *name;
u64 type; /* RC_TYPE_RC5, etc */
u32 polling_interval; /* 0 means DEFAULT_POLLING_INTERVAL */
/*
* Specify either a function pointer or a value indicating one of
* ir_kbd_i2c's internal get_key functions
*/
int (*get_key)(struct IR_i2c*, u32*, u32*);
enum ir_kbd_get_key_fn internal_get_key_func;
struct rc_dev *rc_dev;
};
#endif
kernel/include/media/lirc.h
+168
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/*
* lirc.h - linux infrared remote control header file
* last modified 2010/07/13 by Jarod Wilson
*/
#ifndef _LINUX_LIRC_H
#define _LINUX_LIRC_H
#include <linux/types.h>
#include <linux/ioctl.h>
#define PULSE_BIT 0x01000000
#define PULSE_MASK 0x00FFFFFF
#define LIRC_MODE2_SPACE 0x00000000
#define LIRC_MODE2_PULSE 0x01000000
#define LIRC_MODE2_FREQUENCY 0x02000000
#define LIRC_MODE2_TIMEOUT 0x03000000
#define LIRC_VALUE_MASK 0x00FFFFFF
#define LIRC_MODE2_MASK 0xFF000000
#define LIRC_SPACE(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_SPACE)
#define LIRC_PULSE(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_PULSE)
#define LIRC_FREQUENCY(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_FREQUENCY)
#define LIRC_TIMEOUT(val) (((val)&LIRC_VALUE_MASK) | LIRC_MODE2_TIMEOUT)
#define LIRC_VALUE(val) ((val)&LIRC_VALUE_MASK)
#define LIRC_MODE2(val) ((val)&LIRC_MODE2_MASK)
#define LIRC_IS_SPACE(val) (LIRC_MODE2(val) == LIRC_MODE2_SPACE)
#define LIRC_IS_PULSE(val) (LIRC_MODE2(val) == LIRC_MODE2_PULSE)
#define LIRC_IS_FREQUENCY(val) (LIRC_MODE2(val) == LIRC_MODE2_FREQUENCY)
#define LIRC_IS_TIMEOUT(val) (LIRC_MODE2(val) == LIRC_MODE2_TIMEOUT)
/* used heavily by lirc userspace */
#define lirc_t int
/*** lirc compatible hardware features ***/
#define LIRC_MODE2SEND(x) (x)
#define LIRC_SEND2MODE(x) (x)
#define LIRC_MODE2REC(x) ((x) << 16)
#define LIRC_REC2MODE(x) ((x) >> 16)
#define LIRC_MODE_RAW 0x00000001
#define LIRC_MODE_PULSE 0x00000002
#define LIRC_MODE_MODE2 0x00000004
#define LIRC_MODE_LIRCCODE 0x00000010
#define LIRC_CAN_SEND_RAW LIRC_MODE2SEND(LIRC_MODE_RAW)
#define LIRC_CAN_SEND_PULSE LIRC_MODE2SEND(LIRC_MODE_PULSE)
#define LIRC_CAN_SEND_MODE2 LIRC_MODE2SEND(LIRC_MODE_MODE2)
#define LIRC_CAN_SEND_LIRCCODE LIRC_MODE2SEND(LIRC_MODE_LIRCCODE)
#define LIRC_CAN_SEND_MASK 0x0000003f
#define LIRC_CAN_SET_SEND_CARRIER 0x00000100
#define LIRC_CAN_SET_SEND_DUTY_CYCLE 0x00000200
#define LIRC_CAN_SET_TRANSMITTER_MASK 0x00000400
#define LIRC_CAN_REC_RAW LIRC_MODE2REC(LIRC_MODE_RAW)
#define LIRC_CAN_REC_PULSE LIRC_MODE2REC(LIRC_MODE_PULSE)
#define LIRC_CAN_REC_MODE2 LIRC_MODE2REC(LIRC_MODE_MODE2)
#define LIRC_CAN_REC_LIRCCODE LIRC_MODE2REC(LIRC_MODE_LIRCCODE)
#define LIRC_CAN_REC_MASK LIRC_MODE2REC(LIRC_CAN_SEND_MASK)
#define LIRC_CAN_SET_REC_CARRIER (LIRC_CAN_SET_SEND_CARRIER << 16)
#define LIRC_CAN_SET_REC_DUTY_CYCLE (LIRC_CAN_SET_SEND_DUTY_CYCLE << 16)
#define LIRC_CAN_SET_REC_DUTY_CYCLE_RANGE 0x40000000
#define LIRC_CAN_SET_REC_CARRIER_RANGE 0x80000000
#define LIRC_CAN_GET_REC_RESOLUTION 0x20000000
#define LIRC_CAN_SET_REC_TIMEOUT 0x10000000
#define LIRC_CAN_SET_REC_FILTER 0x08000000
#define LIRC_CAN_MEASURE_CARRIER 0x02000000
#define LIRC_CAN_USE_WIDEBAND_RECEIVER 0x04000000
#define LIRC_CAN_SEND(x) ((x)&LIRC_CAN_SEND_MASK)
#define LIRC_CAN_REC(x) ((x)&LIRC_CAN_REC_MASK)
#define LIRC_CAN_NOTIFY_DECODE 0x01000000
/*** IOCTL commands for lirc driver ***/
#define LIRC_GET_FEATURES _IOR('i', 0x00000000, __u32)
#define LIRC_GET_SEND_MODE _IOR('i', 0x00000001, __u32)
#define LIRC_GET_REC_MODE _IOR('i', 0x00000002, __u32)
#define LIRC_GET_SEND_CARRIER _IOR('i', 0x00000003, __u32)
#define LIRC_GET_REC_CARRIER _IOR('i', 0x00000004, __u32)
#define LIRC_GET_SEND_DUTY_CYCLE _IOR('i', 0x00000005, __u32)
#define LIRC_GET_REC_DUTY_CYCLE _IOR('i', 0x00000006, __u32)
#define LIRC_GET_REC_RESOLUTION _IOR('i', 0x00000007, __u32)
#define LIRC_GET_MIN_TIMEOUT _IOR('i', 0x00000008, __u32)
#define LIRC_GET_MAX_TIMEOUT _IOR('i', 0x00000009, __u32)
#define LIRC_GET_MIN_FILTER_PULSE _IOR('i', 0x0000000a, __u32)
#define LIRC_GET_MAX_FILTER_PULSE _IOR('i', 0x0000000b, __u32)
#define LIRC_GET_MIN_FILTER_SPACE _IOR('i', 0x0000000c, __u32)
#define LIRC_GET_MAX_FILTER_SPACE _IOR('i', 0x0000000d, __u32)
/* code length in bits, currently only for LIRC_MODE_LIRCCODE */
#define LIRC_GET_LENGTH _IOR('i', 0x0000000f, __u32)
#define LIRC_SET_SEND_MODE _IOW('i', 0x00000011, __u32)
#define LIRC_SET_REC_MODE _IOW('i', 0x00000012, __u32)
/* Note: these can reset the according pulse_width */
#define LIRC_SET_SEND_CARRIER _IOW('i', 0x00000013, __u32)
#define LIRC_SET_REC_CARRIER _IOW('i', 0x00000014, __u32)
#define LIRC_SET_SEND_DUTY_CYCLE _IOW('i', 0x00000015, __u32)
#define LIRC_SET_REC_DUTY_CYCLE _IOW('i', 0x00000016, __u32)
#define LIRC_SET_TRANSMITTER_MASK _IOW('i', 0x00000017, __u32)
/*
* when a timeout != 0 is set the driver will send a
* LIRC_MODE2_TIMEOUT data packet, otherwise LIRC_MODE2_TIMEOUT is
* never sent, timeout is disabled by default
*/
#define LIRC_SET_REC_TIMEOUT _IOW('i', 0x00000018, __u32)
/* 1 enables, 0 disables timeout reports in MODE2 */
#define LIRC_SET_REC_TIMEOUT_REPORTS _IOW('i', 0x00000019, __u32)
/*
* pulses shorter than this are filtered out by hardware (software
* emulation in lirc_dev?)
*/
#define LIRC_SET_REC_FILTER_PULSE _IOW('i', 0x0000001a, __u32)
/*
* spaces shorter than this are filtered out by hardware (software
* emulation in lirc_dev?)
*/
#define LIRC_SET_REC_FILTER_SPACE _IOW('i', 0x0000001b, __u32)
/*
* if filter cannot be set independently for pulse/space, this should
* be used
*/
#define LIRC_SET_REC_FILTER _IOW('i', 0x0000001c, __u32)
/*
* if enabled from the next key press on the driver will send
* LIRC_MODE2_FREQUENCY packets
*/
#define LIRC_SET_MEASURE_CARRIER_MODE _IOW('i', 0x0000001d, __u32)
/*
* to set a range use
* LIRC_SET_REC_DUTY_CYCLE_RANGE/LIRC_SET_REC_CARRIER_RANGE with the
* lower bound first and later
* LIRC_SET_REC_DUTY_CYCLE/LIRC_SET_REC_CARRIER with the upper bound
*/
#define LIRC_SET_REC_DUTY_CYCLE_RANGE _IOW('i', 0x0000001e, __u32)
#define LIRC_SET_REC_CARRIER_RANGE _IOW('i', 0x0000001f, __u32)
#define LIRC_NOTIFY_DECODE _IO('i', 0x00000020)
#define LIRC_SETUP_START _IO('i', 0x00000021)
#define LIRC_SETUP_END _IO('i', 0x00000022)
#define LIRC_SET_WIDEBAND_RECEIVER _IOW('i', 0x00000023, __u32)
#endif
kernel/include/media/lirc_dev.h
+225
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/*
* LIRC base driver
*
* by Artur Lipowski <alipowski@interia.pl>
* This code is licensed under GNU GPL
*
*/
#ifndef _LINUX_LIRC_DEV_H
#define _LINUX_LIRC_DEV_H
#define MAX_IRCTL_DEVICES 8
#define BUFLEN 16
#define mod(n, div) ((n) % (div))
#include <linux/slab.h>
#include <linux/fs.h>
#include <linux/ioctl.h>
#include <linux/poll.h>
#include <linux/kfifo.h>
#include <media/lirc.h>
struct lirc_buffer {
wait_queue_head_t wait_poll;
spinlock_t fifo_lock;
unsigned int chunk_size;
unsigned int size; /* in chunks */
/* Using chunks instead of bytes pretends to simplify boundary checking
* And should allow for some performance fine tunning later */
struct kfifo fifo;
u8 fifo_initialized;
};
static inline void lirc_buffer_clear(struct lirc_buffer *buf)
{
unsigned long flags;
if (buf->fifo_initialized) {
spin_lock_irqsave(&buf->fifo_lock, flags);
kfifo_reset(&buf->fifo);
spin_unlock_irqrestore(&buf->fifo_lock, flags);
} else
WARN(1, "calling %s on an uninitialized lirc_buffer\n",
__func__);
}
static inline int lirc_buffer_init(struct lirc_buffer *buf,
unsigned int chunk_size,
unsigned int size)
{
int ret;
init_waitqueue_head(&buf->wait_poll);
spin_lock_init(&buf->fifo_lock);
buf->chunk_size = chunk_size;
buf->size = size;
ret = kfifo_alloc(&buf->fifo, size * chunk_size, GFP_KERNEL);
if (ret == 0)
buf->fifo_initialized = 1;
return ret;
}
static inline void lirc_buffer_free(struct lirc_buffer *buf)
{
if (buf->fifo_initialized) {
kfifo_free(&buf->fifo);
buf->fifo_initialized = 0;
} else
WARN(1, "calling %s on an uninitialized lirc_buffer\n",
__func__);
}
static inline int lirc_buffer_len(struct lirc_buffer *buf)
{
int len;
unsigned long flags;
spin_lock_irqsave(&buf->fifo_lock, flags);
len = kfifo_len(&buf->fifo);
spin_unlock_irqrestore(&buf->fifo_lock, flags);
return len;
}
static inline int lirc_buffer_full(struct lirc_buffer *buf)
{
return lirc_buffer_len(buf) == buf->size * buf->chunk_size;
}
static inline int lirc_buffer_empty(struct lirc_buffer *buf)
{
return !lirc_buffer_len(buf);
}
static inline int lirc_buffer_available(struct lirc_buffer *buf)
{
return buf->size - (lirc_buffer_len(buf) / buf->chunk_size);
}
static inline unsigned int lirc_buffer_read(struct lirc_buffer *buf,
unsigned char *dest)
{
unsigned int ret = 0;
if (lirc_buffer_len(buf) >= buf->chunk_size)
ret = kfifo_out_locked(&buf->fifo, dest, buf->chunk_size,
&buf->fifo_lock);
return ret;
}
static inline unsigned int lirc_buffer_write(struct lirc_buffer *buf,
unsigned char *orig)
{
unsigned int ret;
ret = kfifo_in_locked(&buf->fifo, orig, buf->chunk_size,
&buf->fifo_lock);
return ret;
}
struct lirc_driver {
char name[40];
int minor;
__u32 code_length;
unsigned int buffer_size; /* in chunks holding one code each */
int sample_rate;
__u32 features;
unsigned int chunk_size;
void *data;
int min_timeout;
int max_timeout;
int (*add_to_buf) (void *data, struct lirc_buffer *buf);
struct lirc_buffer *rbuf;
int (*set_use_inc) (void *data);
void (*set_use_dec) (void *data);
const struct file_operations *fops;
struct device *dev;
struct module *owner;
};
/* name:
* this string will be used for logs
*
* minor:
* indicates minor device (/dev/lirc) number for registered driver
* if caller fills it with negative value, then the first free minor
* number will be used (if available)
*
* code_length:
* length of the remote control key code expressed in bits
*
* sample_rate:
*
* data:
* it may point to any driver data and this pointer will be passed to
* all callback functions
*
* add_to_buf:
* add_to_buf will be called after specified period of the time or
* triggered by the external event, this behavior depends on value of
* the sample_rate this function will be called in user context. This
* routine should return 0 if data was added to the buffer and
* -ENODATA if none was available. This should add some number of bits
* evenly divisible by code_length to the buffer
*
* rbuf:
* if not NULL, it will be used as a read buffer, you will have to
* write to the buffer by other means, like irq's (see also
* lirc_serial.c).
*
* set_use_inc:
* set_use_inc will be called after device is opened
*
* set_use_dec:
* set_use_dec will be called after device is closed
*
* fops:
* file_operations for drivers which don't fit the current driver model.
*
* Some ioctl's can be directly handled by lirc_dev if the driver's
* ioctl function is NULL or if it returns -ENOIOCTLCMD (see also
* lirc_serial.c).
*
* owner:
* the module owning this struct
*
*/
/* following functions can be called ONLY from user context
*
* returns negative value on error or minor number
* of the registered device if success
* contents of the structure pointed by p is copied
*/
extern int lirc_register_driver(struct lirc_driver *d);
/* returns negative value on error or 0 if success
*/
extern int lirc_unregister_driver(int minor);
/* Returns the private data stored in the lirc_driver
* associated with the given device file pointer.
*/
void *lirc_get_pdata(struct file *file);
/* default file operations
* used by drivers if they override only some operations
*/
int lirc_dev_fop_open(struct inode *inode, struct file *file);
int lirc_dev_fop_close(struct inode *inode, struct file *file);
unsigned int lirc_dev_fop_poll(struct file *file, poll_table *wait);
long lirc_dev_fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
ssize_t lirc_dev_fop_read(struct file *file, char __user *buffer, size_t length,
loff_t *ppos);
ssize_t lirc_dev_fop_write(struct file *file, const char __user *buffer,
size_t length, loff_t *ppos);
#endif
kernel/include/media/m52790.h
+93
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/*
m52790.h - definition for m52790 inputs and outputs
Copyright (C) 2007 Hans Verkuil (hverkuil@xs4all.nl)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _M52790_H_
#define _M52790_H_
/* Input routing switch 1 */
#define M52790_SW1_IN_MASK 0x0003
#define M52790_SW1_IN_TUNER 0x0000
#define M52790_SW1_IN_V2 0x0001
#define M52790_SW1_IN_V3 0x0002
#define M52790_SW1_IN_V4 0x0003
/* Selects component input instead of composite */
#define M52790_SW1_YCMIX 0x0004
/* Input routing switch 2 */
#define M52790_SW2_IN_MASK 0x0300
#define M52790_SW2_IN_TUNER 0x0000
#define M52790_SW2_IN_V2 0x0100
#define M52790_SW2_IN_V3 0x0200
#define M52790_SW2_IN_V4 0x0300
/* Selects component input instead of composite */
#define M52790_SW2_YCMIX 0x0400
/* Output routing switch 1 */
/* Enable 6dB amplifier for composite out */
#define M52790_SW1_V_AMP 0x0008
/* Enable 6dB amplifier for component out */
#define M52790_SW1_YC_AMP 0x0010
/* Audio output mode */
#define M52790_SW1_AUDIO_MASK 0x00c0
#define M52790_SW1_AUDIO_MUTE 0x0000
#define M52790_SW1_AUDIO_R 0x0040
#define M52790_SW1_AUDIO_L 0x0080
#define M52790_SW1_AUDIO_STEREO 0x00c0
/* Output routing switch 2 */
/* Enable 6dB amplifier for composite out */
#define M52790_SW2_V_AMP 0x0800
/* Enable 6dB amplifier for component out */
#define M52790_SW2_YC_AMP 0x1000
/* Audio output mode */
#define M52790_SW2_AUDIO_MASK 0xc000
#define M52790_SW2_AUDIO_MUTE 0x0000
#define M52790_SW2_AUDIO_R 0x4000
#define M52790_SW2_AUDIO_L 0x8000
#define M52790_SW2_AUDIO_STEREO 0xc000
/* Common values */
#define M52790_IN_TUNER (M52790_SW1_IN_TUNER | M52790_SW2_IN_TUNER)
#define M52790_IN_V2 (M52790_SW1_IN_V2 | M52790_SW2_IN_V2)
#define M52790_IN_V3 (M52790_SW1_IN_V3 | M52790_SW2_IN_V3)
#define M52790_IN_V4 (M52790_SW1_IN_V4 | M52790_SW2_IN_V4)
#define M52790_OUT_STEREO (M52790_SW1_AUDIO_STEREO | \
M52790_SW2_AUDIO_STEREO)
#define M52790_OUT_AMP_STEREO (M52790_SW1_AUDIO_STEREO | \
M52790_SW1_V_AMP | \
M52790_SW2_AUDIO_STEREO | \
M52790_SW2_V_AMP)
#endif
kernel/include/media/m5mols.h
+33
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/*
* Driver header for M-5MOLS 8M Pixel camera sensor with ISP
*
* Copyright (C) 2011 Samsung Electronics Co., Ltd.
* Author: HeungJun Kim <riverful.kim@samsung.com>
*
* Copyright (C) 2009 Samsung Electronics Co., Ltd.
* Author: Dongsoo Nathaniel Kim <dongsoo45.kim@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef MEDIA_M5MOLS_H
#define MEDIA_M5MOLS_H
/**
* struct m5mols_platform_data - platform data for M-5MOLS driver
* @gpio_reset: GPIO driving the reset pin of M-5MOLS
* @reset_polarity: active state for gpio_reset pin, 0 or 1
* @set_power: an additional callback to the board setup code
* to be called after enabling and before disabling
* the sensor's supply regulators
*/
struct m5mols_platform_data {
int gpio_reset;
u8 reset_polarity;
int (*set_power)(struct device *dev, int on);
};
#endif /* MEDIA_M5MOLS_H */
kernel/include/media/media-device.h
+96
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/*
* Media device
*
* Copyright (C) 2010 Nokia Corporation
*
* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MEDIA_DEVICE_H
#define _MEDIA_DEVICE_H
#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/spinlock.h>
#include <media/media-devnode.h>
#include <media/media-entity.h>
struct device;
/**
* struct media_device - Media device
* @dev: Parent device
* @devnode: Media device node
* @model: Device model name
* @serial: Device serial number (optional)
* @bus_info: Unique and stable device location identifier
* @hw_revision: Hardware device revision
* @driver_version: Device driver version
* @entity_id: ID of the next entity to be registered
* @entities: List of registered entities
* @lock: Entities list lock
* @graph_mutex: Entities graph operation lock
*
* This structure represents an abstract high-level media device. It allows easy
* access to entities and provides basic media device-level support. The
* structure can be allocated directly or embedded in a larger structure.
*
* The parent @dev is a physical device. It must be set before registering the
* media device.
*
* @model is a descriptive model name exported through sysfs. It doesn't have to
* be unique.
*/
struct media_device {
/* dev->driver_data points to this struct. */
struct device *dev;
struct media_devnode devnode;
char model[32];
char serial[40];
char bus_info[32];
u32 hw_revision;
u32 driver_version;
u32 entity_id;
struct list_head entities;
/* Protects the entities list */
spinlock_t lock;
/* Serializes graph operations. */
struct mutex graph_mutex;
int (*link_notify)(struct media_pad *source,
struct media_pad *sink, u32 flags);
};
/* media_devnode to media_device */
#define to_media_device(node) container_of(node, struct media_device, devnode)
int __must_check media_device_register(struct media_device *mdev);
void media_device_unregister(struct media_device *mdev);
int __must_check media_device_register_entity(struct media_device *mdev,
struct media_entity *entity);
void media_device_unregister_entity(struct media_entity *entity);
/* Iterate over all entities. */
#define media_device_for_each_entity(entity, mdev) \
list_for_each_entry(entity, &(mdev)->entities, list)
#endif
kernel/include/media/media-devnode.h
+97
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/*
* Media device node
*
* Copyright (C) 2010 Nokia Corporation
*
* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* --
*
* Common functions for media-related drivers to register and unregister media
* device nodes.
*/
#ifndef _MEDIA_DEVNODE_H
#define _MEDIA_DEVNODE_H
#include <linux/poll.h>
#include <linux/fs.h>
#include <linux/device.h>
#include <linux/cdev.h>
/*
* Flag to mark the media_devnode struct as registered. Drivers must not touch
* this flag directly, it will be set and cleared by media_devnode_register and
* media_devnode_unregister.
*/
#define MEDIA_FLAG_REGISTERED 0
struct media_file_operations {
struct module *owner;
ssize_t (*read) (struct file *, char __user *, size_t, loff_t *);
ssize_t (*write) (struct file *, const char __user *, size_t, loff_t *);
unsigned int (*poll) (struct file *, struct poll_table_struct *);
long (*ioctl) (struct file *, unsigned int, unsigned long);
int (*open) (struct file *);
int (*release) (struct file *);
};
/**
* struct media_devnode - Media device node
* @parent: parent device
* @minor: device node minor number
* @flags: flags, combination of the MEDIA_FLAG_* constants
*
* This structure represents a media-related device node.
*
* The @parent is a physical device. It must be set by core or device drivers
* before registering the node.
*/
struct media_devnode {
/* device ops */
const struct media_file_operations *fops;
/* sysfs */
struct device dev; /* media device */
struct cdev cdev; /* character device */
struct device *parent; /* device parent */
/* device info */
int minor;
unsigned long flags; /* Use bitops to access flags */
/* callbacks */
void (*release)(struct media_devnode *mdev);
};
/* dev to media_devnode */
#define to_media_devnode(cd) container_of(cd, struct media_devnode, dev)
int __must_check media_devnode_register(struct media_devnode *mdev);
void media_devnode_unregister(struct media_devnode *mdev);
static inline struct media_devnode *media_devnode_data(struct file *filp)
{
return filp->private_data;
}
static inline int media_devnode_is_registered(struct media_devnode *mdev)
{
return test_bit(MEDIA_FLAG_REGISTERED, &mdev->flags);
}
#endif /* _MEDIA_DEVNODE_H */
kernel/include/media/media-entity.h
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/*
* Media entity
*
* Copyright (C) 2010 Nokia Corporation
*
* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _MEDIA_ENTITY_H
#define _MEDIA_ENTITY_H
#include <linux/list.h>
#include <linux/media.h>
struct media_pipeline {
};
struct media_link {
struct media_pad *source; /* Source pad */
struct media_pad *sink; /* Sink pad */
struct media_link *reverse; /* Link in the reverse direction */
unsigned long flags; /* Link flags (MEDIA_LNK_FL_*) */
};
struct media_pad {
struct media_entity *entity; /* Entity this pad belongs to */
u16 index; /* Pad index in the entity pads array */
unsigned long flags; /* Pad flags (MEDIA_PAD_FL_*) */
};
struct media_entity_operations {
int (*link_setup)(struct media_entity *entity,
const struct media_pad *local,
const struct media_pad *remote, u32 flags);
};
struct media_entity {
struct list_head list;
struct media_device *parent; /* Media device this entity belongs to*/
u32 id; /* Entity ID, unique in the parent media
* device context */
const char *name; /* Entity name */
u32 type; /* Entity type (MEDIA_ENT_T_*) */
u32 revision; /* Entity revision, driver specific */
unsigned long flags; /* Entity flags (MEDIA_ENT_FL_*) */
u32 group_id; /* Entity group ID */
u16 num_pads; /* Number of sink and source pads */
u16 num_links; /* Number of existing links, both
* enabled and disabled */
u16 num_backlinks; /* Number of backlinks */
u16 max_links; /* Maximum number of links */
struct media_pad *pads; /* Pads array (num_pads elements) */
struct media_link *links; /* Links array (max_links elements)*/
const struct media_entity_operations *ops; /* Entity operations */
/* Reference counts must never be negative, but are signed integers on
* purpose: a simple WARN_ON(<0) check can be used to detect reference
* count bugs that would make them negative.
*/
int stream_count; /* Stream count for the entity. */
int use_count; /* Use count for the entity. */
struct media_pipeline *pipe; /* Pipeline this entity belongs to. */
union {
/* Node specifications */
struct {
u32 major;
u32 minor;
} v4l;
struct {
u32 major;
u32 minor;
} fb;
struct {
u32 card;
u32 device;
u32 subdevice;
} alsa;
int dvb;
/* Sub-device specifications */
/* Nothing needed yet */
} info;
};
static inline u32 media_entity_type(struct media_entity *entity)
{
return entity->type & MEDIA_ENT_TYPE_MASK;
}
static inline u32 media_entity_subtype(struct media_entity *entity)
{
return entity->type & MEDIA_ENT_SUBTYPE_MASK;
}
#define MEDIA_ENTITY_ENUM_MAX_DEPTH 16
struct media_entity_graph {
struct {
struct media_entity *entity;
int link;
} stack[MEDIA_ENTITY_ENUM_MAX_DEPTH];
int top;
};
int media_entity_init(struct media_entity *entity, u16 num_pads,
struct media_pad *pads, u16 extra_links);
void media_entity_cleanup(struct media_entity *entity);
int media_entity_create_link(struct media_entity *source, u16 source_pad,
struct media_entity *sink, u16 sink_pad, u32 flags);
int __media_entity_setup_link(struct media_link *link, u32 flags);
int media_entity_setup_link(struct media_link *link, u32 flags);
struct media_link *media_entity_find_link(struct media_pad *source,
struct media_pad *sink);
struct media_pad *media_entity_remote_source(struct media_pad *pad);
struct media_entity *media_entity_get(struct media_entity *entity);
void media_entity_put(struct media_entity *entity);
void media_entity_graph_walk_start(struct media_entity_graph *graph,
struct media_entity *entity);
struct media_entity *
media_entity_graph_walk_next(struct media_entity_graph *graph);
void media_entity_pipeline_start(struct media_entity *entity,
struct media_pipeline *pipe);
void media_entity_pipeline_stop(struct media_entity *entity);
#define media_entity_call(entity, operation, args...) \
(((entity)->ops && (entity)->ops->operation) ? \
(entity)->ops->operation((entity) , ##args) : -ENOIOCTLCMD)
#endif
kernel/include/media/mmp-camera.h
+9
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/*
* Information for the Marvell Armada MMP camera
*/
struct mmp_camera_platform_data {
struct platform_device *i2c_device;
int sensor_power_gpio;
int sensor_reset_gpio;
};
kernel/include/media/msm/vcd_api.h
+160
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/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _VCD_API_H_
#define _VCD_API_H_
#include <linux/types.h>
#include "vcd_property.h"
#include "vcd_status.h"
#define VCD_FRAME_FLAG_EOS 0x00000001
#define VCD_FRAME_FLAG_DECODEONLY 0x00000004
#define VCD_FRAME_FLAG_DATACORRUPT 0x00000008
#define VCD_FRAME_FLAG_ENDOFFRAME 0x00000010
#define VCD_FRAME_FLAG_SYNCFRAME 0x00000020
#define VCD_FRAME_FLAG_EXTRADATA 0x00000040
#define VCD_FRAME_FLAG_CODECCONFIG 0x00000080
#define VCD_FRAME_FLAG_BFRAME 0x00100000
#define VCD_FRAME_FLAG_EOSEQ 0x00200000
#define VCD_FLUSH_INPUT 0x0001
#define VCD_FLUSH_OUTPUT 0x0002
#define VCD_FLUSH_ALL 0x0003
#define VCD_FRAMETAG_INVALID 0xffffffff
struct vcd_handle_container {
void *handle;
};
struct vcd_flush_cmd {
u32 mode;
};
enum vcd_frame {
VCD_FRAME_YUV = 1,
VCD_FRAME_I,
VCD_FRAME_P,
VCD_FRAME_B,
VCD_FRAME_NOTCODED,
VCD_FRAME_IDR,
VCD_FRAME_32BIT = 0x7fffffff
};
enum vcd_power_state {
VCD_PWR_STATE_ON = 1,
VCD_PWR_STATE_SLEEP,
};
struct vcd_aspect_ratio {
u32 aspect_ratio;
u32 par_width;
u32 par_height;
};
struct vcd_frame_data {
u8 *virtual;
u8 *physical;
u32 ion_flag;
u32 alloc_len;
u32 data_len;
u32 offset;
s64 time_stamp; /* in usecs*/
u32 flags;
u32 frm_clnt_data;
struct vcd_property_dec_output_buffer dec_op_prop;
u32 interlaced;
enum vcd_frame frame;
u32 ip_frm_tag;
u32 intrlcd_ip_frm_tag;
u8 *desc_buf;
u32 desc_size;
struct ion_handle *buff_ion_handle;
struct vcd_aspect_ratio aspect_ratio_info;
};
struct vcd_sequence_hdr {
u8 *sequence_header;
u32 sequence_header_len;
};
enum vcd_buffer_type {
VCD_BUFFER_INPUT = 0x1,
VCD_BUFFER_OUTPUT = 0x2,
VCD_BUFFER_INVALID = 0x3,
VCD_BUFFER_32BIT = 0x7FFFFFFF
};
struct vcd_buffer_requirement {
u32 min_count;
u32 actual_count;
u32 max_count;
size_t sz;
u32 align;
u32 buf_pool_id;
size_t meta_buffer_size;
};
struct vcd_init_config {
void *device_name;
void *(*map_dev_base_addr) (void *device_name);
void (*un_map_dev_base_addr) (void);
void (*interrupt_clr) (void);
void (*register_isr) (void *device_name);
void (*deregister_isr) (void);
u32 (*timer_create) (void (*timer_handler)(void *),
void *user_data, void **timer_handle);
void (*timer_release) (void *timer_handle);
void (*timer_start) (void *timer_handle, u32 time_out);
void (*timer_stop) (void *timer_handle);
};
/*Flags passed to vcd_open*/
#define VCD_CP_SESSION 0x00000001
u32 vcd_init(struct vcd_init_config *config, s32 *driver_handle);
u32 vcd_term(s32 driver_handle);
u32 vcd_open(s32 driver_handle, u32 decoding,
void (*callback) (u32 event, u32 status, void *info, size_t sz,
void *handle, void *const client_data), void *client_data, int flags);
u32 vcd_close(void *handle);
u32 vcd_encode_start(void *handle);
u32 vcd_encode_frame(void *handle, struct vcd_frame_data *input_frame);
u32 vcd_decode_start(void *handle, struct vcd_sequence_hdr *seq_hdr);
u32 vcd_decode_frame(void *handle, struct vcd_frame_data *input_frame);
u32 vcd_pause(void *handle);
u32 vcd_resume(void *handle);
u32 vcd_flush(void *handle, u32 mode);
u32 vcd_stop(void *handle);
u32 vcd_set_property(void *handle, struct vcd_property_hdr *prop_hdr,
void *prop_val);
u32 vcd_get_property(void *handle, struct vcd_property_hdr *prop_hdr,
void *prop_val);
u32 vcd_set_buffer_requirements(void *handle, enum vcd_buffer_type buffer,
struct vcd_buffer_requirement *buffer_req);
u32 vcd_get_buffer_requirements(void *handle, enum vcd_buffer_type buffer,
struct vcd_buffer_requirement *buffer_req);
u32 vcd_set_buffer(void *handle, enum vcd_buffer_type buffer_type,
u8 *buffer, u32 buf_size);
u32 vcd_allocate_buffer(void *handle, enum vcd_buffer_type buffer,
u32 buf_size, u8 **vir_buf_addr, u8 **phy_buf_addr);
u32 vcd_free_buffer(void *handle, enum vcd_buffer_type buffer_type, u8 *buffer);
u32 vcd_fill_output_buffer(void *handle, struct vcd_frame_data *buffer);
u32 vcd_set_device_power(s32 driver_handle,
enum vcd_power_state pwr_state);
void vcd_read_and_clear_interrupt(void);
void vcd_response_handler(void);
u8 vcd_get_num_of_clients(void);
u32 vcd_get_ion_status(void);
struct ion_client *vcd_get_ion_client(void);
#endif
kernel/include/media/msm/vcd_property.h
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/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _VCD_DRIVER_PROPERTY_H_
#define _VCD_DRIVER_PROPERTY_H_
#include <linux/types.h>
#define VCD_START_BASE 0x0
#define VCD_I_LIVE (VCD_START_BASE + 0x1)
#define VCD_I_CODEC (VCD_START_BASE + 0x2)
#define VCD_I_FRAME_SIZE (VCD_START_BASE + 0x3)
#define VCD_I_METADATA_ENABLE (VCD_START_BASE + 0x4)
#define VCD_I_METADATA_HEADER (VCD_START_BASE + 0x5)
#define VCD_I_PROFILE (VCD_START_BASE + 0x6)
#define VCD_I_LEVEL (VCD_START_BASE + 0x7)
#define VCD_I_BUFFER_FORMAT (VCD_START_BASE + 0x8)
#define VCD_I_FRAME_RATE (VCD_START_BASE + 0x9)
#define VCD_I_TARGET_BITRATE (VCD_START_BASE + 0xA)
#define VCD_I_MULTI_SLICE (VCD_START_BASE + 0xB)
#define VCD_I_ENTROPY_CTRL (VCD_START_BASE + 0xC)
#define VCD_I_DEBLOCKING (VCD_START_BASE + 0xD)
#define VCD_I_RATE_CONTROL (VCD_START_BASE + 0xE)
#define VCD_I_QP_RANGE (VCD_START_BASE + 0xF)
#define VCD_I_SESSION_QP (VCD_START_BASE + 0x10)
#define VCD_I_INTRA_PERIOD (VCD_START_BASE + 0x11)
#define VCD_I_VOP_TIMING (VCD_START_BASE + 0x12)
#define VCD_I_SHORT_HEADER (VCD_START_BASE + 0x13)
#define VCD_I_SEQ_HEADER (VCD_START_BASE + 0x14)
#define VCD_I_HEADER_EXTENSION (VCD_START_BASE + 0x15)
#define VCD_I_INTRA_REFRESH (VCD_START_BASE + 0x16)
#define VCD_I_POST_FILTER (VCD_START_BASE + 0x17)
#define VCD_I_PROGRESSIVE_ONLY (VCD_START_BASE + 0x18)
#define VCD_I_OUTPUT_ORDER (VCD_START_BASE + 0x19)
#define VCD_I_RECON_BUFFERS (VCD_START_BASE + 0x1A)
#define VCD_I_FREE_RECON_BUFFERS (VCD_START_BASE + 0x1B)
#define VCD_I_GET_RECON_BUFFER_SIZE (VCD_START_BASE + 0x1C)
#define VCD_I_H264_MV_BUFFER (VCD_START_BASE + 0x1D)
#define VCD_I_FREE_H264_MV_BUFFER (VCD_START_BASE + 0x1E)
#define VCD_I_GET_H264_MV_SIZE (VCD_START_BASE + 0x1F)
#define VCD_I_DEC_PICTYPE (VCD_START_BASE + 0x20)
#define VCD_I_CONT_ON_RECONFIG (VCD_START_BASE + 0x21)
#define VCD_I_META_BUFFER_MODE (VCD_START_BASE + 0x22)
#define VCD_I_DISABLE_DMX (VCD_START_BASE + 0x23)
#define VCD_I_DISABLE_DMX_SUPPORT (VCD_START_BASE + 0x24)
#define VCD_I_ENABLE_SPS_PPS_FOR_IDR (VCD_START_BASE + 0x25)
#define VCD_REQ_PERF_LEVEL (VCD_START_BASE + 0x26)
#define VCD_I_SLICE_DELIVERY_MODE (VCD_START_BASE + 0x27)
#define VCD_I_VOP_TIMING_CONSTANT_DELTA (VCD_START_BASE + 0x28)
#define VCD_I_SET_TURBO_CLK (VCD_START_BASE + 0x29)
#define VCD_I_ENABLE_DELIMITER_FLAG (VCD_START_BASE + 0x2A)
#define VCD_I_ENABLE_VUI_TIMING_INFO (VCD_START_BASE + 0x2B)
#define VCD_I_H263_PLUSPTYPE (VCD_START_BASE + 0x2C)
#define VCD_I_LTR_MODE (VCD_START_BASE + 0x2D)
#define VCD_I_LTR_COUNT (VCD_START_BASE + 0x2E)
#define VCD_I_LTR_PERIOD (VCD_START_BASE + 0x2F)
#define VCD_I_LTR_USE (VCD_START_BASE + 0x30)
#define VCD_I_CAPABILITY_LTR_COUNT (VCD_START_BASE + 0x31)
#define VCD_I_LTR_MARK (VCD_START_BASE + 0x32)
#define VCD_I_SET_EXT_METABUFFER (VCD_START_BASE + 0x33)
#define VCD_I_FREE_EXT_METABUFFER (VCD_START_BASE + 0x34)
#define VCD_START_REQ (VCD_START_BASE + 0x1000)
#define VCD_I_REQ_IFRAME (VCD_START_REQ + 0x1)
#define VCD_I_RESERVED_BASE (VCD_START_BASE + 0x10000)
struct vcd_property_hdr {
u32 prop_id;
size_t sz;
};
struct vcd_property_live {
u32 live;
};
enum vcd_codec {
VCD_CODEC_H264 = 0x1,
VCD_CODEC_H263 = 0x2,
VCD_CODEC_MPEG1 = 0x3,
VCD_CODEC_MPEG2 = 0x4,
VCD_CODEC_MPEG4 = 0x5,
VCD_CODEC_DIVX_3 = 0x6,
VCD_CODEC_DIVX_4 = 0x7,
VCD_CODEC_DIVX_5 = 0x8,
VCD_CODEC_DIVX_6 = 0x9,
VCD_CODEC_XVID = 0xA,
VCD_CODEC_VC1 = 0xB,
VCD_CODEC_VC1_RCV = 0xC
};
struct vcd_property_codec {
enum vcd_codec codec;
};
struct vcd_property_frame_size {
u32 width;
u32 height;
u32 stride;
u32 scan_lines;
};
enum vcd_perf_level {
VCD_PERF_LEVEL0,
VCD_PERF_LEVEL1,
VCD_PERF_LEVEL2,
VCD_PERF_LEVEL_TURBO,
};
#define VCD_METADATA_DATANONE 0x001
#define VCD_METADATA_QCOMFILLER 0x002
#define VCD_METADATA_QPARRAY 0x004
#define VCD_METADATA_CONCEALMB 0x008
#define VCD_METADATA_SEI 0x010
#define VCD_METADATA_VUI 0x020
#define VCD_METADATA_VC1 0x040
#define VCD_METADATA_PASSTHROUGH 0x080
#define VCD_METADATA_ENC_SLICE 0x100
#define VCD_METADATA_LTR_INFO 0x200
#define VCD_METADATA_EXT_DATA 0x0800
#define VCD_METADATA_USER_DATA 0x1000
#define VCD_METADATA_SEPARATE_BUF 0x2000
struct vcd_property_meta_data_enable {
u32 meta_data_enable_flag;
};
struct vcd_property_metadata_hdr {
u32 meta_data_id;
u32 version;
u32 port_index;
u32 type;
};
struct vcd_property_frame_rate {
u32 fps_denominator;
u32 fps_numerator;
};
struct vcd_property_target_bitrate {
u32 target_bitrate;
};
struct vcd_property_perf_level {
enum vcd_perf_level level;
};
enum vcd_yuv_buffer_format {
VCD_BUFFER_FORMAT_NV12 = 0x1,
VCD_BUFFER_FORMAT_TILE_4x2 = 0x2,
VCD_BUFFER_FORMAT_NV12_16M2KA = 0x3,
VCD_BUFFER_FORMAT_TILE_1x1 = 0x4
};
struct vcd_property_buffer_format {
enum vcd_yuv_buffer_format buffer_format;
};
struct vcd_property_post_filter {
u32 post_filter;
};
enum vcd_codec_profile {
VCD_PROFILE_UNKNOWN = 0x0,
VCD_PROFILE_MPEG4_SP = 0x1,
VCD_PROFILE_MPEG4_ASP = 0x2,
VCD_PROFILE_H264_BASELINE = 0x3,
VCD_PROFILE_H264_MAIN = 0x4,
VCD_PROFILE_H264_HIGH = 0x5,
VCD_PROFILE_H263_BASELINE = 0x6,
VCD_PROFILE_VC1_SIMPLE = 0x7,
VCD_PROFILE_VC1_MAIN = 0x8,
VCD_PROFILE_VC1_ADVANCE = 0x9,
VCD_PROFILE_MPEG2_MAIN = 0xA,
VCD_PROFILE_MPEG2_SIMPLE = 0xB
};
struct vcd_property_profile {
enum vcd_codec_profile profile;
};
enum vcd_codec_level {
VCD_LEVEL_UNKNOWN = 0x0,
VCD_LEVEL_MPEG4_0 = 0x1,
VCD_LEVEL_MPEG4_0b = 0x2,
VCD_LEVEL_MPEG4_1 = 0x3,
VCD_LEVEL_MPEG4_2 = 0x4,
VCD_LEVEL_MPEG4_3 = 0x5,
VCD_LEVEL_MPEG4_3b = 0x6,
VCD_LEVEL_MPEG4_4 = 0x7,
VCD_LEVEL_MPEG4_4a = 0x8,
VCD_LEVEL_MPEG4_5 = 0x9,
VCD_LEVEL_MPEG4_6 = 0xA,
VCD_LEVEL_MPEG4_7 = 0xB,
VCD_LEVEL_MPEG4_X = 0xC,
VCD_LEVEL_H264_1 = 0x10,
VCD_LEVEL_H264_1b = 0x11,
VCD_LEVEL_H264_1p1 = 0x12,
VCD_LEVEL_H264_1p2 = 0x13,
VCD_LEVEL_H264_1p3 = 0x14,
VCD_LEVEL_H264_2 = 0x15,
VCD_LEVEL_H264_2p1 = 0x16,
VCD_LEVEL_H264_2p2 = 0x17,
VCD_LEVEL_H264_3 = 0x18,
VCD_LEVEL_H264_3p1 = 0x19,
VCD_LEVEL_H264_3p2 = 0x1A,
VCD_LEVEL_H264_4 = 0x1B,
VCD_LEVEL_H264_4p1 = 0x1C,
VCD_LEVEL_H264_4p2 = 0x1D,
VCD_LEVEL_H264_5 = 0x1E,
VCD_LEVEL_H264_5p1 = 0x1F,
VCD_LEVEL_H263_10 = 0x20,
VCD_LEVEL_H263_20 = 0x21,
VCD_LEVEL_H263_30 = 0x22,
VCD_LEVEL_H263_40 = 0x23,
VCD_LEVEL_H263_45 = 0x24,
VCD_LEVEL_H263_50 = 0x25,
VCD_LEVEL_H263_60 = 0x26,
VCD_LEVEL_H263_70 = 0x27,
VCD_LEVEL_H263_X = 0x28,
VCD_LEVEL_MPEG2_LOW = 0x30,
VCD_LEVEL_MPEG2_MAIN = 0x31,
VCD_LEVEL_MPEG2_HIGH_14 = 0x32,
VCD_LEVEL_MPEG2_HIGH = 0x33,
VCD_LEVEL_MPEG2_X = 0x34,
VCD_LEVEL_VC1_S_LOW = 0x40,
VCD_LEVEL_VC1_S_MEDIUM = 0x41,
VCD_LEVEL_VC1_M_LOW = 0x42,
VCD_LEVEL_VC1_M_MEDIUM = 0x43,
VCD_LEVEL_VC1_M_HIGH = 0x44,
VCD_LEVEL_VC1_A_0 = 0x45,
VCD_LEVEL_VC1_A_1 = 0x46,
VCD_LEVEL_VC1_A_2 = 0x47,
VCD_LEVEL_VC1_A_3 = 0x48,
VCD_LEVEL_VC1_A_4 = 0x49,
VCD_LEVEL_VC1_X = 0x4A
};
struct vcd_property_level {
enum vcd_codec_level level;
};
enum vcd_m_slice_sel {
VCD_MSLICE_OFF = 0x1,
VCD_MSLICE_BY_MB_COUNT = 0x2,
VCD_MSLICE_BY_BYTE_COUNT = 0x3,
VCD_MSLICE_BY_GOB = 0x4
};
struct vcd_property_multi_slice {
enum vcd_m_slice_sel m_slice_sel;
u32 m_slice_size;
};
enum vcd_entropy_sel {
VCD_ENTROPY_SEL_CAVLC = 0x1,
VCD_ENTROPY_SEL_CABAC = 0x2
};
enum vcd_cabac_model {
VCD_CABAC_MODEL_NUMBER_0 = 0x1,
VCD_CABAC_MODEL_NUMBER_1 = 0x2,
VCD_CABAC_MODEL_NUMBER_2 = 0x3
};
struct vcd_property_entropy_control {
enum vcd_entropy_sel entropy_sel;
enum vcd_cabac_model cabac_model;
};
enum vcd_db_config {
VCD_DB_ALL_BLOCKING_BOUNDARY = 0x1,
VCD_DB_DISABLE = 0x2,
VCD_DB_SKIP_SLICE_BOUNDARY = 0x3
};
struct vcd_property_db_config {
enum vcd_db_config db_config;
u32 slice_alpha_offset;
u32 slice_beta_offset;
};
enum vcd_rate_control {
VCD_RATE_CONTROL_OFF = 0x1,
VCD_RATE_CONTROL_VBR_VFR = 0x2,
VCD_RATE_CONTROL_VBR_CFR = 0x3,
VCD_RATE_CONTROL_CBR_VFR = 0x4,
VCD_RATE_CONTROL_CBR_CFR = 0x5
};
struct vcd_property_rate_control {
enum vcd_rate_control rate_control;
};
struct vcd_property_qp_range {
u32 max_qp;
u32 min_qp;
};
struct vcd_property_plusptype {
u32 plusptype_enable;
};
struct vcd_property_session_qp {
u32 i_frame_qp;
u32 p_frame_qp;
u32 b_frame_qp;
};
struct vcd_property_i_period {
u32 p_frames;
u32 b_frames;
};
struct vcd_property_vop_timing {
u32 vop_time_resolution;
};
struct vcd_property_vop_timing_constant_delta {
u32 constant_delta; /*In usecs */
};
struct vcd_property_short_header {
u32 short_header;
};
struct vcd_property_intra_refresh_mb_number {
u32 cir_mb_number;
};
struct vcd_property_req_i_frame {
u32 req_i_frame;
};
struct vcd_frame_rect {
u32 left;
u32 top;
u32 right;
u32 bottom;
};
struct vcd_property_dec_output_buffer {
struct vcd_frame_rect disp_frm;
struct vcd_property_frame_size frm_size;
};
enum vcd_output_order {
VCD_DEC_ORDER_DISPLAY = 0x0,
VCD_DEC_ORDER_DECODE = 0x1
};
struct vcd_property_enc_recon_buffer {
u8 *user_virtual_addr;
u8 *kernel_virtual_addr;
u8 *physical_addr;
u8 *dev_addr;
u32 buffer_size;
u32 ysize;
int pmem_fd;
u32 offset;
void *client_data;
};
struct vcd_property_h264_mv_buffer {
u8 *kernel_virtual_addr;
u8 *physical_addr;
u32 size;
u32 count;
int pmem_fd;
u32 offset;
u8 *dev_addr;
void *client_data;
};
struct vcd_property_buffer_size {
int width;
int height;
int size;
int alignment;
};
struct vcd_property_sps_pps_for_idr_enable {
u32 sps_pps_for_idr_enable_flag;
};
struct vcd_property_avc_delimiter_enable {
u32 avc_delimiter_enable_flag;
};
struct vcd_property_vui_timing_info_enable {
u32 vui_timing_info;
};
struct vcd_property_range_type {
u32 min;
u32 max;
u32 step_size;
};
enum vcd_property_ltrmode {
VCD_LTR_MODE_DISABLE = 0,
VCD_LTR_MODE_MANUAL = 1,
VCD_LTR_MODE_AUTO = 2,
VCD_LTR_MODE_MAX = 0x7fffffff
};
struct vcd_property_ltrmode_type {
enum vcd_property_ltrmode ltr_mode;
};
struct vcd_property_ltrcount_type {
u32 ltr_count;
};
struct vcd_property_ltrperiod_type {
u32 ltr_period;
};
struct vcd_property_ltruse_type {
u32 ltr_id;
u32 ltr_frames;
};
struct vcd_property_meta_buffer {
u8 *kernel_virtual_addr;
u8 *physical_addr;
u32 size;
u32 count;
int pmem_fd;
u32 offset;
u8 *dev_addr;
void *client_data;
u8 *kernel_virt_addr_iommu;
u8 *physical_addr_iommu;
int pmem_fd_iommu;
u8 *dev_addr_iommu;
void *client_data_iommu;
};
#endif
kernel/include/media/msm/vcd_status.h
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/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _VCD_ERR_STATUS_H_
#define _VCD_ERR_STATUS_H_
#define VCD_EVT_RESP_BASE 0x1000
#define VCD_EVT_RESP_OPEN (VCD_EVT_RESP_BASE + 0x1)
#define VCD_EVT_RESP_START (VCD_EVT_RESP_BASE + 0x2)
#define VCD_EVT_RESP_STOP (VCD_EVT_RESP_BASE + 0x3)
#define VCD_EVT_RESP_PAUSE (VCD_EVT_RESP_BASE + 0x4)
#define VCD_EVT_RESP_FLUSH_INPUT_DONE (VCD_EVT_RESP_BASE + 0x5)
#define VCD_EVT_RESP_FLUSH_OUTPUT_DONE (VCD_EVT_RESP_BASE + 0x6)
#define VCD_EVT_RESP_INPUT_FLUSHED (VCD_EVT_RESP_BASE + 0x7)
#define VCD_EVT_RESP_OUTPUT_FLUSHED (VCD_EVT_RESP_BASE + 0x8)
#define VCD_EVT_RESP_INPUT_DONE (VCD_EVT_RESP_BASE + 0x9)
#define VCD_EVT_RESP_OUTPUT_DONE (VCD_EVT_RESP_BASE + 0xa)
#define VCD_EVT_IND_BASE 0x2000
#define VCD_EVT_IND_INPUT_RECONFIG (VCD_EVT_IND_BASE + 0x1)
#define VCD_EVT_IND_OUTPUT_RECONFIG (VCD_EVT_IND_BASE + 0x2)
#define VCD_EVT_IND_HWERRFATAL (VCD_EVT_IND_BASE + 0x3)
#define VCD_EVT_IND_RESOURCES_LOST (VCD_EVT_IND_BASE + 0x4)
#define VCD_EVT_IND_INFO_OUTPUT_RECONFIG (VCD_EVT_IND_BASE + 0x5)
#define VCD_EVT_IND_INFO_FIELD_DROPPED (VCD_EVT_IND_BASE + 0x6)
#define VCD_EVT_IND_INFO_LTRUSE_FAILED (VCD_EVT_IND_BASE + 0x7)
#define VCD_S_SUCCESS 0x0
#define VCD_S_ERR_BASE 0x80000000
#define VCD_ERR_FAIL (VCD_S_ERR_BASE + 0x01)
#define VCD_ERR_ALLOC_FAIL (VCD_S_ERR_BASE + 0x02)
#define VCD_ERR_ILLEGAL_OP (VCD_S_ERR_BASE + 0x03)
#define VCD_ERR_ILLEGAL_PARM (VCD_S_ERR_BASE + 0x04)
#define VCD_ERR_BAD_POINTER (VCD_S_ERR_BASE + 0x05)
#define VCD_ERR_BAD_HANDLE (VCD_S_ERR_BASE + 0x06)
#define VCD_ERR_NOT_SUPPORTED (VCD_S_ERR_BASE + 0x07)
#define VCD_ERR_BAD_STATE (VCD_S_ERR_BASE + 0x08)
#define VCD_ERR_BUSY (VCD_S_ERR_BASE + 0x09)
#define VCD_ERR_MAX_CLIENT (VCD_S_ERR_BASE + 0x0a)
#define VCD_ERR_IFRAME_EXPECTED (VCD_S_ERR_BASE + 0x0b)
#define VCD_ERR_INTRLCD_FIELD_DROP (VCD_S_ERR_BASE + 0x0c)
#define VCD_ERR_HW_FATAL (VCD_S_ERR_BASE + 0x0d)
#define VCD_ERR_BITSTREAM_ERR (VCD_S_ERR_BASE + 0x0e)
#define VCD_ERR_QEMPTY (VCD_S_ERR_BASE + 0x0f)
#define VCD_ERR_SEQHDR_PARSE_FAIL (VCD_S_ERR_BASE + 0x10)
#define VCD_ERR_INPUT_NOT_PROCESSED (VCD_S_ERR_BASE + 0x11)
#define VCD_ERR_INDEX_NOMORE (VCD_S_ERR_BASE + 0x12)
#define VCD_FAILED(rc) ((rc > VCD_S_ERR_BASE) ? true : false)
#endif
kernel/include/media/msm/vidc_init.h
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/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef VIDC_INIT_H
#define VIDC_INIT_H
#include <linux/msm_ion.h>
#include <media/msm/vidc_type.h>
#include <media/msm/vcd_property.h>
#define VIDC_MAX_NUM_CLIENTS 4
#define MAX_VIDEO_NUM_OF_BUFF 100
#define MAX_META_BUFFERS 32
enum buffer_dir {
BUFFER_TYPE_INPUT,
BUFFER_TYPE_OUTPUT
};
struct buf_addr_table {
unsigned long user_vaddr;
unsigned long kernel_vaddr;
unsigned long phy_addr;
unsigned long buff_ion_flag;
struct ion_handle *buff_ion_handle;
int pmem_fd;
struct file *file;
unsigned long dev_addr;
void *client_data;
};
struct meta_buffer_addr_table {
u8 *kernel_vir_addr;
u8 *kernel_vir_addr_iommu;
};
struct video_client_ctx {
void *vcd_handle;
u32 num_of_input_buffers;
u32 num_of_output_buffers;
struct buf_addr_table input_buf_addr_table[MAX_VIDEO_NUM_OF_BUFF];
struct buf_addr_table output_buf_addr_table[MAX_VIDEO_NUM_OF_BUFF];
struct list_head msg_queue;
struct mutex msg_queue_lock;
struct mutex enrty_queue_lock;
wait_queue_head_t msg_wait;
struct completion event;
struct vcd_property_h264_mv_buffer vcd_h264_mv_buffer;
struct vcd_property_meta_buffer vcd_meta_buffer;
struct vcd_property_enc_recon_buffer recon_buffer[4];
u32 event_status;
u32 seq_header_set;
u32 stop_msg;
u32 stop_called;
u32 stop_sync_cb;
size_t meta_buf_size;
struct ion_client *user_ion_client;
struct ion_handle *seq_hdr_ion_handle;
struct ion_handle *h264_mv_ion_handle;
struct ion_handle *recon_buffer_ion_handle[4];
struct ion_handle *meta_buffer_ion_handle;
struct ion_handle *meta_buffer_iommu_ion_handle;
u32 dmx_disable;
struct meta_buffer_addr_table meta_addr_table[MAX_META_BUFFERS];
};
void __iomem *vidc_get_ioaddr(void);
int vidc_load_firmware(void);
void vidc_release_firmware(void);
u32 vidc_get_fd_info(struct video_client_ctx *client_ctx,
enum buffer_dir buffer, int pmem_fd,
unsigned long kvaddr, int index,
struct ion_handle **buff_handle);
u32 vidc_lookup_addr_table(struct video_client_ctx *client_ctx,
enum buffer_dir buffer, u32 search_with_user_vaddr,
unsigned long *user_vaddr, unsigned long *kernel_vaddr,
unsigned long *phy_addr, int *pmem_fd, struct file **file,
s32 *buffer_index);
u32 vidc_insert_addr_table(struct video_client_ctx *client_ctx,
enum buffer_dir buffer, unsigned long user_vaddr,
unsigned long *kernel_vaddr, int pmem_fd,
unsigned long buffer_addr_offset,
unsigned int max_num_buffers, unsigned long length);
u32 vidc_insert_addr_table_kernel(struct video_client_ctx *client_ctx,
enum buffer_dir buffer, unsigned long user_vaddr,
unsigned long kernel_vaddr, unsigned long phys_addr,
unsigned int max_num_buffers,
unsigned long length);
u32 vidc_delete_addr_table(struct video_client_ctx *client_ctx,
enum buffer_dir buffer, unsigned long user_vaddr,
unsigned long *kernel_vaddr);
void vidc_cleanup_addr_table(struct video_client_ctx *client_ctx,
enum buffer_dir buffer);
u32 vidc_timer_create(void (*timer_handler)(void *),
void *user_data, void **timer_handle);
void vidc_timer_release(void *timer_handle);
void vidc_timer_start(void *timer_handle, u32 time_out);
void vidc_timer_stop(void *timer_handle);
#endif
kernel/include/media/msm/vidc_type.h
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/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef VIDC_TYPE_H
#define VIDC_TYPE_H
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mutex.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/list.h>
#include <linux/time.h>
#include <linux/dma-mapping.h>
#define DDL_MSG_LOG 0
#define DEBUG 0
#define VIDC_ENABLE_DBGFS
#define USE_RES_TRACKER
#endif
kernel/include/media/msm_cam_sensor.h
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#ifndef __LINUX_MSM_CAM_SENSOR_H
#define __LINUX_MSM_CAM_SENSOR_H
#ifdef MSM_CAMERA_BIONIC
#include <sys/types.h>
#endif
#include <linux/types.h>
#include <linux/v4l2-mediabus.h>
#include <linux/i2c.h>
#define I2C_SEQ_REG_SETTING_MAX 5
#define I2C_SEQ_REG_DATA_MAX 20
#define MAX_CID 16
#define MSM_SENSOR_MCLK_8HZ 8000000
#define MSM_SENSOR_MCLK_16HZ 16000000
#define MSM_SENSOR_MCLK_24HZ 24000000
#define GPIO_OUT_LOW (0 << 1)
#define GPIO_OUT_HIGH (1 << 1)
#define CSI_EMBED_DATA 0x12
#define CSI_RESERVED_DATA_0 0x13
#define CSI_YUV422_8 0x1E
#define CSI_RAW8 0x2A
#define CSI_RAW10 0x2B
#define CSI_RAW12 0x2C
#define CSI_DECODE_6BIT 0
#define CSI_DECODE_8BIT 1
#define CSI_DECODE_10BIT 2
#define CSI_DECODE_DPCM_10_8_10 5
#define MAX_SENSOR_NAME 32
#define MAX_ACT_MOD_NAME_SIZE 32
#define MAX_ACT_NAME_SIZE 32
#define NUM_ACTUATOR_DIR 2
#define MAX_ACTUATOR_SCENARIO 8
#define MAX_ACTUATOR_REGION 5
#define MAX_ACTUATOR_INIT_SET 12
#define MAX_ACTUATOR_REG_TBL_SIZE 8
#define MOVE_NEAR 0
#define MOVE_FAR 1
#define MAX_EEPROM_NAME 32
enum msm_camera_i2c_reg_addr_type {
MSM_CAMERA_I2C_BYTE_ADDR = 1,
MSM_CAMERA_I2C_WORD_ADDR,
MSM_CAMERA_I2C_3B_ADDR,
};
enum msm_camera_i2c_data_type {
MSM_CAMERA_I2C_BYTE_DATA = 1,
MSM_CAMERA_I2C_WORD_DATA,
MSM_CAMERA_I2C_SET_BYTE_MASK,
MSM_CAMERA_I2C_UNSET_BYTE_MASK,
MSM_CAMERA_I2C_SET_WORD_MASK,
MSM_CAMERA_I2C_UNSET_WORD_MASK,
MSM_CAMERA_I2C_SET_BYTE_WRITE_MASK_DATA,
};
enum msm_sensor_power_seq_type_t {
SENSOR_CLK,
SENSOR_GPIO,
SENSOR_VREG,
SENSOR_I2C_MUX,
};
enum msm_sensor_clk_type_t {
SENSOR_CAM_MCLK,
SENSOR_CAM_CLK,
SENSOR_CAM_CLK_MAX,
};
enum msm_sensor_power_seq_gpio_t {
SENSOR_GPIO_RESET,
SENSOR_GPIO_STANDBY,
SENSOR_GPIO_MAX,
};
enum msm_camera_vreg_name_t {
CAM_VDIG,
CAM_VIO,
CAM_VANA,
CAM_VAF,
CAM_VREG_MAX,
};
enum msm_sensor_resolution_t {
MSM_SENSOR_RES_FULL,
MSM_SENSOR_RES_QTR,
MSM_SENSOR_RES_2,
MSM_SENSOR_RES_3,
MSM_SENSOR_RES_4,
MSM_SENSOR_RES_5,
MSM_SENSOR_RES_6,
MSM_SENSOR_RES_7,
MSM_SENSOR_INVALID_RES,
};
enum sensor_sub_module_t {
SUB_MODULE_SENSOR,
SUB_MODULE_CHROMATIX,
SUB_MODULE_ACTUATOR,
SUB_MODULE_EEPROM,
SUB_MODULE_LED_FLASH,
SUB_MODULE_STROBE_FLASH,
SUB_MODULE_CSID,
SUB_MODULE_CSID_3D,
SUB_MODULE_CSIPHY,
SUB_MODULE_CSIPHY_3D,
SUB_MODULE_MAX,
};
enum csid_cfg_type_t {
CSID_INIT,
CSID_CFG,
CSID_RELEASE,
};
enum csiphy_cfg_type_t {
CSIPHY_INIT,
CSIPHY_CFG,
CSIPHY_RELEASE,
};
enum camera_vreg_type {
REG_LDO,
REG_VS,
REG_GPIO,
};
struct msm_sensor_power_setting {
enum msm_sensor_power_seq_type_t seq_type;
uint16_t seq_val;
long config_val;
uint16_t delay;
void *data[10];
};
struct msm_sensor_power_setting_array {
struct msm_sensor_power_setting *power_setting;
uint16_t size;
};
struct msm_sensor_id_info_t {
uint16_t sensor_id_reg_addr;
uint16_t sensor_id;
};
struct msm_camera_sensor_slave_info {
uint16_t slave_addr;
enum msm_camera_i2c_reg_addr_type addr_type;
struct msm_sensor_id_info_t sensor_id_info;
struct msm_sensor_power_setting_array power_setting_array;
};
struct msm_camera_i2c_reg_array {
uint16_t reg_addr;
uint16_t reg_data;
};
struct msm_camera_i2c_reg_setting {
struct msm_camera_i2c_reg_array *reg_setting;
uint16_t size;
enum msm_camera_i2c_reg_addr_type addr_type;
enum msm_camera_i2c_data_type data_type;
uint16_t delay;
};
struct msm_camera_i2c_seq_reg_array {
uint16_t reg_addr;
uint8_t reg_data[I2C_SEQ_REG_DATA_MAX];
uint16_t reg_data_size;
};
struct msm_camera_i2c_seq_reg_setting {
struct msm_camera_i2c_seq_reg_array *reg_setting;
uint16_t size;
enum msm_camera_i2c_reg_addr_type addr_type;
uint16_t delay;
};
struct msm_camera_i2c_array_write_config {
struct msm_camera_i2c_reg_setting conf_array;
uint16_t slave_addr;
};
struct msm_camera_i2c_read_config {
uint16_t slave_addr;
uint16_t reg_addr;
enum msm_camera_i2c_data_type data_type;
uint16_t *data;
};
struct msm_camera_csid_vc_cfg {
uint8_t cid;
uint8_t dt;
uint8_t decode_format;
};
struct msm_camera_csid_lut_params {
uint8_t num_cid;
struct msm_camera_csid_vc_cfg *vc_cfg[MAX_CID];
};
struct msm_camera_csid_params {
uint8_t lane_cnt;
uint16_t lane_assign;
uint8_t phy_sel;
struct msm_camera_csid_lut_params lut_params;
};
struct msm_camera_csiphy_params {
uint8_t lane_cnt;
uint8_t settle_cnt;
uint16_t lane_mask;
uint8_t combo_mode;
uint8_t csid_core;
};
struct msm_camera_csi2_params {
struct msm_camera_csid_params csid_params;
struct msm_camera_csiphy_params csiphy_params;
};
struct msm_camera_csi_lane_params {
uint16_t csi_lane_assign;
uint16_t csi_lane_mask;
};
struct csi_lane_params_t {
uint16_t csi_lane_assign;
uint8_t csi_lane_mask;
uint8_t csi_if;
uint8_t csid_core[2];
uint8_t csi_phy_sel;
};
struct msm_sensor_info_t {
char sensor_name[MAX_SENSOR_NAME];
int32_t session_id;
int32_t subdev_id[SUB_MODULE_MAX];
};
struct camera_vreg_t {
const char *reg_name;
enum camera_vreg_type type;
int min_voltage;
int max_voltage;
int op_mode;
uint32_t delay;
};
enum camb_position_t {
BACK_CAMERA_B,
FRONT_CAMERA_B,
};
enum camerab_mode_t {
CAMERA_MODE_2D_B = (1<<0),
CAMERA_MODE_3D_B = (1<<1)
};
struct msm_sensor_init_params {
/* mask of modes supported: 2D, 3D */
int modes_supported;
/* sensor position: front, back */
enum camb_position_t position;
/* sensor mount angle */
uint32_t sensor_mount_angle;
};
struct sensorb_cfg_data {
int cfgtype;
union {
struct msm_sensor_info_t sensor_info;
struct msm_sensor_init_params sensor_init_params;
void *setting;
} cfg;
};
struct csid_cfg_data {
enum csid_cfg_type_t cfgtype;
union {
uint32_t csid_version;
struct msm_camera_csid_params *csid_params;
} cfg;
};
struct csiphy_cfg_data {
enum csiphy_cfg_type_t cfgtype;
union {
struct msm_camera_csiphy_params *csiphy_params;
struct msm_camera_csi_lane_params *csi_lane_params;
} cfg;
};
enum eeprom_cfg_type_t {
CFG_EEPROM_GET_INFO,
CFG_EEPROM_GET_CAL_DATA,
CFG_EEPROM_READ_CAL_DATA,
CFG_EEPROM_WRITE_DATA,
};
struct eeprom_get_t {
uint16_t num_bytes;
};
struct eeprom_read_t {
uint8_t *dbuffer;
uint16_t num_bytes;
};
struct eeprom_write_t {
uint8_t *dbuffer;
uint16_t num_bytes;
};
struct msm_eeprom_cfg_data {
enum eeprom_cfg_type_t cfgtype;
uint8_t is_supported;
union {
char eeprom_name[MAX_SENSOR_NAME];
struct eeprom_get_t get_data;
struct eeprom_read_t read_data;
struct eeprom_write_t write_data;
} cfg;
};
enum msm_sensor_cfg_type_t {
CFG_SET_SLAVE_INFO,
CFG_SLAVE_READ_I2C,
CFG_WRITE_I2C_ARRAY,
CFG_SLAVE_WRITE_I2C_ARRAY,
CFG_WRITE_I2C_SEQ_ARRAY,
CFG_POWER_UP,
CFG_POWER_DOWN,
CFG_SET_STOP_STREAM_SETTING,
CFG_GET_SENSOR_INFO,
CFG_GET_SENSOR_INIT_PARAMS,
CFG_SET_INIT_SETTING,
CFG_SET_RESOLUTION,
CFG_SET_STOP_STREAM,
CFG_SET_START_STREAM,
};
enum msm_actuator_cfg_type_t {
CFG_GET_ACTUATOR_INFO,
CFG_SET_ACTUATOR_INFO,
CFG_SET_DEFAULT_FOCUS,
CFG_MOVE_FOCUS,
};
enum actuator_type {
ACTUATOR_VCM,
ACTUATOR_PIEZO,
};
enum msm_actuator_data_type {
MSM_ACTUATOR_BYTE_DATA = 1,
MSM_ACTUATOR_WORD_DATA,
};
enum msm_actuator_addr_type {
MSM_ACTUATOR_BYTE_ADDR = 1,
MSM_ACTUATOR_WORD_ADDR,
};
struct reg_settings_t {
uint16_t reg_addr;
uint16_t reg_data;
};
struct region_params_t {
/* [0] = ForwardDirection Macro boundary
[1] = ReverseDirection Inf boundary
*/
uint16_t step_bound[2];
uint16_t code_per_step;
};
struct damping_params_t {
uint32_t damping_step;
uint32_t damping_delay;
uint32_t hw_params;
};
struct msm_actuator_move_params_t {
int8_t dir;
int8_t sign_dir;
int16_t dest_step_pos;
int32_t num_steps;
struct damping_params_t *ringing_params;
};
struct msm_actuator_tuning_params_t {
int16_t initial_code;
uint16_t pwd_step;
uint16_t region_size;
uint32_t total_steps;
struct region_params_t *region_params;
};
struct msm_actuator_params_t {
enum actuator_type act_type;
uint8_t reg_tbl_size;
uint16_t data_size;
uint16_t init_setting_size;
uint32_t i2c_addr;
enum msm_actuator_addr_type i2c_addr_type;
enum msm_actuator_data_type i2c_data_type;
struct msm_actuator_reg_params_t *reg_tbl_params;
struct reg_settings_t *init_settings;
};
struct msm_actuator_set_info_t {
struct msm_actuator_params_t actuator_params;
struct msm_actuator_tuning_params_t af_tuning_params;
};
struct msm_actuator_get_info_t {
uint32_t focal_length_num;
uint32_t focal_length_den;
uint32_t f_number_num;
uint32_t f_number_den;
uint32_t f_pix_num;
uint32_t f_pix_den;
uint32_t total_f_dist_num;
uint32_t total_f_dist_den;
uint32_t hor_view_angle_num;
uint32_t hor_view_angle_den;
uint32_t ver_view_angle_num;
uint32_t ver_view_angle_den;
};
enum af_camera_name {
ACTUATOR_MAIN_CAM_0,
ACTUATOR_MAIN_CAM_1,
ACTUATOR_MAIN_CAM_2,
ACTUATOR_MAIN_CAM_3,
ACTUATOR_MAIN_CAM_4,
ACTUATOR_MAIN_CAM_5,
ACTUATOR_WEB_CAM_0,
ACTUATOR_WEB_CAM_1,
ACTUATOR_WEB_CAM_2,
};
struct msm_actuator_cfg_data {
int cfgtype;
uint8_t is_af_supported;
union {
struct msm_actuator_move_params_t move;
struct msm_actuator_set_info_t set_info;
struct msm_actuator_get_info_t get_info;
enum af_camera_name cam_name;
} cfg;
};
enum msm_actuator_write_type {
MSM_ACTUATOR_WRITE_HW_DAMP,
MSM_ACTUATOR_WRITE_DAC,
};
struct msm_actuator_reg_params_t {
enum msm_actuator_write_type reg_write_type;
uint32_t hw_mask;
uint16_t reg_addr;
uint16_t hw_shift;
uint16_t data_shift;
};
enum msm_camera_led_config_t {
MSM_CAMERA_LED_OFF,
MSM_CAMERA_LED_LOW,
MSM_CAMERA_LED_HIGH,
MSM_CAMERA_LED_INIT,
MSM_CAMERA_LED_RELEASE,
};
struct msm_camera_led_cfg_t {
enum msm_camera_led_config_t cfgtype;
};
#define VIDIOC_MSM_SENSOR_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct sensorb_cfg_data)
#define VIDIOC_MSM_SENSOR_RELEASE \
_IO('V', BASE_VIDIOC_PRIVATE + 2)
#define VIDIOC_MSM_SENSOR_GET_SUBDEV_ID \
_IOWR('V', BASE_VIDIOC_PRIVATE + 3, uint32_t)
#define VIDIOC_MSM_CSIPHY_IO_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct csid_cfg_data)
#define VIDIOC_MSM_CSID_IO_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct csiphy_cfg_data)
#define VIDIOC_MSM_ACTUATOR_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_actuator_cfg_data)
#define VIDIOC_MSM_FLASH_LED_DATA_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_led_cfg_t)
#define VIDIOC_MSM_EEPROM_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_eeprom_cfg_data)
#define MSM_V4L2_PIX_FMT_META v4l2_fourcc('M', 'E', 'T', 'A') /* META */
#endif /* __LINUX_MSM_CAM_SENSOR_H */
kernel/include/media/msm_camera.h
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kernel/include/media/msm_gemini.h
+123
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#ifndef __LINUX_MSM_GEMINI_H
#define __LINUX_MSM_GEMINI_H
#include <linux/types.h>
#include <linux/ioctl.h>
#define MSM_GMN_IOCTL_MAGIC 'g'
#define MSM_GMN_IOCTL_GET_HW_VERSION \
_IOW(MSM_GMN_IOCTL_MAGIC, 1, struct msm_gemini_hw_cmd *)
#define MSM_GMN_IOCTL_RESET \
_IOW(MSM_GMN_IOCTL_MAGIC, 2, struct msm_gemini_ctrl_cmd *)
#define MSM_GMN_IOCTL_STOP \
_IOW(MSM_GMN_IOCTL_MAGIC, 3, struct msm_gemini_hw_cmds *)
#define MSM_GMN_IOCTL_START \
_IOW(MSM_GMN_IOCTL_MAGIC, 4, struct msm_gemini_hw_cmds *)
#define MSM_GMN_IOCTL_INPUT_BUF_ENQUEUE \
_IOW(MSM_GMN_IOCTL_MAGIC, 5, struct msm_gemini_buf *)
#define MSM_GMN_IOCTL_INPUT_GET \
_IOW(MSM_GMN_IOCTL_MAGIC, 6, struct msm_gemini_buf *)
#define MSM_GMN_IOCTL_INPUT_GET_UNBLOCK \
_IOW(MSM_GMN_IOCTL_MAGIC, 7, int)
#define MSM_GMN_IOCTL_OUTPUT_BUF_ENQUEUE \
_IOW(MSM_GMN_IOCTL_MAGIC, 8, struct msm_gemini_buf *)
#define MSM_GMN_IOCTL_OUTPUT_GET \
_IOW(MSM_GMN_IOCTL_MAGIC, 9, struct msm_gemini_buf *)
#define MSM_GMN_IOCTL_OUTPUT_GET_UNBLOCK \
_IOW(MSM_GMN_IOCTL_MAGIC, 10, int)
#define MSM_GMN_IOCTL_EVT_GET \
_IOW(MSM_GMN_IOCTL_MAGIC, 11, struct msm_gemini_ctrl_cmd *)
#define MSM_GMN_IOCTL_EVT_GET_UNBLOCK \
_IOW(MSM_GMN_IOCTL_MAGIC, 12, int)
#define MSM_GMN_IOCTL_HW_CMD \
_IOW(MSM_GMN_IOCTL_MAGIC, 13, struct msm_gemini_hw_cmd *)
#define MSM_GMN_IOCTL_HW_CMDS \
_IOW(MSM_GMN_IOCTL_MAGIC, 14, struct msm_gemini_hw_cmds *)
#define MSM_GMN_IOCTL_TEST_DUMP_REGION \
_IOW(MSM_GMN_IOCTL_MAGIC, 15, unsigned long)
#define MSM_GMN_IOCTL_SET_MODE \
_IOW(MSM_GMN_IOCTL_MAGIC, 16, enum msm_gmn_out_mode)
#define MSM_GEMINI_MODE_REALTIME_ENCODE 0
#define MSM_GEMINI_MODE_OFFLINE_ENCODE 1
#define MSM_GEMINI_MODE_REALTIME_ROTATION 2
#define MSM_GEMINI_MODE_OFFLINE_ROTATION 3
enum msm_gmn_out_mode {
MSM_GMN_OUTMODE_FRAGMENTED,
MSM_GMN_OUTMODE_SINGLE
};
struct msm_gemini_ctrl_cmd {
uint32_t type;
uint32_t len;
void *value;
};
#define MSM_GEMINI_EVT_RESET 0
#define MSM_GEMINI_EVT_FRAMEDONE 1
#define MSM_GEMINI_EVT_ERR 2
struct msm_gemini_buf {
uint32_t type;
int fd;
void *vaddr;
uint32_t y_off;
uint32_t y_len;
uint32_t framedone_len;
uint32_t cbcr_off;
uint32_t cbcr_len;
uint32_t num_of_mcu_rows;
uint32_t offset;
};
#define MSM_GEMINI_HW_CMD_TYPE_READ 0
#define MSM_GEMINI_HW_CMD_TYPE_WRITE 1
#define MSM_GEMINI_HW_CMD_TYPE_WRITE_OR 2
#define MSM_GEMINI_HW_CMD_TYPE_UWAIT 3
#define MSM_GEMINI_HW_CMD_TYPE_MWAIT 4
#define MSM_GEMINI_HW_CMD_TYPE_MDELAY 5
#define MSM_GEMINI_HW_CMD_TYPE_UDELAY 6
struct msm_gemini_hw_cmd {
uint32_t type:4;
/* n microseconds of timeout for WAIT */
/* n microseconds of time for DELAY */
/* repeat n times for READ/WRITE */
/* max is 0xFFF, 4095 */
uint32_t n:12;
uint32_t offset:16;
uint32_t mask;
union {
uint32_t data; /* for single READ/WRITE/WAIT, n = 1 */
uint32_t *pdata; /* for multiple READ/WRITE/WAIT, n > 1 */
};
};
struct msm_gemini_hw_cmds {
uint32_t m; /* number of elements in the hw_cmd array */
struct msm_gemini_hw_cmd hw_cmd[1];
};
#endif /* __LINUX_MSM_GEMINI_H */
kernel/include/media/msm_gestures.h
+54
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#ifndef __LINUX_MSM_GESTURES_H
#define __LINUX_MSM_GESTURES_H
#include <linux/types.h>
#include <linux/ioctl.h>
#include <media/msm_camera.h>
#define MSM_GES_IOCTL_CTRL_COMMAND \
_IOW('V', BASE_VIDIOC_PRIVATE + 20, struct v4l2_control)
#define VIDIOC_MSM_GESTURE_EVT \
_IOWR('V', BASE_VIDIOC_PRIVATE + 21, struct v4l2_event)
#define MSM_GES_GET_EVT_PAYLOAD \
_IOW('V', BASE_VIDIOC_PRIVATE + 22, struct msm_ges_evt)
#define VIDIOC_MSM_GESTURE_CAM_EVT \
_IOWR('V', BASE_VIDIOC_PRIVATE + 23, int)
#define MSM_GES_RESP_V4L2 MSM_CAM_RESP_MAX
#define MSM_GES_RESP_MAX (MSM_GES_RESP_V4L2 + 1)
#define MSM_SVR_RESP_MAX MSM_GES_RESP_MAX
#define MSM_V4L2_GES_BASE 100
#define MSM_V4L2_GES_OPEN (MSM_V4L2_GES_BASE + 0)
#define MSM_V4L2_GES_CLOSE (MSM_V4L2_GES_BASE + 1)
#define MSM_V4L2_GES_CAM_OPEN (MSM_V4L2_GES_BASE + 2)
#define MSM_V4L2_GES_CAM_CLOSE (MSM_V4L2_GES_BASE + 3)
#define MSM_GES_APP_EVT_MIN (V4L2_EVENT_PRIVATE_START + 0x14)
#define MSM_GES_APP_NOTIFY_EVENT (MSM_GES_APP_EVT_MIN + 0)
#define MSM_GES_APP_NOTIFY_ERROR_EVENT (MSM_GES_APP_EVT_MIN + 1)
#define MSM_GES_APP_EVT_MAX (MSM_GES_APP_EVT_MIN + 2)
#define MSM_GESTURE_CID_CTRL_CMD V4L2_CID_BRIGHTNESS
#define MAX_GES_EVENTS 25
struct msm_ges_ctrl_cmd {
int type;
void *value;
int len;
int fd;
uint32_t cookie;
};
struct msm_ges_evt {
void *evt_data;
int evt_len;
};
#endif /*__LINUX_MSM_GESTURES_H*/
kernel/include/media/msm_isp.h
+344
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#ifndef __MSM_ISP_H__
#define __MSM_ISP_H__
#define BIT(nr) (1UL << (nr))
/* ISP message IDs */
#define MSG_ID_RESET_ACK 0
#define MSG_ID_START_ACK 1
#define MSG_ID_STOP_ACK 2
#define MSG_ID_UPDATE_ACK 3
#define MSG_ID_OUTPUT_P 4
#define MSG_ID_OUTPUT_T 5
#define MSG_ID_OUTPUT_S 6
#define MSG_ID_OUTPUT_V 7
#define MSG_ID_SNAPSHOT_DONE 8
#define MSG_ID_STATS_AEC 9
#define MSG_ID_STATS_AF 10
#define MSG_ID_STATS_AWB 11
#define MSG_ID_STATS_RS 12
#define MSG_ID_STATS_CS 13
#define MSG_ID_STATS_IHIST 14
#define MSG_ID_STATS_SKIN 15
#define MSG_ID_EPOCH1 16
#define MSG_ID_EPOCH2 17
#define MSG_ID_SYNC_TIMER0_DONE 18
#define MSG_ID_SYNC_TIMER1_DONE 19
#define MSG_ID_SYNC_TIMER2_DONE 20
#define MSG_ID_ASYNC_TIMER0_DONE 21
#define MSG_ID_ASYNC_TIMER1_DONE 22
#define MSG_ID_ASYNC_TIMER2_DONE 23
#define MSG_ID_ASYNC_TIMER3_DONE 24
#define MSG_ID_AE_OVERFLOW 25
#define MSG_ID_AF_OVERFLOW 26
#define MSG_ID_AWB_OVERFLOW 27
#define MSG_ID_RS_OVERFLOW 28
#define MSG_ID_CS_OVERFLOW 29
#define MSG_ID_IHIST_OVERFLOW 30
#define MSG_ID_SKIN_OVERFLOW 31
#define MSG_ID_AXI_ERROR 32
#define MSG_ID_CAMIF_OVERFLOW 33
#define MSG_ID_VIOLATION 34
#define MSG_ID_CAMIF_ERROR 35
#define MSG_ID_BUS_OVERFLOW 36
#define MSG_ID_SOF_ACK 37
#define MSG_ID_STOP_REC_ACK 38
#define MSG_ID_STATS_AWB_AEC 39
#define MSG_ID_OUTPUT_PRIMARY 40
#define MSG_ID_OUTPUT_SECONDARY 41
#define MSG_ID_STATS_COMPOSITE 42
#define MSG_ID_OUTPUT_TERTIARY1 43
#define MSG_ID_STOP_LS_ACK 44
#define MSG_ID_OUTPUT_TERTIARY2 45
#define MSG_ID_STATS_BG 46
#define MSG_ID_STATS_BF 47
#define MSG_ID_STATS_BHIST 48
#define MSG_ID_RDI0_UPDATE_ACK 49
#define MSG_ID_RDI1_UPDATE_ACK 50
#define MSG_ID_RDI2_UPDATE_ACK 51
#define MSG_ID_PIX0_UPDATE_ACK 52
#define MSG_ID_PREV_STOP_ACK 53
#define MSG_ID_STATS_BE 54
/* ISP command IDs */
#define VFE_CMD_DUMMY_0 0
#define VFE_CMD_SET_CLK 1
#define VFE_CMD_RESET 2
#define VFE_CMD_START 3
#define VFE_CMD_TEST_GEN_START 4
#define VFE_CMD_OPERATION_CFG 5
#define VFE_CMD_AXI_OUT_CFG 6
#define VFE_CMD_CAMIF_CFG 7
#define VFE_CMD_AXI_INPUT_CFG 8
#define VFE_CMD_BLACK_LEVEL_CFG 9
#define VFE_CMD_MESH_ROLL_OFF_CFG 10
#define VFE_CMD_DEMUX_CFG 11
#define VFE_CMD_FOV_CFG 12
#define VFE_CMD_MAIN_SCALER_CFG 13
#define VFE_CMD_WB_CFG 14
#define VFE_CMD_COLOR_COR_CFG 15
#define VFE_CMD_RGB_G_CFG 16
#define VFE_CMD_LA_CFG 17
#define VFE_CMD_CHROMA_EN_CFG 18
#define VFE_CMD_CHROMA_SUP_CFG 19
#define VFE_CMD_MCE_CFG 20
#define VFE_CMD_SK_ENHAN_CFG 21
#define VFE_CMD_ASF_CFG 22
#define VFE_CMD_S2Y_CFG 23
#define VFE_CMD_S2CbCr_CFG 24
#define VFE_CMD_CHROMA_SUBS_CFG 25
#define VFE_CMD_OUT_CLAMP_CFG 26
#define VFE_CMD_FRAME_SKIP_CFG 27
#define VFE_CMD_DUMMY_1 28
#define VFE_CMD_DUMMY_2 29
#define VFE_CMD_DUMMY_3 30
#define VFE_CMD_UPDATE 31
#define VFE_CMD_BL_LVL_UPDATE 32
#define VFE_CMD_DEMUX_UPDATE 33
#define VFE_CMD_FOV_UPDATE 34
#define VFE_CMD_MAIN_SCALER_UPDATE 35
#define VFE_CMD_WB_UPDATE 36
#define VFE_CMD_COLOR_COR_UPDATE 37
#define VFE_CMD_RGB_G_UPDATE 38
#define VFE_CMD_LA_UPDATE 39
#define VFE_CMD_CHROMA_EN_UPDATE 40
#define VFE_CMD_CHROMA_SUP_UPDATE 41
#define VFE_CMD_MCE_UPDATE 42
#define VFE_CMD_SK_ENHAN_UPDATE 43
#define VFE_CMD_S2CbCr_UPDATE 44
#define VFE_CMD_S2Y_UPDATE 45
#define VFE_CMD_ASF_UPDATE 46
#define VFE_CMD_FRAME_SKIP_UPDATE 47
#define VFE_CMD_CAMIF_FRAME_UPDATE 48
#define VFE_CMD_STATS_AF_UPDATE 49
#define VFE_CMD_STATS_AE_UPDATE 50
#define VFE_CMD_STATS_AWB_UPDATE 51
#define VFE_CMD_STATS_RS_UPDATE 52
#define VFE_CMD_STATS_CS_UPDATE 53
#define VFE_CMD_STATS_SKIN_UPDATE 54
#define VFE_CMD_STATS_IHIST_UPDATE 55
#define VFE_CMD_DUMMY_4 56
#define VFE_CMD_EPOCH1_ACK 57
#define VFE_CMD_EPOCH2_ACK 58
#define VFE_CMD_START_RECORDING 59
#define VFE_CMD_STOP_RECORDING 60
#define VFE_CMD_DUMMY_5 61
#define VFE_CMD_DUMMY_6 62
#define VFE_CMD_CAPTURE 63
#define VFE_CMD_DUMMY_7 64
#define VFE_CMD_STOP 65
#define VFE_CMD_GET_HW_VERSION 66
#define VFE_CMD_GET_FRAME_SKIP_COUNTS 67
#define VFE_CMD_OUTPUT1_BUFFER_ENQ 68
#define VFE_CMD_OUTPUT2_BUFFER_ENQ 69
#define VFE_CMD_OUTPUT3_BUFFER_ENQ 70
#define VFE_CMD_JPEG_OUT_BUF_ENQ 71
#define VFE_CMD_RAW_OUT_BUF_ENQ 72
#define VFE_CMD_RAW_IN_BUF_ENQ 73
#define VFE_CMD_STATS_AF_ENQ 74
#define VFE_CMD_STATS_AE_ENQ 75
#define VFE_CMD_STATS_AWB_ENQ 76
#define VFE_CMD_STATS_RS_ENQ 77
#define VFE_CMD_STATS_CS_ENQ 78
#define VFE_CMD_STATS_SKIN_ENQ 79
#define VFE_CMD_STATS_IHIST_ENQ 80
#define VFE_CMD_DUMMY_8 81
#define VFE_CMD_JPEG_ENC_CFG 82
#define VFE_CMD_DUMMY_9 83
#define VFE_CMD_STATS_AF_START 84
#define VFE_CMD_STATS_AF_STOP 85
#define VFE_CMD_STATS_AE_START 86
#define VFE_CMD_STATS_AE_STOP 87
#define VFE_CMD_STATS_AWB_START 88
#define VFE_CMD_STATS_AWB_STOP 89
#define VFE_CMD_STATS_RS_START 90
#define VFE_CMD_STATS_RS_STOP 91
#define VFE_CMD_STATS_CS_START 92
#define VFE_CMD_STATS_CS_STOP 93
#define VFE_CMD_STATS_SKIN_START 94
#define VFE_CMD_STATS_SKIN_STOP 95
#define VFE_CMD_STATS_IHIST_START 96
#define VFE_CMD_STATS_IHIST_STOP 97
#define VFE_CMD_DUMMY_10 98
#define VFE_CMD_SYNC_TIMER_SETTING 99
#define VFE_CMD_ASYNC_TIMER_SETTING 100
#define VFE_CMD_LIVESHOT 101
#define VFE_CMD_LA_SETUP 102
#define VFE_CMD_LINEARIZATION_CFG 103
#define VFE_CMD_DEMOSAICV3 104
#define VFE_CMD_DEMOSAICV3_ABCC_CFG 105
#define VFE_CMD_DEMOSAICV3_DBCC_CFG 106
#define VFE_CMD_DEMOSAICV3_DBPC_CFG 107
#define VFE_CMD_DEMOSAICV3_ABF_CFG 108
#define VFE_CMD_DEMOSAICV3_ABCC_UPDATE 109
#define VFE_CMD_DEMOSAICV3_DBCC_UPDATE 110
#define VFE_CMD_DEMOSAICV3_DBPC_UPDATE 111
#define VFE_CMD_XBAR_CFG 112
#define VFE_CMD_MODULE_CFG 113
#define VFE_CMD_ZSL 114
#define VFE_CMD_LINEARIZATION_UPDATE 115
#define VFE_CMD_DEMOSAICV3_ABF_UPDATE 116
#define VFE_CMD_CLF_CFG 117
#define VFE_CMD_CLF_LUMA_UPDATE 118
#define VFE_CMD_CLF_CHROMA_UPDATE 119
#define VFE_CMD_PCA_ROLL_OFF_CFG 120
#define VFE_CMD_PCA_ROLL_OFF_UPDATE 121
#define VFE_CMD_GET_REG_DUMP 122
#define VFE_CMD_GET_LINEARIZATON_TABLE 123
#define VFE_CMD_GET_MESH_ROLLOFF_TABLE 124
#define VFE_CMD_GET_PCA_ROLLOFF_TABLE 125
#define VFE_CMD_GET_RGB_G_TABLE 126
#define VFE_CMD_GET_LA_TABLE 127
#define VFE_CMD_DEMOSAICV3_UPDATE 128
#define VFE_CMD_ACTIVE_REGION_CFG 129
#define VFE_CMD_COLOR_PROCESSING_CONFIG 130
#define VFE_CMD_STATS_WB_AEC_CONFIG 131
#define VFE_CMD_STATS_WB_AEC_UPDATE 132
#define VFE_CMD_Y_GAMMA_CONFIG 133
#define VFE_CMD_SCALE_OUTPUT1_CONFIG 134
#define VFE_CMD_SCALE_OUTPUT2_CONFIG 135
#define VFE_CMD_CAPTURE_RAW 136
#define VFE_CMD_STOP_LIVESHOT 137
#define VFE_CMD_RECONFIG_VFE 138
#define VFE_CMD_STATS_REQBUF 139
#define VFE_CMD_STATS_ENQUEUEBUF 140
#define VFE_CMD_STATS_FLUSH_BUFQ 141
#define VFE_CMD_STATS_UNREGBUF 142
#define VFE_CMD_STATS_BG_START 143
#define VFE_CMD_STATS_BG_STOP 144
#define VFE_CMD_STATS_BF_START 145
#define VFE_CMD_STATS_BF_STOP 146
#define VFE_CMD_STATS_BHIST_START 147
#define VFE_CMD_STATS_BHIST_STOP 148
#define VFE_CMD_RESET_2 149
#define VFE_CMD_FOV_ENC_CFG 150
#define VFE_CMD_FOV_VIEW_CFG 151
#define VFE_CMD_FOV_ENC_UPDATE 152
#define VFE_CMD_FOV_VIEW_UPDATE 153
#define VFE_CMD_SCALER_ENC_CFG 154
#define VFE_CMD_SCALER_VIEW_CFG 155
#define VFE_CMD_SCALER_ENC_UPDATE 156
#define VFE_CMD_SCALER_VIEW_UPDATE 157
#define VFE_CMD_COLORXFORM_ENC_CFG 158
#define VFE_CMD_COLORXFORM_VIEW_CFG 159
#define VFE_CMD_COLORXFORM_ENC_UPDATE 160
#define VFE_CMD_COLORXFORM_VIEW_UPDATE 161
#define VFE_CMD_TEST_GEN_CFG 162
#define VFE_CMD_STATS_BE_START 163
#define VFE_CMD_STATS_BE_STOP 164
struct msm_isp_cmd {
int32_t id;
uint16_t length;
void *value;
};
#define VPE_CMD_DUMMY_0 0
#define VPE_CMD_INIT 1
#define VPE_CMD_DEINIT 2
#define VPE_CMD_ENABLE 3
#define VPE_CMD_DISABLE 4
#define VPE_CMD_RESET 5
#define VPE_CMD_FLUSH 6
#define VPE_CMD_OPERATION_MODE_CFG 7
#define VPE_CMD_INPUT_PLANE_CFG 8
#define VPE_CMD_OUTPUT_PLANE_CFG 9
#define VPE_CMD_INPUT_PLANE_UPDATE 10
#define VPE_CMD_SCALE_CFG_TYPE 11
#define VPE_CMD_ZOOM 13
#define VPE_CMD_MAX 14
#define MSM_PP_CMD_TYPE_NOT_USED 0 /* not used */
#define MSM_PP_CMD_TYPE_VPE 1 /* VPE cmd */
#define MSM_PP_CMD_TYPE_MCTL 2 /* MCTL cmd */
#define MCTL_CMD_DUMMY_0 0 /* not used */
#define MCTL_CMD_GET_FRAME_BUFFER 1 /* reserve a free frame buffer */
#define MCTL_CMD_PUT_FRAME_BUFFER 2 /* return the free frame buffer */
#define MCTL_CMD_DIVERT_FRAME_PP_PATH 3 /* divert frame for pp */
/* event typese sending to MCTL PP module */
#define MCTL_PP_EVENT_NOTUSED 0
#define MCTL_PP_EVENT_CMD_ACK 1
#define VPE_OPERATION_MODE_CFG_LEN 4
#define VPE_INPUT_PLANE_CFG_LEN 24
#define VPE_OUTPUT_PLANE_CFG_LEN 20
#define VPE_INPUT_PLANE_UPDATE_LEN 12
#define VPE_SCALER_CONFIG_LEN 260
#define VPE_DIS_OFFSET_CFG_LEN 12
#define CAPTURE_WIDTH 1280
#define IMEM_Y_SIZE (CAPTURE_WIDTH*16)
#define IMEM_CBCR_SIZE (CAPTURE_WIDTH*8)
#define IMEM_Y_PING_OFFSET 0x2E000000
#define IMEM_CBCR_PING_OFFSET (IMEM_Y_PING_OFFSET + IMEM_Y_SIZE)
#define IMEM_Y_PONG_OFFSET (IMEM_CBCR_PING_OFFSET + IMEM_CBCR_SIZE)
#define IMEM_CBCR_PONG_OFFSET (IMEM_Y_PONG_OFFSET + IMEM_Y_SIZE)
struct msm_vpe_op_mode_cfg {
uint8_t op_mode_cfg[VPE_OPERATION_MODE_CFG_LEN];
};
struct msm_vpe_input_plane_cfg {
uint8_t input_plane_cfg[VPE_INPUT_PLANE_CFG_LEN];
};
struct msm_vpe_output_plane_cfg {
uint8_t output_plane_cfg[VPE_OUTPUT_PLANE_CFG_LEN];
};
struct msm_vpe_input_plane_update_cfg {
uint8_t input_plane_update_cfg[VPE_INPUT_PLANE_UPDATE_LEN];
};
struct msm_vpe_scaler_cfg {
uint8_t scaler_cfg[VPE_SCALER_CONFIG_LEN];
};
struct msm_vpe_flush_frame_buffer {
uint32_t src_buf_handle;
uint32_t dest_buf_handle;
int path;
};
struct msm_mctl_pp_frame_buffer {
uint32_t buf_handle;
int path;
};
struct msm_mctl_pp_divert_pp {
int path;
int enable;
};
struct msm_vpe_clock_rate {
uint32_t rate;
};
#define MSM_MCTL_PP_VPE_FRAME_ACK (1<<0)
#define MSM_MCTL_PP_VPE_FRAME_TO_APP (1<<1)
#define VFE_OUTPUTS_MAIN_AND_PREVIEW BIT(0)
#define VFE_OUTPUTS_MAIN_AND_VIDEO BIT(1)
#define VFE_OUTPUTS_MAIN_AND_THUMB BIT(2)
#define VFE_OUTPUTS_THUMB_AND_MAIN BIT(3)
#define VFE_OUTPUTS_PREVIEW_AND_VIDEO BIT(4)
#define VFE_OUTPUTS_VIDEO_AND_PREVIEW BIT(5)
#define VFE_OUTPUTS_PREVIEW BIT(6)
#define VFE_OUTPUTS_VIDEO BIT(7)
#define VFE_OUTPUTS_RAW BIT(8)
#define VFE_OUTPUTS_JPEG_AND_THUMB BIT(9)
#define VFE_OUTPUTS_THUMB_AND_JPEG BIT(10)
#define VFE_OUTPUTS_RDI0 BIT(11)
#define VFE_OUTPUTS_RDI1 BIT(12)
struct msm_frame_info {
uint32_t inst_handle;
uint32_t path;
};
#endif /*__MSM_ISP_H__*/
kernel/include/media/msm_jpeg.h
+121
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#ifndef __LINUX_MSM_JPEG_H
#define __LINUX_MSM_JPEG_H
#include <linux/types.h>
#include <linux/ioctl.h>
#define OUTPUT_H2V1 0
#define OUTPUT_H2V2 1
#define OUTPUT_BYTE 6
#define MSM_JPEG_IOCTL_MAGIC 'g'
#define MSM_JPEG_IOCTL_GET_HW_VERSION \
_IOW(MSM_JPEG_IOCTL_MAGIC, 1, struct msm_jpeg_hw_cmd *)
#define MSM_JPEG_IOCTL_RESET \
_IOW(MSM_JPEG_IOCTL_MAGIC, 2, struct msm_jpeg_ctrl_cmd *)
#define MSM_JPEG_IOCTL_STOP \
_IOW(MSM_JPEG_IOCTL_MAGIC, 3, struct msm_jpeg_hw_cmds *)
#define MSM_JPEG_IOCTL_START \
_IOW(MSM_JPEG_IOCTL_MAGIC, 4, struct msm_jpeg_hw_cmds *)
#define MSM_JPEG_IOCTL_INPUT_BUF_ENQUEUE \
_IOW(MSM_JPEG_IOCTL_MAGIC, 5, struct msm_jpeg_buf *)
#define MSM_JPEG_IOCTL_INPUT_GET \
_IOW(MSM_JPEG_IOCTL_MAGIC, 6, struct msm_jpeg_buf *)
#define MSM_JPEG_IOCTL_INPUT_GET_UNBLOCK \
_IOW(MSM_JPEG_IOCTL_MAGIC, 7, int)
#define MSM_JPEG_IOCTL_OUTPUT_BUF_ENQUEUE \
_IOW(MSM_JPEG_IOCTL_MAGIC, 8, struct msm_jpeg_buf *)
#define MSM_JPEG_IOCTL_OUTPUT_GET \
_IOW(MSM_JPEG_IOCTL_MAGIC, 9, struct msm_jpeg_buf *)
#define MSM_JPEG_IOCTL_OUTPUT_GET_UNBLOCK \
_IOW(MSM_JPEG_IOCTL_MAGIC, 10, int)
#define MSM_JPEG_IOCTL_EVT_GET \
_IOW(MSM_JPEG_IOCTL_MAGIC, 11, struct msm_jpeg_ctrl_cmd *)
#define MSM_JPEG_IOCTL_EVT_GET_UNBLOCK \
_IOW(MSM_JPEG_IOCTL_MAGIC, 12, int)
#define MSM_JPEG_IOCTL_HW_CMD \
_IOW(MSM_JPEG_IOCTL_MAGIC, 13, struct msm_jpeg_hw_cmd *)
#define MSM_JPEG_IOCTL_HW_CMDS \
_IOW(MSM_JPEG_IOCTL_MAGIC, 14, struct msm_jpeg_hw_cmds *)
#define MSM_JPEG_IOCTL_TEST_DUMP_REGION \
_IOW(MSM_JPEG_IOCTL_MAGIC, 15, unsigned long)
#define MSM_JPEG_MODE_REALTIME_ENCODE 0
#define MSM_JPEG_MODE_OFFLINE_ENCODE 1
#define MSM_JPEG_MODE_REALTIME_ROTATION 2
#define MSM_JPEG_MODE_OFFLINE_ROTATION 3
struct msm_jpeg_ctrl_cmd {
uint32_t type;
uint32_t len;
void *value;
};
#define MSM_JPEG_EVT_RESET 0
#define MSM_JPEG_EVT_SESSION_DONE 1
#define MSM_JPEG_EVT_ERR 2
struct msm_jpeg_buf {
uint32_t type;
int fd;
void *vaddr;
uint32_t y_off;
uint32_t y_len;
uint32_t framedone_len;
uint32_t cbcr_off;
uint32_t cbcr_len;
uint32_t num_of_mcu_rows;
uint32_t offset;
uint32_t pln2_off;
uint32_t pln2_len;
};
#define MSM_JPEG_HW_CMD_TYPE_READ 0
#define MSM_JPEG_HW_CMD_TYPE_WRITE 1
#define MSM_JPEG_HW_CMD_TYPE_WRITE_OR 2
#define MSM_JPEG_HW_CMD_TYPE_UWAIT 3
#define MSM_JPEG_HW_CMD_TYPE_MWAIT 4
#define MSM_JPEG_HW_CMD_TYPE_MDELAY 5
#define MSM_JPEG_HW_CMD_TYPE_UDELAY 6
struct msm_jpeg_hw_cmd {
uint32_t type:4;
/* n microseconds of timeout for WAIT */
/* n microseconds of time for DELAY */
/* repeat n times for READ/WRITE */
/* max is 0xFFF, 4095 */
uint32_t n:12;
uint32_t offset:16;
uint32_t mask;
union {
uint32_t data; /* for single READ/WRITE/WAIT, n = 1 */
uint32_t *pdata; /* for multiple READ/WRITE/WAIT, n > 1 */
};
};
struct msm_jpeg_hw_cmds {
uint32_t m; /* number of elements in the hw_cmd array */
struct msm_jpeg_hw_cmd hw_cmd[1];
};
#endif /* __LINUX_MSM_JPEG_H */
kernel/include/media/msm_media_info.h
+119
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#ifndef __MEDIA_INFO_H__
#define __MEDIA_INFO_H__
#ifndef MSM_MEDIA_ALIGN
#define MSM_MEDIA_ALIGN(__sz, __align) (((__sz) + (__align-1)) & (~(__align-1)))
#endif
enum color_fmts {
COLOR_FMT_NV12,
COLOR_FMT_NV21,
};
static inline unsigned int VENUS_Y_STRIDE(int color_fmt, int width)
{
unsigned int alignment, stride = 0;
if (!width)
goto invalid_input;
switch (color_fmt) {
case COLOR_FMT_NV21:
case COLOR_FMT_NV12:
alignment = 128;
stride = MSM_MEDIA_ALIGN(width, alignment);
break;
default:
break;
}
invalid_input:
return stride;
}
static inline unsigned int VENUS_UV_STRIDE(int color_fmt, int width)
{
unsigned int alignment, stride = 0;
if (!width)
goto invalid_input;
switch (color_fmt) {
case COLOR_FMT_NV21:
case COLOR_FMT_NV12:
alignment = 128;
stride = MSM_MEDIA_ALIGN(width, alignment);
break;
default:
break;
}
invalid_input:
return stride;
}
static inline unsigned int VENUS_Y_SCANLINES(int color_fmt, int height)
{
unsigned int alignment, sclines = 0;
if (!height)
goto invalid_input;
switch (color_fmt) {
case COLOR_FMT_NV21:
case COLOR_FMT_NV12:
alignment = 32;
sclines = MSM_MEDIA_ALIGN(height, alignment);
break;
default:
break;
}
invalid_input:
return sclines;
}
static inline unsigned int VENUS_UV_SCANLINES(int color_fmt, int height)
{
unsigned int alignment, sclines = 0;
if (!height)
goto invalid_input;
switch (color_fmt) {
case COLOR_FMT_NV21:
case COLOR_FMT_NV12:
alignment = 16;
sclines = MSM_MEDIA_ALIGN(((height + 1) >> 1), alignment);
break;
default:
break;
}
invalid_input:
return sclines;
}
static inline unsigned int VENUS_BUFFER_SIZE(
int color_fmt, int width, int height)
{
unsigned int uv_alignment;
unsigned int size = 0;
unsigned int y_plane, uv_plane, y_stride,
uv_stride, y_sclines, uv_sclines;
if (!width || !height)
goto invalid_input;
y_stride = VENUS_Y_STRIDE(color_fmt, width);
uv_stride = VENUS_UV_STRIDE(color_fmt, width);
y_sclines = VENUS_Y_SCANLINES(color_fmt, height);
uv_sclines = VENUS_UV_SCANLINES(color_fmt, height);
switch (color_fmt) {
case COLOR_FMT_NV21:
case COLOR_FMT_NV12:
uv_alignment = 4096;
y_plane = y_stride * y_sclines;
uv_plane = uv_stride * uv_sclines + uv_alignment;
size = y_plane + uv_plane;
size = MSM_MEDIA_ALIGN(size, 4096);
break;
default:
break;
}
invalid_input:
return size;
}
#endif
kernel/include/media/msm_mercury.h
+119
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#ifndef __LINUX_MSM_MERCURY_H
#define __LINUX_MSM_MERCURY_H
#include <linux/types.h>
#include <linux/ioctl.h>
#define MSM_MERCURY_HW_VERSION_REG 0x0004/* this offset does not exist in HW*/
#define OUTPUT_H2V1 0
#define OUTPUT_H2V2 1
#define OUTPUT_BYTE 6
#define MSM_MERCURY_MODE_REALTIME_ENCODE 0
#define MSM_MERCURY_MODE_OFFLINE_ENCODE 1
#define MSM_MERCURY_MODE_REALTIME_ROTATION 2
#define MSM_MERCURY_MODE_OFFLINE_ROTATION 3
#define MSM_MERCURY_EVT_RESET 1
#define MSM_MERCURY_EVT_FRAMEDONE 2
#define MSM_MERCURY_EVT_ERR 3
#define MSM_MERCURY_EVT_UNBLOCK 4
#define MSM_MERCURY_HW_CMD_TYPE_READ 0
#define MSM_MERCURY_HW_CMD_TYPE_WRITE 1
#define MSM_MERCURY_HW_CMD_TYPE_WRITE_OR 2
#define MSM_MERCURY_HW_CMD_TYPE_UWAIT 3
#define MSM_MERCURY_HW_CMD_TYPE_MWAIT 4
#define MSM_MERCURY_HW_CMD_TYPE_MDELAY 5
#define MSM_MERCURY_HW_CMD_TYPE_UDELAY 6
#define MSM_MCR_IOCTL_MAGIC 'g'
#define MSM_MCR_IOCTL_GET_HW_VERSION \
_IOW(MSM_MCR_IOCTL_MAGIC, 1, struct msm_mercury_hw_cmd *)
#define MSM_MCR_IOCTL_RESET \
_IOW(MSM_MCR_IOCTL_MAGIC, 2, struct msm_mercury_ctrl_cmd *)
#define MSM_MCR_IOCTL_STOP \
_IOW(MSM_MCR_IOCTL_MAGIC, 3, struct msm_mercury_hw_cmds *)
#define MSM_MCR_IOCTL_START \
_IOW(MSM_MCR_IOCTL_MAGIC, 4, struct msm_mercury_hw_cmds *)
#define MSM_MCR_IOCTL_INPUT_BUF_CFG \
_IOW(MSM_MCR_IOCTL_MAGIC, 5, struct msm_mercury_buf *)
#define MSM_MCR_IOCTL_INPUT_GET \
_IOW(MSM_MCR_IOCTL_MAGIC, 6, struct msm_mercury_buf *)
#define MSM_MCR_IOCTL_INPUT_GET_UNBLOCK \
_IOW(MSM_MCR_IOCTL_MAGIC, 7, int)
#define MSM_MCR_IOCTL_OUTPUT_BUF_CFG \
_IOW(MSM_MCR_IOCTL_MAGIC, 8, struct msm_mercury_buf *)
#define MSM_MCR_IOCTL_OUTPUT_GET \
_IOW(MSM_MCR_IOCTL_MAGIC, 9, struct msm_mercury_buf *)
#define MSM_MCR_IOCTL_OUTPUT_GET_UNBLOCK \
_IOW(MSM_MCR_IOCTL_MAGIC, 10, int)
#define MSM_MCR_IOCTL_EVT_GET \
_IOW(MSM_MCR_IOCTL_MAGIC, 11, struct msm_mercury_ctrl_cmd *)
#define MSM_MCR_IOCTL_EVT_GET_UNBLOCK \
_IOW(MSM_MCR_IOCTL_MAGIC, 12, int)
#define MSM_MCR_IOCTL_HW_CMD \
_IOW(MSM_MCR_IOCTL_MAGIC, 13, struct msm_mercury_hw_cmd *)
#define MSM_MCR_IOCTL_HW_CMDS \
_IOW(MSM_MCR_IOCTL_MAGIC, 14, struct msm_mercury_hw_cmds *)
#define MSM_MCR_IOCTL_TEST_DUMP_REGION \
_IOW(MSM_MCR_IOCTL_MAGIC, 15, unsigned long)
struct msm_mercury_ctrl_cmd {
uint32_t type;
uint32_t len;
void *value;
};
struct msm_mercury_buf {
uint32_t type;
int fd;
void *vaddr;
uint32_t y_off;
uint32_t y_len;
uint32_t framedone_len;
uint32_t cbcr_off;
uint32_t cbcr_len;
uint32_t num_of_mcu_rows;
uint32_t offset;
};
struct msm_mercury_hw_cmd {
uint32_t type:4;
/* n microseconds of timeout for WAIT */
/* n microseconds of time for DELAY */
/* repeat n times for READ/WRITE */
/* max is 0xFFF, 4095 */
uint32_t n:12;
uint32_t offset:16;
uint32_t mask;
union {
/* for single READ/WRITE/WAIT, n = 1 */
uint32_t data;
uint32_t *pdata;/* for multiple READ/WRITE/WAIT, n > 1 */
};
};
struct msm_mercury_hw_cmds {
uint32_t m; /* number of elements in the hw_cmd array */
struct msm_mercury_hw_cmd hw_cmd[1];
};
#endif /* __LINUX_MSM_MERCURY_H */
kernel/include/media/msm_v4l2_overlay.h
+9
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#ifndef LINUX_MSM_V4L2_OVERLAY
#define LINUX_MSM_V4L2_OVERLAY
#include <linux/videodev2.h>
#define VIDIOC_MSM_USERPTR_QBUF \
_IOWR('V', BASE_VIDIOC_PRIVATE, struct v4l2_buffer)
#endif
kernel/include/media/msm_vidc.h
+127
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#ifndef _MSM_VIDC_H_
#define _MSM_VIDC_H_
#ifdef __KERNEL__
#include <linux/poll.h>
#include <linux/videodev2.h>
enum core_id {
MSM_VIDC_CORE_0 = 0,
MSM_VIDC_CORE_1, /* for Q6 core */
MSM_VIDC_CORES_MAX,
};
enum session_type {
MSM_VIDC_ENCODER = 0,
MSM_VIDC_DECODER,
MSM_VIDC_MAX_DEVICES,
};
void *msm_vidc_open(int core_id, int session_type);
int msm_vidc_close(void *instance);
int msm_vidc_querycap(void *instance, struct v4l2_capability *cap);
int msm_vidc_enum_fmt(void *instance, struct v4l2_fmtdesc *f);
int msm_vidc_s_fmt(void *instance, struct v4l2_format *f);
int msm_vidc_g_fmt(void *instance, struct v4l2_format *f);
int msm_vidc_s_ctrl(void *instance, struct v4l2_control *a);
int msm_vidc_g_ctrl(void *instance, struct v4l2_control *a);
int msm_vidc_reqbufs(void *instance, struct v4l2_requestbuffers *b);
int msm_vidc_prepare_buf(void *instance, struct v4l2_buffer *b);
int msm_vidc_release_buf(void *instance, struct v4l2_buffer *b);
int msm_vidc_qbuf(void *instance, struct v4l2_buffer *b);
int msm_vidc_dqbuf(void *instance, struct v4l2_buffer *b);
int msm_vidc_streamon(void *instance, enum v4l2_buf_type i);
int msm_vidc_streamoff(void *instance, enum v4l2_buf_type i);
int msm_vidc_decoder_cmd(void *instance, struct v4l2_decoder_cmd *dec);
int msm_vidc_encoder_cmd(void *instance, struct v4l2_encoder_cmd *enc);
int msm_vidc_poll(void *instance, struct file *filp,
struct poll_table_struct *pt);
int msm_vidc_get_iommu_domain_partition(void *instance, u32 flags,
enum v4l2_buf_type, int *domain, int *partition);
int msm_vidc_subscribe_event(void *instance,
struct v4l2_event_subscription *sub);
int msm_vidc_unsubscribe_event(void *instance,
struct v4l2_event_subscription *sub);
int msm_vidc_dqevent(void *instance, struct v4l2_event *event);
int msm_vidc_wait(void *instance);
int msm_vidc_s_parm(void *instance, struct v4l2_streamparm *a);
int msm_vidc_enum_framesizes(void *instance, struct v4l2_frmsizeenum *fsize);
#endif
struct msm_vidc_interlace_payload {
unsigned int format;
};
struct msm_vidc_framerate_payload {
unsigned int frame_rate;
};
struct msm_vidc_ts_payload {
unsigned int timestamp_lo;
unsigned int timestamp_hi;
};
struct msm_vidc_concealmb_payload {
unsigned int num_mbs;
};
struct msm_vidc_recoverysei_payload {
unsigned int flags;
};
struct msm_vidc_aspect_ratio_payload {
unsigned int size;
unsigned int version;
unsigned int port_index;
unsigned int aspect_width;
unsigned int aspect_height;
};
struct msm_vidc_mpeg2_seqdisp_payload {
unsigned int video_format;
bool color_descp;
unsigned int color_primaries;
unsigned int transfer_char;
unsigned int matrix_coeffs;
unsigned int disp_width;
unsigned int disp_height;
};
struct msm_vidc_panscan_window {
unsigned int panscan_height_offset;
unsigned int panscan_width_offset;
unsigned int panscan_window_width;
unsigned int panscan_window_height;
};
struct msm_vidc_panscan_window_payload {
unsigned int num_panscan_windows;
struct msm_vidc_panscan_window wnd[1];
};
enum msm_vidc_extradata_type {
EXTRADATA_NONE = 0x00000000,
EXTRADATA_MB_QUANTIZATION = 0x00000001,
EXTRADATA_INTERLACE_VIDEO = 0x00000002,
EXTRADATA_VC1_FRAMEDISP = 0x00000003,
EXTRADATA_VC1_SEQDISP = 0x00000004,
EXTRADATA_TIMESTAMP = 0x00000005,
EXTRADATA_S3D_FRAME_PACKING = 0x00000006,
EXTRADATA_FRAME_RATE = 0x00000007,
EXTRADATA_PANSCAN_WINDOW = 0x00000008,
EXTRADATA_RECOVERY_POINT_SEI = 0x00000009,
EXTRADATA_MPEG2_SEQDISP = 0x0000000D,
EXTRADATA_MULTISLICE_INFO = 0x7F100000,
EXTRADATA_NUM_CONCEALED_MB = 0x7F100001,
EXTRADATA_INDEX = 0x7F100002,
EXTRADATA_ASPECT_RATIO = 0x7F100003,
EXTRADATA_METADATA_FILLER = 0x7FE00002,
};
enum msm_vidc_interlace_type {
INTERLACE_FRAME_PROGRESSIVE = 0x01,
INTERLACE_INTERLEAVE_FRAME_TOPFIELDFIRST = 0x02,
INTERLACE_INTERLEAVE_FRAME_BOTTOMFIELDFIRST = 0x04,
INTERLACE_FRAME_TOPFIELDFIRST = 0x08,
INTERLACE_FRAME_BOTTOMFIELDFIRST = 0x10,
};
enum msm_vidc_recovery_sei {
FRAME_RECONSTRUCTION_INCORRECT = 0x0,
FRAME_RECONSTRUCTION_CORRECT = 0x01,
FRAME_RECONSTRUCTION_APPROXIMATELY_CORRECT = 0x02,
};
#endif
kernel/include/media/msmb_camera.h
+163
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#ifndef __LINUX_MSMB_CAMERA_H
#define __LINUX_MSMB_CAMERA_H
#include <linux/videodev2.h>
#include <linux/types.h>
#include <linux/ioctl.h>
#define MSM_CAM_V4L2_IOCTL_NOTIFY \
_IOW('V', BASE_VIDIOC_PRIVATE + 30, struct v4l2_event)
#define MSM_CAM_V4L2_IOCTL_NOTIFY_META \
_IOW('V', BASE_VIDIOC_PRIVATE + 31, struct v4l2_event)
#define MSM_CAM_V4L2_IOCTL_CMD_ACK \
_IOW('V', BASE_VIDIOC_PRIVATE + 32, struct v4l2_event)
#define MSM_CAM_V4L2_IOCTL_NOTIFY_ERROR \
_IOW('V', BASE_VIDIOC_PRIVATE + 33, struct v4l2_event)
#define QCAMERA_DEVICE_GROUP_ID 1
#define QCAMERA_VNODE_GROUP_ID 2
#define MSM_CAMERA_NAME "msm_camera"
#define MSM_CONFIGURATION_NAME "msm_config"
#define MSM_CAMERA_SUBDEV_CSIPHY 0
#define MSM_CAMERA_SUBDEV_CSID 1
#define MSM_CAMERA_SUBDEV_ISPIF 2
#define MSM_CAMERA_SUBDEV_VFE 3
#define MSM_CAMERA_SUBDEV_AXI 4
#define MSM_CAMERA_SUBDEV_VPE 5
#define MSM_CAMERA_SUBDEV_SENSOR 6
#define MSM_CAMERA_SUBDEV_ACTUATOR 7
#define MSM_CAMERA_SUBDEV_EEPROM 8
#define MSM_CAMERA_SUBDEV_CPP 9
#define MSM_CAMERA_SUBDEV_CCI 10
#define MSM_CAMERA_SUBDEV_LED_FLASH 11
#define MSM_CAMERA_SUBDEV_STROBE_FLASH 12
#define MSM_CAMERA_SUBDEV_BUF_MNGR 13
#define MSM_MAX_CAMERA_SENSORS 5
/* featur base */
#define MSM_CAMERA_FEATURE_BASE 0x00010000
#define MSM_CAMERA_FEATURE_SHUTDOWN (MSM_CAMERA_FEATURE_BASE + 1)
#define MSM_CAMERA_STATUS_BASE 0x00020000
#define MSM_CAMERA_STATUS_FAIL (MSM_CAMERA_STATUS_BASE + 1)
#define MSM_CAMERA_STATUS_SUCCESS (MSM_CAMERA_STATUS_BASE + 2)
/* event type */
#define MSM_CAMERA_V4L2_EVENT_TYPE (V4L2_EVENT_PRIVATE_START + 0x00002000)
/* event id */
#define MSM_CAMERA_EVENT_MIN 0
#define MSM_CAMERA_NEW_SESSION (MSM_CAMERA_EVENT_MIN + 1)
#define MSM_CAMERA_DEL_SESSION (MSM_CAMERA_EVENT_MIN + 2)
#define MSM_CAMERA_SET_PARM (MSM_CAMERA_EVENT_MIN + 3)
#define MSM_CAMERA_GET_PARM (MSM_CAMERA_EVENT_MIN + 4)
#define MSM_CAMERA_MAPPING_CFG (MSM_CAMERA_EVENT_MIN + 5)
#define MSM_CAMERA_MAPPING_SES (MSM_CAMERA_EVENT_MIN + 6)
#define MSM_CAMERA_MSM_NOTIFY (MSM_CAMERA_EVENT_MIN + 7)
#define MSM_CAMERA_EVENT_MAX (MSM_CAMERA_EVENT_MIN + 8)
/* data.command */
#define MSM_CAMERA_PRIV_S_CROP (V4L2_CID_PRIVATE_BASE + 1)
#define MSM_CAMERA_PRIV_G_CROP (V4L2_CID_PRIVATE_BASE + 2)
#define MSM_CAMERA_PRIV_G_FMT (V4L2_CID_PRIVATE_BASE + 3)
#define MSM_CAMERA_PRIV_S_FMT (V4L2_CID_PRIVATE_BASE + 4)
#define MSM_CAMERA_PRIV_TRY_FMT (V4L2_CID_PRIVATE_BASE + 5)
#define MSM_CAMERA_PRIV_METADATA (V4L2_CID_PRIVATE_BASE + 6)
#define MSM_CAMERA_PRIV_QUERY_CAP (V4L2_CID_PRIVATE_BASE + 7)
#define MSM_CAMERA_PRIV_STREAM_ON (V4L2_CID_PRIVATE_BASE + 8)
#define MSM_CAMERA_PRIV_STREAM_OFF (V4L2_CID_PRIVATE_BASE + 9)
#define MSM_CAMERA_PRIV_NEW_STREAM (V4L2_CID_PRIVATE_BASE + 10)
#define MSM_CAMERA_PRIV_DEL_STREAM (V4L2_CID_PRIVATE_BASE + 11)
#define MSM_CAMERA_PRIV_SHUTDOWN (V4L2_CID_PRIVATE_BASE + 12)
#define MSM_CAMERA_PRIV_STREAM_INFO_SYNC \
(V4L2_CID_PRIVATE_BASE + 13)
/* data.status - success */
#define MSM_CAMERA_CMD_SUCESS 0x00000001
#define MSM_CAMERA_BUF_MAP_SUCESS 0x00000002
/* data.status - error */
#define MSM_CAMERA_ERR_EVT_BASE 0x00010000
#define MSM_CAMERA_ERR_CMD_FAIL (MSM_CAMERA_ERR_EVT_BASE + 1)
#define MSM_CAMERA_ERR_MAPPING (MSM_CAMERA_ERR_EVT_BASE + 2)
/* The msm_v4l2_event_data structure should match the
* v4l2_event.u.data field.
* should not exceed 16 elements */
struct msm_v4l2_event_data {
/*word 0*/
unsigned int command;
/*word 1*/
unsigned int status;
/*word 2*/
unsigned int session_id;
/*word 3*/
unsigned int stream_id;
/*word 4*/
unsigned int map_op;
/*word 5*/
unsigned int map_buf_idx;
/*word 6*/
unsigned int notify;
/*word 7*/
unsigned int arg_value;
/*word 8*/
unsigned int ret_value;
/*word 9*/
unsigned int nop3;
/*word 10*/
unsigned int nop4;
/*word 11*/
unsigned int nop5;
/*word 12*/
unsigned int nop6;
/*word 13*/
unsigned int nop7;
/*word 14*/
unsigned int nop8;
/*word 15*/
unsigned int nop9;
};
/* map to v4l2_format.fmt.raw_data */
struct msm_v4l2_format_data {
enum v4l2_buf_type type;
unsigned int width;
unsigned int height;
unsigned int pixelformat; /* FOURCC */
unsigned char num_planes;
unsigned int plane_sizes[VIDEO_MAX_PLANES];
};
/* MSM Four-character-code (FOURCC) */
#define msm_v4l2_fourcc(a, b, c, d)\
((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) |\
((__u32)(d) << 24))
/* Composite stats */
#define MSM_V4L2_PIX_FMT_STATS_COMB v4l2_fourcc('S', 'T', 'C', 'M')
/* AEC stats */
#define MSM_V4L2_PIX_FMT_STATS_AE v4l2_fourcc('S', 'T', 'A', 'E')
/* AF stats */
#define MSM_V4L2_PIX_FMT_STATS_AF v4l2_fourcc('S', 'T', 'A', 'F')
/* AWB stats */
#define MSM_V4L2_PIX_FMT_STATS_AWB v4l2_fourcc('S', 'T', 'W', 'B')
/* IHIST stats */
#define MSM_V4L2_PIX_FMT_STATS_IHST v4l2_fourcc('I', 'H', 'S', 'T')
/* Column count stats */
#define MSM_V4L2_PIX_FMT_STATS_CS v4l2_fourcc('S', 'T', 'C', 'S')
/* Row count stats */
#define MSM_V4L2_PIX_FMT_STATS_RS v4l2_fourcc('S', 'T', 'R', 'S')
/* Bayer Grid stats */
#define MSM_V4L2_PIX_FMT_STATS_BG v4l2_fourcc('S', 'T', 'B', 'G')
/* Bayer focus stats */
#define MSM_V4L2_PIX_FMT_STATS_BF v4l2_fourcc('S', 'T', 'B', 'F')
/* Bayer hist stats */
#define MSM_V4L2_PIX_FMT_STATS_BHST v4l2_fourcc('B', 'H', 'S', 'T')
#endif /* __LINUX_MSMB_CAMERA_H */
kernel/include/media/msmb_generic_buf_mgr.h
+23
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@@ -0,0 +1,23 @@
#ifndef __MEDIA_MSMB_BUF_MNGR_H__
#define __MEDIA_MSMB_BUF_MNGR_H__
struct msm_buf_mngr_info {
uint32_t session_id;
uint32_t stream_id;
uint32_t frame_id;
struct timeval timestamp;
uint32_t index;
};
struct v4l2_subdev *msm_buf_mngr_get_subdev(void);
#define VIDIOC_MSM_BUF_MNGR_GET_BUF \
_IOWR('V', BASE_VIDIOC_PRIVATE + 33, struct msm_buf_mngr_info)
#define VIDIOC_MSM_BUF_MNGR_PUT_BUF \
_IOWR('V', BASE_VIDIOC_PRIVATE + 34, struct msm_buf_mngr_info)
#define VIDIOC_MSM_BUF_MNGR_BUF_DONE \
_IOWR('V', BASE_VIDIOC_PRIVATE + 35, struct msm_buf_mngr_info)
#endif
kernel/include/media/msmb_isp.h
+421
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@@ -0,0 +1,421 @@
#ifndef __MSMB_ISP__
#define __MSMB_ISP__
#include <linux/videodev2.h>
#define MAX_PLANES_PER_STREAM 3
#define MAX_NUM_STREAM 7
#define ISP_VERSION_40 40
#define ISP_VERSION_32 32
#define ISP_NATIVE_BUF_BIT 0x10000
#define ISP0_BIT 0x20000
#define ISP1_BIT 0x40000
#define ISP_STATS_STREAM_BIT 0x80000000
enum ISP_START_PIXEL_PATTERN {
ISP_BAYER_RGRGRG,
ISP_BAYER_GRGRGR,
ISP_BAYER_BGBGBG,
ISP_BAYER_GBGBGB,
ISP_YUV_YCbYCr,
ISP_YUV_YCrYCb,
ISP_YUV_CbYCrY,
ISP_YUV_CrYCbY,
ISP_PIX_PATTERN_MAX
};
enum msm_vfe_plane_fmt {
Y_PLANE,
CB_PLANE,
CR_PLANE,
CRCB_PLANE,
CBCR_PLANE,
VFE_PLANE_FMT_MAX
};
enum msm_vfe_input_src {
VFE_PIX_0,
VFE_RAW_0,
VFE_RAW_1,
VFE_RAW_2,
VFE_SRC_MAX,
};
enum msm_vfe_axi_stream_src {
PIX_ENCODER,
PIX_VIEWFINDER,
CAMIF_RAW,
IDEAL_RAW,
RDI_INTF_0,
RDI_INTF_1,
RDI_INTF_2,
VFE_AXI_SRC_MAX
};
enum msm_vfe_frame_skip_pattern {
NO_SKIP,
EVERY_2FRAME,
EVERY_3FRAME,
EVERY_4FRAME,
EVERY_5FRAME,
EVERY_6FRAME,
EVERY_7FRAME,
EVERY_8FRAME,
EVERY_16FRAME,
EVERY_32FRAME,
SKIP_ALL,
MAX_SKIP,
};
enum msm_vfe_camif_input {
CAMIF_DISABLED,
CAMIF_PAD_REG_INPUT,
CAMIF_MIDDI_INPUT,
CAMIF_MIPI_INPUT,
};
struct msm_vfe_camif_cfg {
uint32_t lines_per_frame;
uint32_t pixels_per_line;
uint32_t first_pixel;
uint32_t last_pixel;
uint32_t first_line;
uint32_t last_line;
uint32_t epoch_line0;
uint32_t epoch_line1;
enum msm_vfe_camif_input camif_input;
};
enum msm_vfe_inputmux {
CAMIF,
TESTGEN,
EXTERNAL_READ,
};
struct msm_vfe_pix_cfg {
struct msm_vfe_camif_cfg camif_cfg;
enum msm_vfe_inputmux input_mux;
enum ISP_START_PIXEL_PATTERN pixel_pattern;
};
struct msm_vfe_rdi_cfg {
uint8_t cid;
uint8_t frame_based;
};
struct msm_vfe_input_cfg {
union {
struct msm_vfe_pix_cfg pix_cfg;
struct msm_vfe_rdi_cfg rdi_cfg;
} d;
enum msm_vfe_input_src input_src;
uint32_t input_pix_clk;
};
struct msm_vfe_axi_plane_cfg {
uint32_t output_width; /*Include padding*/
uint32_t output_height;
uint32_t output_stride;
uint32_t output_scan_lines;
uint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/
uint32_t plane_addr_offset;
uint8_t csid_src; /*RDI 0-2*/
uint8_t rdi_cid;/*CID 1-16*/
};
struct msm_vfe_axi_stream_request_cmd {
uint32_t session_id;
uint32_t stream_id;
uint32_t output_format;/*Planar/RAW/Misc*/
enum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/
struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
uint32_t burst_count;
uint32_t hfr_mode;
uint8_t frame_base;
uint32_t init_frame_drop; /*MAX 31 Frames*/
enum msm_vfe_frame_skip_pattern frame_skip_pattern;
uint8_t buf_divert; /* if TRUE no vb2 buf done. */
/*Return values*/
uint32_t axi_stream_handle;
};
struct msm_vfe_axi_stream_release_cmd {
uint32_t stream_handle;
};
enum msm_vfe_axi_stream_cmd {
STOP_STREAM,
START_STREAM,
};
struct msm_vfe_axi_stream_cfg_cmd {
uint8_t num_streams;
uint32_t stream_handle[MAX_NUM_STREAM];
enum msm_vfe_axi_stream_cmd cmd;
};
enum msm_vfe_axi_stream_update_type {
ENABLE_STREAM_BUF_DIVERT,
DISABLE_STREAM_BUF_DIVERT,
UPDATE_STREAM_FRAMEDROP_PATTERN,
UPDATE_STREAM_AXI_CONFIG,
};
struct msm_vfe_axi_stream_cfg_update_info {
uint32_t stream_handle;
uint32_t output_format;
enum msm_vfe_frame_skip_pattern skip_pattern;
struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
};
struct msm_vfe_axi_stream_update_cmd {
uint32_t num_streams;
enum msm_vfe_axi_stream_update_type update_type;
struct msm_vfe_axi_stream_cfg_update_info update_info[MAX_NUM_STREAM];
};
enum msm_isp_stats_type {
MSM_ISP_STATS_AEC, /* legacy based AEC */
MSM_ISP_STATS_AF, /* legacy based AF */
MSM_ISP_STATS_AWB, /* legacy based AWB */
MSM_ISP_STATS_RS, /* legacy based RS */
MSM_ISP_STATS_CS, /* legacy based CS */
MSM_ISP_STATS_IHIST, /* legacy based HIST */
MSM_ISP_STATS_SKIN, /* legacy based SKIN */
MSM_ISP_STATS_BG, /* Bayer Grids */
MSM_ISP_STATS_BF, /* Bayer Focus */
MSM_ISP_STATS_BE, /* Bayer Exposure*/
MSM_ISP_STATS_BHIST, /* Bayer Hist */
MSM_ISP_STATS_MAX /* MAX */
};
struct msm_vfe_stats_stream_request_cmd {
uint32_t session_id;
uint32_t stream_id;
enum msm_isp_stats_type stats_type;
uint32_t composite_flag;
uint32_t framedrop_pattern;
uint32_t irq_subsample_pattern;
uint32_t buffer_offset;
uint32_t stream_handle;
};
struct msm_vfe_stats_stream_release_cmd {
uint32_t stream_handle;
};
struct msm_vfe_stats_stream_cfg_cmd {
uint8_t num_streams;
uint32_t stream_handle[MSM_ISP_STATS_MAX];
uint8_t enable;
};
enum msm_vfe_reg_cfg_type {
VFE_WRITE,
VFE_WRITE_MB,
VFE_READ,
VFE_CFG_MASK,
VFE_WRITE_DMI_16BIT,
VFE_WRITE_DMI_32BIT,
VFE_WRITE_DMI_64BIT,
VFE_READ_DMI_16BIT,
VFE_READ_DMI_32BIT,
VFE_READ_DMI_64BIT,
};
struct msm_vfe_cfg_cmd2 {
uint16_t num_cfg;
uint16_t cmd_len;
void __user *cfg_data;
void __user *cfg_cmd;
};
struct msm_vfe_reg_rw_info {
uint32_t reg_offset;
uint32_t cmd_data_offset;
uint32_t len;
};
struct msm_vfe_reg_mask_info {
uint32_t reg_offset;
uint32_t mask;
uint32_t val;
};
struct msm_vfe_reg_dmi_info {
uint32_t hi_tbl_offset; /*Optional*/
uint32_t lo_tbl_offset; /*Required*/
uint32_t len;
};
struct msm_vfe_reg_cfg_cmd {
union {
struct msm_vfe_reg_rw_info rw_info;
struct msm_vfe_reg_mask_info mask_info;
struct msm_vfe_reg_dmi_info dmi_info;
} u;
enum msm_vfe_reg_cfg_type cmd_type;
};
enum msm_isp_buf_type {
ISP_PRIVATE_BUF,
ISP_SHARE_BUF,
MAX_ISP_BUF_TYPE,
};
struct msm_isp_buf_request {
uint32_t session_id;
uint32_t stream_id;
uint8_t num_buf;
uint32_t handle;
enum msm_isp_buf_type buf_type;
};
struct msm_isp_qbuf_info {
uint32_t handle;
int buf_idx;
/*Only used for prepare buffer*/
struct v4l2_buffer buffer;
/*Only used for diverted buffer*/
uint32_t dirty_buf;
};
struct msm_vfe_axi_src_state {
enum msm_vfe_input_src input_src;
uint32_t src_active;
};
enum msm_isp_event_idx {
ISP_REG_UPDATE = 0,
ISP_START_ACK = 1,
ISP_STOP_ACK = 2,
ISP_IRQ_VIOLATION = 3,
ISP_WM_BUS_OVERFLOW = 4,
ISP_STATS_OVERFLOW = 5,
ISP_CAMIF_ERROR = 6,
ISP_SOF = 7,
ISP_EOF = 8,
ISP_EVENT_MAX = 9
};
#define ISP_EVENT_OFFSET 8
#define ISP_EVENT_BASE (V4L2_EVENT_PRIVATE_START)
#define ISP_BUF_EVENT_BASE (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET))
#define ISP_STATS_EVENT_BASE (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET))
#define ISP_EVENT_REG_UPDATE (ISP_EVENT_BASE + ISP_REG_UPDATE)
#define ISP_EVENT_START_ACK (ISP_EVENT_BASE + ISP_START_ACK)
#define ISP_EVENT_STOP_ACK (ISP_EVENT_BASE + ISP_STOP_ACK)
#define ISP_EVENT_IRQ_VIOLATION (ISP_EVENT_BASE + ISP_IRQ_VIOLATION)
#define ISP_EVENT_WM_BUS_OVERFLOW (ISP_EVENT_BASE + ISP_WM_BUS_OVERFLOW)
#define ISP_EVENT_STATS_OVERFLOW (ISP_EVENT_BASE + ISP_STATS_OVERFLOW)
#define ISP_EVENT_CAMIF_ERROR (ISP_EVENT_BASE + ISP_CAMIF_ERROR)
#define ISP_EVENT_SOF (ISP_EVENT_BASE + ISP_SOF)
#define ISP_EVENT_EOF (ISP_EVENT_BASE + ISP_EOF)
#define ISP_EVENT_BUF_DIVERT (ISP_BUF_EVENT_BASE)
#define ISP_EVENT_STATS_NOTIFY (ISP_STATS_EVENT_BASE)
#define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX)
/* The msm_v4l2_event_data structure should match the
* v4l2_event.u.data field.
* should not exceed 64 bytes */
struct msm_isp_buf_event {
uint32_t session_id;
uint32_t stream_id;
uint32_t handle;
uint32_t output_format;
int8_t buf_idx;
};
struct msm_isp_stats_event {
uint32_t stats_mask; /* 4 bytes */
uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX]; /* 11 bytes */
};
struct msm_isp_stream_ack {
uint32_t session_id;
uint32_t stream_id;
uint32_t handle;
};
struct msm_isp_event_data {
/*Wall clock except for buffer divert events
*which use monotonic clock
*/
struct timeval timestamp;
/* Monotonic timestamp since bootup */
struct timeval mono_timestamp;
/* if pix is a src frame_id is from camif */
uint32_t frame_id;
union {
/* START_ACK, STOP_ACK */
struct msm_isp_stream_ack stream_ack;
/* REG_UPDATE_TRIGGER, bus over flow */
enum msm_vfe_input_src input_src;
/* stats notify */
struct msm_isp_stats_event stats;
/* IRQ_VIOLATION, STATS_OVER_FLOW, WM_OVER_FLOW */
uint32_t irq_status_mask;
struct msm_isp_buf_event buf_done;
} u; /* union can have max 52 bytes */
};
#define V4L2_PIX_FMT_QBGGR8 v4l2_fourcc('Q', 'B', 'G', '8')
#define V4L2_PIX_FMT_QGBRG8 v4l2_fourcc('Q', 'G', 'B', '8')
#define V4L2_PIX_FMT_QGRBG8 v4l2_fourcc('Q', 'G', 'R', '8')
#define V4L2_PIX_FMT_QRGGB8 v4l2_fourcc('Q', 'R', 'G', '8')
#define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0')
#define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0')
#define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0')
#define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0')
#define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2')
#define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2')
#define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2')
#define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2')
#define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4')
#define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1')
#define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T')
#define VIDIOC_MSM_VFE_REG_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_vfe_cfg_cmd2)
#define VIDIOC_MSM_ISP_REQUEST_BUF \
_IOWR('V', BASE_VIDIOC_PRIVATE+1, struct msm_isp_buf_request)
#define VIDIOC_MSM_ISP_ENQUEUE_BUF \
_IOWR('V', BASE_VIDIOC_PRIVATE+2, struct msm_isp_qbuf_info)
#define VIDIOC_MSM_ISP_RELEASE_BUF \
_IOWR('V', BASE_VIDIOC_PRIVATE+3, struct msm_isp_buf_request)
#define VIDIOC_MSM_ISP_REQUEST_STREAM \
_IOWR('V', BASE_VIDIOC_PRIVATE+4, struct msm_vfe_axi_stream_request_cmd)
#define VIDIOC_MSM_ISP_CFG_STREAM \
_IOWR('V', BASE_VIDIOC_PRIVATE+5, struct msm_vfe_axi_stream_cfg_cmd)
#define VIDIOC_MSM_ISP_RELEASE_STREAM \
_IOWR('V', BASE_VIDIOC_PRIVATE+6, struct msm_vfe_axi_stream_release_cmd)
#define VIDIOC_MSM_ISP_INPUT_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE+7, struct msm_vfe_input_cfg)
#define VIDIOC_MSM_ISP_SET_SRC_STATE \
_IOWR('V', BASE_VIDIOC_PRIVATE+8, struct msm_vfe_axi_src_state)
#define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \
_IOWR('V', BASE_VIDIOC_PRIVATE+9, \
struct msm_vfe_stats_stream_request_cmd)
#define VIDIOC_MSM_ISP_CFG_STATS_STREAM \
_IOWR('V', BASE_VIDIOC_PRIVATE+10, struct msm_vfe_stats_stream_cfg_cmd)
#define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \
_IOWR('V', BASE_VIDIOC_PRIVATE+11, \
struct msm_vfe_stats_stream_release_cmd)
#define VIDIOC_MSM_ISP_UPDATE_STREAM \
_IOWR('V', BASE_VIDIOC_PRIVATE+13, struct msm_vfe_axi_stream_update_cmd)
#endif /* __MSMB_ISP__ */
kernel/include/media/msmb_ispif.h
+123
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@@ -0,0 +1,123 @@
#ifndef MSM_CAM_ISPIF_H
#define MSM_CAM_ISPIF_H
#define CSID_VERSION_V20 0x02000011
#define CSID_VERSION_V22 0x02001000
#define CSID_VERSION_V30 0x30000000
#define CSID_VERSION_V3 0x30000000
enum msm_ispif_vfe_intf {
VFE0,
VFE1,
VFE_MAX
};
#define VFE0_MASK (1 << VFE0)
#define VFE1_MASK (1 << VFE1)
enum msm_ispif_intftype {
PIX0,
RDI0,
PIX1,
RDI1,
RDI2,
INTF_MAX
};
#define MAX_PARAM_ENTRIES (INTF_MAX * 2)
#define PIX0_MASK (1 << PIX0)
#define PIX1_MASK (1 << PIX1)
#define RDI0_MASK (1 << RDI0)
#define RDI1_MASK (1 << RDI1)
#define RDI2_MASK (1 << RDI2)
enum msm_ispif_vc {
VC0,
VC1,
VC2,
VC3,
VC_MAX
};
enum msm_ispif_cid {
CID0,
CID1,
CID2,
CID3,
CID4,
CID5,
CID6,
CID7,
CID8,
CID9,
CID10,
CID11,
CID12,
CID13,
CID14,
CID15,
CID_MAX
};
enum msm_ispif_csid {
CSID0,
CSID1,
CSID2,
CSID3,
CSID_MAX
};
struct msm_ispif_params_entry {
enum msm_ispif_vfe_intf vfe_intf;
enum msm_ispif_intftype intftype;
int num_cids;
enum msm_ispif_cid cids[3];
enum msm_ispif_csid csid;
int crop_enable;
uint16_t crop_start_pixel;
uint16_t crop_end_pixel;
};
struct msm_ispif_param_data {
uint32_t num;
struct msm_ispif_params_entry entries[MAX_PARAM_ENTRIES];
};
struct msm_isp_info {
uint32_t max_resolution;
uint32_t id;
uint32_t ver;
};
struct msm_ispif_vfe_info {
int num_vfe;
struct msm_isp_info info[VFE_MAX];
};
enum ispif_cfg_type_t {
ISPIF_CLK_ENABLE,
ISPIF_CLK_DISABLE,
ISPIF_INIT,
ISPIF_CFG,
ISPIF_START_FRAME_BOUNDARY,
ISPIF_STOP_FRAME_BOUNDARY,
ISPIF_STOP_IMMEDIATELY,
ISPIF_RELEASE,
ISPIF_ENABLE_REG_DUMP,
ISPIF_SET_VFE_INFO,
};
struct ispif_cfg_data {
enum ispif_cfg_type_t cfg_type;
union {
int reg_dump; /* ISPIF_ENABLE_REG_DUMP */
uint32_t csid_version; /* ISPIF_INIT */
struct msm_ispif_vfe_info vfe_info; /* ISPIF_SET_VFE_INFO */
struct msm_ispif_param_data params; /* CFG, START, STOP */
};
};
#define VIDIOC_MSM_ISPIF_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE, struct ispif_cfg_data)
#endif /* MSM_CAM_ISPIF_H */
kernel/include/media/msmb_pproc.h
+230
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@@ -0,0 +1,230 @@
#ifndef __MSMB_PPROC_H
#define __MSMB_PPROC_H
#ifdef MSM_CAMERA_BIONIC
#include <sys/types.h>
#endif
#include <linux/videodev2.h>
#include <linux/types.h>
/* Should be same as VIDEO_MAX_PLANES in videodev2.h */
#define MAX_PLANES VIDEO_MAX_PLANES
#define MAX_NUM_CPP_STRIPS 8
#define MSM_CPP_MAX_NUM_PLANES 3
enum msm_cpp_frame_type {
MSM_CPP_OFFLINE_FRAME,
MSM_CPP_REALTIME_FRAME,
};
enum msm_vpe_frame_type {
MSM_VPE_OFFLINE_FRAME,
MSM_VPE_REALTIME_FRAME,
};
struct msm_cpp_frame_strip_info {
int scale_v_en;
int scale_h_en;
int upscale_v_en;
int upscale_h_en;
int src_start_x;
int src_end_x;
int src_start_y;
int src_end_y;
/* Padding is required for upscaler because it does not
* pad internally like other blocks, also needed for rotation
* rotation expects all the blocks in the stripe to be the same size
* Padding is done such that all the extra padded pixels
* are on the right and bottom
*/
int pad_bottom;
int pad_top;
int pad_right;
int pad_left;
int v_init_phase;
int h_init_phase;
int h_phase_step;
int v_phase_step;
int prescale_crop_width_first_pixel;
int prescale_crop_width_last_pixel;
int prescale_crop_height_first_line;
int prescale_crop_height_last_line;
int postscale_crop_height_first_line;
int postscale_crop_height_last_line;
int postscale_crop_width_first_pixel;
int postscale_crop_width_last_pixel;
int dst_start_x;
int dst_end_x;
int dst_start_y;
int dst_end_y;
int bytes_per_pixel;
unsigned int source_address;
unsigned int destination_address;
unsigned int src_stride;
unsigned int dst_stride;
int rotate_270;
int horizontal_flip;
int vertical_flip;
int scale_output_width;
int scale_output_height;
int prescale_crop_en;
int postscale_crop_en;
};
struct msm_cpp_buffer_info_t {
int fd;
uint32_t index;
uint32_t offset;
uint8_t native_buff;
uint8_t processed_divert;
};
struct msm_cpp_stream_buff_info_t {
uint32_t identity;
uint32_t num_buffs;
struct msm_cpp_buffer_info_t *buffer_info;
};
struct msm_cpp_frame_info_t {
int32_t frame_id;
struct timeval timestamp;
uint32_t inst_id;
uint32_t identity;
uint32_t client_id;
enum msm_cpp_frame_type frame_type;
uint32_t num_strips;
struct msm_cpp_frame_strip_info *strip_info;
uint32_t msg_len;
uint32_t *cpp_cmd_msg;
int src_fd;
int dst_fd;
struct ion_handle *src_ion_handle;
struct ion_handle *dest_ion_handle;
struct timeval in_time, out_time;
void *cookie;
int32_t *status;
int32_t duplicate_output;
uint32_t duplicate_identity;
struct msm_cpp_buffer_info_t input_buffer_info;
struct msm_cpp_buffer_info_t output_buffer_info[2];
};
struct cpp_hw_info {
uint32_t cpp_hw_version;
uint32_t cpp_hw_caps;
};
struct msm_vpe_frame_strip_info {
uint32_t src_w;
uint32_t src_h;
uint32_t dst_w;
uint32_t dst_h;
uint32_t src_x;
uint32_t src_y;
uint32_t phase_step_x;
uint32_t phase_step_y;
uint32_t phase_init_x;
uint32_t phase_init_y;
};
struct msm_vpe_buffer_info_t {
int fd;
uint32_t index;
uint32_t offset;
uint8_t native_buff;
uint8_t processed_divert;
};
struct msm_vpe_stream_buff_info_t {
uint32_t identity;
uint32_t num_buffs;
struct msm_vpe_buffer_info_t *buffer_info;
};
struct msm_vpe_frame_info_t {
int32_t frame_id;
struct timeval timestamp;
uint32_t inst_id;
uint32_t identity;
uint32_t client_id;
enum msm_vpe_frame_type frame_type;
struct msm_vpe_frame_strip_info strip_info;
int src_fd;
int dst_fd;
struct ion_handle *src_ion_handle;
struct ion_handle *dest_ion_handle;
unsigned long src_phyaddr;
unsigned long dest_phyaddr;
unsigned long src_chroma_plane_offset;
unsigned long dest_chroma_plane_offset;
struct timeval in_time, out_time;
void *cookie;
struct msm_vpe_buffer_info_t input_buffer_info;
struct msm_vpe_buffer_info_t output_buffer_info;
};
#define VIDIOC_MSM_CPP_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_GET_EVENTPAYLOAD \
_IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_GET_INST_INFO \
_IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_LOAD_FIRMWARE \
_IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_GET_HW_INFO \
_IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_FLUSH_QUEUE \
_IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_ENQUEUE_STREAM_BUFF_INFO \
_IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_CPP_DEQUEUE_STREAM_BUFF_INFO \
_IOWR('V', BASE_VIDIOC_PRIVATE + 7, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_VPE_CFG \
_IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_VPE_TRANSACTION_SETUP \
_IOWR('V', BASE_VIDIOC_PRIVATE + 9, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_VPE_GET_EVENTPAYLOAD \
_IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_VPE_GET_INST_INFO \
_IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_VPE_ENQUEUE_STREAM_BUFF_INFO \
_IOWR('V', BASE_VIDIOC_PRIVATE + 12, struct msm_camera_v4l2_ioctl_t)
#define VIDIOC_MSM_VPE_DEQUEUE_STREAM_BUFF_INFO \
_IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_camera_v4l2_ioctl_t)
#define V4L2_EVENT_CPP_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 0)
#define V4L2_EVENT_VPE_FRAME_DONE (V4L2_EVENT_PRIVATE_START + 1)
struct msm_camera_v4l2_ioctl_t {
uint32_t id;
uint32_t len;
int32_t trans_code;
void __user *ioctl_ptr;
};
#endif /* __MSMB_PPROC_H */
kernel/include/media/msp3400.h
+226
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/*
msp3400.h - definition for msp3400 inputs and outputs
Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _MSP3400_H_
#define _MSP3400_H_
/* msp3400 routing
===============
The msp3400 has a complicated routing scheme with many possible
combinations. The details are all in the datasheets but I will try
to give a short description here.
Inputs
======
There are 1) tuner inputs, 2) I2S inputs, 3) SCART inputs. You will have
to select which tuner input to use and which SCART input to use. The
selected tuner input, the selected SCART input and all I2S inputs go to
the DSP (the tuner input first goes through the demodulator).
The DSP handles things like volume, bass/treble, balance, and some chips
have support for surround sound. It has several outputs: MAIN, AUX, I2S
and SCART1/2. Each output can select which DSP input to use. So the MAIN
output can select the tuner input while at the same time the SCART1 output
uses the I2S input.
Outputs
=======
Most DSP outputs are also the outputs of the msp3400. However, the SCART
outputs of the msp3400 can select which input to use: either the SCART1 or
SCART2 output from the DSP, or the msp3400 SCART inputs, thus completely
bypassing the DSP.
Summary
=======
So to specify a complete routing scheme for the msp3400 you will have to
specify in the 'input' arg of the s_routing function:
1) which tuner input to use
2) which SCART input to use
3) which DSP input to use for each DSP output
And in the 'output' arg of the s_routing function you specify:
1) which SCART input to use for each SCART output
Depending on how the msp is wired to the other components you can
ignore or mute certain inputs or outputs.
Also, depending on the msp version only a subset of the inputs or
outputs may be present. At the end of this header some tables are
added containing a list of what is available for each msp version.
*/
/* Inputs to the DSP unit: two independent selections have to be made:
1) the tuner (SIF) input
2) the SCART input
Bits 0-2 are used for the SCART input select, bit 3 is used for the tuner
input, bits 4-7 are reserved.
*/
/* SCART input to DSP selection */
#define MSP_IN_SCART1 0 /* Pin SC1_IN */
#define MSP_IN_SCART2 1 /* Pin SC2_IN */
#define MSP_IN_SCART3 2 /* Pin SC3_IN */
#define MSP_IN_SCART4 3 /* Pin SC4_IN */
#define MSP_IN_MONO 6 /* Pin MONO_IN */
#define MSP_IN_MUTE 7 /* Mute DSP input */
#define MSP_SCART_TO_DSP(in) (in)
/* Tuner input to demodulator and DSP selection */
#define MSP_IN_TUNER1 0 /* Analog Sound IF input pin ANA_IN1 */
#define MSP_IN_TUNER2 1 /* Analog Sound IF input pin ANA_IN2 */
#define MSP_TUNER_TO_DSP(in) ((in) << 3)
/* The msp has up to 5 DSP outputs, each output can independently select
a DSP input.
The DSP outputs are: loudspeaker output (aka MAIN), headphones output
(aka AUX), SCART1 DA output, SCART2 DA output and an I2S output.
There also is a quasi-peak detector output, but that is not used by
this driver and is set to the same input as the loudspeaker output.
Not all outputs are supported by all msp models. Setting the input
of an unsupported output will be ignored by the driver.
There are up to 16 DSP inputs to choose from, so each output is
assigned 4 bits.
Note: the 44x8G can mix two inputs and feed the result back to the
DSP. This is currently not implemented. Also not implemented is the
multi-channel capable I2S3 input of the 44x0G. If someone can demonstrate
a need for one of those features then additional support can be added. */
#define MSP_DSP_IN_TUNER 0 /* Tuner DSP input */
#define MSP_DSP_IN_SCART 2 /* SCART DSP input */
#define MSP_DSP_IN_I2S1 5 /* I2S1 DSP input */
#define MSP_DSP_IN_I2S2 6 /* I2S2 DSP input */
#define MSP_DSP_IN_I2S3 7 /* I2S3 DSP input */
#define MSP_DSP_IN_MAIN_AVC 11 /* MAIN AVC processed DSP input */
#define MSP_DSP_IN_MAIN 12 /* MAIN DSP input */
#define MSP_DSP_IN_AUX 13 /* AUX DSP input */
#define MSP_DSP_TO_MAIN(in) ((in) << 4)
#define MSP_DSP_TO_AUX(in) ((in) << 8)
#define MSP_DSP_TO_SCART1(in) ((in) << 12)
#define MSP_DSP_TO_SCART2(in) ((in) << 16)
#define MSP_DSP_TO_I2S(in) ((in) << 20)
/* Output SCART select: the SCART outputs can select which input
to use. */
#define MSP_SC_IN_SCART1 0 /* SCART1 input, bypassing the DSP */
#define MSP_SC_IN_SCART2 1 /* SCART2 input, bypassing the DSP */
#define MSP_SC_IN_SCART3 2 /* SCART3 input, bypassing the DSP */
#define MSP_SC_IN_SCART4 3 /* SCART4 input, bypassing the DSP */
#define MSP_SC_IN_DSP_SCART1 4 /* DSP SCART1 input */
#define MSP_SC_IN_DSP_SCART2 5 /* DSP SCART2 input */
#define MSP_SC_IN_MONO 6 /* MONO input, bypassing the DSP */
#define MSP_SC_IN_MUTE 7 /* MUTE output */
#define MSP_SC_TO_SCART1(in) (in)
#define MSP_SC_TO_SCART2(in) ((in) << 4)
/* Shortcut macros */
#define MSP_INPUT(sc, t, main_aux_src, sc_i2s_src) \
(MSP_SCART_TO_DSP(sc) | \
MSP_TUNER_TO_DSP(t) | \
MSP_DSP_TO_MAIN(main_aux_src) | \
MSP_DSP_TO_AUX(main_aux_src) | \
MSP_DSP_TO_SCART1(sc_i2s_src) | \
MSP_DSP_TO_SCART2(sc_i2s_src) | \
MSP_DSP_TO_I2S(sc_i2s_src))
#define MSP_INPUT_DEFAULT MSP_INPUT(MSP_IN_SCART1, MSP_IN_TUNER1, \
MSP_DSP_IN_TUNER, MSP_DSP_IN_TUNER)
#define MSP_OUTPUT(sc) \
(MSP_SC_TO_SCART1(sc) | \
MSP_SC_TO_SCART2(sc))
/* This equals the RESET position of the msp3400 ACB register */
#define MSP_OUTPUT_DEFAULT (MSP_SC_TO_SCART1(MSP_SC_IN_SCART3) | \
MSP_SC_TO_SCART2(MSP_SC_IN_DSP_SCART1))
/* Tuner inputs vs. msp version */
/* Chip TUNER_1 TUNER_2
-------------------------
msp34x0b y y
msp34x0c y y
msp34x0d y y
msp34x5d y n
msp34x7d y n
msp34x0g y y
msp34x1g y y
msp34x2g y y
msp34x5g y n
msp34x7g y n
msp44x0g y y
msp44x8g y y
*/
/* SCART inputs vs. msp version */
/* Chip SC1 SC2 SC3 SC4
-------------------------
msp34x0b y y y n
msp34x0c y y y n
msp34x0d y y y y
msp34x5d y y n n
msp34x7d y n n n
msp34x0g y y y y
msp34x1g y y y y
msp34x2g y y y y
msp34x5g y y n n
msp34x7g y n n n
msp44x0g y y y y
msp44x8g y y y y
*/
/* DSP inputs vs. msp version (tuner and SCART inputs are always available) */
/* Chip I2S1 I2S2 I2S3 MAIN_AVC MAIN AUX
------------------------------------------
msp34x0b y n n n n n
msp34x0c y y n n n n
msp34x0d y y n n n n
msp34x5d y y n n n n
msp34x7d n n n n n n
msp34x0g y y n n n n
msp34x1g y y n n n n
msp34x2g y y n y y y
msp34x5g y y n n n n
msp34x7g n n n n n n
msp44x0g y y y y y y
msp44x8g y y y n n n
*/
/* DSP outputs vs. msp version */
/* Chip MAIN AUX SCART1 SCART2 I2S
------------------------------------
msp34x0b y y y n y
msp34x0c y y y n y
msp34x0d y y y y y
msp34x5d y n y n y
msp34x7d y n y n n
msp34x0g y y y y y
msp34x1g y y y y y
msp34x2g y y y y y
msp34x5g y n y n y
msp34x7g y n y n n
msp44x0g y y y y y
msp44x8g y y y y y
*/
#endif /* MSP3400_H */
kernel/include/media/mt9m032.h
+36
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/*
* Driver for MT9M032 CMOS Image Sensor from Micron
*
* Copyright (C) 2010-2011 Lund Engineering
* Contact: Gil Lund <gwlund@lundeng.com>
* Author: Martin Hostettler <martin@neutronstar.dyndns.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#ifndef MT9M032_H
#define MT9M032_H
#define MT9M032_NAME "mt9m032"
#define MT9M032_I2C_ADDR (0xb8 >> 1)
struct mt9m032_platform_data {
u32 ext_clock;
u32 pix_clock;
bool invert_pixclock;
};
#endif /* MT9M032_H */
kernel/include/media/mt9p031.h
+19
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@@ -0,0 +1,19 @@
#ifndef MT9P031_H
#define MT9P031_H
struct v4l2_subdev;
enum {
MT9P031_COLOR_VERSION,
MT9P031_MONOCHROME_VERSION,
};
struct mt9p031_platform_data {
int (*set_xclk)(struct v4l2_subdev *subdev, int hz);
int (*reset)(struct v4l2_subdev *subdev, int active);
int ext_freq; /* input frequency to the mt9p031 for PLL dividers */
int target_freq; /* frequency target for the PLL */
int version; /* MT9P031_COLOR_VERSION or MT9P031_MONOCHROME_VERSION */
};
#endif
kernel/include/media/mt9t001.h
+8
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@@ -0,0 +1,8 @@
#ifndef _MEDIA_MT9T001_H
#define _MEDIA_MT9T001_H
struct mt9t001_platform_data {
unsigned int clk_pol:1;
};
#endif
kernel/include/media/mt9t112.h
+30
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@@ -0,0 +1,30 @@
/* mt9t112 Camera
*
* Copyright (C) 2009 Renesas Solutions Corp.
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __MT9T112_H__
#define __MT9T112_H__
#define MT9T112_FLAG_PCLK_RISING_EDGE (1 << 0)
#define MT9T112_FLAG_DATAWIDTH_8 (1 << 1) /* default width is 10 */
struct mt9t112_pll_divider {
u8 m, n;
u8 p1, p2, p3, p4, p5, p6, p7;
};
/*
* mt9t112 camera info
*/
struct mt9t112_camera_info {
u32 flags;
struct mt9t112_pll_divider divider;
};
#endif /* __MT9T112_H__ */
kernel/include/media/mt9v011.h
+17
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@@ -0,0 +1,17 @@
/* mt9v011 sensor
*
* Copyright (C) 2011 Hans Verkuil <hverkuil@xs4all.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __MT9V011_H__
#define __MT9V011_H__
struct mt9v011_platform_data {
unsigned xtal; /* Hz */
};
#endif
kernel/include/media/mt9v032.h
+12
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@@ -0,0 +1,12 @@
#ifndef _MEDIA_MT9V032_H
#define _MEDIA_MT9V032_H
struct v4l2_subdev;
struct mt9v032_platform_data {
unsigned int clk_pol:1;
void (*set_clock)(struct v4l2_subdev *subdev, unsigned int rate);
};
#endif
kernel/include/media/noon010pc30.h
+28
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@@ -0,0 +1,28 @@
/*
* Driver header for NOON010PC30L camera sensor chip.
*
* Copyright (c) 2010 Samsung Electronics, Co. Ltd
* Contact: Sylwester Nawrocki <s.nawrocki@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef NOON010PC30_H
#define NOON010PC30_H
/**
* @clk_rate: the clock frequency in Hz
* @gpio_nreset: GPIO driving nRESET pin
* @gpio_nstby: GPIO driving nSTBY pin
*/
struct noon010pc30_platform_data {
unsigned long clk_rate;
int gpio_nreset;
int gpio_nstby;
};
#endif /* NOON010PC30_H */
kernel/include/media/omap1_camera.h
+35
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/*
* Header for V4L2 SoC Camera driver for OMAP1 Camera Interface
*
* Copyright (C) 2010, Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __MEDIA_OMAP1_CAMERA_H_
#define __MEDIA_OMAP1_CAMERA_H_
#include <linux/bitops.h>
#define OMAP1_CAMERA_IOSIZE 0x1c
enum omap1_cam_vb_mode {
OMAP1_CAM_DMA_CONTIG = 0,
OMAP1_CAM_DMA_SG,
};
#define OMAP1_CAMERA_MIN_BUF_COUNT(x) ((x) == OMAP1_CAM_DMA_CONTIG ? 3 : 2)
struct omap1_cam_platform_data {
unsigned long camexclk_khz;
unsigned long lclk_khz_max;
unsigned long flags;
};
#define OMAP1_CAMERA_LCLK_RISING BIT(0)
#define OMAP1_CAMERA_RST_LOW BIT(1)
#define OMAP1_CAMERA_RST_HIGH BIT(2)
#endif /* __MEDIA_OMAP1_CAMERA_H_ */
kernel/include/media/omap3isp.h
+140
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/*
* omap3isp.h
*
* TI OMAP3 ISP - Platform data
*
* Copyright (C) 2011 Nokia Corporation
*
* Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
* Sakari Ailus <sakari.ailus@iki.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef __MEDIA_OMAP3ISP_H__
#define __MEDIA_OMAP3ISP_H__
struct i2c_board_info;
struct isp_device;
enum isp_interface_type {
ISP_INTERFACE_PARALLEL,
ISP_INTERFACE_CSI2A_PHY2,
ISP_INTERFACE_CCP2B_PHY1,
ISP_INTERFACE_CCP2B_PHY2,
ISP_INTERFACE_CSI2C_PHY1,
};
enum {
ISP_BRIDGE_DISABLE = 0,
ISP_BRIDGE_LITTLE_ENDIAN = 2,
ISP_BRIDGE_BIG_ENDIAN = 3,
};
enum {
ISP_LANE_SHIFT_0 = 0,
ISP_LANE_SHIFT_2 = 1,
ISP_LANE_SHIFT_4 = 2,
ISP_LANE_SHIFT_6 = 3,
};
/**
* struct isp_parallel_platform_data - Parallel interface platform data
* @data_lane_shift: Data lane shifter
* ISP_LANE_SHIFT_0 - CAMEXT[13:0] -> CAM[13:0]
* ISP_LANE_SHIFT_2 - CAMEXT[13:2] -> CAM[11:0]
* ISP_LANE_SHIFT_4 - CAMEXT[13:4] -> CAM[9:0]
* ISP_LANE_SHIFT_6 - CAMEXT[13:6] -> CAM[7:0]
* @clk_pol: Pixel clock polarity
* 0 - Sample on rising edge, 1 - Sample on falling edge
* @hs_pol: Horizontal synchronization polarity
* 0 - Active high, 1 - Active low
* @vs_pol: Vertical synchronization polarity
* 0 - Active high, 1 - Active low
* @bridge: CCDC Bridge input control
* ISP_BRIDGE_DISABLE - Disable
* ISP_BRIDGE_LITTLE_ENDIAN - Little endian
* ISP_BRIDGE_BIG_ENDIAN - Big endian
*/
struct isp_parallel_platform_data {
unsigned int data_lane_shift:2;
unsigned int clk_pol:1;
unsigned int hs_pol:1;
unsigned int vs_pol:1;
unsigned int bridge:2;
};
enum {
ISP_CCP2_PHY_DATA_CLOCK = 0,
ISP_CCP2_PHY_DATA_STROBE = 1,
};
enum {
ISP_CCP2_MODE_MIPI = 0,
ISP_CCP2_MODE_CCP2 = 1,
};
/**
* struct isp_ccp2_platform_data - CCP2 interface platform data
* @strobe_clk_pol: Strobe/clock polarity
* 0 - Non Inverted, 1 - Inverted
* @crc: Enable the cyclic redundancy check
* @ccp2_mode: Enable CCP2 compatibility mode
* ISP_CCP2_MODE_MIPI - MIPI-CSI1 mode
* ISP_CCP2_MODE_CCP2 - CCP2 mode
* @phy_layer: Physical layer selection
* ISP_CCP2_PHY_DATA_CLOCK - Data/clock physical layer
* ISP_CCP2_PHY_DATA_STROBE - Data/strobe physical layer
* @vpclk_div: Video port output clock control
*/
struct isp_ccp2_platform_data {
unsigned int strobe_clk_pol:1;
unsigned int crc:1;
unsigned int ccp2_mode:1;
unsigned int phy_layer:1;
unsigned int vpclk_div:2;
};
/**
* struct isp_csi2_platform_data - CSI2 interface platform data
* @crc: Enable the cyclic redundancy check
* @vpclk_div: Video port output clock control
*/
struct isp_csi2_platform_data {
unsigned crc:1;
unsigned vpclk_div:2;
};
struct isp_subdev_i2c_board_info {
struct i2c_board_info *board_info;
int i2c_adapter_id;
};
struct isp_v4l2_subdevs_group {
struct isp_subdev_i2c_board_info *subdevs;
enum isp_interface_type interface;
union {
struct isp_parallel_platform_data parallel;
struct isp_ccp2_platform_data ccp2;
struct isp_csi2_platform_data csi2;
} bus; /* gcc < 4.6.0 chokes on anonymous union initializers */
};
struct isp_platform_data {
struct isp_v4l2_subdevs_group *subdevs;
void (*set_constraints)(struct isp_device *isp, bool enable);
};
#endif /* __MEDIA_OMAP3ISP_H__ */
kernel/include/media/ov7670.h
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/*
* A V4L2 driver for OmniVision OV7670 cameras.
*
* Copyright 2010 One Laptop Per Child
*
* This file may be distributed under the terms of the GNU General
* Public License, version 2.
*/
#ifndef __OV7670_H
#define __OV7670_H
struct ov7670_config {
int min_width; /* Filter out smaller sizes */
int min_height; /* Filter out smaller sizes */
int clock_speed; /* External clock speed (MHz) */
bool use_smbus; /* Use smbus I/O instead of I2C */
};
#endif
kernel/include/media/ov772x.h
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/*
* ov772x Camera
*
* Copyright (C) 2008 Renesas Solutions Corp.
* Kuninori Morimoto <morimoto.kuninori@renesas.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __OV772X_H__
#define __OV772X_H__
/* for flags */
#define OV772X_FLAG_VFLIP (1 << 0) /* Vertical flip image */
#define OV772X_FLAG_HFLIP (1 << 1) /* Horizontal flip image */
/*
* for Edge ctrl
*
* strength also control Auto or Manual Edge Control Mode
* see also OV772X_MANUAL_EDGE_CTRL
*/
struct ov772x_edge_ctrl {
unsigned char strength;
unsigned char threshold;
unsigned char upper;
unsigned char lower;
};
#define OV772X_MANUAL_EDGE_CTRL 0x80 /* un-used bit of strength */
#define OV772X_EDGE_STRENGTH_MASK 0x1F
#define OV772X_EDGE_THRESHOLD_MASK 0x0F
#define OV772X_EDGE_UPPER_MASK 0xFF
#define OV772X_EDGE_LOWER_MASK 0xFF
#define OV772X_AUTO_EDGECTRL(u, l) \
{ \
.upper = (u & OV772X_EDGE_UPPER_MASK), \
.lower = (l & OV772X_EDGE_LOWER_MASK), \
}
#define OV772X_MANUAL_EDGECTRL(s, t) \
{ \
.strength = (s & OV772X_EDGE_STRENGTH_MASK) | \
OV772X_MANUAL_EDGE_CTRL, \
.threshold = (t & OV772X_EDGE_THRESHOLD_MASK), \
}
/*
* ov772x camera info
*/
struct ov772x_camera_info {
unsigned long flags;
struct ov772x_edge_ctrl edgectrl;
};
#endif /* __OV772X_H__ */
kernel/include/media/radio-iris-commands.h
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#ifndef __RADIO_IRIS_COMMANDS_H
#define __RADIO_IRIS_COMMANDS_H
#include <linux/skbuff.h>
#include <linux/interrupt.h>
#include <linux/mutex.h>
#include <linux/atomic.h>
enum v4l2_cid_private_iris_t {
V4L2_CID_PRIVATE_IRIS_SRCHMODE = (0x08000000 + 1),
V4L2_CID_PRIVATE_IRIS_SCANDWELL,
V4L2_CID_PRIVATE_IRIS_SRCHON,
V4L2_CID_PRIVATE_IRIS_STATE,
V4L2_CID_PRIVATE_IRIS_TRANSMIT_MODE,
V4L2_CID_PRIVATE_IRIS_RDSGROUP_MASK,
V4L2_CID_PRIVATE_IRIS_REGION,
V4L2_CID_PRIVATE_IRIS_SIGNAL_TH,
V4L2_CID_PRIVATE_IRIS_SRCH_PTY,
V4L2_CID_PRIVATE_IRIS_SRCH_PI,
V4L2_CID_PRIVATE_IRIS_SRCH_CNT,
V4L2_CID_PRIVATE_IRIS_EMPHASIS,
V4L2_CID_PRIVATE_IRIS_RDS_STD,
V4L2_CID_PRIVATE_IRIS_SPACING,
V4L2_CID_PRIVATE_IRIS_RDSON,
V4L2_CID_PRIVATE_IRIS_RDSGROUP_PROC,
V4L2_CID_PRIVATE_IRIS_LP_MODE,
V4L2_CID_PRIVATE_IRIS_ANTENNA,
V4L2_CID_PRIVATE_IRIS_RDSD_BUF,
V4L2_CID_PRIVATE_IRIS_PSALL, /*0x8000014*/
/*v4l2 Tx controls*/
V4L2_CID_PRIVATE_IRIS_TX_SETPSREPEATCOUNT,
V4L2_CID_PRIVATE_IRIS_STOP_RDS_TX_PS_NAME,
V4L2_CID_PRIVATE_IRIS_STOP_RDS_TX_RT,
V4L2_CID_PRIVATE_IRIS_IOVERC,
V4L2_CID_PRIVATE_IRIS_INTDET,
V4L2_CID_PRIVATE_IRIS_MPX_DCC,
V4L2_CID_PRIVATE_IRIS_AF_JUMP,
V4L2_CID_PRIVATE_IRIS_RSSI_DELTA,
V4L2_CID_PRIVATE_IRIS_HLSI, /*0x800001d*/
/*Diagnostic commands*/
V4L2_CID_PRIVATE_IRIS_SOFT_MUTE,
V4L2_CID_PRIVATE_IRIS_RIVA_ACCS_ADDR,
V4L2_CID_PRIVATE_IRIS_RIVA_ACCS_LEN,
V4L2_CID_PRIVATE_IRIS_RIVA_PEEK,
V4L2_CID_PRIVATE_IRIS_RIVA_POKE,
V4L2_CID_PRIVATE_IRIS_SSBI_ACCS_ADDR,
V4L2_CID_PRIVATE_IRIS_SSBI_PEEK,
V4L2_CID_PRIVATE_IRIS_SSBI_POKE,
V4L2_CID_PRIVATE_IRIS_TX_TONE,
V4L2_CID_PRIVATE_IRIS_RDS_GRP_COUNTERS,
V4L2_CID_PRIVATE_IRIS_SET_NOTCH_FILTER, /* 0x8000028 */
V4L2_CID_PRIVATE_IRIS_SET_AUDIO_PATH, /* TAVARUA specific command */
V4L2_CID_PRIVATE_IRIS_DO_CALIBRATION,
V4L2_CID_PRIVATE_IRIS_SRCH_ALGORITHM, /* TAVARUA specific command */
V4L2_CID_PRIVATE_IRIS_GET_SINR,
V4L2_CID_PRIVATE_INTF_LOW_THRESHOLD,
V4L2_CID_PRIVATE_INTF_HIGH_THRESHOLD,
V4L2_CID_PRIVATE_SINR_THRESHOLD,
V4L2_CID_PRIVATE_SINR_SAMPLES,
V4L2_CID_PRIVATE_SPUR_FREQ,
V4L2_CID_PRIVATE_SPUR_FREQ_RMSSI,
V4L2_CID_PRIVATE_SPUR_SELECTION,
V4L2_CID_PRIVATE_UPDATE_SPUR_TABLE,
V4L2_CID_PRIVATE_VALID_CHANNEL,
V4L2_CID_PRIVATE_AF_RMSSI_TH,
V4L2_CID_PRIVATE_AF_RMSSI_SAMPLES,
V4L2_CID_PRIVATE_GOOD_CH_RMSSI_TH,
V4L2_CID_PRIVATE_SRCHALGOTYPE,
V4L2_CID_PRIVATE_CF0TH12,
V4L2_CID_PRIVATE_SINRFIRSTSTAGE,
V4L2_CID_PRIVATE_RMSSIFIRSTSTAGE,
V4L2_CID_PRIVATE_RXREPEATCOUNT,
/*using private CIDs under userclass*/
V4L2_CID_PRIVATE_IRIS_READ_DEFAULT = 0x00980928,
V4L2_CID_PRIVATE_IRIS_WRITE_DEFAULT,
V4L2_CID_PRIVATE_IRIS_SET_CALIBRATION,
};
enum iris_evt_t {
IRIS_EVT_RADIO_READY,
IRIS_EVT_TUNE_SUCC,
IRIS_EVT_SEEK_COMPLETE,
IRIS_EVT_SCAN_NEXT,
IRIS_EVT_NEW_RAW_RDS,
IRIS_EVT_NEW_RT_RDS,
IRIS_EVT_NEW_PS_RDS,
IRIS_EVT_ERROR,
IRIS_EVT_BELOW_TH,
IRIS_EVT_ABOVE_TH,
IRIS_EVT_STEREO,
IRIS_EVT_MONO,
IRIS_EVT_RDS_AVAIL,
IRIS_EVT_RDS_NOT_AVAIL,
IRIS_EVT_NEW_SRCH_LIST,
IRIS_EVT_NEW_AF_LIST,
IRIS_EVT_TXRDSDAT,
IRIS_EVT_TXRDSDONE,
IRIS_EVT_RADIO_DISABLED,
IRIS_EVT_NEW_ODA,
IRIS_EVT_NEW_RT_PLUS,
IRIS_EVT_NEW_ERT,
};
#endif /* __RADIO_IRIS_COMMANDS_H */
kernel/include/media/radio-iris.h
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/*
*
* Copyright (c) 2011-2013 The Linux Foundation. All rights reserved.
*
* This file is based on include/net/bluetooth/hci_core.h
*
* Written 2000,2001 by Maxim Krasnyansky <maxk@qualcomm.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation;
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS.
* IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) AND AUTHOR(S) BE LIABLE FOR ANY
* CLAIM, OR ANY SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF ANY PATENTS,
* COPYRIGHTS, TRADEMARKS OR OTHER RIGHTS, RELATING TO USE OF THIS
* SOFTWARE IS DISCLAIMED.
*/
#ifndef __RADIO_HCI_CORE_H
#define __RADIO_HCI_CORE_H
#include <linux/skbuff.h>
#include <linux/interrupt.h>
#include <linux/mutex.h>
#include <linux/atomic.h>
#include "radio-iris-commands.h"
/* ---- HCI Packet structures ---- */
#define RADIO_HCI_COMMAND_HDR_SIZE sizeof(struct radio_hci_command_hdr)
#define RADIO_HCI_EVENT_HDR_SIZE sizeof(struct radio_hci_event_hdr)
/* HCI data types */
#define RADIO_HCI_COMMAND_PKT 0x11
#define RADIO_HCI_EVENT_PKT 0x14
/*HCI reponce packets*/
#define MAX_RIVA_PEEK_RSP_SIZE 251
/* default data access */
#define DEFAULT_DATA_OFFSET 2
#define DEFAULT_DATA_SIZE 249
/* Power levels are 0-7, but SOC will expect values from 0-255
* So the each level step size will be 255/7 = 36 */
#define FM_TX_PWR_LVL_STEP_SIZE 36
#define FM_TX_PWR_LVL_0 0 /* Lowest power lvl that can be set for Tx */
#define FM_TX_PWR_LVL_MAX 7 /* Max power lvl for Tx */
#define FM_TX_PHY_CFG_MODE 0x3c
#define FM_TX_PHY_CFG_LEN 0x10
#define FM_TX_PWR_GAIN_OFFSET 14
/**RDS CONFIG MODE**/
#define FM_RDS_CNFG_MODE 0x0f
#define FM_RDS_CNFG_LEN 0x10
#define AF_RMSSI_TH_LSB_OFFSET 10
#define AF_RMSSI_TH_MSB_OFFSET 11
#define AF_RMSSI_SAMPLES_OFFSET 15
/**RX CONFIG MODE**/
#define FM_RX_CONFG_MODE 0x15
#define FM_RX_CNFG_LEN 0x20
#define GD_CH_RMSSI_TH_OFFSET 12
#define MAX_GD_CH_RMSSI_TH 127
#define SRCH_ALGO_TYPE_OFFSET 25
#define SINRFIRSTSTAGE_OFFSET 26
#define RMSSIFIRSTSTAGE_OFFSET 27
#define CF0TH12_BYTE1_OFFSET 8
#define CF0TH12_BYTE2_OFFSET 9
#define CF0TH12_BYTE3_OFFSET 10
#define CF0TH12_BYTE4_OFFSET 11
#define MAX_SINR_FIRSTSTAGE 127
#define MAX_RMSSI_FIRSTSTAGE 127
#define RDS_PS0_XFR_MODE 0x01
#define RDS_PS0_LEN 6
#define RX_REPEATE_BYTE_OFFSET 5
/* HCI timeouts */
#define RADIO_HCI_TIMEOUT (10000) /* 10 seconds */
#define TUNE_PARAM 16
struct radio_hci_command_hdr {
__le16 opcode; /* OCF & OGF */
__u8 plen;
} __packed;
struct radio_hci_event_hdr {
__u8 evt;
__u8 plen;
} __packed;
struct radio_hci_dev {
char name[8];
unsigned long flags;
__u16 id;
__u8 bus;
__u8 dev_type;
__u8 dev_name[248];
__u8 dev_class[3];
__u8 features[8];
__u8 commands[64];
unsigned int data_block_len;
unsigned long cmd_last_tx;
struct sk_buff *sent_cmd;
__u32 req_status;
__u32 req_result;
atomic_t cmd_cnt;
struct tasklet_struct cmd_task;
struct tasklet_struct rx_task;
struct tasklet_struct tx_task;
struct sk_buff_head rx_q;
struct sk_buff_head raw_q;
struct sk_buff_head cmd_q;
struct mutex req_lock;
wait_queue_head_t req_wait_q;
int (*open)(struct radio_hci_dev *hdev);
int (*close)(struct radio_hci_dev *hdev);
int (*flush)(struct radio_hci_dev *hdev);
int (*send)(struct sk_buff *skb);
void (*destruct)(struct radio_hci_dev *hdev);
void (*notify)(struct radio_hci_dev *hdev, unsigned int evt);
};
int radio_hci_register_dev(struct radio_hci_dev *hdev);
int radio_hci_unregister_dev(struct radio_hci_dev *hdev);
int radio_hci_recv_frame(struct sk_buff *skb);
int radio_hci_send_cmd(struct radio_hci_dev *hdev, __u16 opcode, __u32 plen,
void *param);
void radio_hci_event_packet(struct radio_hci_dev *hdev, struct sk_buff *skb);
/* Opcode OCF */
/* HCI recv control commands opcode */
#define HCI_OCF_FM_ENABLE_RECV_REQ 0x0001
#define HCI_OCF_FM_DISABLE_RECV_REQ 0x0002
#define HCI_OCF_FM_GET_RECV_CONF_REQ 0x0003
#define HCI_OCF_FM_SET_RECV_CONF_REQ 0x0004
#define HCI_OCF_FM_SET_MUTE_MODE_REQ 0x0005
#define HCI_OCF_FM_SET_STEREO_MODE_REQ 0x0006
#define HCI_OCF_FM_SET_ANTENNA 0x0007
#define HCI_OCF_FM_SET_SIGNAL_THRESHOLD 0x0008
#define HCI_OCF_FM_GET_SIGNAL_THRESHOLD 0x0009
#define HCI_OCF_FM_GET_STATION_PARAM_REQ 0x000A
#define HCI_OCF_FM_GET_PROGRAM_SERVICE_REQ 0x000B
#define HCI_OCF_FM_GET_RADIO_TEXT_REQ 0x000C
#define HCI_OCF_FM_GET_AF_LIST_REQ 0x000D
#define HCI_OCF_FM_SEARCH_STATIONS 0x000E
#define HCI_OCF_FM_SEARCH_RDS_STATIONS 0x000F
#define HCI_OCF_FM_SEARCH_STATIONS_LIST 0x0010
#define HCI_OCF_FM_CANCEL_SEARCH 0x0011
#define HCI_OCF_FM_RDS_GRP 0x0012
#define HCI_OCF_FM_RDS_GRP_PROCESS 0x0013
#define HCI_OCF_FM_EN_WAN_AVD_CTRL 0x0014
#define HCI_OCF_FM_EN_NOTCH_CTRL 0x0015
#define HCI_OCF_FM_SET_EVENT_MASK 0x0016
#define HCI_OCF_FM_SET_CH_DET_THRESHOLD 0x0017
#define HCI_OCF_FM_GET_CH_DET_THRESHOLD 0x0018
/* HCI trans control commans opcode*/
#define HCI_OCF_FM_ENABLE_TRANS_REQ 0x0001
#define HCI_OCF_FM_DISABLE_TRANS_REQ 0x0002
#define HCI_OCF_FM_GET_TRANS_CONF_REQ 0x0003
#define HCI_OCF_FM_SET_TRANS_CONF_REQ 0x0004
#define HCI_OCF_FM_RDS_RT_REQ 0x0008
#define HCI_OCF_FM_RDS_PS_REQ 0x0009
/* HCI common control commands opcode */
#define HCI_OCF_FM_TUNE_STATION_REQ 0x0001
#define HCI_OCF_FM_DEFAULT_DATA_READ 0x0002
#define HCI_OCF_FM_DEFAULT_DATA_WRITE 0x0003
#define HCI_OCF_FM_RESET 0x0004
#define HCI_OCF_FM_GET_FEATURE_LIST 0x0005
#define HCI_OCF_FM_DO_CALIBRATION 0x0006
#define HCI_OCF_FM_SET_CALIBRATION 0x0007
/*HCI Status parameters commands*/
#define HCI_OCF_FM_READ_GRP_COUNTERS 0x0001
/*HCI Diagnostic commands*/
#define HCI_OCF_FM_PEEK_DATA 0x0002
#define HCI_OCF_FM_POKE_DATA 0x0003
#define HCI_OCF_FM_SSBI_PEEK_REG 0x0004
#define HCI_OCF_FM_SSBI_POKE_REG 0x0005
#define HCI_OCF_FM_STATION_DBG_PARAM 0x0007
#define HCI_FM_SET_INTERNAL_TONE_GENRATOR 0x0008
/* Opcode OGF */
#define HCI_OGF_FM_RECV_CTRL_CMD_REQ 0x0013
#define HCI_OGF_FM_TRANS_CTRL_CMD_REQ 0x0014
#define HCI_OGF_FM_COMMON_CTRL_CMD_REQ 0x0015
#define HCI_OGF_FM_STATUS_PARAMETERS_CMD_REQ 0x0016
#define HCI_OGF_FM_TEST_CMD_REQ 0x0017
#define HCI_OGF_FM_DIAGNOSTIC_CMD_REQ 0x003F
/* Command opcode pack/unpack */
#define hci_opcode_pack(ogf, ocf) (__u16) ((ocf & 0x03ff)|(ogf << 10))
#define hci_opcode_ogf(op) (op >> 10)
#define hci_opcode_ocf(op) (op & 0x03ff)
#define hci_recv_ctrl_cmd_op_pack(ocf) \
(__u16) hci_opcode_pack(HCI_OGF_FM_RECV_CTRL_CMD_REQ, ocf)
#define hci_trans_ctrl_cmd_op_pack(ocf) \
(__u16) hci_opcode_pack(HCI_OGF_FM_TRANS_CTRL_CMD_REQ, ocf)
#define hci_common_cmd_op_pack(ocf) \
(__u16) hci_opcode_pack(HCI_OGF_FM_COMMON_CTRL_CMD_REQ, ocf)
#define hci_status_param_op_pack(ocf) \
(__u16) hci_opcode_pack(HCI_OGF_FM_STATUS_PARAMETERS_CMD_REQ, ocf)
#define hci_diagnostic_cmd_op_pack(ocf) \
(__u16) hci_opcode_pack(HCI_OGF_FM_DIAGNOSTIC_CMD_REQ, ocf)
/* HCI commands with no arguments*/
#define HCI_FM_ENABLE_RECV_CMD 1
#define HCI_FM_DISABLE_RECV_CMD 2
#define HCI_FM_GET_RECV_CONF_CMD 3
#define HCI_FM_GET_STATION_PARAM_CMD 4
#define HCI_FM_GET_SIGNAL_TH_CMD 5
#define HCI_FM_GET_PROGRAM_SERVICE_CMD 6
#define HCI_FM_GET_RADIO_TEXT_CMD 7
#define HCI_FM_GET_AF_LIST_CMD 8
#define HCI_FM_CANCEL_SEARCH_CMD 9
#define HCI_FM_RESET_CMD 10
#define HCI_FM_GET_FEATURES_CMD 11
#define HCI_FM_STATION_DBG_PARAM_CMD 12
#define HCI_FM_ENABLE_TRANS_CMD 13
#define HCI_FM_DISABLE_TRANS_CMD 14
#define HCI_FM_GET_TX_CONFIG 15
#define HCI_FM_GET_DET_CH_TH_CMD 16
/* Defines for FM TX*/
#define TX_PS_DATA_LENGTH 108
#define TX_RT_DATA_LENGTH 64
#define PS_STRING_LEN 9
/* ----- HCI Command request ----- */
struct hci_fm_recv_conf_req {
__u8 emphasis;
__u8 ch_spacing;
__u8 rds_std;
__u8 hlsi;
__u32 band_low_limit;
__u32 band_high_limit;
} __packed;
/* ----- HCI Command request ----- */
struct hci_fm_trans_conf_req_struct {
__u8 emphasis;
__u8 rds_std;
__u32 band_low_limit;
__u32 band_high_limit;
} __packed;
/* ----- HCI Command request ----- */
struct hci_fm_tx_ps {
__u8 ps_control;
__u16 pi;
__u8 pty;
__u8 ps_repeatcount;
__u8 ps_num;
__u8 ps_data[TX_PS_DATA_LENGTH];
} __packed;
struct hci_fm_tx_rt {
__u8 rt_control;
__u16 pi;
__u8 pty;
__u8 rt_len;
__u8 rt_data[TX_RT_DATA_LENGTH];
} __packed;
struct hci_fm_mute_mode_req {
__u8 hard_mute;
__u8 soft_mute;
} __packed;
struct hci_fm_stereo_mode_req {
__u8 stereo_mode;
__u8 sig_blend;
__u8 intf_blend;
__u8 most_switch;
} __packed;
struct hci_fm_search_station_req {
__u8 srch_mode;
__u8 scan_time;
__u8 srch_dir;
} __packed;
struct hci_fm_search_rds_station_req {
struct hci_fm_search_station_req srch_station;
__u8 srch_pty;
__u16 srch_pi;
} __packed;
struct hci_fm_search_station_list_req {
__u8 srch_list_mode;
__u8 srch_list_dir;
__u32 srch_list_max;
__u8 srch_pty;
} __packed;
struct hci_fm_rds_grp_req {
__u32 rds_grp_enable_mask;
__u32 rds_buf_size;
__u8 en_rds_change_filter;
} __packed;
struct hci_fm_en_avd_ctrl_req {
__u8 no_freqs;
__u8 freq_index;
__u8 lo_shft;
__u16 freq_min;
__u16 freq_max;
} __packed;
struct hci_fm_def_data_rd_req {
__u8 mode;
__u8 length;
__u8 param_len;
__u8 param;
} __packed;
struct hci_fm_def_data_wr_req {
__u8 mode;
__u8 length;
__u8 data[DEFAULT_DATA_SIZE];
} __packed;
struct hci_fm_riva_data {
__u8 subopcode;
__u32 start_addr;
__u8 length;
} __packed;
struct hci_fm_riva_poke {
struct hci_fm_riva_data cmd_params;
__u8 data[MAX_RIVA_PEEK_RSP_SIZE];
} __packed;
struct hci_fm_ssbi_req {
__u16 start_addr;
__u8 data;
} __packed;
struct hci_fm_ssbi_peek {
__u16 start_address;
} __packed;
struct hci_fm_ch_det_threshold {
char sinr;
__u8 sinr_samples;
__u8 low_th;
__u8 high_th;
} __packed;
/*HCI events*/
#define HCI_EV_TUNE_STATUS 0x01
#define HCI_EV_RDS_LOCK_STATUS 0x02
#define HCI_EV_STEREO_STATUS 0x03
#define HCI_EV_SERVICE_AVAILABLE 0x04
#define HCI_EV_SEARCH_PROGRESS 0x05
#define HCI_EV_SEARCH_RDS_PROGRESS 0x06
#define HCI_EV_SEARCH_LIST_PROGRESS 0x07
#define HCI_EV_RDS_RX_DATA 0x08
#define HCI_EV_PROGRAM_SERVICE 0x09
#define HCI_EV_RADIO_TEXT 0x0A
#define HCI_EV_FM_AF_LIST 0x0B
#define HCI_EV_TX_RDS_GRP_AVBLE 0x0C
#define HCI_EV_TX_RDS_GRP_COMPL 0x0D
#define HCI_EV_TX_RDS_CONT_GRP_COMPL 0x0E
#define HCI_EV_CMD_COMPLETE 0x0F
#define HCI_EV_CMD_STATUS 0x10
#define HCI_EV_TUNE_COMPLETE 0x11
#define HCI_EV_SEARCH_COMPLETE 0x12
#define HCI_EV_SEARCH_RDS_COMPLETE 0x13
#define HCI_EV_SEARCH_LIST_COMPLETE 0x14
#define HCI_REQ_DONE 0
#define HCI_REQ_PEND 1
#define HCI_REQ_CANCELED 2
#define HCI_REQ_STATUS 3
#define MAX_RAW_RDS_GRPS 21
#define RDSGRP_DATA_OFFSET 0x1
/*RT PLUS*/
#define DUMMY_CLASS 0
#define RT_PLUS_LEN_1_TAG 3
#define RT_ERT_FLAG_BIT 5
/*TAG1*/
#define TAG1_MSB_OFFSET 3
#define TAG1_MSB_MASK 7
#define TAG1_LSB_OFFSET 5
#define TAG1_POS_MSB_MASK 31
#define TAG1_POS_MSB_OFFSET 1
#define TAG1_POS_LSB_OFFSET 7
#define TAG1_LEN_OFFSET 1
#define TAG1_LEN_MASK 63
/*TAG2*/
#define TAG2_MSB_OFFSET 5
#define TAG2_MSB_MASK 1
#define TAG2_LSB_OFFSET 3
#define TAG2_POS_MSB_MASK 7
#define TAG2_POS_MSB_OFFSET 3
#define TAG2_POS_LSB_OFFSET 5
#define TAG2_LEN_MASK 31
#define AGT_MASK 31
/*Extract 5 left most bits of lsb of 2nd block*/
#define AGT(x) (x & AGT_MASK)
/*16 bits of 4th block*/
#define AID(lsb, msb) ((msb << 8) | (lsb))
/*Extract 5 right most bits of msb of 2nd block*/
#define GTC(blk2msb) (blk2msb >> 3)
#define GRP_3A 0x6
#define RT_PLUS_AID 0x4bd7
/*ERT*/
#define ERT_AID 0x6552
#define CARRIAGE_RETURN 0x000D
#define MAX_ERT_SEGMENT 31
#define ERT_FORMAT_DIR_BIT 1
#define EXTRACT_BIT(data, bit_pos) ((data & (1 << bit_pos)) >> bit_pos)
struct hci_ev_tune_status {
__u8 sub_event;
__le32 station_freq;
__u8 serv_avble;
__u8 rssi;
__u8 stereo_prg;
__u8 rds_sync_status;
__u8 mute_mode;
char sinr;
__u8 intf_det_th;
} __packed;
struct rds_blk_data {
__u8 rdsMsb;
__u8 rdsLsb;
__u8 blockStatus;
} __packed;
struct rds_grp_data {
struct rds_blk_data rdsBlk[4];
} __packed;
struct hci_ev_rds_rx_data {
__u8 num_rds_grps;
struct rds_grp_data rds_grp_data[MAX_RAW_RDS_GRPS];
} __packed;
struct hci_ev_prg_service {
__le16 pi_prg_id;
__u8 pty_prg_type;
__u8 ta_prg_code_type;
__u8 ta_ann_code_flag;
__u8 ms_switch_code_flag;
__u8 dec_id_ctrl_code_flag;
__u8 ps_num;
__u8 prg_service_name[119];
} __packed;
struct hci_ev_radio_text {
__le16 pi_prg_id;
__u8 pty_prg_type;
__u8 ta_prg_code_type;
__u8 txt_ab_flag;
__u8 radio_txt[64];
} __packed;
struct hci_ev_af_list {
__le32 tune_freq;
__le16 pi_code;
__u8 af_size;
__u8 af_list[25];
} __packed;
struct hci_ev_cmd_complete {
__u8 num_hci_cmd_pkts;
__le16 cmd_opcode;
} __packed;
struct hci_ev_cmd_status {
__u8 status;
__u8 num_hci_cmd_pkts;
__le16 status_opcode;
} __packed;
struct hci_ev_srch_st {
__le32 station_freq;
__u8 rds_cap;
__u8 pty;
__le16 status_opcode;
} __packed;
struct hci_ev_rel_freq {
__u8 rel_freq_msb;
__u8 rel_freq_lsb;
} __packed;
struct hci_ev_srch_list_compl {
__u8 num_stations_found;
struct hci_ev_rel_freq rel_freq[20];
} __packed;
/* ----- HCI Event Response ----- */
struct hci_fm_conf_rsp {
__u8 status;
struct hci_fm_recv_conf_req recv_conf_rsp;
} __packed;
struct hci_fm_get_trans_conf_rsp {
__u8 status;
struct hci_fm_trans_conf_req_struct trans_conf_rsp;
} __packed;
struct hci_fm_sig_threshold_rsp {
__u8 status;
__u8 sig_threshold;
} __packed;
struct hci_fm_station_rsp {
struct hci_ev_tune_status station_rsp;
} __packed;
struct hci_fm_prgm_srv_rsp {
__u8 status;
struct hci_ev_prg_service prg_srv;
} __packed;
struct hci_fm_radio_txt_rsp {
__u8 status;
struct hci_ev_radio_text rd_txt;
} __packed;
struct hci_fm_af_list_rsp {
__u8 status;
struct hci_ev_af_list rd_txt;
} __packed;
struct hci_fm_data_rd_rsp {
__u8 status;
__u8 ret_data_len;
__u8 data[DEFAULT_DATA_SIZE];
} __packed;
struct hci_fm_feature_list_rsp {
__u8 status;
__u8 feature_mask;
} __packed;
struct hci_fm_dbg_param_rsp {
__u8 status;
__u8 blend;
__u8 soft_mute;
__u8 inf_blend;
__u8 inf_soft_mute;
__u8 pilot_pil;
__u8 io_verc;
__u8 in_det_out;
} __packed;
#define CLKSPURID_INDEX0 0
#define CLKSPURID_INDEX1 5
#define CLKSPURID_INDEX2 10
#define CLKSPURID_INDEX3 15
#define CLKSPURID_INDEX4 20
#define CLKSPURID_INDEX5 25
#define MAX_SPUR_FREQ_LIMIT 30
#define CKK_SPUR 0x3B
#define SPUR_DATA_SIZE 0x4
#define SPUR_ENTRIES_PER_ID 0x5
#define COMPUTE_SPUR(val) ((((val) - (76000)) / (50)))
#define GET_FREQ(val, bit) ((bit == 1) ? ((val) >> 8) : ((val) & 0xFF))
#define GET_SPUR_ENTRY_LEVEL(val) ((val) / (5))
struct hci_fm_spur_data {
__u32 freq[MAX_SPUR_FREQ_LIMIT];
__s8 rmssi[MAX_SPUR_FREQ_LIMIT];
__u8 enable[MAX_SPUR_FREQ_LIMIT];
} __packed;
/* HCI dev events */
#define RADIO_HCI_DEV_REG 1
#define RADIO_HCI_DEV_WRITE 2
#define hci_req_lock(d) mutex_lock(&d->req_lock)
#define hci_req_unlock(d) mutex_unlock(&d->req_lock)
/* FM RDS */
#define RDS_PTYPE 2
#define RDS_PID_LOWER 1
#define RDS_PID_HIGHER 0
#define RDS_OFFSET 5
#define RDS_PS_LENGTH_OFFSET 7
#define RDS_STRING 8
#define RDS_PS_DATA_OFFSET 8
#define RDS_CONFIG_OFFSET 3
#define RDS_AF_JUMP_OFFSET 4
#define PI_CODE_OFFSET 4
#define AF_SIZE_OFFSET 6
#define AF_LIST_OFFSET 7
/*FM states*/
enum radio_state_t {
FM_OFF,
FM_RECV,
FM_TRANS,
FM_RESET,
FM_CALIB
};
enum emphasis_type {
FM_RX_EMP75 = 0x0,
FM_RX_EMP50 = 0x1
};
enum channel_space_type {
FM_RX_SPACE_200KHZ = 0x0,
FM_RX_SPACE_100KHZ = 0x1,
FM_RX_SPACE_50KHZ = 0x2
};
enum high_low_injection {
AUTO_HI_LO_INJECTION = 0x0,
LOW_SIDE_INJECTION = 0x1,
HIGH_SIDE_INJECTION = 0x2
};
enum fm_rds_type {
FM_RX_RDBS_SYSTEM = 0x0,
FM_RX_RDS_SYSTEM = 0x1
};
enum iris_region_t {
IRIS_REGION_US,
IRIS_REGION_EU,
IRIS_REGION_JAPAN,
IRIS_REGION_JAPAN_WIDE,
IRIS_REGION_OTHER
};
#define STD_BUF_SIZE (256)
enum iris_buf_t {
IRIS_BUF_SRCH_LIST,
IRIS_BUF_EVENTS,
IRIS_BUF_RT_RDS,
IRIS_BUF_PS_RDS,
IRIS_BUF_RAW_RDS,
IRIS_BUF_AF_LIST,
IRIS_BUF_PEEK,
IRIS_BUF_SSBI_PEEK,
IRIS_BUF_RDS_CNTRS,
IRIS_BUF_RD_DEFAULT,
IRIS_BUF_CAL_DATA,
IRIS_BUF_RT_PLUS,
IRIS_BUF_ERT,
IRIS_BUF_MAX,
};
enum iris_xfr_t {
IRIS_XFR_SYNC,
IRIS_XFR_ERROR,
IRIS_XFR_SRCH_LIST,
IRIS_XFR_RT_RDS,
IRIS_XFR_PS_RDS,
IRIS_XFR_AF_LIST,
IRIS_XFR_MAX
};
#undef FMDBG
#ifdef FM_DEBUG
#define FMDBG(fmt, args...) pr_info("iris_radio: " fmt, ##args)
#else
#define FMDBG(fmt, args...)
#endif
#undef FMDERR
#define FMDERR(fmt, args...) pr_err("iris_radio: " fmt, ##args)
/* Search options */
enum search_t {
SEEK,
SCAN,
SCAN_FOR_STRONG,
SCAN_FOR_WEAK,
RDS_SEEK_PTY,
RDS_SCAN_PTY,
RDS_SEEK_PI,
RDS_AF_JUMP,
};
enum spur_entry_levels {
ENTRY_0,
ENTRY_1,
ENTRY_2,
ENTRY_3,
ENTRY_4,
ENTRY_5,
};
/* Band limits */
#define REGION_US_EU_BAND_LOW 87500
#define REGION_US_EU_BAND_HIGH 108000
#define REGION_JAPAN_STANDARD_BAND_LOW 76000
#define REGION_JAPAN_STANDARD_BAND_HIGH 90000
#define REGION_JAPAN_WIDE_BAND_LOW 90000
#define REGION_JAPAN_WIDE_BAND_HIGH 108000
#define SRCH_MODE 0x07
#define SRCH_DIR 0x08 /* 0-up 1-down */
#define SCAN_DWELL 0x70
#define SRCH_ON 0x80
/* I/O Control */
#define IOC_HRD_MUTE 0x03
#define IOC_SFT_MUTE 0x01
#define IOC_MON_STR 0x01
#define IOC_SIG_BLND 0x01
#define IOC_INTF_BLND 0x01
#define IOC_ANTENNA 0x01
/* RDS Control */
#define RDS_ON 0x01
#define RDS_BUF_SZ 100
/* constants */
#define RDS_BLOCKS_NUM (4)
#define BYTES_PER_BLOCK (3)
#define MAX_PS_LENGTH (108)
#define MAX_RT_LENGTH (64)
#define RDS_GRP_CNTR_LEN (36)
#define RX_RT_DATA_LENGTH (63)
/* Search direction */
#define SRCH_DIR_UP (0)
#define SRCH_DIR_DOWN (1)
/*Search RDS stations*/
#define SEARCH_RDS_STNS_MODE_OFFSET 4
/*Search Station list */
#define PARAMS_PER_STATION 0x08
#define STN_NUM_OFFSET 0x01
#define STN_FREQ_OFFSET 0x02
#define KHZ_TO_MHZ 1000
#define GET_MSB(x)((x >> 8) & 0xFF)
#define GET_LSB(x)((x) & 0xFF)
/* control options */
#define CTRL_ON (1)
#define CTRL_OFF (0)
/*Diagnostic commands*/
#define RIVA_PEEK_OPCODE 0x0D
#define RIVA_POKE_OPCODE 0x0C
#define PEEK_DATA_OFSET 0x1
#define RIVA_PEEK_PARAM 0x6
#define RIVA_PEEK_LEN_OFSET 0x6
#define SSBI_PEEK_LEN 0x01
/*Calibration data*/
#define PROCS_CALIB_MODE 1
#define PROCS_CALIB_SIZE 23
#define DC_CALIB_MODE 2
#define DC_CALIB_SIZE 48
#define RSB_CALIB_MODE 3
#define RSB_CALIB_SIZE 4
#define CALIB_DATA_OFSET 2
#define CALIB_MODE_OFSET 1
#define MAX_CALIB_SIZE 75
/* Channel validity */
#define INVALID_CHANNEL (0)
#define VALID_CHANNEL (1)
struct hci_fm_set_cal_req_proc {
__u8 mode;
/*Max process calibration data size*/
__u8 data[PROCS_CALIB_SIZE];
} __packed;
struct hci_fm_set_cal_req_dc {
__u8 mode;
/*Max DC calibration data size*/
__u8 data[DC_CALIB_SIZE];
} __packed;
struct hci_cc_do_calibration_rsp {
__u8 status;
__u8 mode;
__u8 data[MAX_CALIB_SIZE];
} __packed;
/* Low Power mode*/
#define SIG_LEVEL_INTR (1 << 0)
#define RDS_SYNC_INTR (1 << 1)
#define AUDIO_CTRL_INTR (1 << 2)
#define AF_JUMP_ENABLE (1 << 4)
int hci_def_data_read(struct hci_fm_def_data_rd_req *arg,
struct radio_hci_dev *hdev);
int hci_def_data_write(struct hci_fm_def_data_wr_req *arg,
struct radio_hci_dev *hdev);
int hci_fm_do_calibration(__u8 *arg, struct radio_hci_dev *hdev);
int hci_fm_do_calibration(__u8 *arg, struct radio_hci_dev *hdev);
#endif /* __RADIO_HCI_CORE_H */
kernel/include/media/radio-si4713.h
+30
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/*
* include/media/radio-si4713.h
*
* Board related data definitions for Si4713 radio transmitter chip.
*
* Copyright (c) 2009 Nokia Corporation
* Contact: Eduardo Valentin <eduardo.valentin@nokia.com>
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*
*/
#ifndef RADIO_SI4713_H
#define RADIO_SI4713_H
#include <linux/i2c.h>
#define SI4713_NAME "radio-si4713"
/*
* Platform dependent definition
*/
struct radio_si4713_platform_data {
int i2c_bus;
struct i2c_board_info *subdev_board_info;
};
#endif /* ifndef RADIO_SI4713_H*/
kernel/include/media/rc-core.h
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/*
* Remote Controller core header
*
* Copyright (C) 2009-2010 by Mauro Carvalho Chehab <mchehab@redhat.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _RC_CORE
#define _RC_CORE
#include <linux/spinlock.h>
#include <linux/kfifo.h>
#include <linux/time.h>
#include <linux/timer.h>
#include <media/rc-map.h>
extern int rc_core_debug;
#define IR_dprintk(level, fmt, ...) \
do { \
if (rc_core_debug >= level) \
pr_debug("%s: " fmt, __func__, ##__VA_ARGS__); \
} while (0)
enum rc_driver_type {
RC_DRIVER_SCANCODE = 0, /* Driver or hardware generates a scancode */
RC_DRIVER_IR_RAW, /* Needs a Infra-Red pulse/space decoder */
};
/**
* struct rc_dev - represents a remote control device
* @dev: driver model's view of this device
* @input_name: name of the input child device
* @input_phys: physical path to the input child device
* @input_id: id of the input child device (struct input_id)
* @driver_name: name of the hardware driver which registered this device
* @map_name: name of the default keymap
* @rc_map: current scan/key table
* @lock: used to ensure we've filled in all protocol details before
* anyone can call show_protocols or store_protocols
* @devno: unique remote control device number
* @raw: additional data for raw pulse/space devices
* @input_dev: the input child device used to communicate events to userspace
* @driver_type: specifies if protocol decoding is done in hardware or software
* @idle: used to keep track of RX state
* @allowed_protos: bitmask with the supported RC_TYPE_* protocols
* @scanmask: some hardware decoders are not capable of providing the full
* scancode to the application. As this is a hardware limit, we can't do
* anything with it. Yet, as the same keycode table can be used with other
* devices, a mask is provided to allow its usage. Drivers should generally
* leave this field in blank
* @priv: driver-specific data
* @keylock: protects the remaining members of the struct
* @keypressed: whether a key is currently pressed
* @keyup_jiffies: time (in jiffies) when the current keypress should be released
* @timer_keyup: timer for releasing a keypress
* @last_keycode: keycode of last keypress
* @last_scancode: scancode of last keypress
* @last_toggle: toggle value of last command
* @timeout: optional time after which device stops sending data
* @min_timeout: minimum timeout supported by device
* @max_timeout: maximum timeout supported by device
* @rx_resolution : resolution (in ns) of input sampler
* @tx_resolution: resolution (in ns) of output sampler
* @change_protocol: allow changing the protocol used on hardware decoders
* @open: callback to allow drivers to enable polling/irq when IR input device
* is opened.
* @close: callback to allow drivers to disable polling/irq when IR input device
* is opened.
* @s_tx_mask: set transmitter mask (for devices with multiple tx outputs)
* @s_tx_carrier: set transmit carrier frequency
* @s_tx_duty_cycle: set transmit duty cycle (0% - 100%)
* @s_rx_carrier: inform driver about carrier it is expected to handle
* @tx_ir: transmit IR
* @s_idle: enable/disable hardware idle mode, upon which,
* device doesn't interrupt host until it sees IR pulses
* @s_learning_mode: enable wide band receiver used for learning
* @s_carrier_report: enable carrier reports
*/
struct rc_dev {
struct device dev;
const char *input_name;
const char *input_phys;
struct input_id input_id;
char *driver_name;
const char *map_name;
struct rc_map rc_map;
struct mutex lock;
unsigned long devno;
struct ir_raw_event_ctrl *raw;
struct input_dev *input_dev;
enum rc_driver_type driver_type;
bool idle;
u64 allowed_protos;
u32 scanmask;
void *priv;
spinlock_t keylock;
bool keypressed;
unsigned long keyup_jiffies;
struct timer_list timer_keyup;
u32 last_keycode;
u32 last_scancode;
u8 last_toggle;
u32 timeout;
u32 min_timeout;
u32 max_timeout;
u32 rx_resolution;
u32 tx_resolution;
int (*change_protocol)(struct rc_dev *dev, u64 rc_type);
int (*open)(struct rc_dev *dev);
void (*close)(struct rc_dev *dev);
int (*s_tx_mask)(struct rc_dev *dev, u32 mask);
int (*s_tx_carrier)(struct rc_dev *dev, u32 carrier);
int (*s_tx_duty_cycle)(struct rc_dev *dev, u32 duty_cycle);
int (*s_rx_carrier_range)(struct rc_dev *dev, u32 min, u32 max);
int (*tx_ir)(struct rc_dev *dev, unsigned *txbuf, unsigned n);
void (*s_idle)(struct rc_dev *dev, bool enable);
int (*s_learning_mode)(struct rc_dev *dev, int enable);
int (*s_carrier_report) (struct rc_dev *dev, int enable);
};
#define to_rc_dev(d) container_of(d, struct rc_dev, dev)
/*
* From rc-main.c
* Those functions can be used on any type of Remote Controller. They
* basically creates an input_dev and properly reports the device as a
* Remote Controller, at sys/class/rc.
*/
struct rc_dev *rc_allocate_device(void);
void rc_free_device(struct rc_dev *dev);
int rc_register_device(struct rc_dev *dev);
void rc_unregister_device(struct rc_dev *dev);
void rc_repeat(struct rc_dev *dev);
void rc_keydown(struct rc_dev *dev, int scancode, u8 toggle);
void rc_keydown_notimeout(struct rc_dev *dev, int scancode, u8 toggle);
void rc_keyup(struct rc_dev *dev);
u32 rc_g_keycode_from_table(struct rc_dev *dev, u32 scancode);
/*
* From rc-raw.c
* The Raw interface is specific to InfraRed. It may be a good idea to
* split it later into a separate header.
*/
enum raw_event_type {
IR_SPACE = (1 << 0),
IR_PULSE = (1 << 1),
IR_START_EVENT = (1 << 2),
IR_STOP_EVENT = (1 << 3),
};
struct ir_raw_event {
union {
u32 duration;
struct {
u32 carrier;
u8 duty_cycle;
};
};
unsigned pulse:1;
unsigned reset:1;
unsigned timeout:1;
unsigned carrier_report:1;
};
#define DEFINE_IR_RAW_EVENT(event) \
struct ir_raw_event event = { \
{ .duration = 0 } , \
.pulse = 0, \
.reset = 0, \
.timeout = 0, \
.carrier_report = 0 }
static inline void init_ir_raw_event(struct ir_raw_event *ev)
{
memset(ev, 0, sizeof(*ev));
}
#define IR_MAX_DURATION 0xFFFFFFFF /* a bit more than 4 seconds */
#define US_TO_NS(usec) ((usec) * 1000)
#define MS_TO_US(msec) ((msec) * 1000)
#define MS_TO_NS(msec) ((msec) * 1000 * 1000)
void ir_raw_event_handle(struct rc_dev *dev);
int ir_raw_event_store(struct rc_dev *dev, struct ir_raw_event *ev);
int ir_raw_event_store_edge(struct rc_dev *dev, enum raw_event_type type);
int ir_raw_event_store_with_filter(struct rc_dev *dev,
struct ir_raw_event *ev);
void ir_raw_event_set_idle(struct rc_dev *dev, bool idle);
static inline void ir_raw_event_reset(struct rc_dev *dev)
{
DEFINE_IR_RAW_EVENT(ev);
ev.reset = true;
ir_raw_event_store(dev, &ev);
ir_raw_event_handle(dev);
}
/* extract mask bits out of data and pack them into the result */
static inline u32 ir_extract_bits(u32 data, u32 mask)
{
u32 vbit = 1, value = 0;
do {
if (mask & 1) {
if (data & 1)
value |= vbit;
vbit <<= 1;
}
data >>= 1;
} while (mask >>= 1);
return value;
}
#endif /* _RC_CORE */
kernel/include/media/rc-map.h
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/*
* rc-map.h - define RC map names used by RC drivers
*
* Copyright (c) 2010 by Mauro Carvalho Chehab <mchehab@redhat.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/input.h>
#define RC_TYPE_UNKNOWN 0
#define RC_TYPE_RC5 (1 << 0) /* Philips RC5 protocol */
#define RC_TYPE_NEC (1 << 1)
#define RC_TYPE_RC6 (1 << 2) /* Philips RC6 protocol */
#define RC_TYPE_JVC (1 << 3) /* JVC protocol */
#define RC_TYPE_SONY (1 << 4) /* Sony12/15/20 protocol */
#define RC_TYPE_RC5_SZ (1 << 5) /* RC5 variant used by Streamzap */
#define RC_TYPE_SANYO (1 << 6) /* Sanyo protocol */
#define RC_TYPE_MCE_KBD (1 << 29) /* RC6-ish MCE keyboard/mouse */
#define RC_TYPE_LIRC (1 << 30) /* Pass raw IR to lirc userspace */
#define RC_TYPE_OTHER (1u << 31)
#define RC_TYPE_ALL (RC_TYPE_RC5 | RC_TYPE_NEC | RC_TYPE_RC6 | \
RC_TYPE_JVC | RC_TYPE_SONY | RC_TYPE_LIRC | \
RC_TYPE_RC5_SZ | RC_TYPE_SANYO | RC_TYPE_MCE_KBD | \
RC_TYPE_OTHER)
struct rc_map_table {
u32 scancode;
u32 keycode;
};
struct rc_map {
struct rc_map_table *scan;
unsigned int size; /* Max number of entries */
unsigned int len; /* Used number of entries */
unsigned int alloc; /* Size of *scan in bytes */
u64 rc_type;
const char *name;
spinlock_t lock;
};
struct rc_map_list {
struct list_head list;
struct rc_map map;
};
/* Routines from rc-map.c */
int rc_map_register(struct rc_map_list *map);
void rc_map_unregister(struct rc_map_list *map);
struct rc_map *rc_map_get(const char *name);
void rc_map_init(void);
/* Names of the several keytables defined in-kernel */
#define RC_MAP_ADSTECH_DVB_T_PCI "rc-adstech-dvb-t-pci"
#define RC_MAP_ALINK_DTU_M "rc-alink-dtu-m"
#define RC_MAP_ANYSEE "rc-anysee"
#define RC_MAP_APAC_VIEWCOMP "rc-apac-viewcomp"
#define RC_MAP_ASUS_PC39 "rc-asus-pc39"
#define RC_MAP_ATI_TV_WONDER_HD_600 "rc-ati-tv-wonder-hd-600"
#define RC_MAP_ATI_X10 "rc-ati-x10"
#define RC_MAP_AVERMEDIA_A16D "rc-avermedia-a16d"
#define RC_MAP_AVERMEDIA_CARDBUS "rc-avermedia-cardbus"
#define RC_MAP_AVERMEDIA_DVBT "rc-avermedia-dvbt"
#define RC_MAP_AVERMEDIA_M135A "rc-avermedia-m135a"
#define RC_MAP_AVERMEDIA_M733A_RM_K6 "rc-avermedia-m733a-rm-k6"
#define RC_MAP_AVERMEDIA_RM_KS "rc-avermedia-rm-ks"
#define RC_MAP_AVERMEDIA "rc-avermedia"
#define RC_MAP_AVERTV_303 "rc-avertv-303"
#define RC_MAP_AZUREWAVE_AD_TU700 "rc-azurewave-ad-tu700"
#define RC_MAP_BEHOLD_COLUMBUS "rc-behold-columbus"
#define RC_MAP_BEHOLD "rc-behold"
#define RC_MAP_BUDGET_CI_OLD "rc-budget-ci-old"
#define RC_MAP_CINERGY_1400 "rc-cinergy-1400"
#define RC_MAP_CINERGY "rc-cinergy"
#define RC_MAP_DIB0700_NEC_TABLE "rc-dib0700-nec"
#define RC_MAP_DIB0700_RC5_TABLE "rc-dib0700-rc5"
#define RC_MAP_DIGITALNOW_TINYTWIN "rc-digitalnow-tinytwin"
#define RC_MAP_DIGITTRADE "rc-digittrade"
#define RC_MAP_DM1105_NEC "rc-dm1105-nec"
#define RC_MAP_DNTV_LIVE_DVBT_PRO "rc-dntv-live-dvbt-pro"
#define RC_MAP_DNTV_LIVE_DVB_T "rc-dntv-live-dvb-t"
#define RC_MAP_EMPTY "rc-empty"
#define RC_MAP_EM_TERRATEC "rc-em-terratec"
#define RC_MAP_ENCORE_ENLTV2 "rc-encore-enltv2"
#define RC_MAP_ENCORE_ENLTV_FM53 "rc-encore-enltv-fm53"
#define RC_MAP_ENCORE_ENLTV "rc-encore-enltv"
#define RC_MAP_EVGA_INDTUBE "rc-evga-indtube"
#define RC_MAP_EZTV "rc-eztv"
#define RC_MAP_FLYDVB "rc-flydvb"
#define RC_MAP_FLYVIDEO "rc-flyvideo"
#define RC_MAP_FUSIONHDTV_MCE "rc-fusionhdtv-mce"
#define RC_MAP_GADMEI_RM008Z "rc-gadmei-rm008z"
#define RC_MAP_GENIUS_TVGO_A11MCE "rc-genius-tvgo-a11mce"
#define RC_MAP_GOTVIEW7135 "rc-gotview7135"
#define RC_MAP_HAUPPAUGE_NEW "rc-hauppauge"
#define RC_MAP_IMON_MCE "rc-imon-mce"
#define RC_MAP_IMON_PAD "rc-imon-pad"
#define RC_MAP_IODATA_BCTV7E "rc-iodata-bctv7e"
#define RC_MAP_IT913X_V1 "rc-it913x-v1"
#define RC_MAP_IT913X_V2 "rc-it913x-v2"
#define RC_MAP_KAIOMY "rc-kaiomy"
#define RC_MAP_KWORLD_315U "rc-kworld-315u"
#define RC_MAP_KWORLD_PC150U "rc-kworld-pc150u"
#define RC_MAP_KWORLD_PLUS_TV_ANALOG "rc-kworld-plus-tv-analog"
#define RC_MAP_LEADTEK_Y04G0051 "rc-leadtek-y04g0051"
#define RC_MAP_LIRC "rc-lirc"
#define RC_MAP_LME2510 "rc-lme2510"
#define RC_MAP_MANLI "rc-manli"
#define RC_MAP_MEDION_X10 "rc-medion-x10"
#define RC_MAP_MSI_DIGIVOX_II "rc-msi-digivox-ii"
#define RC_MAP_MSI_DIGIVOX_III "rc-msi-digivox-iii"
#define RC_MAP_MSI_TVANYWHERE_PLUS "rc-msi-tvanywhere-plus"
#define RC_MAP_MSI_TVANYWHERE "rc-msi-tvanywhere"
#define RC_MAP_NEBULA "rc-nebula"
#define RC_MAP_NEC_TERRATEC_CINERGY_XS "rc-nec-terratec-cinergy-xs"
#define RC_MAP_NORWOOD "rc-norwood"
#define RC_MAP_NPGTECH "rc-npgtech"
#define RC_MAP_PCTV_SEDNA "rc-pctv-sedna"
#define RC_MAP_RC6_PHILIPS "rc-philips"
#define RC_MAP_PINNACLE_COLOR "rc-pinnacle-color"
#define RC_MAP_PINNACLE_GREY "rc-pinnacle-grey"
#define RC_MAP_PINNACLE_PCTV_HD "rc-pinnacle-pctv-hd"
#define RC_MAP_PIXELVIEW_NEW "rc-pixelview-new"
#define RC_MAP_PIXELVIEW "rc-pixelview"
#define RC_MAP_PIXELVIEW_002T "rc-pixelview-002t"
#define RC_MAP_PIXELVIEW_MK12 "rc-pixelview-mk12"
#define RC_MAP_POWERCOLOR_REAL_ANGEL "rc-powercolor-real-angel"
#define RC_MAP_PROTEUS_2309 "rc-proteus-2309"
#define RC_MAP_PURPLETV "rc-purpletv"
#define RC_MAP_PV951 "rc-pv951"
#define RC_MAP_HAUPPAUGE "rc-hauppauge"
#define RC_MAP_RC5_TV "rc-rc5-tv"
#define RC_MAP_RC6_MCE "rc-rc6-mce"
#define RC_MAP_REAL_AUDIO_220_32_KEYS "rc-real-audio-220-32-keys"
#define RC_MAP_SNAPSTREAM_FIREFLY "rc-snapstream-firefly"
#define RC_MAP_SAMSUNG_NECX "rc-samsung-necx"
#define RC_MAP_STREAMZAP "rc-streamzap"
#define RC_MAP_TBS_NEC "rc-tbs-nec"
#define RC_MAP_TECHNISAT_USB2 "rc-technisat-usb2"
#define RC_MAP_TERRATEC_CINERGY_XS "rc-terratec-cinergy-xs"
#define RC_MAP_TERRATEC_SLIM "rc-terratec-slim"
#define RC_MAP_TERRATEC_SLIM_2 "rc-terratec-slim-2"
#define RC_MAP_TEVII_NEC "rc-tevii-nec"
#define RC_MAP_TIVO "rc-tivo"
#define RC_MAP_TOTAL_MEDIA_IN_HAND "rc-total-media-in-hand"
#define RC_MAP_TREKSTOR "rc-trekstor"
#define RC_MAP_TT_1500 "rc-tt-1500"
#define RC_MAP_TWINHAN_VP1027_DVBS "rc-twinhan1027"
#define RC_MAP_UE_RF4CE "rc-ue-rf4ce"
#define RC_MAP_VIDEOMATE_K100 "rc-videomate-k100"
#define RC_MAP_VIDEOMATE_S350 "rc-videomate-s350"
#define RC_MAP_VIDEOMATE_TV_PVR "rc-videomate-tv-pvr"
#define RC_MAP_WINFAST "rc-winfast"
#define RC_MAP_WINFAST_USBII_DELUXE "rc-winfast-usbii-deluxe"
/*
* Please, do not just append newer Remote Controller names at the end.
* The names should be ordered in alphabetical order
*/
kernel/include/media/rj54n1cb0c.h
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/*
* RJ54N1CB0C Private data
*
* Copyright (C) 2009, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __RJ54N1CB0C_H__
#define __RJ54N1CB0C_H__
struct rj54n1_pdata {
unsigned int mclk_freq;
bool ioctl_high;
};
#endif
kernel/include/media/s5k6aa.h
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/*
* S5K6AAFX camera sensor driver header
*
* Copyright (C) 2011 Samsung Electronics Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef S5K6AA_H
#define S5K6AA_H
#include <media/v4l2-mediabus.h>
/**
* struct s5k6aa_gpio - data structure describing a GPIO
* @gpio: GPIO number
* @level: indicates active state of the @gpio
*/
struct s5k6aa_gpio {
int gpio;
int level;
};
/**
* struct s5k6aa_platform_data - s5k6aa driver platform data
* @set_power: an additional callback to the board code, called
* after enabling the regulators and before switching
* the sensor off
* @mclk_frequency: sensor's master clock frequency in Hz
* @gpio_reset: GPIO driving RESET pin
* @gpio_stby: GPIO driving STBY pin
* @nlanes: maximum number of MIPI-CSI lanes used
* @horiz_flip: default horizontal image flip value, non zero to enable
* @vert_flip: default vertical image flip value, non zero to enable
*/
struct s5k6aa_platform_data {
int (*set_power)(int enable);
unsigned long mclk_frequency;
struct s5k6aa_gpio gpio_reset;
struct s5k6aa_gpio gpio_stby;
enum v4l2_mbus_type bus_type;
u8 nlanes;
u8 horiz_flip;
u8 vert_flip;
};
#endif /* S5K6AA_H */
kernel/include/media/s5p_fimc.h
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/*
* Samsung S5P SoC camera interface driver header
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd
* Author: Sylwester Nawrocki, <s.nawrocki@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef S5P_FIMC_H_
#define S5P_FIMC_H_
enum cam_bus_type {
FIMC_ITU_601 = 1,
FIMC_ITU_656,
FIMC_MIPI_CSI2,
FIMC_LCD_WB, /* FIFO link from LCD mixer */
};
struct i2c_board_info;
/**
* struct s5p_fimc_isp_info - image sensor information required for host
* interace configuration.
*
* @board_info: pointer to I2C subdevice's board info
* @clk_frequency: frequency of the clock the host interface provides to sensor
* @bus_type: determines bus type, MIPI, ITU-R BT.601 etc.
* @csi_data_align: MIPI-CSI interface data alignment in bits
* @i2c_bus_num: i2c control bus id the sensor is attached to
* @mux_id: FIMC camera interface multiplexer index (separate for MIPI and ITU)
* @clk_id: index of the SoC peripheral clock for sensors
* @flags: the parallel bus flags defining signals polarity (V4L2_MBUS_*)
*/
struct s5p_fimc_isp_info {
struct i2c_board_info *board_info;
unsigned long clk_frequency;
enum cam_bus_type bus_type;
u16 csi_data_align;
u16 i2c_bus_num;
u16 mux_id;
u16 flags;
u8 clk_id;
};
/**
* struct s5p_platform_fimc - camera host interface platform data
*
* @isp_info: properties of camera sensor required for host interface setup
* @num_clients: the number of attached image sensors
*/
struct s5p_platform_fimc {
struct s5p_fimc_isp_info *isp_info;
int num_clients;
};
/*
* v4l2_device notification id. This is only for internal use in the kernel.
* Sensor subdevs should issue S5P_FIMC_TX_END_NOTIFY notification in single
* frame capture mode when there is only one VSYNC pulse issued by the sensor
* at begining of the frame transmission.
*/
#define S5P_FIMC_TX_END_NOTIFY _IO('e', 0)
#endif /* S5P_FIMC_H_ */
kernel/include/media/s5p_hdmi.h
+35
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/*
* Driver header for S5P HDMI chip.
*
* Copyright (c) 2011 Samsung Electronics, Co. Ltd
* Contact: Tomasz Stanislawski <t.stanislaws@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef S5P_HDMI_H
#define S5P_HDMI_H
struct i2c_board_info;
/**
* @hdmiphy_bus: controller id for HDMIPHY bus
* @hdmiphy_info: template for HDMIPHY I2C device
* @mhl_bus: controller id for MHL control bus
* @mhl_info: template for MHL I2C device
*
* NULL pointer for *_info fields indicates that
* the corresponding chip is not present
*/
struct s5p_hdmi_platform_data {
int hdmiphy_bus;
struct i2c_board_info *hdmiphy_info;
int mhl_bus;
struct i2c_board_info *mhl_info;
};
#endif /* S5P_HDMI_H */
kernel/include/media/saa6588.h
+42
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/*
Types and defines needed for RDS. This is included by
saa6588.c and every driver (e.g. bttv-driver.c) that wants
to use the saa6588 module.
(c) 2005 by Hans J. Koch
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _SAA6588_H
#define _SAA6588_H
struct saa6588_command {
unsigned int block_count;
int result;
unsigned char __user *buffer;
struct file *instance;
poll_table *event_list;
};
/* These ioctls are internal to the kernel */
#define SAA6588_CMD_OPEN _IOW('R', 1, int)
#define SAA6588_CMD_CLOSE _IOW('R', 2, int)
#define SAA6588_CMD_READ _IOR('R', 3, int)
#define SAA6588_CMD_POLL _IOR('R', 4, int)
#endif
kernel/include/media/saa6752hs.h
+26
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/*
saa6752hs.h - definition for saa6752hs MPEG encoder
Copyright (C) 2003 Andrew de Quincey <adq@lidskialf.net>
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* Local variables:
* c-basic-offset: 8
* End:
*/
kernel/include/media/saa7115.h
+56
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/*
saa7115.h - definition for saa7111/3/4/5 inputs and frequency flags
Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _SAA7115_H_
#define _SAA7115_H_
/* SAA7111/3/4/5 HW inputs */
#define SAA7115_COMPOSITE0 0
#define SAA7115_COMPOSITE1 1
#define SAA7115_COMPOSITE2 2
#define SAA7115_COMPOSITE3 3
#define SAA7115_COMPOSITE4 4 /* not available for the saa7111/3 */
#define SAA7115_COMPOSITE5 5 /* not available for the saa7111/3 */
#define SAA7115_SVIDEO0 6
#define SAA7115_SVIDEO1 7
#define SAA7115_SVIDEO2 8
#define SAA7115_SVIDEO3 9
/* SAA7115 v4l2_crystal_freq frequency values */
#define SAA7115_FREQ_32_11_MHZ 32110000 /* 32.11 MHz crystal, SAA7114/5 only */
#define SAA7115_FREQ_24_576_MHZ 24576000 /* 24.576 MHz crystal */
/* SAA7115 v4l2_crystal_freq audio clock control flags */
#define SAA7115_FREQ_FL_UCGC (1 << 0) /* SA 3A[7], UCGC, SAA7115 only */
#define SAA7115_FREQ_FL_CGCDIV (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */
#define SAA7115_FREQ_FL_APLL (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */
#define SAA7115_IPORT_ON 1
#define SAA7115_IPORT_OFF 0
/* SAA7111 specific output flags */
#define SAA7111_VBI_BYPASS 2
#define SAA7111_FMT_YUV422 0x00
#define SAA7111_FMT_RGB 0x40
#define SAA7111_FMT_CCIR 0x80
#define SAA7111_FMT_YUV411 0xc0
#endif
kernel/include/media/saa7127.h
+41
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@@ -0,0 +1,41 @@
/*
saa7127.h - definition for saa7126/7/8/9 inputs/outputs
Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _SAA7127_H_
#define _SAA7127_H_
/* Enumeration for the supported input types */
enum saa7127_input_type {
SAA7127_INPUT_TYPE_NORMAL,
SAA7127_INPUT_TYPE_TEST_IMAGE
};
/* Enumeration for the supported output signal types */
enum saa7127_output_type {
SAA7127_OUTPUT_TYPE_BOTH,
SAA7127_OUTPUT_TYPE_COMPOSITE,
SAA7127_OUTPUT_TYPE_SVIDEO,
SAA7127_OUTPUT_TYPE_RGB,
SAA7127_OUTPUT_TYPE_YUV_C,
SAA7127_OUTPUT_TYPE_YUV_V
};
#endif
kernel/include/media/saa7146.h
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#ifndef __SAA7146__
#define __SAA7146__
#include <linux/delay.h> /* for delay-stuff */
#include <linux/slab.h> /* for kmalloc/kfree */
#include <linux/pci.h> /* for pci-config-stuff, vendor ids etc. */
#include <linux/init.h> /* for "__init" */
#include <linux/interrupt.h> /* for IMMEDIATE_BH */
#include <linux/kmod.h> /* for kernel module loader */
#include <linux/i2c.h> /* for i2c subsystem */
#include <asm/io.h> /* for accessing devices */
#include <linux/stringify.h>
#include <linux/mutex.h>
#include <linux/scatterlist.h>
#include <media/v4l2-device.h>
#include <linux/vmalloc.h> /* for vmalloc() */
#include <linux/mm.h> /* for vmalloc_to_page() */
#define SAA7146_VERSION_CODE 0x000600 /* 0.6.0 */
#define saa7146_write(sxy,adr,dat) writel((dat),(sxy->mem+(adr)))
#define saa7146_read(sxy,adr) readl(sxy->mem+(adr))
extern unsigned int saa7146_debug;
#ifndef DEBUG_VARIABLE
#define DEBUG_VARIABLE saa7146_debug
#endif
#define ERR(fmt, ...) pr_err("%s: " fmt, __func__, ##__VA_ARGS__)
#define _DBG(mask, fmt, ...) \
do { \
if (DEBUG_VARIABLE & mask) \
pr_debug("%s(): " fmt, __func__, ##__VA_ARGS__); \
} while (0)
/* simple debug messages */
#define DEB_S(fmt, ...) _DBG(0x01, fmt, ##__VA_ARGS__)
/* more detailed debug messages */
#define DEB_D(fmt, ...) _DBG(0x02, fmt, ##__VA_ARGS__)
/* print enter and exit of functions */
#define DEB_EE(fmt, ...) _DBG(0x04, fmt, ##__VA_ARGS__)
/* i2c debug messages */
#define DEB_I2C(fmt, ...) _DBG(0x08, fmt, ##__VA_ARGS__)
/* vbi debug messages */
#define DEB_VBI(fmt, ...) _DBG(0x10, fmt, ##__VA_ARGS__)
/* interrupt debug messages */
#define DEB_INT(fmt, ...) _DBG(0x20, fmt, ##__VA_ARGS__)
/* capture debug messages */
#define DEB_CAP(fmt, ...) _DBG(0x40, fmt, ##__VA_ARGS__)
#define SAA7146_ISR_CLEAR(x,y) \
saa7146_write(x, ISR, (y));
struct module;
struct saa7146_dev;
struct saa7146_extension;
struct saa7146_vv;
/* saa7146 page table */
struct saa7146_pgtable {
unsigned int size;
__le32 *cpu;
dma_addr_t dma;
/* used for offsets for u,v planes for planar capture modes */
unsigned long offset;
/* used for custom pagetables (used for example by budget dvb cards) */
struct scatterlist *slist;
int nents;
};
struct saa7146_pci_extension_data {
struct saa7146_extension *ext;
void *ext_priv; /* most likely a name string */
};
#define MAKE_EXTENSION_PCI(x_var, x_vendor, x_device) \
{ \
.vendor = PCI_VENDOR_ID_PHILIPS, \
.device = PCI_DEVICE_ID_PHILIPS_SAA7146, \
.subvendor = x_vendor, \
.subdevice = x_device, \
.driver_data = (unsigned long)& x_var, \
}
struct saa7146_extension
{
char name[32]; /* name of the device */
#define SAA7146_USE_I2C_IRQ 0x1
#define SAA7146_I2C_SHORT_DELAY 0x2
int flags;
/* pairs of subvendor and subdevice ids for
supported devices, last entry 0xffff, 0xfff */
struct module *module;
struct pci_driver driver;
struct pci_device_id *pci_tbl;
/* extension functions */
int (*probe)(struct saa7146_dev *);
int (*attach)(struct saa7146_dev *, struct saa7146_pci_extension_data *);
int (*detach)(struct saa7146_dev*);
u32 irq_mask; /* mask to indicate, which irq-events are handled by the extension */
void (*irq_func)(struct saa7146_dev*, u32* irq_mask);
};
struct saa7146_dma
{
dma_addr_t dma_handle;
__le32 *cpu_addr;
};
struct saa7146_dev
{
struct module *module;
struct list_head item;
struct v4l2_device v4l2_dev;
/* different device locks */
spinlock_t slock;
struct mutex v4l2_lock;
unsigned char __iomem *mem; /* pointer to mapped IO memory */
u32 revision; /* chip revision; needed for bug-workarounds*/
/* pci-device & irq stuff*/
char name[32];
struct pci_dev *pci;
u32 int_todo;
spinlock_t int_slock;
/* extension handling */
struct saa7146_extension *ext; /* indicates if handled by extension */
void *ext_priv; /* pointer for extension private use (most likely some private data) */
struct saa7146_ext_vv *ext_vv_data;
/* per device video/vbi informations (if available) */
struct saa7146_vv *vv_data;
void (*vv_callback)(struct saa7146_dev *dev, unsigned long status);
/* i2c-stuff */
struct mutex i2c_lock;
u32 i2c_bitrate;
struct saa7146_dma d_i2c; /* pointer to i2c memory */
wait_queue_head_t i2c_wq;
int i2c_op;
/* memories */
struct saa7146_dma d_rps0;
struct saa7146_dma d_rps1;
};
static inline struct saa7146_dev *to_saa7146_dev(struct v4l2_device *v4l2_dev)
{
return container_of(v4l2_dev, struct saa7146_dev, v4l2_dev);
}
/* from saa7146_i2c.c */
int saa7146_i2c_adapter_prepare(struct saa7146_dev *dev, struct i2c_adapter *i2c_adapter, u32 bitrate);
/* from saa7146_core.c */
extern struct list_head saa7146_devices;
extern struct mutex saa7146_devices_lock;
int saa7146_register_extension(struct saa7146_extension*);
int saa7146_unregister_extension(struct saa7146_extension*);
struct saa7146_format* saa7146_format_by_fourcc(struct saa7146_dev *dev, int fourcc);
int saa7146_pgtable_alloc(struct pci_dev *pci, struct saa7146_pgtable *pt);
void saa7146_pgtable_free(struct pci_dev *pci, struct saa7146_pgtable *pt);
int saa7146_pgtable_build_single(struct pci_dev *pci, struct saa7146_pgtable *pt, struct scatterlist *list, int length );
void *saa7146_vmalloc_build_pgtable(struct pci_dev *pci, long length, struct saa7146_pgtable *pt);
void saa7146_vfree_destroy_pgtable(struct pci_dev *pci, void *mem, struct saa7146_pgtable *pt);
void saa7146_setgpio(struct saa7146_dev *dev, int port, u32 data);
int saa7146_wait_for_debi_done(struct saa7146_dev *dev, int nobusyloop);
/* some memory sizes */
#define SAA7146_I2C_MEM ( 1*PAGE_SIZE)
#define SAA7146_RPS_MEM ( 1*PAGE_SIZE)
/* some i2c constants */
#define SAA7146_I2C_TIMEOUT 100 /* i2c-timeout-value in ms */
#define SAA7146_I2C_RETRIES 3 /* how many times shall we retry an i2c-operation? */
#define SAA7146_I2C_DELAY 5 /* time we wait after certain i2c-operations */
/* unsorted defines */
#define ME1 0x0000000800
#define PV1 0x0000000008
/* gpio defines */
#define SAA7146_GPIO_INPUT 0x00
#define SAA7146_GPIO_IRQHI 0x10
#define SAA7146_GPIO_IRQLO 0x20
#define SAA7146_GPIO_IRQHL 0x30
#define SAA7146_GPIO_OUTLO 0x40
#define SAA7146_GPIO_OUTHI 0x50
/* debi defines */
#define DEBINOSWAP 0x000e0000
/* define for the register programming sequencer (rps) */
#define CMD_NOP 0x00000000 /* No operation */
#define CMD_CLR_EVENT 0x00000000 /* Clear event */
#define CMD_SET_EVENT 0x10000000 /* Set signal event */
#define CMD_PAUSE 0x20000000 /* Pause */
#define CMD_CHECK_LATE 0x30000000 /* Check late */
#define CMD_UPLOAD 0x40000000 /* Upload */
#define CMD_STOP 0x50000000 /* Stop */
#define CMD_INTERRUPT 0x60000000 /* Interrupt */
#define CMD_JUMP 0x80000000 /* Jump */
#define CMD_WR_REG 0x90000000 /* Write (load) register */
#define CMD_RD_REG 0xa0000000 /* Read (store) register */
#define CMD_WR_REG_MASK 0xc0000000 /* Write register with mask */
#define CMD_OAN MASK_27
#define CMD_INV MASK_26
#define CMD_SIG4 MASK_25
#define CMD_SIG3 MASK_24
#define CMD_SIG2 MASK_23
#define CMD_SIG1 MASK_22
#define CMD_SIG0 MASK_21
#define CMD_O_FID_B MASK_14
#define CMD_E_FID_B MASK_13
#define CMD_O_FID_A MASK_12
#define CMD_E_FID_A MASK_11
/* some events and command modifiers for rps1 squarewave generator */
#define EVT_HS (1<<15) // Source Line Threshold reached
#define EVT_VBI_B (1<<9) // VSYNC Event
#define RPS_OAN (1<<27) // 1: OR events, 0: AND events
#define RPS_INV (1<<26) // Invert (compound) event
#define GPIO3_MSK 0xFF000000 // GPIO #3 control bits
/* Bit mask constants */
#define MASK_00 0x00000001 /* Mask value for bit 0 */
#define MASK_01 0x00000002 /* Mask value for bit 1 */
#define MASK_02 0x00000004 /* Mask value for bit 2 */
#define MASK_03 0x00000008 /* Mask value for bit 3 */
#define MASK_04 0x00000010 /* Mask value for bit 4 */
#define MASK_05 0x00000020 /* Mask value for bit 5 */
#define MASK_06 0x00000040 /* Mask value for bit 6 */
#define MASK_07 0x00000080 /* Mask value for bit 7 */
#define MASK_08 0x00000100 /* Mask value for bit 8 */
#define MASK_09 0x00000200 /* Mask value for bit 9 */
#define MASK_10 0x00000400 /* Mask value for bit 10 */
#define MASK_11 0x00000800 /* Mask value for bit 11 */
#define MASK_12 0x00001000 /* Mask value for bit 12 */
#define MASK_13 0x00002000 /* Mask value for bit 13 */
#define MASK_14 0x00004000 /* Mask value for bit 14 */
#define MASK_15 0x00008000 /* Mask value for bit 15 */
#define MASK_16 0x00010000 /* Mask value for bit 16 */
#define MASK_17 0x00020000 /* Mask value for bit 17 */
#define MASK_18 0x00040000 /* Mask value for bit 18 */
#define MASK_19 0x00080000 /* Mask value for bit 19 */
#define MASK_20 0x00100000 /* Mask value for bit 20 */
#define MASK_21 0x00200000 /* Mask value for bit 21 */
#define MASK_22 0x00400000 /* Mask value for bit 22 */
#define MASK_23 0x00800000 /* Mask value for bit 23 */
#define MASK_24 0x01000000 /* Mask value for bit 24 */
#define MASK_25 0x02000000 /* Mask value for bit 25 */
#define MASK_26 0x04000000 /* Mask value for bit 26 */
#define MASK_27 0x08000000 /* Mask value for bit 27 */
#define MASK_28 0x10000000 /* Mask value for bit 28 */
#define MASK_29 0x20000000 /* Mask value for bit 29 */
#define MASK_30 0x40000000 /* Mask value for bit 30 */
#define MASK_31 0x80000000 /* Mask value for bit 31 */
#define MASK_B0 0x000000ff /* Mask value for byte 0 */
#define MASK_B1 0x0000ff00 /* Mask value for byte 1 */
#define MASK_B2 0x00ff0000 /* Mask value for byte 2 */
#define MASK_B3 0xff000000 /* Mask value for byte 3 */
#define MASK_W0 0x0000ffff /* Mask value for word 0 */
#define MASK_W1 0xffff0000 /* Mask value for word 1 */
#define MASK_PA 0xfffffffc /* Mask value for physical address */
#define MASK_PR 0xfffffffe /* Mask value for protection register */
#define MASK_ER 0xffffffff /* Mask value for the entire register */
#define MASK_NONE 0x00000000 /* No mask */
/* register aliases */
#define BASE_ODD1 0x00 /* Video DMA 1 registers */
#define BASE_EVEN1 0x04
#define PROT_ADDR1 0x08
#define PITCH1 0x0C
#define BASE_PAGE1 0x10 /* Video DMA 1 base page */
#define NUM_LINE_BYTE1 0x14
#define BASE_ODD2 0x18 /* Video DMA 2 registers */
#define BASE_EVEN2 0x1C
#define PROT_ADDR2 0x20
#define PITCH2 0x24
#define BASE_PAGE2 0x28 /* Video DMA 2 base page */
#define NUM_LINE_BYTE2 0x2C
#define BASE_ODD3 0x30 /* Video DMA 3 registers */
#define BASE_EVEN3 0x34
#define PROT_ADDR3 0x38
#define PITCH3 0x3C
#define BASE_PAGE3 0x40 /* Video DMA 3 base page */
#define NUM_LINE_BYTE3 0x44
#define PCI_BT_V1 0x48 /* Video/FIFO 1 */
#define PCI_BT_V2 0x49 /* Video/FIFO 2 */
#define PCI_BT_V3 0x4A /* Video/FIFO 3 */
#define PCI_BT_DEBI 0x4B /* DEBI */
#define PCI_BT_A 0x4C /* Audio */
#define DD1_INIT 0x50 /* Init setting of DD1 interface */
#define DD1_STREAM_B 0x54 /* DD1 B video data stream handling */
#define DD1_STREAM_A 0x56 /* DD1 A video data stream handling */
#define BRS_CTRL 0x58 /* BRS control register */
#define HPS_CTRL 0x5C /* HPS control register */
#define HPS_V_SCALE 0x60 /* HPS vertical scale */
#define HPS_V_GAIN 0x64 /* HPS vertical ACL and gain */
#define HPS_H_PRESCALE 0x68 /* HPS horizontal prescale */
#define HPS_H_SCALE 0x6C /* HPS horizontal scale */
#define BCS_CTRL 0x70 /* BCS control */
#define CHROMA_KEY_RANGE 0x74
#define CLIP_FORMAT_CTRL 0x78 /* HPS outputs formats & clipping */
#define DEBI_CONFIG 0x7C
#define DEBI_COMMAND 0x80
#define DEBI_PAGE 0x84
#define DEBI_AD 0x88
#define I2C_TRANSFER 0x8C
#define I2C_STATUS 0x90
#define BASE_A1_IN 0x94 /* Audio 1 input DMA */
#define PROT_A1_IN 0x98
#define PAGE_A1_IN 0x9C
#define BASE_A1_OUT 0xA0 /* Audio 1 output DMA */
#define PROT_A1_OUT 0xA4
#define PAGE_A1_OUT 0xA8
#define BASE_A2_IN 0xAC /* Audio 2 input DMA */
#define PROT_A2_IN 0xB0
#define PAGE_A2_IN 0xB4
#define BASE_A2_OUT 0xB8 /* Audio 2 output DMA */
#define PROT_A2_OUT 0xBC
#define PAGE_A2_OUT 0xC0
#define RPS_PAGE0 0xC4 /* RPS task 0 page register */
#define RPS_PAGE1 0xC8 /* RPS task 1 page register */
#define RPS_THRESH0 0xCC /* HBI threshold for task 0 */
#define RPS_THRESH1 0xD0 /* HBI threshold for task 1 */
#define RPS_TOV0 0xD4 /* RPS timeout for task 0 */
#define RPS_TOV1 0xD8 /* RPS timeout for task 1 */
#define IER 0xDC /* Interrupt enable register */
#define GPIO_CTRL 0xE0 /* GPIO 0-3 register */
#define EC1SSR 0xE4 /* Event cnt set 1 source select */
#define EC2SSR 0xE8 /* Event cnt set 2 source select */
#define ECT1R 0xEC /* Event cnt set 1 thresholds */
#define ECT2R 0xF0 /* Event cnt set 2 thresholds */
#define ACON1 0xF4
#define ACON2 0xF8
#define MC1 0xFC /* Main control register 1 */
#define MC2 0x100 /* Main control register 2 */
#define RPS_ADDR0 0x104 /* RPS task 0 address register */
#define RPS_ADDR1 0x108 /* RPS task 1 address register */
#define ISR 0x10C /* Interrupt status register */
#define PSR 0x110 /* Primary status register */
#define SSR 0x114 /* Secondary status register */
#define EC1R 0x118 /* Event counter set 1 register */
#define EC2R 0x11C /* Event counter set 2 register */
#define PCI_VDP1 0x120 /* Video DMA pointer of FIFO 1 */
#define PCI_VDP2 0x124 /* Video DMA pointer of FIFO 2 */
#define PCI_VDP3 0x128 /* Video DMA pointer of FIFO 3 */
#define PCI_ADP1 0x12C /* Audio DMA pointer of audio out 1 */
#define PCI_ADP2 0x130 /* Audio DMA pointer of audio in 1 */
#define PCI_ADP3 0x134 /* Audio DMA pointer of audio out 2 */
#define PCI_ADP4 0x138 /* Audio DMA pointer of audio in 2 */
#define PCI_DMA_DDP 0x13C /* DEBI DMA pointer */
#define LEVEL_REP 0x140,
#define A_TIME_SLOT1 0x180, /* from 180 - 1BC */
#define A_TIME_SLOT2 0x1C0, /* from 1C0 - 1FC */
/* isr masks */
#define SPCI_PPEF 0x80000000 /* PCI parity error */
#define SPCI_PABO 0x40000000 /* PCI access error (target or master abort) */
#define SPCI_PPED 0x20000000 /* PCI parity error on 'real time data' */
#define SPCI_RPS_I1 0x10000000 /* Interrupt issued by RPS1 */
#define SPCI_RPS_I0 0x08000000 /* Interrupt issued by RPS0 */
#define SPCI_RPS_LATE1 0x04000000 /* RPS task 1 is late */
#define SPCI_RPS_LATE0 0x02000000 /* RPS task 0 is late */
#define SPCI_RPS_E1 0x01000000 /* RPS error from task 1 */
#define SPCI_RPS_E0 0x00800000 /* RPS error from task 0 */
#define SPCI_RPS_TO1 0x00400000 /* RPS timeout task 1 */
#define SPCI_RPS_TO0 0x00200000 /* RPS timeout task 0 */
#define SPCI_UPLD 0x00100000 /* RPS in upload */
#define SPCI_DEBI_S 0x00080000 /* DEBI status */
#define SPCI_DEBI_E 0x00040000 /* DEBI error */
#define SPCI_IIC_S 0x00020000 /* I2C status */
#define SPCI_IIC_E 0x00010000 /* I2C error */
#define SPCI_A2_IN 0x00008000 /* Audio 2 input DMA protection / limit */
#define SPCI_A2_OUT 0x00004000 /* Audio 2 output DMA protection / limit */
#define SPCI_A1_IN 0x00002000 /* Audio 1 input DMA protection / limit */
#define SPCI_A1_OUT 0x00001000 /* Audio 1 output DMA protection / limit */
#define SPCI_AFOU 0x00000800 /* Audio FIFO over- / underflow */
#define SPCI_V_PE 0x00000400 /* Video protection address */
#define SPCI_VFOU 0x00000200 /* Video FIFO over- / underflow */
#define SPCI_FIDA 0x00000100 /* Field ID video port A */
#define SPCI_FIDB 0x00000080 /* Field ID video port B */
#define SPCI_PIN3 0x00000040 /* GPIO pin 3 */
#define SPCI_PIN2 0x00000020 /* GPIO pin 2 */
#define SPCI_PIN1 0x00000010 /* GPIO pin 1 */
#define SPCI_PIN0 0x00000008 /* GPIO pin 0 */
#define SPCI_ECS 0x00000004 /* Event counter 1, 2, 4, 5 */
#define SPCI_EC3S 0x00000002 /* Event counter 3 */
#define SPCI_EC0S 0x00000001 /* Event counter 0 */
/* i2c */
#define SAA7146_I2C_ABORT (1<<7)
#define SAA7146_I2C_SPERR (1<<6)
#define SAA7146_I2C_APERR (1<<5)
#define SAA7146_I2C_DTERR (1<<4)
#define SAA7146_I2C_DRERR (1<<3)
#define SAA7146_I2C_AL (1<<2)
#define SAA7146_I2C_ERR (1<<1)
#define SAA7146_I2C_BUSY (1<<0)
#define SAA7146_I2C_START (0x3)
#define SAA7146_I2C_CONT (0x2)
#define SAA7146_I2C_STOP (0x1)
#define SAA7146_I2C_NOP (0x0)
#define SAA7146_I2C_BUS_BIT_RATE_6400 (0x500)
#define SAA7146_I2C_BUS_BIT_RATE_3200 (0x100)
#define SAA7146_I2C_BUS_BIT_RATE_480 (0x400)
#define SAA7146_I2C_BUS_BIT_RATE_320 (0x600)
#define SAA7146_I2C_BUS_BIT_RATE_240 (0x700)
#define SAA7146_I2C_BUS_BIT_RATE_120 (0x000)
#define SAA7146_I2C_BUS_BIT_RATE_80 (0x200)
#define SAA7146_I2C_BUS_BIT_RATE_60 (0x300)
static inline void SAA7146_IER_DISABLE(struct saa7146_dev *x, unsigned y)
{
unsigned long flags;
spin_lock_irqsave(&x->int_slock, flags);
saa7146_write(x, IER, saa7146_read(x, IER) & ~y);
spin_unlock_irqrestore(&x->int_slock, flags);
}
static inline void SAA7146_IER_ENABLE(struct saa7146_dev *x, unsigned y)
{
unsigned long flags;
spin_lock_irqsave(&x->int_slock, flags);
saa7146_write(x, IER, saa7146_read(x, IER) | y);
spin_unlock_irqrestore(&x->int_slock, flags);
}
#endif
kernel/include/media/saa7146_vv.h
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#ifndef __SAA7146_VV__
#define __SAA7146_VV__
#include <media/v4l2-common.h>
#include <media/v4l2-ioctl.h>
#include <media/saa7146.h>
#include <media/videobuf-dma-sg.h>
#define MAX_SAA7146_CAPTURE_BUFFERS 32 /* arbitrary */
#define BUFFER_TIMEOUT (HZ/2) /* 0.5 seconds */
#define WRITE_RPS0(x) do { \
dev->d_rps0.cpu_addr[ count++ ] = cpu_to_le32(x); \
} while (0);
#define WRITE_RPS1(x) do { \
dev->d_rps1.cpu_addr[ count++ ] = cpu_to_le32(x); \
} while (0);
struct saa7146_video_dma {
u32 base_odd;
u32 base_even;
u32 prot_addr;
u32 pitch;
u32 base_page;
u32 num_line_byte;
};
#define FORMAT_BYTE_SWAP 0x1
#define FORMAT_IS_PLANAR 0x2
struct saa7146_format {
char *name;
u32 pixelformat;
u32 trans;
u8 depth;
u8 flags;
u8 swap;
};
struct saa7146_standard
{
char *name;
v4l2_std_id id;
int v_offset; /* number of lines of vertical offset before processing */
int v_field; /* number of lines in a field for HPS to process */
int h_offset; /* horizontal offset of processing window */
int h_pixels; /* number of horizontal pixels to process */
int v_max_out;
int h_max_out;
};
/* buffer for one video/vbi frame */
struct saa7146_buf {
/* common v4l buffer stuff -- must be first */
struct videobuf_buffer vb;
/* saa7146 specific */
struct v4l2_pix_format *fmt;
int (*activate)(struct saa7146_dev *dev,
struct saa7146_buf *buf,
struct saa7146_buf *next);
/* page tables */
struct saa7146_pgtable pt[3];
};
struct saa7146_dmaqueue {
struct saa7146_dev *dev;
struct saa7146_buf *curr;
struct list_head queue;
struct timer_list timeout;
};
struct saa7146_overlay {
struct saa7146_fh *fh;
struct v4l2_window win;
struct v4l2_clip clips[16];
int nclips;
};
/* per open data */
struct saa7146_fh {
struct saa7146_dev *dev;
/* if this is a vbi or capture open */
enum v4l2_buf_type type;
/* video overlay */
struct saa7146_overlay ov;
/* video capture */
struct videobuf_queue video_q;
struct v4l2_pix_format video_fmt;
/* vbi capture */
struct videobuf_queue vbi_q;
struct v4l2_vbi_format vbi_fmt;
struct timer_list vbi_read_timeout;
unsigned int resources; /* resource management for device open */
};
#define STATUS_OVERLAY 0x01
#define STATUS_CAPTURE 0x02
struct saa7146_vv
{
/* vbi capture */
struct saa7146_dmaqueue vbi_q;
/* vbi workaround interrupt queue */
wait_queue_head_t vbi_wq;
int vbi_fieldcount;
struct saa7146_fh *vbi_streaming;
int video_status;
struct saa7146_fh *video_fh;
/* video overlay */
struct v4l2_framebuffer ov_fb;
struct saa7146_format *ov_fmt;
struct saa7146_overlay *ov_data;
struct saa7146_fh *ov_suspend;
/* video capture */
struct saa7146_dmaqueue video_q;
enum v4l2_field last_field;
/* common: fixme? shouldn't this be in saa7146_fh?
(this leads to a more complicated question: shall the driver
store the different settings (for example S_INPUT) for every open
and restore it appropriately, or should all settings be common for
all opens? currently, we do the latter, like all other
drivers do... */
struct saa7146_standard *standard;
int vflip;
int hflip;
int current_hps_source;
int current_hps_sync;
struct saa7146_dma d_clipping; /* pointer to clipping memory */
unsigned int resources; /* resource management for device */
};
/* flags */
#define SAA7146_USE_PORT_B_FOR_VBI 0x2 /* use input port b for vbi hardware bug workaround */
struct saa7146_ext_vv
{
/* informations about the video capabilities of the device */
int inputs;
int audios;
u32 capabilities;
int flags;
/* additionally supported transmission standards */
struct saa7146_standard *stds;
int num_stds;
int (*std_callback)(struct saa7146_dev*, struct saa7146_standard *);
/* the extension can override this */
struct v4l2_ioctl_ops ops;
/* pointer to the saa7146 core ops */
const struct v4l2_ioctl_ops *core_ops;
struct v4l2_file_operations vbi_fops;
};
struct saa7146_use_ops {
void (*init)(struct saa7146_dev *, struct saa7146_vv *);
int(*open)(struct saa7146_dev *, struct file *);
void (*release)(struct saa7146_dev *, struct file *);
void (*irq_done)(struct saa7146_dev *, unsigned long status);
ssize_t (*read)(struct file *, char __user *, size_t, loff_t *);
};
/* from saa7146_fops.c */
int saa7146_register_device(struct video_device **vid, struct saa7146_dev* dev, char *name, int type);
int saa7146_unregister_device(struct video_device **vid, struct saa7146_dev* dev);
void saa7146_buffer_finish(struct saa7146_dev *dev, struct saa7146_dmaqueue *q, int state);
void saa7146_buffer_next(struct saa7146_dev *dev, struct saa7146_dmaqueue *q,int vbi);
int saa7146_buffer_queue(struct saa7146_dev *dev, struct saa7146_dmaqueue *q, struct saa7146_buf *buf);
void saa7146_buffer_timeout(unsigned long data);
void saa7146_dma_free(struct saa7146_dev* dev,struct videobuf_queue *q,
struct saa7146_buf *buf);
int saa7146_vv_init(struct saa7146_dev* dev, struct saa7146_ext_vv *ext_vv);
int saa7146_vv_release(struct saa7146_dev* dev);
/* from saa7146_hlp.c */
int saa7146_enable_overlay(struct saa7146_fh *fh);
void saa7146_disable_overlay(struct saa7146_fh *fh);
void saa7146_set_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next);
void saa7146_write_out_dma(struct saa7146_dev* dev, int which, struct saa7146_video_dma* vdma) ;
void saa7146_set_hps_source_and_sync(struct saa7146_dev *saa, int source, int sync);
void saa7146_set_gpio(struct saa7146_dev *saa, u8 pin, u8 data);
/* from saa7146_video.c */
extern const struct v4l2_ioctl_ops saa7146_video_ioctl_ops;
extern struct saa7146_use_ops saa7146_video_uops;
int saa7146_start_preview(struct saa7146_fh *fh);
int saa7146_stop_preview(struct saa7146_fh *fh);
long saa7146_video_do_ioctl(struct file *file, unsigned int cmd, void *arg);
/* from saa7146_vbi.c */
extern struct saa7146_use_ops saa7146_vbi_uops;
/* resource management functions */
int saa7146_res_get(struct saa7146_fh *fh, unsigned int bit);
void saa7146_res_free(struct saa7146_fh *fh, unsigned int bits);
#define RESOURCE_DMA1_HPS 0x1
#define RESOURCE_DMA2_CLP 0x2
#define RESOURCE_DMA3_BRS 0x4
/* saa7146 source inputs */
#define SAA7146_HPS_SOURCE_PORT_A 0x00
#define SAA7146_HPS_SOURCE_PORT_B 0x01
#define SAA7146_HPS_SOURCE_YPB_CPA 0x02
#define SAA7146_HPS_SOURCE_YPA_CPB 0x03
/* sync inputs */
#define SAA7146_HPS_SYNC_PORT_A 0x00
#define SAA7146_HPS_SYNC_PORT_B 0x01
/* some memory sizes */
/* max. 16 clipping rectangles */
#define SAA7146_CLIPPING_MEM (16 * 4 * sizeof(u32))
/* some defines for the various clipping-modes */
#define SAA7146_CLIPPING_RECT 0x4
#define SAA7146_CLIPPING_RECT_INVERTED 0x5
#define SAA7146_CLIPPING_MASK 0x6
#define SAA7146_CLIPPING_MASK_INVERTED 0x7
/* output formats: each entry holds four informations */
#define RGB08_COMPOSED 0x0217 /* composed is used in the sense of "not-planar" */
/* this means: planar?=0, yuv2rgb-conversation-mode=2, dither=yes(=1), format-mode = 7 */
#define RGB15_COMPOSED 0x0213
#define RGB16_COMPOSED 0x0210
#define RGB24_COMPOSED 0x0201
#define RGB32_COMPOSED 0x0202
#define Y8 0x0006
#define YUV411_COMPOSED 0x0003
#define YUV422_COMPOSED 0x0000
/* this means: planar?=1, yuv2rgb-conversion-mode=0, dither=no(=0), format-mode = b */
#define YUV411_DECOMPOSED 0x100b
#define YUV422_DECOMPOSED 0x1009
#define YUV420_DECOMPOSED 0x100a
#define IS_PLANAR(x) (x & 0xf000)
/* misc defines */
#define SAA7146_NO_SWAP (0x0)
#define SAA7146_TWO_BYTE_SWAP (0x1)
#define SAA7146_FOUR_BYTE_SWAP (0x2)
#endif
kernel/include/media/sh_mobile_ceu.h
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#ifndef __ASM_SH_MOBILE_CEU_H__
#define __ASM_SH_MOBILE_CEU_H__
#define SH_CEU_FLAG_USE_8BIT_BUS (1 << 0) /* use 8bit bus width */
#define SH_CEU_FLAG_USE_16BIT_BUS (1 << 1) /* use 16bit bus width */
#define SH_CEU_FLAG_HSYNC_LOW (1 << 2) /* default High if possible */
#define SH_CEU_FLAG_VSYNC_LOW (1 << 3) /* default High if possible */
struct device;
struct resource;
struct sh_mobile_ceu_companion {
u32 num_resources;
struct resource *resource;
int id;
void *platform_data;
};
struct sh_mobile_ceu_info {
unsigned long flags;
int max_width;
int max_height;
struct sh_mobile_ceu_companion *csi2;
};
#endif /* __ASM_SH_MOBILE_CEU_H__ */
kernel/include/media/sh_mobile_csi2.h
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/*
* Driver header for the SH-Mobile MIPI CSI-2 unit
*
* Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef SH_MIPI_CSI
#define SH_MIPI_CSI
#include <linux/list.h>
enum sh_csi2_phy {
SH_CSI2_PHY_MAIN,
SH_CSI2_PHY_SUB,
};
enum sh_csi2_type {
SH_CSI2C,
SH_CSI2I,
};
#define SH_CSI2_CRC (1 << 0)
#define SH_CSI2_ECC (1 << 1)
struct platform_device;
struct sh_csi2_client_config {
enum sh_csi2_phy phy;
unsigned char lanes; /* bitmask[3:0] */
unsigned char channel; /* 0..3 */
struct platform_device *pdev; /* client platform device */
};
struct v4l2_device;
struct sh_csi2_pdata {
enum sh_csi2_type type;
unsigned int flags;
struct sh_csi2_client_config *clients;
int num_clients;
struct v4l2_device *v4l2_dev;
};
#endif
kernel/include/media/sh_vou.h
+33
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/*
* SuperH Video Output Unit (VOU) driver header
*
* Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef SH_VOU_H
#define SH_VOU_H
#include <linux/i2c.h>
/* Bus flags */
#define SH_VOU_PCLK_FALLING (1 << 0)
#define SH_VOU_HSYNC_LOW (1 << 1)
#define SH_VOU_VSYNC_LOW (1 << 2)
enum sh_vou_bus_fmt {
SH_VOU_BUS_8BIT,
SH_VOU_BUS_16BIT,
SH_VOU_BUS_BT656,
};
struct sh_vou_pdata {
enum sh_vou_bus_fmt bus_fmt;
int i2c_adap;
struct i2c_board_info *board_info;
unsigned long flags;
};
#endif
kernel/include/media/si4713.h
+48
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/*
* include/media/si4713.h
*
* Board related data definitions for Si4713 i2c device driver.
*
* Copyright (c) 2009 Nokia Corporation
* Contact: Eduardo Valentin <eduardo.valentin@nokia.com>
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*
*/
#ifndef SI4713_H
#define SI4713_H
/* The SI4713 I2C sensor chip has a fixed slave address of 0xc6 or 0x22. */
#define SI4713_I2C_ADDR_BUSEN_HIGH 0x63
#define SI4713_I2C_ADDR_BUSEN_LOW 0x11
/*
* Platform dependent definition
*/
struct si4713_platform_data {
int gpio_reset; /* < 0 if not used */
};
/*
* Structure to query for Received Noise Level (RNL).
*/
struct si4713_rnl {
__u32 index; /* modulator index */
__u32 frequency; /* frequency to peform rnl measurement */
__s32 rnl; /* result of measurement in dBuV */
__u32 reserved[4]; /* drivers and apps must init this to 0 */
};
/*
* This is the ioctl number to query for rnl. Users must pass a
* struct si4713_rnl pointer specifying desired frequency in 'frequency' field
* following driver capabilities (i.e V4L2_TUNER_CAP_LOW).
* Driver must return measured value in the same struture, filling 'rnl' field.
*/
#define SI4713_IOC_MEASURE_RNL _IOWR('V', BASE_VIDIOC_PRIVATE + 0, \
struct si4713_rnl)
#endif /* ifndef SI4713_H*/
kernel/include/media/sii9234.h
+24
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/*
* Driver header for SII9234 MHL converter chip.
*
* Copyright (c) 2011 Samsung Electronics, Co. Ltd
* Contact: Tomasz Stanislawski <t.stanislaws@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef SII9234_H
#define SII9234_H
/**
* @gpio_n_reset: GPIO driving nRESET pin
*/
struct sii9234_platform_data {
int gpio_n_reset;
};
#endif /* SII9234_H */
kernel/include/media/soc_camera.h
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/*
* camera image capture (abstract) bus driver header
*
* Copyright (C) 2006, Sascha Hauer, Pengutronix
* Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef SOC_CAMERA_H
#define SOC_CAMERA_H
#include <linux/bitops.h>
#include <linux/device.h>
#include <linux/mutex.h>
#include <linux/pm.h>
#include <linux/videodev2.h>
#include <media/videobuf-core.h>
#include <media/videobuf2-core.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
struct file;
struct soc_camera_link;
struct soc_camera_device {
struct list_head list; /* list of all registered devices */
struct soc_camera_link *link;
struct device *pdev; /* Platform device */
struct device *parent; /* Camera host device */
struct device *control; /* E.g., the i2c client */
s32 user_width;
s32 user_height;
u32 bytesperline; /* for padding, zero if unused */
u32 sizeimage;
enum v4l2_colorspace colorspace;
unsigned char iface; /* Host number */
unsigned char devnum; /* Device number per host */
struct soc_camera_sense *sense; /* See comment in struct definition */
struct video_device *vdev;
struct v4l2_ctrl_handler ctrl_handler;
const struct soc_camera_format_xlate *current_fmt;
struct soc_camera_format_xlate *user_formats;
int num_user_formats;
enum v4l2_field field; /* Preserve field over close() */
void *host_priv; /* Per-device host private data */
/* soc_camera.c private count. Only accessed with .video_lock held */
int use_count;
struct mutex video_lock; /* Protects device data */
struct file *streamer; /* stream owner */
union {
struct videobuf_queue vb_vidq;
struct vb2_queue vb2_vidq;
};
};
struct soc_camera_host {
struct v4l2_device v4l2_dev;
struct list_head list;
struct mutex host_lock; /* Protect during probing */
unsigned char nr; /* Host number */
void *priv;
const char *drv_name;
struct soc_camera_host_ops *ops;
};
struct soc_camera_host_ops {
struct module *owner;
int (*add)(struct soc_camera_device *);
void (*remove)(struct soc_camera_device *);
/*
* .get_formats() is called for each client device format, but
* .put_formats() is only called once. Further, if any of the calls to
* .get_formats() fail, .put_formats() will not be called at all, the
* failing .get_formats() must then clean up internally.
*/
int (*get_formats)(struct soc_camera_device *, unsigned int,
struct soc_camera_format_xlate *);
void (*put_formats)(struct soc_camera_device *);
int (*cropcap)(struct soc_camera_device *, struct v4l2_cropcap *);
int (*get_crop)(struct soc_camera_device *, struct v4l2_crop *);
int (*set_crop)(struct soc_camera_device *, struct v4l2_crop *);
/*
* The difference to .set_crop() is, that .set_livecrop is not allowed
* to change the output sizes
*/
int (*set_livecrop)(struct soc_camera_device *, struct v4l2_crop *);
int (*set_fmt)(struct soc_camera_device *, struct v4l2_format *);
int (*try_fmt)(struct soc_camera_device *, struct v4l2_format *);
void (*init_videobuf)(struct videobuf_queue *,
struct soc_camera_device *);
int (*init_videobuf2)(struct vb2_queue *,
struct soc_camera_device *);
int (*reqbufs)(struct soc_camera_device *, struct v4l2_requestbuffers *);
int (*querycap)(struct soc_camera_host *, struct v4l2_capability *);
int (*set_bus_param)(struct soc_camera_device *);
int (*get_parm)(struct soc_camera_device *, struct v4l2_streamparm *);
int (*set_parm)(struct soc_camera_device *, struct v4l2_streamparm *);
int (*enum_fsizes)(struct soc_camera_device *, struct v4l2_frmsizeenum *);
unsigned int (*poll)(struct file *, poll_table *);
};
#define SOCAM_SENSOR_INVERT_PCLK (1 << 0)
#define SOCAM_SENSOR_INVERT_MCLK (1 << 1)
#define SOCAM_SENSOR_INVERT_HSYNC (1 << 2)
#define SOCAM_SENSOR_INVERT_VSYNC (1 << 3)
#define SOCAM_SENSOR_INVERT_DATA (1 << 4)
struct i2c_board_info;
struct regulator_bulk_data;
struct soc_camera_link {
/* Camera bus id, used to match a camera and a bus */
int bus_id;
/* Per camera SOCAM_SENSOR_* bus flags */
unsigned long flags;
int i2c_adapter_id;
struct i2c_board_info *board_info;
const char *module_name;
void *priv;
/* Optional regulators that have to be managed on power on/off events */
struct regulator_bulk_data *regulators;
int num_regulators;
/*
* For non-I2C devices platform has to provide methods to add a device
* to the system and to remove it
*/
int (*add_device)(struct soc_camera_device *);
void (*del_device)(struct soc_camera_device *);
/* Optional callbacks to power on or off and reset the sensor */
int (*power)(struct device *, int);
int (*reset)(struct device *);
/*
* some platforms may support different data widths than the sensors
* native ones due to different data line routing. Let the board code
* overwrite the width flags.
*/
int (*set_bus_param)(struct soc_camera_link *, unsigned long flags);
unsigned long (*query_bus_param)(struct soc_camera_link *);
void (*free_bus)(struct soc_camera_link *);
};
static inline struct soc_camera_host *to_soc_camera_host(
const struct device *dev)
{
struct v4l2_device *v4l2_dev = dev_get_drvdata(dev);
return container_of(v4l2_dev, struct soc_camera_host, v4l2_dev);
}
static inline struct soc_camera_link *to_soc_camera_link(
const struct soc_camera_device *icd)
{
return icd->link;
}
static inline struct device *to_soc_camera_control(
const struct soc_camera_device *icd)
{
return icd->control;
}
static inline struct v4l2_subdev *soc_camera_to_subdev(
const struct soc_camera_device *icd)
{
struct device *control = to_soc_camera_control(icd);
return dev_get_drvdata(control);
}
int soc_camera_host_register(struct soc_camera_host *ici);
void soc_camera_host_unregister(struct soc_camera_host *ici);
const struct soc_camera_format_xlate *soc_camera_xlate_by_fourcc(
struct soc_camera_device *icd, unsigned int fourcc);
/**
* struct soc_camera_format_xlate - match between host and sensor formats
* @code: code of a sensor provided format
* @host_fmt: host format after host translation from code
*
* Host and sensor translation structure. Used in table of host and sensor
* formats matchings in soc_camera_device. A host can override the generic list
* generation by implementing get_formats(), and use it for format checks and
* format setup.
*/
struct soc_camera_format_xlate {
enum v4l2_mbus_pixelcode code;
const struct soc_mbus_pixelfmt *host_fmt;
};
#define SOCAM_SENSE_PCLK_CHANGED (1 << 0)
/**
* This struct can be attached to struct soc_camera_device by the host driver
* to request sense from the camera, for example, when calling .set_fmt(). The
* host then can check which flags are set and verify respective values if any.
* For example, if SOCAM_SENSE_PCLK_CHANGED is set, it means, pixclock has
* changed during this operation. After completion the host should detach sense.
*
* @flags ored SOCAM_SENSE_* flags
* @master_clock if the host wants to be informed about pixel-clock
* change, it better set master_clock.
* @pixel_clock_max maximum pixel clock frequency supported by the host,
* camera is not allowed to exceed this.
* @pixel_clock if the camera driver changed pixel clock during this
* operation, it sets SOCAM_SENSE_PCLK_CHANGED, uses
* master_clock to calculate the new pixel-clock and
* sets this field.
*/
struct soc_camera_sense {
unsigned long flags;
unsigned long master_clock;
unsigned long pixel_clock_max;
unsigned long pixel_clock;
};
#define SOCAM_DATAWIDTH(x) BIT((x) - 1)
#define SOCAM_DATAWIDTH_4 SOCAM_DATAWIDTH(4)
#define SOCAM_DATAWIDTH_8 SOCAM_DATAWIDTH(8)
#define SOCAM_DATAWIDTH_9 SOCAM_DATAWIDTH(9)
#define SOCAM_DATAWIDTH_10 SOCAM_DATAWIDTH(10)
#define SOCAM_DATAWIDTH_15 SOCAM_DATAWIDTH(15)
#define SOCAM_DATAWIDTH_16 SOCAM_DATAWIDTH(16)
#define SOCAM_DATAWIDTH_MASK (SOCAM_DATAWIDTH_4 | SOCAM_DATAWIDTH_8 | \
SOCAM_DATAWIDTH_9 | SOCAM_DATAWIDTH_10 | \
SOCAM_DATAWIDTH_15 | SOCAM_DATAWIDTH_16)
static inline void soc_camera_limit_side(int *start, int *length,
unsigned int start_min,
unsigned int length_min, unsigned int length_max)
{
if (*length < length_min)
*length = length_min;
else if (*length > length_max)
*length = length_max;
if (*start < start_min)
*start = start_min;
else if (*start > start_min + length_max - *length)
*start = start_min + length_max - *length;
}
unsigned long soc_camera_apply_sensor_flags(struct soc_camera_link *icl,
unsigned long flags);
unsigned long soc_camera_apply_board_flags(struct soc_camera_link *icl,
const struct v4l2_mbus_config *cfg);
/* This is only temporary here - until v4l2-subdev begins to link to video_device */
#include <linux/i2c.h>
static inline struct video_device *soc_camera_i2c_to_vdev(const struct i2c_client *client)
{
struct v4l2_subdev *sd = i2c_get_clientdata(client);
struct soc_camera_device *icd = v4l2_get_subdev_hostdata(sd);
return icd ? icd->vdev : NULL;
}
static inline struct soc_camera_link *soc_camera_i2c_to_link(const struct i2c_client *client)
{
return client->dev.platform_data;
}
static inline struct v4l2_subdev *soc_camera_vdev_to_subdev(const struct video_device *vdev)
{
struct soc_camera_device *icd = dev_get_drvdata(vdev->parent);
return soc_camera_to_subdev(icd);
}
static inline struct soc_camera_device *soc_camera_from_vb2q(const struct vb2_queue *vq)
{
return container_of(vq, struct soc_camera_device, vb2_vidq);
}
static inline struct soc_camera_device *soc_camera_from_vbq(const struct videobuf_queue *vq)
{
return container_of(vq, struct soc_camera_device, vb_vidq);
}
static inline u32 soc_camera_grp_id(const struct soc_camera_device *icd)
{
return (icd->iface << 8) | (icd->devnum + 1);
}
void soc_camera_lock(struct vb2_queue *vq);
void soc_camera_unlock(struct vb2_queue *vq);
#endif
kernel/include/media/soc_camera_platform.h
+79
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/*
* Generic Platform Camera Driver Header
*
* Copyright (C) 2008 Magnus Damm
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __SOC_CAMERA_H__
#define __SOC_CAMERA_H__
#include <linux/videodev2.h>
#include <media/soc_camera.h>
#include <media/v4l2-mediabus.h>
struct device;
struct soc_camera_platform_info {
const char *format_name;
unsigned long format_depth;
struct v4l2_mbus_framefmt format;
unsigned long mbus_param;
enum v4l2_mbus_type mbus_type;
struct soc_camera_device *icd;
int (*set_capture)(struct soc_camera_platform_info *info, int enable);
};
static inline void soc_camera_platform_release(struct platform_device **pdev)
{
*pdev = NULL;
}
static inline int soc_camera_platform_add(struct soc_camera_device *icd,
struct platform_device **pdev,
struct soc_camera_link *plink,
void (*release)(struct device *dev),
int id)
{
struct soc_camera_platform_info *info = plink->priv;
int ret;
if (icd->link != plink)
return -ENODEV;
if (*pdev)
return -EBUSY;
*pdev = platform_device_alloc("soc_camera_platform", id);
if (!*pdev)
return -ENOMEM;
info->icd = icd;
(*pdev)->dev.platform_data = info;
(*pdev)->dev.release = release;
ret = platform_device_add(*pdev);
if (ret < 0) {
platform_device_put(*pdev);
*pdev = NULL;
info->icd = NULL;
}
return ret;
}
static inline void soc_camera_platform_del(const struct soc_camera_device *icd,
struct platform_device *pdev,
const struct soc_camera_link *plink)
{
if (icd->link != plink || !pdev)
return;
platform_device_unregister(pdev);
}
#endif /* __SOC_CAMERA_H__ */
kernel/include/media/soc_mediabus.h
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/*
* SoC-camera Media Bus API extensions
*
* Copyright (C) 2009, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef SOC_MEDIABUS_H
#define SOC_MEDIABUS_H
#include <linux/videodev2.h>
#include <linux/v4l2-mediabus.h>
/**
* enum soc_mbus_packing - data packing types on the media-bus
* @SOC_MBUS_PACKING_NONE: no packing, bit-for-bit transfer to RAM, one
* sample represents one pixel
* @SOC_MBUS_PACKING_2X8_PADHI: 16 bits transferred in 2 8-bit samples, in the
* possibly incomplete byte high bits are padding
* @SOC_MBUS_PACKING_2X8_PADLO: as above, but low bits are padding
* @SOC_MBUS_PACKING_EXTEND16: sample width (e.g., 10 bits) has to be extended
* to 16 bits
* @SOC_MBUS_PACKING_VARIABLE: compressed formats with variable packing
* @SOC_MBUS_PACKING_1_5X8: used for packed YUV 4:2:0 formats, where 4
* pixels occupy 6 bytes in RAM
*/
enum soc_mbus_packing {
SOC_MBUS_PACKING_NONE,
SOC_MBUS_PACKING_2X8_PADHI,
SOC_MBUS_PACKING_2X8_PADLO,
SOC_MBUS_PACKING_EXTEND16,
SOC_MBUS_PACKING_VARIABLE,
SOC_MBUS_PACKING_1_5X8,
};
/**
* enum soc_mbus_order - sample order on the media bus
* @SOC_MBUS_ORDER_LE: least significant sample first
* @SOC_MBUS_ORDER_BE: most significant sample first
*/
enum soc_mbus_order {
SOC_MBUS_ORDER_LE,
SOC_MBUS_ORDER_BE,
};
/**
* struct soc_mbus_pixelfmt - Data format on the media bus
* @name: Name of the format
* @fourcc: Fourcc code, that will be obtained if the data is
* stored in memory in the following way:
* @packing: Type of sample-packing, that has to be used
* @order: Sample order when storing in memory
* @bits_per_sample: How many bits the bridge has to sample
*/
struct soc_mbus_pixelfmt {
const char *name;
u32 fourcc;
enum soc_mbus_packing packing;
enum soc_mbus_order order;
u8 bits_per_sample;
};
/**
* struct soc_mbus_lookup - Lookup FOURCC IDs by mediabus codes for pass-through
* @code: mediabus pixel-code
* @fmt: pixel format description
*/
struct soc_mbus_lookup {
enum v4l2_mbus_pixelcode code;
struct soc_mbus_pixelfmt fmt;
};
const struct soc_mbus_pixelfmt *soc_mbus_find_fmtdesc(
enum v4l2_mbus_pixelcode code,
const struct soc_mbus_lookup *lookup,
int n);
const struct soc_mbus_pixelfmt *soc_mbus_get_fmtdesc(
enum v4l2_mbus_pixelcode code);
s32 soc_mbus_bytes_per_line(u32 width, const struct soc_mbus_pixelfmt *mf);
int soc_mbus_samples_per_pixel(const struct soc_mbus_pixelfmt *mf,
unsigned int *numerator, unsigned int *denominator);
unsigned int soc_mbus_config_compatible(const struct v4l2_mbus_config *cfg,
unsigned int flags);
#endif
kernel/include/media/sr030pc30.h
+21
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/*
* Driver header for SR030PC30 camera sensor
*
* Copyright (c) 2010 Samsung Electronics, Co. Ltd
* Contact: Sylwester Nawrocki <s.nawrocki@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef SR030PC30_H
#define SR030PC30_H
struct sr030pc30_platform_data {
unsigned long clk_rate; /* master clock frequency in Hz */
int (*set_power)(struct device *dev, int on);
};
#endif /* SR030PC30_H */
kernel/include/media/tavarua.h
+595
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#ifndef __LINUX_TAVARUA_H
#define __LINUX_TAVARUA_H
#ifdef __KERNEL__
#include <linux/types.h>
#include <asm/sizes.h>
#else
#include <stdint.h>
#endif
#include <linux/ioctl.h>
#include <linux/videodev2.h>
#undef FM_DEBUG
/* constants */
#define RDS_BLOCKS_NUM (4)
#define BYTES_PER_BLOCK (3)
#define MAX_PS_LENGTH (96)
#define MAX_RT_LENGTH (64)
#define RX_STATIONS0_LEN (15)
#define XFRDAT0 (0x20)
#define XFRDAT1 (0x21)
#define XFRDAT2 (0x22)
#define INTDET_PEEK_MSB (0x88)
#define INTDET_PEEK_LSB (0x26)
#define RMSSI_PEEK_MSB (0x88)
#define RMSSI_PEEK_LSB (0xA8)
#define MPX_DCC_BYPASS_POKE_MSB (0x88)
#define MPX_DCC_BYPASS_POKE_LSB (0xC0)
#define MPX_DCC_PEEK_MSB_REG1 (0x88)
#define MPX_DCC_PEEK_LSB_REG1 (0xC2)
#define MPX_DCC_PEEK_MSB_REG2 (0x88)
#define MPX_DCC_PEEK_LSB_REG2 (0xC3)
#define MPX_DCC_PEEK_MSB_REG3 (0x88)
#define MPX_DCC_PEEK_LSB_REG3 (0xC4)
#define ON_CHANNEL_TH_MSB (0x0B)
#define ON_CHANNEL_TH_LSB (0xA8)
#define OFF_CHANNEL_TH_MSB (0x0B)
#define OFF_CHANNEL_TH_LSB (0xAC)
#define ENF_200Khz (1)
#define SRCH200KHZ_OFFSET (7)
#define SRCH_MASK (1 << SRCH200KHZ_OFFSET)
/* Standard buffer size */
#define STD_BUF_SIZE (256)
/* Search direction */
#define SRCH_DIR_UP (0)
#define SRCH_DIR_DOWN (1)
/* control options */
#define CTRL_ON (1)
#define CTRL_OFF (0)
#define US_LOW_BAND (87.5)
#define US_HIGH_BAND (108)
/* constant for Tx */
#define MASK_PI (0x0000FFFF)
#define MASK_PI_MSB (0x0000FF00)
#define MASK_PI_LSB (0x000000FF)
#define MASK_PTY (0x0000001F)
#define MASK_TXREPCOUNT (0x0000000F)
#undef FMDBG
#ifdef FM_DEBUG
#define FMDBG(fmt, args...) printk(KERN_INFO "tavarua_radio: " fmt, ##args)
#else
#define FMDBG(fmt, args...)
#endif
#undef FMDERR
#define FMDERR(fmt, args...) printk(KERN_INFO "tavarua_radio: " fmt, ##args)
#undef FMDBG_I2C
#ifdef FM_DEBUG_I2C
#define FMDBG_I2C(fmt, args...) printk(KERN_INFO "fm_i2c: " fmt, ##args)
#else
#define FMDBG_I2C(fmt, args...)
#endif
/* function declarations */
/* FM Core audio paths. */
#define TAVARUA_AUDIO_OUT_ANALOG_OFF (0)
#define TAVARUA_AUDIO_OUT_ANALOG_ON (1)
#define TAVARUA_AUDIO_OUT_DIGITAL_OFF (0)
#define TAVARUA_AUDIO_OUT_DIGITAL_ON (1)
int tavarua_set_audio_path(int digital_on, int analog_on);
/* defines and enums*/
#define MARIMBA_A0 0x01010013
#define MARIMBA_2_1 0x02010204
#define BAHAMA_1_0 0x0302010A
#define BAHAMA_2_0 0x04020205
#define BAHAMA_2_1 0x04020309
#define WAIT_TIMEOUT 2000
#define RADIO_INIT_TIME 15
#define TAVARUA_DELAY 10
/*
* The frequency is set in units of 62.5 Hz when using V4L2_TUNER_CAP_LOW,
* 62.5 kHz otherwise.
* The tuner is able to have a channel spacing of 50, 100 or 200 kHz.
* tuner->capability is therefore set to V4L2_TUNER_CAP_LOW
* The FREQ_MUL is then: 1 MHz / 62.5 Hz = 16000
*/
#define FREQ_MUL (1000000 / 62.5)
enum v4l2_cid_private_tavarua_t {
V4L2_CID_PRIVATE_TAVARUA_SRCHMODE = (V4L2_CID_PRIVATE_BASE + 1),
V4L2_CID_PRIVATE_TAVARUA_SCANDWELL,
V4L2_CID_PRIVATE_TAVARUA_SRCHON,
V4L2_CID_PRIVATE_TAVARUA_STATE,
V4L2_CID_PRIVATE_TAVARUA_TRANSMIT_MODE,
V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_MASK,
V4L2_CID_PRIVATE_TAVARUA_REGION,
V4L2_CID_PRIVATE_TAVARUA_SIGNAL_TH,
V4L2_CID_PRIVATE_TAVARUA_SRCH_PTY,
V4L2_CID_PRIVATE_TAVARUA_SRCH_PI,
V4L2_CID_PRIVATE_TAVARUA_SRCH_CNT,
V4L2_CID_PRIVATE_TAVARUA_EMPHASIS,
V4L2_CID_PRIVATE_TAVARUA_RDS_STD,
V4L2_CID_PRIVATE_TAVARUA_SPACING,
V4L2_CID_PRIVATE_TAVARUA_RDSON,
V4L2_CID_PRIVATE_TAVARUA_RDSGROUP_PROC,
V4L2_CID_PRIVATE_TAVARUA_LP_MODE,
V4L2_CID_PRIVATE_TAVARUA_ANTENNA,
V4L2_CID_PRIVATE_TAVARUA_RDSD_BUF,
V4L2_CID_PRIVATE_TAVARUA_PSALL,
/*v4l2 Tx controls*/
V4L2_CID_PRIVATE_TAVARUA_TX_SETPSREPEATCOUNT,
V4L2_CID_PRIVATE_TAVARUA_STOP_RDS_TX_PS_NAME,
V4L2_CID_PRIVATE_TAVARUA_STOP_RDS_TX_RT,
V4L2_CID_PRIVATE_TAVARUA_IOVERC,
V4L2_CID_PRIVATE_TAVARUA_INTDET,
V4L2_CID_PRIVATE_TAVARUA_MPX_DCC,
V4L2_CID_PRIVATE_TAVARUA_AF_JUMP,
V4L2_CID_PRIVATE_TAVARUA_RSSI_DELTA,
V4L2_CID_PRIVATE_TAVARUA_HLSI,
/*
* Here we have IOCTl's that are specific to IRIS
* (V4L2_CID_PRIVATE_BASE + 0x1E to V4L2_CID_PRIVATE_BASE + 0x28)
*/
V4L2_CID_PRIVATE_SOFT_MUTE,/* 0x800001E*/
V4L2_CID_PRIVATE_RIVA_ACCS_ADDR,
V4L2_CID_PRIVATE_RIVA_ACCS_LEN,
V4L2_CID_PRIVATE_RIVA_PEEK,
V4L2_CID_PRIVATE_RIVA_POKE,
V4L2_CID_PRIVATE_SSBI_ACCS_ADDR,
V4L2_CID_PRIVATE_SSBI_PEEK,
V4L2_CID_PRIVATE_SSBI_POKE,
V4L2_CID_PRIVATE_TX_TONE,
V4L2_CID_PRIVATE_RDS_GRP_COUNTERS,
V4L2_CID_PRIVATE_SET_NOTCH_FILTER,/* 0x8000028 */
V4L2_CID_PRIVATE_TAVARUA_SET_AUDIO_PATH,/* 0x8000029 */
V4L2_CID_PRIVATE_TAVARUA_DO_CALIBRATION,/* 0x800002A : IRIS */
V4L2_CID_PRIVATE_TAVARUA_SRCH_ALGORITHM,/* 0x800002B */
V4L2_CID_PRIVATE_IRIS_GET_SINR, /* 0x800002C : IRIS */
V4L2_CID_PRIVATE_INTF_LOW_THRESHOLD, /* 0x800002D */
V4L2_CID_PRIVATE_INTF_HIGH_THRESHOLD, /* 0x800002E */
V4L2_CID_PRIVATE_SINR_THRESHOLD, /* 0x800002F : IRIS */
V4L2_CID_PRIVATE_SINR_SAMPLES, /* 0x8000030 : IRIS */
V4L2_CID_PRIVATE_SPUR_FREQ,
V4L2_CID_PRIVATE_SPUR_FREQ_RMSSI,
V4L2_CID_PRIVATE_SPUR_SELECTION,
V4L2_CID_PRIVATE_UPDATE_SPUR_TABLE,
V4L2_CID_PRIVATE_VALID_CHANNEL,
};
enum tavarua_buf_t {
TAVARUA_BUF_SRCH_LIST,
TAVARUA_BUF_EVENTS,
TAVARUA_BUF_RT_RDS,
TAVARUA_BUF_PS_RDS,
TAVARUA_BUF_RAW_RDS,
TAVARUA_BUF_AF_LIST,
TAVARUA_BUF_MAX
};
enum tavarua_xfr_t {
TAVARUA_XFR_SYNC,
TAVARUA_XFR_ERROR,
TAVARUA_XFR_SRCH_LIST,
TAVARUA_XFR_RT_RDS,
TAVARUA_XFR_PS_RDS,
TAVARUA_XFR_AF_LIST,
TAVARUA_XFR_MAX
};
enum channel_spacing {
FM_CH_SPACE_200KHZ,
FM_CH_SPACE_100KHZ,
FM_CH_SPACE_50KHZ
};
enum step_size {
NO_SRCH200khz,
ENF_SRCH200khz
};
enum emphasis {
EMP_75,
EMP_50
};
enum rds_std {
RBDS_STD,
RDS_STD
};
/* offsets */
#define RAW_RDS 0x0F
#define RDS_BLOCK 3
/* registers*/
#define MARIMBA_XO_BUFF_CNTRL 0x07
#define RADIO_REGISTERS 0x30
#define XFR_REG_NUM 16
#define STATUS_REG_NUM 3
/* TX constants */
#define HEADER_SIZE 4
#define TX_ON 0x80
#define TAVARUA_TX_RT RDS_RT_0
#define TAVARUA_TX_PS RDS_PS_0
enum register_t {
STATUS_REG1 = 0,
STATUS_REG2,
STATUS_REG3,
RDCTRL,
FREQ,
TUNECTRL,
SRCHRDS1,
SRCHRDS2,
SRCHCTRL,
IOCTRL,
RDSCTRL,
ADVCTRL,
AUDIOCTRL,
RMSSI,
IOVERC,
AUDIOIND = 0x1E,
XFRCTRL,
FM_CTL0 = 0xFF,
LEAKAGE_CNTRL = 0xFE,
};
#define BAHAMA_RBIAS_CTL1 0x07
#define BAHAMA_FM_MODE_REG 0xFD
#define BAHAMA_FM_CTL1_REG 0xFE
#define BAHAMA_FM_CTL0_REG 0xFF
#define BAHAMA_FM_MODE_NORMAL 0x00
#define BAHAMA_LDO_DREG_CTL0 0xF0
#define BAHAMA_LDO_AREG_CTL0 0xF4
/* Radio Control */
#define RDCTRL_STATE_OFFSET 0
#define RDCTRL_STATE_MASK (3 << RDCTRL_STATE_OFFSET)
#define RDCTRL_BAND_OFFSET 2
#define RDCTRL_BAND_MASK (1 << RDCTRL_BAND_OFFSET)
#define RDCTRL_CHSPACE_OFFSET 3
#define RDCTRL_CHSPACE_MASK (3 << RDCTRL_CHSPACE_OFFSET)
#define RDCTRL_DEEMPHASIS_OFFSET 5
#define RDCTRL_DEEMPHASIS_MASK (1 << RDCTRL_DEEMPHASIS_OFFSET)
#define RDCTRL_HLSI_OFFSET 6
#define RDCTRL_HLSI_MASK (3 << RDCTRL_HLSI_OFFSET)
#define RDSAF_OFFSET 6
#define RDSAF_MASK (1 << RDSAF_OFFSET)
/* Tune Control */
#define TUNE_STATION 0x01
#define ADD_OFFSET (1 << 1)
#define SIGSTATE (1 << 5)
#define MOSTSTATE (1 << 6)
#define RDSSYNC (1 << 7)
/* Search Control */
#define SRCH_MODE_OFFSET 0
#define SRCH_MODE_MASK (7 << SRCH_MODE_OFFSET)
#define SRCH_DIR_OFFSET 3
#define SRCH_DIR_MASK (1 << SRCH_DIR_OFFSET)
#define SRCH_DWELL_OFFSET 4
#define SRCH_DWELL_MASK (7 << SRCH_DWELL_OFFSET)
#define SRCH_STATE_OFFSET 7
#define SRCH_STATE_MASK (1 << SRCH_STATE_OFFSET)
/* I/O Control */
#define IOC_HRD_MUTE 0x03
#define IOC_SFT_MUTE (1 << 2)
#define IOC_MON_STR (1 << 3)
#define IOC_SIG_BLND (1 << 4)
#define IOC_INTF_BLND (1 << 5)
#define IOC_ANTENNA (1 << 6)
#define IOC_ANTENNA_OFFSET 6
#define IOC_ANTENNA_MASK (1 << IOC_ANTENNA_OFFSET)
/* RDS Control */
#define RDS_ON 0x01
#define RDSCTRL_STANDARD_OFFSET 1
#define RDSCTRL_STANDARD_MASK (1 << RDSCTRL_STANDARD_OFFSET)
/* Advanced features controls */
#define RDSRTEN (1 << 3)
#define RDSPSEN (1 << 4)
/* Audio path control */
#define AUDIORX_ANALOG_OFFSET 0
#define AUDIORX_ANALOG_MASK (1 << AUDIORX_ANALOG_OFFSET)
#define AUDIORX_DIGITAL_OFFSET 1
#define AUDIORX_DIGITAL_MASK (1 << AUDIORX_DIGITAL_OFFSET)
#define AUDIOTX_OFFSET 2
#define AUDIOTX_MASK (1 << AUDIOTX_OFFSET)
#define I2SCTRL_OFFSET 3
#define I2SCTRL_MASK (1 << I2SCTRL_OFFSET)
/* Search options */
enum search_t {
SEEK,
SCAN,
SCAN_FOR_STRONG,
SCAN_FOR_WEAK,
RDS_SEEK_PTY,
RDS_SCAN_PTY,
RDS_SEEK_PI,
RDS_AF_JUMP,
};
/* Band limits */
#define REGION_US_EU_BAND_LOW 87500
#define REGION_US_EU_BAND_HIGH 108000
#define REGION_JAPAN_STANDARD_BAND_LOW 76000
#define REGION_JAPAN_STANDARD_BAND_HIGH 90000
#define REGION_JAPAN_WIDE_BAND_LOW 90000
#define REGION_JAPAN_WIDE_BAND_HIGH 108000
#define MPX_DCC_BYPASS_REG 0x88C0
#define MPX_DCC_DATA_REG 0x88C2
enum audio_path {
FM_DIGITAL_PATH,
FM_ANALOG_PATH
};
#define SRCH_MODE 0x07
#define SRCH_DIR 0x08 /* 0-up 1-down */
#define SCAN_DWELL 0x70
#define SRCH_ON 0x80
/* RDS CONFIG */
#define RDS_CONFIG_PSALL 0x01
#define FM_ENABLE 0x22
#define SET_REG_FIELD(reg, val, offset, mask) \
(reg = (reg & ~mask) | (((val) << offset) & mask))
#define GET_REG_FIELD(reg, offset, mask) ((reg & mask) >> offset)
#define RSH_DATA(val, offset) ((val) >> (offset))
#define LSH_DATA(val, offset) ((val) << (offset))
#define GET_ABS_VAL(val) ((val) & (0xFF))
enum radio_state_t {
FM_OFF,
FM_RECV,
FM_TRANS,
FM_RESET,
};
#define XFRCTRL_WRITE (1 << 7)
/* Interrupt status */
/* interrupt register 1 */
#define READY (1 << 0) /* Radio ready after powerup or reset */
#define TUNE (1 << 1) /* Tune completed */
#define SEARCH (1 << 2) /* Search completed (read FREQ) */
#define SCANNEXT (1 << 3) /* Scanning for next station */
#define SIGNAL (1 << 4) /* Signal indicator change (read SIGSTATE) */
#define INTF (1 << 5) /* Interference cnt has fallen outside range */
#define SYNC (1 << 6) /* RDS sync state change (read RDSSYNC) */
#define AUDIO (1 << 7) /* Audio Control indicator (read AUDIOIND) */
/* interrupt register 2 */
#define RDSDAT (1 << 0) /* New unread RDS data group available */
#define BLOCKB (1 << 1) /* Block-B match condition exists */
#define PROGID (1 << 2) /* Block-A or Block-C matched stored PI value*/
#define RDSPS (1 << 3) /* New RDS Program Service Table available */
#define RDSRT (1 << 4) /* New RDS Radio Text available */
#define RDSAF (1 << 5) /* New RDS AF List available */
#define TXRDSDAT (1 << 6) /* Transmitted an RDS group */
#define TXRDSDONE (1 << 7) /* RDS raw group one-shot transmit completed */
/* interrupt register 3 */
#define TRANSFER (1 << 0) /* Data transfer (XFR) completed */
#define RDSPROC (1 << 1) /* Dynamic RDS Processing complete */
#define ERROR (1 << 7) /* Err occurred.Read code to determine cause */
#define FM_TX_PWR_LVL_0 0 /* Lowest power lvl that can be set for Tx */
#define FM_TX_PWR_LVL_MAX 7 /* Max power lvl for Tx */
/* Tone Generator control value */
#define TONE_GEN_CTRL_BYTE 0x00
#define TONE_CHANNEL_EN_AND_SCALING_BYTE 0x01
#define TONE_LEFT_FREQ_BYTE 0x02
#define TONE_RIGHT_FREQ_BYTE 0x03
#define TONE_LEFT_PHASE 0x04
#define TONE_RIGHT_PHASE 0x05
#define TONE_LEFT_CH_ENABLED 0x01
#define TONE_RIGHT_CH_ENABLED 0x02
#define TONE_LEFT_RIGHT_CH_ENABLED (TONE_LEFT_CH_ENABLED\
| TONE_RIGHT_CH_ENABLED)
#define TONE_SCALING_SHIFT 0x02
/* Transfer */
enum tavarua_xfr_ctrl_t {
RDS_PS_0 = 0x01,
RDS_PS_1,
RDS_PS_2,
RDS_PS_3,
RDS_PS_4,
RDS_PS_5,
RDS_PS_6,
RDS_RT_0,
RDS_RT_1,
RDS_RT_2,
RDS_RT_3,
RDS_RT_4,
RDS_AF_0,
RDS_AF_1,
RDS_CONFIG,
RDS_TX_GROUPS,
RDS_COUNT_0,
RDS_COUNT_1,
RDS_COUNT_2,
RADIO_CONFIG,
RX_CONFIG,
RX_TIMERS,
RX_STATIONS_0,
RX_STATIONS_1,
INT_CTRL,
ERROR_CODE,
CHIPID,
CAL_DAT_0 = 0x20,
CAL_DAT_1,
CAL_DAT_2,
CAL_DAT_3,
CAL_CFG_0,
CAL_CFG_1,
DIG_INTF_0,
DIG_INTF_1,
DIG_AGC_0,
DIG_AGC_1,
DIG_AGC_2,
DIG_AUDIO_0,
DIG_AUDIO_1,
DIG_AUDIO_2,
DIG_AUDIO_3,
DIG_AUDIO_4,
DIG_RXRDS,
DIG_DCC,
DIG_SPUR,
DIG_MPXDCC,
DIG_PILOT,
DIG_DEMOD,
DIG_MOST,
DIG_TX_0,
DIG_TX_1,
PHY_TXGAIN = 0x3B,
PHY_CONFIG,
PHY_TXBLOCK,
PHY_TCB,
XFR_EXT,
XFR_PEEK_MODE = 0x40,
XFR_POKE_MODE = 0xC0,
TAVARUA_XFR_CTRL_MAX
};
enum tavarua_evt_t {
TAVARUA_EVT_RADIO_READY,
TAVARUA_EVT_TUNE_SUCC,
TAVARUA_EVT_SEEK_COMPLETE,
TAVARUA_EVT_SCAN_NEXT,
TAVARUA_EVT_NEW_RAW_RDS,
TAVARUA_EVT_NEW_RT_RDS,
TAVARUA_EVT_NEW_PS_RDS,
TAVARUA_EVT_ERROR,
TAVARUA_EVT_BELOW_TH,
TAVARUA_EVT_ABOVE_TH,
TAVARUA_EVT_STEREO,
TAVARUA_EVT_MONO,
TAVARUA_EVT_RDS_AVAIL,
TAVARUA_EVT_RDS_NOT_AVAIL,
TAVARUA_EVT_NEW_SRCH_LIST,
TAVARUA_EVT_NEW_AF_LIST,
TAVARUA_EVT_TXRDSDAT,
TAVARUA_EVT_TXRDSDONE,
TAVARUA_EVT_RADIO_DISABLED
};
enum tavarua_region_t {
TAVARUA_REGION_US,
TAVARUA_REGION_EU,
TAVARUA_REGION_JAPAN,
TAVARUA_REGION_JAPAN_WIDE,
TAVARUA_REGION_OTHER
};
enum {
ONE_BYTE = 1,
TWO_BYTE,
THREE_BYTE,
FOUR_BYTE,
FIVE_BYTE,
SIX_BYTE,
SEVEN_BYTE,
EIGHT_BYTE,
NINE_BYTE,
TEN_BYTE,
ELEVEN_BYTE,
TWELVE_BYTE,
THIRTEEN_BYTE
};
#define XFR_READ (0)
#define XFR_WRITE (1)
#define XFR_MODE_OFFSET (0)
#define XFR_ADDR_MSB_OFFSET (1)
#define XFR_ADDR_LSB_OFFSET (2)
#define XFR_DATA_OFFSET (3)
#define SPUR_DATA_SIZE (3)
#define MAX_SPUR_FREQ_LIMIT (30)
#define READ_COMPLETE (0x20)
#define SPUR_TABLE_ADDR (0x0BB7)
#define SPUR_TABLE_START_ADDR (SPUR_TABLE_ADDR + 1)
#define XFR_PEEK_COMPLETE (XFR_PEEK_MODE | READ_COMPLETE)
#define XFR_POKE_COMPLETE (XFR_POKE_MODE)
#define TUNE_MULT (16)
#define ADJ_CHANNEL_KHZ (50)
#define MPX_DCC_UPPER_LIMIT (20000)
#define MPX_DCC_LIMIT (12566)
#define INVALID_CHANNEL (0)
#define VALID_CHANNEL (1)
#define COMPUTE_SPUR(val) ((((val) - (76000)) / (50)))
#define GET_FREQ(val, bit) ((bit == 1) ? ((val) >> 8) : ((val) & 0xFF))
struct fm_spur_data {
int freq[MAX_SPUR_FREQ_LIMIT];
__s8 rmssi[MAX_SPUR_FREQ_LIMIT];
} __packed;
struct fm_def_data_wr_req {
__u8 mode;
__u8 length;
__u8 data[XFR_REG_NUM];
} __packed;
enum Internal_tone_gen_vals {
ONE_KHZ_LR_EQUA_0DBFS = 1,
ONE_KHZ_LEFTONLY_EQUA_0DBFS,
ONE_KHZ_RIGHTONLY_EQUA_0DBFS,
ONE_KHZ_LR_EQUA_l8DBFS,
FIFTEEN_KHZ_LR_EQUA_l8DBFS
};
enum Tone_scaling_indexes {
TONE_SCALE_IND_0,
TONE_SCALE_IND_1,
TONE_SCALE_IND_2,
TONE_SCALE_IND_3,
TONE_SCALE_IND_4,
TONE_SCALE_IND_5,
TONE_SCALE_IND_6,
TONE_SCALE_IND_7,
TONE_SCALE_IND_8,
TONE_SCALE_IND_9,
TONE_SCALE_IND_10,
TONE_SCALE_IND_11,
TONE_SCALE_IND_12
};
#endif /* __LINUX_TAVARUA_H */
kernel/include/media/timb_radio.h
+30
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/*
* timb_radio.h Platform struct for the Timberdale radio driver
* Copyright (c) 2009 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _TIMB_RADIO_
#define _TIMB_RADIO_ 1
#include <linux/i2c.h>
struct timb_radio_platform_data {
int i2c_adapter; /* I2C adapter where the tuner and dsp are attached */
struct i2c_board_info *tuner;
struct i2c_board_info *dsp;
};
#endif
kernel/include/media/timb_video.h
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/*
* timb_video.h Platform struct for the Timberdale video driver
* Copyright (c) 2009-2010 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _TIMB_VIDEO_
#define _TIMB_VIDEO_ 1
#include <linux/i2c.h>
struct timb_video_platform_data {
int dma_channel;
int i2c_adapter; /* The I2C adapter where the encoder is attached */
struct {
const char *module_name;
struct i2c_board_info *info;
} encoder;
};
#endif
kernel/include/media/tuner-types.h
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/*
* descriptions for simple tuners.
*/
#ifndef __TUNER_TYPES_H__
#define __TUNER_TYPES_H__
enum param_type {
TUNER_PARAM_TYPE_RADIO,
TUNER_PARAM_TYPE_PAL,
TUNER_PARAM_TYPE_SECAM,
TUNER_PARAM_TYPE_NTSC,
TUNER_PARAM_TYPE_DIGITAL,
};
struct tuner_range {
unsigned short limit;
unsigned char config;
unsigned char cb;
};
struct tuner_params {
enum param_type type;
/* Many Philips based tuners have a comment like this in their
* datasheet:
*
* For channel selection involving band switching, and to ensure
* smooth tuning to the desired channel without causing
* unnecessary charge pump action, it is recommended to consider
* the difference between wanted channel frequency and the
* current channel frequency. Unnecessary charge pump action
* will result in very low tuning voltage which may drive the
* oscillator to extreme conditions.
*
* Set cb_first_if_lower_freq to 1, if this check is
* required for this tuner.
*
* I tested this for PAL by first setting the TV frequency to
* 203 MHz and then switching to 96.6 MHz FM radio. The result was
* static unless the control byte was sent first.
*/
unsigned int cb_first_if_lower_freq:1;
/* Set to 1 if this tuner uses a tda9887 */
unsigned int has_tda9887:1;
/* Many Philips tuners use tda9887 PORT1 to select the FM radio
sensitivity. If this setting is 1, then set PORT1 to 1 to
get proper FM reception. */
unsigned int port1_fm_high_sensitivity:1;
/* Some Philips tuners use tda9887 PORT2 to select the FM radio
sensitivity. If this setting is 1, then set PORT2 to 1 to
get proper FM reception. */
unsigned int port2_fm_high_sensitivity:1;
/* Some Philips tuners use tda9887 cGainNormal to select the FM radio
sensitivity. If this setting is 1, e register will use cGainNormal
instead of cGainLow. */
unsigned int fm_gain_normal:1;
/* Most tuners with a tda9887 use QSS mode. Some (cheaper) tuners
use Intercarrier mode. If this setting is 1, then the tuner
needs to be set to intercarrier mode. */
unsigned int intercarrier_mode:1;
/* This setting sets the default value for PORT1.
0 means inactive, 1 means active. Note: the actual bit
value written to the tda9887 is inverted. So a 0 here
means a 1 in the B6 bit. */
unsigned int port1_active:1;
/* This setting sets the default value for PORT2.
0 means inactive, 1 means active. Note: the actual bit
value written to the tda9887 is inverted. So a 0 here
means a 1 in the B7 bit. */
unsigned int port2_active:1;
/* Sometimes PORT1 is inverted when the SECAM-L' standard is selected.
Set this bit to 1 if this is needed. */
unsigned int port1_invert_for_secam_lc:1;
/* Sometimes PORT2 is inverted when the SECAM-L' standard is selected.
Set this bit to 1 if this is needed. */
unsigned int port2_invert_for_secam_lc:1;
/* Some cards require PORT1 to be 1 for mono Radio FM and 0 for stereo. */
unsigned int port1_set_for_fm_mono:1;
/* Select 18% (or according to datasheet 0%) L standard PLL gating,
vs the driver default of 36%. */
unsigned int default_pll_gating_18:1;
/* IF to use in radio mode. Tuners with a separate radio IF filter
seem to use 10.7, while those without use 33.3 for PAL/SECAM tuners
and 41.3 for NTSC tuners. 0 = 10.7, 1 = 33.3, 2 = 41.3 */
unsigned int radio_if:2;
/* Default tda9887 TOP value in dB for the low band. Default is 0.
Range: -16:+15 */
signed int default_top_low:5;
/* Default tda9887 TOP value in dB for the mid band. Default is 0.
Range: -16:+15 */
signed int default_top_mid:5;
/* Default tda9887 TOP value in dB for the high band. Default is 0.
Range: -16:+15 */
signed int default_top_high:5;
/* Default tda9887 TOP value in dB for SECAM-L/L' for the low band.
Default is 0. Several tuners require a different TOP value for
the SECAM-L/L' standards. Range: -16:+15 */
signed int default_top_secam_low:5;
/* Default tda9887 TOP value in dB for SECAM-L/L' for the mid band.
Default is 0. Several tuners require a different TOP value for
the SECAM-L/L' standards. Range: -16:+15 */
signed int default_top_secam_mid:5;
/* Default tda9887 TOP value in dB for SECAM-L/L' for the high band.
Default is 0. Several tuners require a different TOP value for
the SECAM-L/L' standards. Range: -16:+15 */
signed int default_top_secam_high:5;
u16 iffreq;
unsigned int count;
struct tuner_range *ranges;
};
struct tunertype {
char *name;
unsigned int count;
struct tuner_params *params;
u16 min;
u16 max;
u32 stepsize;
u8 *initdata;
u8 *sleepdata;
};
extern struct tunertype tuners[];
extern unsigned const int tuner_count;
#endif
kernel/include/media/tuner.h
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/*
tuner.h - definition for different tuners
Copyright (C) 1997 Markus Schroeder (schroedm@uni-duesseldorf.de)
minor modifications by Ralph Metzler (rjkm@thp.uni-koeln.de)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _TUNER_H
#define _TUNER_H
#ifdef __KERNEL__
#include <linux/videodev2.h>
#define ADDR_UNSET (255)
#define TUNER_TEMIC_PAL 0 /* 4002 FH5 (3X 7756, 9483) */
#define TUNER_PHILIPS_PAL_I 1
#define TUNER_PHILIPS_NTSC 2
#define TUNER_PHILIPS_SECAM 3 /* you must actively select B/G, L, L` */
#define TUNER_ABSENT 4
#define TUNER_PHILIPS_PAL 5
#define TUNER_TEMIC_NTSC 6 /* 4032 FY5 (3X 7004, 9498, 9789) */
#define TUNER_TEMIC_PAL_I 7 /* 4062 FY5 (3X 8501, 9957) */
#define TUNER_TEMIC_4036FY5_NTSC 8 /* 4036 FY5 (3X 1223, 1981, 7686) */
#define TUNER_ALPS_TSBH1_NTSC 9
#define TUNER_ALPS_TSBE1_PAL 10
#define TUNER_ALPS_TSBB5_PAL_I 11
#define TUNER_ALPS_TSBE5_PAL 12
#define TUNER_ALPS_TSBC5_PAL 13
#define TUNER_TEMIC_4006FH5_PAL 14 /* 4006 FH5 (3X 9500, 9501, 7291) */
#define TUNER_ALPS_TSHC6_NTSC 15
#define TUNER_TEMIC_PAL_DK 16 /* 4016 FY5 (3X 1392, 1393) */
#define TUNER_PHILIPS_NTSC_M 17
#define TUNER_TEMIC_4066FY5_PAL_I 18 /* 4066 FY5 (3X 7032, 7035) */
#define TUNER_TEMIC_4006FN5_MULTI_PAL 19 /* B/G, I and D/K autodetected (3X 7595, 7606, 7657) */
#define TUNER_TEMIC_4009FR5_PAL 20 /* incl. FM radio (3X 7607, 7488, 7711) */
#define TUNER_TEMIC_4039FR5_NTSC 21 /* incl. FM radio (3X 7246, 7578, 7732) */
#define TUNER_TEMIC_4046FM5 22 /* you must actively select B/G, D/K, I, L, L` ! (3X 7804, 7806, 8103, 8104) */
#define TUNER_PHILIPS_PAL_DK 23
#define TUNER_PHILIPS_FQ1216ME 24 /* you must actively select B/G/D/K, I, L, L` */
#define TUNER_LG_PAL_I_FM 25
#define TUNER_LG_PAL_I 26
#define TUNER_LG_NTSC_FM 27
#define TUNER_LG_PAL_FM 28
#define TUNER_LG_PAL 29
#define TUNER_TEMIC_4009FN5_MULTI_PAL_FM 30 /* B/G, I and D/K autodetected (3X 8155, 8160, 8163) */
#define TUNER_SHARP_2U5JF5540_NTSC 31
#define TUNER_Samsung_PAL_TCPM9091PD27 32
#define TUNER_MT2032 33
#define TUNER_TEMIC_4106FH5 34 /* 4106 FH5 (3X 7808, 7865) */
#define TUNER_TEMIC_4012FY5 35 /* 4012 FY5 (3X 0971, 1099) */
#define TUNER_TEMIC_4136FY5 36 /* 4136 FY5 (3X 7708, 7746) */
#define TUNER_LG_PAL_NEW_TAPC 37
#define TUNER_PHILIPS_FM1216ME_MK3 38
#define TUNER_LG_NTSC_NEW_TAPC 39
#define TUNER_HITACHI_NTSC 40
#define TUNER_PHILIPS_PAL_MK 41
#define TUNER_PHILIPS_FCV1236D 42
#define TUNER_PHILIPS_FM1236_MK3 43
#define TUNER_PHILIPS_4IN1 44 /* ATI TV Wonder Pro - Conexant */
/* Microtune merged with Temic 12/31/1999 partially financed by Alps - these may be similar to Temic */
#define TUNER_MICROTUNE_4049FM5 45
#define TUNER_PANASONIC_VP27 46
#define TUNER_LG_NTSC_TAPE 47
#define TUNER_TNF_8831BGFF 48
#define TUNER_MICROTUNE_4042FI5 49 /* DViCO FusionHDTV 3 Gold-Q - 4042 FI5 (3X 8147) */
#define TUNER_TCL_2002N 50
#define TUNER_PHILIPS_FM1256_IH3 51
#define TUNER_THOMSON_DTT7610 52
#define TUNER_PHILIPS_FQ1286 53
#define TUNER_PHILIPS_TDA8290 54
#define TUNER_TCL_2002MB 55 /* Hauppauge PVR-150 PAL */
#define TUNER_PHILIPS_FQ1216AME_MK4 56 /* Hauppauge PVR-150 PAL */
#define TUNER_PHILIPS_FQ1236A_MK4 57 /* Hauppauge PVR-500MCE NTSC */
#define TUNER_YMEC_TVF_8531MF 58
#define TUNER_YMEC_TVF_5533MF 59 /* Pixelview Pro Ultra NTSC */
#define TUNER_THOMSON_DTT761X 60 /* DTT 7611 7611A 7612 7613 7613A 7614 7615 7615A */
#define TUNER_TENA_9533_DI 61
#define TUNER_TEA5767 62 /* Only FM Radio Tuner */
#define TUNER_PHILIPS_FMD1216ME_MK3 63
#define TUNER_LG_TDVS_H06XF 64 /* TDVS H061F, H062F, H064F */
#define TUNER_YMEC_TVF66T5_B_DFF 65 /* Acorp Y878F */
#define TUNER_LG_TALN 66
#define TUNER_PHILIPS_TD1316 67
#define TUNER_PHILIPS_TUV1236D 68 /* ATI HDTV Wonder */
#define TUNER_TNF_5335MF 69 /* Sabrent Bt848 */
#define TUNER_SAMSUNG_TCPN_2121P30A 70 /* Hauppauge PVR-500MCE NTSC */
#define TUNER_XC2028 71
#define TUNER_THOMSON_FE6600 72 /* DViCO FusionHDTV DVB-T Hybrid */
#define TUNER_SAMSUNG_TCPG_6121P30A 73 /* Hauppauge PVR-500 PAL */
#define TUNER_TDA9887 74 /* This tuner should be used only internally */
#define TUNER_TEA5761 75 /* Only FM Radio Tuner */
#define TUNER_XC5000 76 /* Xceive Silicon Tuner */
#define TUNER_TCL_MF02GIP_5N 77 /* TCL MF02GIP_5N */
#define TUNER_PHILIPS_FMD1216MEX_MK3 78
#define TUNER_PHILIPS_FM1216MK5 79
#define TUNER_PHILIPS_FQ1216LME_MK3 80 /* Active loopthrough, no FM */
#define TUNER_PARTSNIC_PTI_5NF05 81
#define TUNER_PHILIPS_CU1216L 82
#define TUNER_NXP_TDA18271 83
#define TUNER_SONY_BTF_PXN01Z 84
#define TUNER_PHILIPS_FQ1236_MK5 85 /* NTSC, TDA9885, no FM radio */
#define TUNER_TENA_TNF_5337 86
#define TUNER_XC4000 87 /* Xceive Silicon Tuner */
#define TUNER_XC5000C 88 /* Xceive Silicon Tuner */
/* tv card specific */
#define TDA9887_PRESENT (1<<0)
#define TDA9887_PORT1_INACTIVE (1<<1)
#define TDA9887_PORT2_INACTIVE (1<<2)
#define TDA9887_QSS (1<<3)
#define TDA9887_INTERCARRIER (1<<4)
#define TDA9887_PORT1_ACTIVE (1<<5)
#define TDA9887_PORT2_ACTIVE (1<<6)
#define TDA9887_INTERCARRIER_NTSC (1<<7)
/* Tuner takeover point adjustment, in dB, -16 <= top <= 15 */
#define TDA9887_TOP_MASK (0x3f << 8)
#define TDA9887_TOP_SET (1 << 13)
#define TDA9887_TOP(top) (TDA9887_TOP_SET | (((16 + (top)) & 0x1f) << 8))
/* config options */
#define TDA9887_DEEMPHASIS_MASK (3<<16)
#define TDA9887_DEEMPHASIS_NONE (1<<16)
#define TDA9887_DEEMPHASIS_50 (2<<16)
#define TDA9887_DEEMPHASIS_75 (3<<16)
#define TDA9887_AUTOMUTE (1<<18)
#define TDA9887_GATING_18 (1<<19)
#define TDA9887_GAIN_NORMAL (1<<20)
#define TDA9887_RIF_41_3 (1<<21) /* radio IF1 41.3 vs 33.3 */
enum tuner_mode {
T_RADIO = 1 << V4L2_TUNER_RADIO,
T_ANALOG_TV = 1 << V4L2_TUNER_ANALOG_TV,
/* Don't need to map V4L2_TUNER_DIGITAL_TV, as tuner-core won't use it */
};
/* Older boards only had a single tuner device. Nowadays multiple tuner
devices may be present on a single board. Using TUNER_SET_TYPE_ADDR
to pass the tuner_setup structure it is possible to setup each tuner
device in turn.
Since multiple devices may be present it is no longer sufficient to
send a command to a single i2c device. Instead you should broadcast
the command to all i2c devices.
By setting the mode_mask correctly you can select which commands are
accepted by a specific tuner device. For example, set mode_mask to
T_RADIO if the device is a radio-only tuner. That specific tuner will
only accept commands when the tuner is in radio mode and ignore them
when the tuner is set to TV mode.
*/
struct tuner_setup {
unsigned short addr; /* I2C address */
unsigned int type; /* Tuner type */
unsigned int mode_mask; /* Allowed tuner modes */
unsigned int config; /* configuraion for more complex tuners */
int (*tuner_callback) (void *dev, int component, int cmd, int arg);
};
#endif /* __KERNEL__ */
#endif /* _TUNER_H */
kernel/include/media/tvaudio.h
+49
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@@ -0,0 +1,49 @@
/*
tvaudio.h - definition for tvaudio inputs
Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef _TVAUDIO_H
#define _TVAUDIO_H
#include <media/i2c-addr.h>
/* The tvaudio module accepts the following inputs: */
#define TVAUDIO_INPUT_TUNER 0
#define TVAUDIO_INPUT_RADIO 1
#define TVAUDIO_INPUT_EXTERN 2
#define TVAUDIO_INPUT_INTERN 3
static inline const unsigned short *tvaudio_addrs(void)
{
static const unsigned short addrs[] = {
I2C_ADDR_TDA8425 >> 1,
I2C_ADDR_TEA6300 >> 1,
I2C_ADDR_TEA6420 >> 1,
I2C_ADDR_TDA9840 >> 1,
I2C_ADDR_TDA985x_L >> 1,
I2C_ADDR_TDA985x_H >> 1,
I2C_ADDR_TDA9874 >> 1,
I2C_ADDR_PIC16C54 >> 1,
I2C_CLIENT_END
};
return addrs;
}
#endif

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