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kernel/include/linux/mfd/88pm860x.h
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/*
* Marvell 88PM860x Interface
*
* Copyright (C) 2009 Marvell International Ltd.
* Haojian Zhuang <haojian.zhuang@marvell.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_MFD_88PM860X_H
#define __LINUX_MFD_88PM860X_H
#include <linux/interrupt.h>
#define MFD_NAME_SIZE (40)
enum {
CHIP_INVALID = 0,
CHIP_PM8606,
CHIP_PM8607,
CHIP_MAX,
};
enum {
PM8606_ID_INVALID,
PM8606_ID_BACKLIGHT,
PM8606_ID_LED,
PM8606_ID_VIBRATOR,
PM8606_ID_TOUCH,
PM8606_ID_SOUND,
PM8606_ID_CHARGER,
PM8606_ID_MAX,
};
enum {
PM8606_BACKLIGHT1 = 0,
PM8606_BACKLIGHT2,
PM8606_BACKLIGHT3,
};
enum {
PM8606_LED1_RED = 0,
PM8606_LED1_GREEN,
PM8606_LED1_BLUE,
PM8606_LED2_RED,
PM8606_LED2_GREEN,
PM8606_LED2_BLUE,
PM8607_LED_VIBRATOR,
};
/* 8606 Registers */
#define PM8606_DCM_BOOST (0x00)
#define PM8606_PWM (0x01)
/* Backlight Registers */
#define PM8606_WLED1A (0x02)
#define PM8606_WLED1B (0x03)
#define PM8606_WLED2A (0x04)
#define PM8606_WLED2B (0x05)
#define PM8606_WLED3A (0x06)
#define PM8606_WLED3B (0x07)
/* LED Registers */
#define PM8606_RGB2A (0x08)
#define PM8606_RGB2B (0x09)
#define PM8606_RGB2C (0x0A)
#define PM8606_RGB2D (0x0B)
#define PM8606_RGB1A (0x0C)
#define PM8606_RGB1B (0x0D)
#define PM8606_RGB1C (0x0E)
#define PM8606_RGB1D (0x0F)
#define PM8606_PREREGULATORA (0x10)
#define PM8606_PREREGULATORB (0x11)
#define PM8606_VIBRATORA (0x12)
#define PM8606_VIBRATORB (0x13)
#define PM8606_VCHG (0x14)
#define PM8606_VSYS (0x15)
#define PM8606_MISC (0x16)
#define PM8606_CHIP_ID (0x17)
#define PM8606_STATUS (0x18)
#define PM8606_FLAGS (0x19)
#define PM8606_PROTECTA (0x1A)
#define PM8606_PROTECTB (0x1B)
#define PM8606_PROTECTC (0x1C)
/* Bit definitions of PM8606 registers */
#define PM8606_DCM_500MA (0x0) /* current limit */
#define PM8606_DCM_750MA (0x1)
#define PM8606_DCM_1000MA (0x2)
#define PM8606_DCM_1250MA (0x3)
#define PM8606_DCM_250MV (0x0 << 2)
#define PM8606_DCM_300MV (0x1 << 2)
#define PM8606_DCM_350MV (0x2 << 2)
#define PM8606_DCM_400MV (0x3 << 2)
#define PM8606_PWM_31200HZ (0x0)
#define PM8606_PWM_15600HZ (0x1)
#define PM8606_PWM_7800HZ (0x2)
#define PM8606_PWM_3900HZ (0x3)
#define PM8606_PWM_1950HZ (0x4)
#define PM8606_PWM_976HZ (0x5)
#define PM8606_PWM_488HZ (0x6)
#define PM8606_PWM_244HZ (0x7)
#define PM8606_PWM_FREQ_MASK (0x7)
#define PM8606_WLED_ON (1 << 0)
#define PM8606_WLED_CURRENT(x) ((x & 0x1F) << 1)
#define PM8606_LED_CURRENT(x) (((x >> 2) & 0x07) << 5)
#define PM8606_VSYS_EN (1 << 1)
#define PM8606_MISC_OSC_EN (1 << 4)
enum {
PM8607_ID_BUCK1 = 0,
PM8607_ID_BUCK2,
PM8607_ID_BUCK3,
PM8607_ID_LDO1,
PM8607_ID_LDO2,
PM8607_ID_LDO3,
PM8607_ID_LDO4,
PM8607_ID_LDO5,
PM8607_ID_LDO6,
PM8607_ID_LDO7,
PM8607_ID_LDO8,
PM8607_ID_LDO9,
PM8607_ID_LDO10,
PM8607_ID_LDO11,
PM8607_ID_LDO12,
PM8607_ID_LDO13,
PM8607_ID_LDO14,
PM8607_ID_LDO15,
PM8607_ID_RG_MAX,
};
/* 8607 chip ID is 0x40 or 0x50 */
#define PM8607_VERSION_MASK (0xF0) /* 8607 chip ID mask */
/* Interrupt Registers */
#define PM8607_STATUS_1 (0x01)
#define PM8607_STATUS_2 (0x02)
#define PM8607_INT_STATUS1 (0x03)
#define PM8607_INT_STATUS2 (0x04)
#define PM8607_INT_STATUS3 (0x05)
#define PM8607_INT_MASK_1 (0x06)
#define PM8607_INT_MASK_2 (0x07)
#define PM8607_INT_MASK_3 (0x08)
/* Regulator Control Registers */
#define PM8607_LDO1 (0x10)
#define PM8607_LDO2 (0x11)
#define PM8607_LDO3 (0x12)
#define PM8607_LDO4 (0x13)
#define PM8607_LDO5 (0x14)
#define PM8607_LDO6 (0x15)
#define PM8607_LDO7 (0x16)
#define PM8607_LDO8 (0x17)
#define PM8607_LDO9 (0x18)
#define PM8607_LDO10 (0x19)
#define PM8607_LDO12 (0x1A)
#define PM8607_LDO14 (0x1B)
#define PM8607_SLEEP_MODE1 (0x1C)
#define PM8607_SLEEP_MODE2 (0x1D)
#define PM8607_SLEEP_MODE3 (0x1E)
#define PM8607_SLEEP_MODE4 (0x1F)
#define PM8607_GO (0x20)
#define PM8607_SLEEP_BUCK1 (0x21)
#define PM8607_SLEEP_BUCK2 (0x22)
#define PM8607_SLEEP_BUCK3 (0x23)
#define PM8607_BUCK1 (0x24)
#define PM8607_BUCK2 (0x25)
#define PM8607_BUCK3 (0x26)
#define PM8607_BUCK_CONTROLS (0x27)
#define PM8607_SUPPLIES_EN11 (0x2B)
#define PM8607_SUPPLIES_EN12 (0x2C)
#define PM8607_GROUP1 (0x2D)
#define PM8607_GROUP2 (0x2E)
#define PM8607_GROUP3 (0x2F)
#define PM8607_GROUP4 (0x30)
#define PM8607_GROUP5 (0x31)
#define PM8607_GROUP6 (0x32)
#define PM8607_SUPPLIES_EN21 (0x33)
#define PM8607_SUPPLIES_EN22 (0x34)
/* Vibrator Control Registers */
#define PM8607_VIBRATOR_SET (0x28)
#define PM8607_VIBRATOR_PWM (0x29)
/* GPADC Registers */
#define PM8607_GP_BIAS1 (0x4F)
#define PM8607_MEAS_EN1 (0x50)
#define PM8607_MEAS_EN2 (0x51)
#define PM8607_MEAS_EN3 (0x52)
#define PM8607_MEAS_OFF_TIME1 (0x53)
#define PM8607_MEAS_OFF_TIME2 (0x54)
#define PM8607_TSI_PREBIAS (0x55) /* prebias time */
#define PM8607_PD_PREBIAS (0x56) /* prebias time */
#define PM8607_GPADC_MISC1 (0x57)
/* RTC Control Registers */
#define PM8607_RTC1 (0xA0)
#define PM8607_RTC_COUNTER1 (0xA1)
#define PM8607_RTC_COUNTER2 (0xA2)
#define PM8607_RTC_COUNTER3 (0xA3)
#define PM8607_RTC_COUNTER4 (0xA4)
#define PM8607_RTC_EXPIRE1 (0xA5)
#define PM8607_RTC_EXPIRE2 (0xA6)
#define PM8607_RTC_EXPIRE3 (0xA7)
#define PM8607_RTC_EXPIRE4 (0xA8)
#define PM8607_RTC_TRIM1 (0xA9)
#define PM8607_RTC_TRIM2 (0xAA)
#define PM8607_RTC_TRIM3 (0xAB)
#define PM8607_RTC_TRIM4 (0xAC)
#define PM8607_RTC_MISC1 (0xAD)
#define PM8607_RTC_MISC2 (0xAE)
#define PM8607_RTC_MISC3 (0xAF)
/* Misc Registers */
#define PM8607_CHIP_ID (0x00)
#define PM8607_B0_MISC1 (0x0C)
#define PM8607_LDO1 (0x10)
#define PM8607_DVC3 (0x26)
#define PM8607_A1_MISC1 (0x40)
/* bit definitions of Status Query Interface */
#define PM8607_STATUS_CC (1 << 3)
#define PM8607_STATUS_PEN (1 << 4)
#define PM8607_STATUS_HEADSET (1 << 5)
#define PM8607_STATUS_HOOK (1 << 6)
#define PM8607_STATUS_MICIN (1 << 7)
#define PM8607_STATUS_ONKEY (1 << 8)
#define PM8607_STATUS_EXTON (1 << 9)
#define PM8607_STATUS_CHG (1 << 10)
#define PM8607_STATUS_BAT (1 << 11)
#define PM8607_STATUS_VBUS (1 << 12)
#define PM8607_STATUS_OV (1 << 13)
/* bit definitions of BUCK3 */
#define PM8607_BUCK3_DOUBLE (1 << 6)
/* bit definitions of Misc1 */
#define PM8607_A1_MISC1_PI2C (1 << 0)
#define PM8607_B0_MISC1_INV_INT (1 << 0)
#define PM8607_B0_MISC1_INT_CLEAR (1 << 1)
#define PM8607_B0_MISC1_INT_MASK (1 << 2)
#define PM8607_B0_MISC1_PI2C (1 << 3)
#define PM8607_B0_MISC1_RESET (1 << 6)
/* bits definitions of GPADC */
#define PM8607_GPADC_EN (1 << 0)
#define PM8607_GPADC_PREBIAS_MASK (3 << 1)
#define PM8607_GPADC_SLOT_CYCLE_MASK (3 << 3) /* slow mode */
#define PM8607_GPADC_OFF_SCALE_MASK (3 << 5) /* GP sleep mode */
#define PM8607_GPADC_SW_CAL_MASK (1 << 7)
#define PM8607_PD_PREBIAS_MASK (0x1F << 0)
#define PM8607_PD_PRECHG_MASK (7 << 5)
#define PM8606_REF_GP_OSC_OFF 0
#define PM8606_REF_GP_OSC_ON 1
#define PM8606_REF_GP_OSC_UNKNOWN 2
/* Clients of reference group and 8MHz oscillator in 88PM8606 */
enum pm8606_ref_gp_and_osc_clients {
REF_GP_NO_CLIENTS = 0,
WLED1_DUTY = (1<<0), /*PF 0x02.7:0*/
WLED2_DUTY = (1<<1), /*PF 0x04.7:0*/
WLED3_DUTY = (1<<2), /*PF 0x06.7:0*/
RGB1_ENABLE = (1<<3), /*PF 0x07.1*/
RGB2_ENABLE = (1<<4), /*PF 0x07.2*/
LDO_VBR_EN = (1<<5), /*PF 0x12.0*/
REF_GP_MAX_CLIENT = 0xFFFF
};
/* Interrupt Number in 88PM8607 */
enum {
PM8607_IRQ_ONKEY,
PM8607_IRQ_EXTON,
PM8607_IRQ_CHG,
PM8607_IRQ_BAT,
PM8607_IRQ_RTC,
PM8607_IRQ_CC,
PM8607_IRQ_VBAT,
PM8607_IRQ_VCHG,
PM8607_IRQ_VSYS,
PM8607_IRQ_TINT,
PM8607_IRQ_GPADC0,
PM8607_IRQ_GPADC1,
PM8607_IRQ_GPADC2,
PM8607_IRQ_GPADC3,
PM8607_IRQ_AUDIO_SHORT,
PM8607_IRQ_PEN,
PM8607_IRQ_HEADSET,
PM8607_IRQ_HOOK,
PM8607_IRQ_MICIN,
PM8607_IRQ_CHG_FAIL,
PM8607_IRQ_CHG_DONE,
PM8607_IRQ_CHG_FAULT,
};
enum {
PM8607_CHIP_A0 = 0x40,
PM8607_CHIP_A1 = 0x41,
PM8607_CHIP_B0 = 0x48,
};
struct pm860x_chip {
struct device *dev;
struct mutex irq_lock;
struct mutex osc_lock;
struct i2c_client *client;
struct i2c_client *companion; /* companion chip client */
struct regmap *regmap;
struct regmap *regmap_companion;
int buck3_double; /* DVC ramp slope double */
unsigned short companion_addr;
unsigned short osc_vote;
int id;
int irq_mode;
int irq_base;
int core_irq;
unsigned char chip_version;
unsigned char osc_status;
unsigned int wakeup_flag;
};
enum {
GI2C_PORT = 0,
PI2C_PORT,
};
struct pm860x_backlight_pdata {
int id;
int pwm;
int iset;
unsigned long flags;
};
struct pm860x_led_pdata {
int id;
int iset;
unsigned long flags;
};
struct pm860x_rtc_pdata {
int (*sync)(unsigned int ticks);
int vrtc;
};
struct pm860x_touch_pdata {
int gpadc_prebias;
int slot_cycle;
int off_scale;
int sw_cal;
int tsi_prebias; /* time, slot */
int pen_prebias; /* time, slot */
int pen_prechg; /* time, slot */
int res_x; /* resistor of Xplate */
unsigned long flags;
};
struct pm860x_power_pdata {
unsigned fast_charge; /* charge current */
};
struct pm860x_platform_data {
struct pm860x_backlight_pdata *backlight;
struct pm860x_led_pdata *led;
struct pm860x_rtc_pdata *rtc;
struct pm860x_touch_pdata *touch;
struct pm860x_power_pdata *power;
struct regulator_init_data *regulator;
unsigned short companion_addr; /* I2C address of companion chip */
int i2c_port; /* Controlled by GI2C or PI2C */
int irq_mode; /* Clear interrupt by read/write(0/1) */
int irq_base; /* IRQ base number of 88pm860x */
int num_leds;
int num_backlights;
int num_regulators;
};
extern int pm8606_osc_enable(struct pm860x_chip *, unsigned short);
extern int pm8606_osc_disable(struct pm860x_chip *, unsigned short);
extern int pm860x_reg_read(struct i2c_client *, int);
extern int pm860x_reg_write(struct i2c_client *, int, unsigned char);
extern int pm860x_bulk_read(struct i2c_client *, int, int, unsigned char *);
extern int pm860x_bulk_write(struct i2c_client *, int, int, unsigned char *);
extern int pm860x_set_bits(struct i2c_client *, int, unsigned char,
unsigned char);
extern int pm860x_page_reg_read(struct i2c_client *, int);
extern int pm860x_page_reg_write(struct i2c_client *, int, unsigned char);
extern int pm860x_page_bulk_read(struct i2c_client *, int, int,
unsigned char *);
extern int pm860x_page_bulk_write(struct i2c_client *, int, int,
unsigned char *);
extern int pm860x_page_set_bits(struct i2c_client *, int, unsigned char,
unsigned char);
extern int pm860x_device_init(struct pm860x_chip *chip,
struct pm860x_platform_data *pdata) __devinit ;
extern void pm860x_device_exit(struct pm860x_chip *chip) __devexit ;
#endif /* __LINUX_MFD_88PM860X_H */
kernel/include/linux/mfd/Kbuild
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header-y += timpani-audio.h
header-y += msm-adie-codec.h
header-y += wcd9xxx/
kernel/include/linux/mfd/aat2870.h
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/*
* linux/include/linux/mfd/aat2870.h
*
* Copyright (c) 2011, NVIDIA Corporation.
* Author: Jin Park <jinyoungp@nvidia.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef __LINUX_MFD_AAT2870_H
#define __LINUX_MFD_AAT2870_H
#include <linux/debugfs.h>
#include <linux/i2c.h>
/* Register offsets */
#define AAT2870_BL_CH_EN 0x00
#define AAT2870_BLM 0x01
#define AAT2870_BLS 0x02
#define AAT2870_BL1 0x03
#define AAT2870_BL2 0x04
#define AAT2870_BL3 0x05
#define AAT2870_BL4 0x06
#define AAT2870_BL5 0x07
#define AAT2870_BL6 0x08
#define AAT2870_BL7 0x09
#define AAT2870_BL8 0x0A
#define AAT2870_FLR 0x0B
#define AAT2870_FM 0x0C
#define AAT2870_FS 0x0D
#define AAT2870_ALS_CFG0 0x0E
#define AAT2870_ALS_CFG1 0x0F
#define AAT2870_ALS_CFG2 0x10
#define AAT2870_AMB 0x11
#define AAT2870_ALS0 0x12
#define AAT2870_ALS1 0x13
#define AAT2870_ALS2 0x14
#define AAT2870_ALS3 0x15
#define AAT2870_ALS4 0x16
#define AAT2870_ALS5 0x17
#define AAT2870_ALS6 0x18
#define AAT2870_ALS7 0x19
#define AAT2870_ALS8 0x1A
#define AAT2870_ALS9 0x1B
#define AAT2870_ALSA 0x1C
#define AAT2870_ALSB 0x1D
#define AAT2870_ALSC 0x1E
#define AAT2870_ALSD 0x1F
#define AAT2870_ALSE 0x20
#define AAT2870_ALSF 0x21
#define AAT2870_SUB_SET 0x22
#define AAT2870_SUB_CTRL 0x23
#define AAT2870_LDO_AB 0x24
#define AAT2870_LDO_CD 0x25
#define AAT2870_LDO_EN 0x26
#define AAT2870_REG_NUM 0x27
/* Device IDs */
enum aat2870_id {
AAT2870_ID_BL,
AAT2870_ID_LDOA,
AAT2870_ID_LDOB,
AAT2870_ID_LDOC,
AAT2870_ID_LDOD
};
/* Backlight channels */
#define AAT2870_BL_CH1 0x01
#define AAT2870_BL_CH2 0x02
#define AAT2870_BL_CH3 0x04
#define AAT2870_BL_CH4 0x08
#define AAT2870_BL_CH5 0x10
#define AAT2870_BL_CH6 0x20
#define AAT2870_BL_CH7 0x40
#define AAT2870_BL_CH8 0x80
#define AAT2870_BL_CH_ALL 0xFF
/* Backlight current magnitude (mA) */
enum aat2870_current {
AAT2870_CURRENT_0_45 = 1,
AAT2870_CURRENT_0_90,
AAT2870_CURRENT_1_80,
AAT2870_CURRENT_2_70,
AAT2870_CURRENT_3_60,
AAT2870_CURRENT_4_50,
AAT2870_CURRENT_5_40,
AAT2870_CURRENT_6_30,
AAT2870_CURRENT_7_20,
AAT2870_CURRENT_8_10,
AAT2870_CURRENT_9_00,
AAT2870_CURRENT_9_90,
AAT2870_CURRENT_10_8,
AAT2870_CURRENT_11_7,
AAT2870_CURRENT_12_6,
AAT2870_CURRENT_13_5,
AAT2870_CURRENT_14_4,
AAT2870_CURRENT_15_3,
AAT2870_CURRENT_16_2,
AAT2870_CURRENT_17_1,
AAT2870_CURRENT_18_0,
AAT2870_CURRENT_18_9,
AAT2870_CURRENT_19_8,
AAT2870_CURRENT_20_7,
AAT2870_CURRENT_21_6,
AAT2870_CURRENT_22_5,
AAT2870_CURRENT_23_4,
AAT2870_CURRENT_24_3,
AAT2870_CURRENT_25_2,
AAT2870_CURRENT_26_1,
AAT2870_CURRENT_27_0,
AAT2870_CURRENT_27_9
};
struct aat2870_register {
bool readable;
bool writeable;
u8 value;
};
struct aat2870_data {
struct device *dev;
struct i2c_client *client;
struct mutex io_lock;
struct aat2870_register *reg_cache; /* register cache */
int en_pin; /* enable GPIO pin (if < 0, ignore this value) */
bool is_enable;
/* init and uninit for platform specified */
int (*init)(struct aat2870_data *aat2870);
void (*uninit)(struct aat2870_data *aat2870);
/* i2c io funcntions */
int (*read)(struct aat2870_data *aat2870, u8 addr, u8 *val);
int (*write)(struct aat2870_data *aat2870, u8 addr, u8 val);
int (*update)(struct aat2870_data *aat2870, u8 addr, u8 mask, u8 val);
/* for debugfs */
struct dentry *dentry_root;
struct dentry *dentry_reg;
};
struct aat2870_subdev_info {
int id;
const char *name;
void *platform_data;
};
struct aat2870_platform_data {
int en_pin; /* enable GPIO pin (if < 0, ignore this value) */
struct aat2870_subdev_info *subdevs;
int num_subdevs;
/* init and uninit for platform specified */
int (*init)(struct aat2870_data *aat2870);
void (*uninit)(struct aat2870_data *aat2870);
};
struct aat2870_bl_platform_data {
/* backlight channels, default is AAT2870_BL_CH_ALL */
int channels;
/* backlight current magnitude, default is AAT2870_CURRENT_27_9 */
int max_current;
/* maximum brightness, default is 255 */
int max_brightness;
};
#endif /* __LINUX_MFD_AAT2870_H */
kernel/include/linux/mfd/abx500.h
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/*
* Copyright (C) 2007-2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* AB3100 core access functions
* Author: Linus Walleij <linus.walleij@stericsson.com>
*
* ABX500 core access functions.
* The abx500 interface is used for the Analog Baseband chip
* ab3100, ab5500, and ab8500.
*
* Author: Mattias Wallin <mattias.wallin@stericsson.com>
* Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
* Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com>
* Author: Rickard Andersson <rickard.andersson@stericsson.com>
*/
#include <linux/regulator/machine.h>
struct device;
#ifndef MFD_ABX500_H
#define MFD_ABX500_H
#define AB3100_P1A 0xc0
#define AB3100_P1B 0xc1
#define AB3100_P1C 0xc2
#define AB3100_P1D 0xc3
#define AB3100_P1E 0xc4
#define AB3100_P1F 0xc5
#define AB3100_P1G 0xc6
#define AB3100_R2A 0xc7
#define AB3100_R2B 0xc8
#define AB5500_1_0 0x20
#define AB5500_1_1 0x21
#define AB5500_2_0 0x24
/*
* AB3100, EVENTA1, A2 and A3 event register flags
* these are catenated into a single 32-bit flag in the code
* for event notification broadcasts.
*/
#define AB3100_EVENTA1_ONSWA (0x01<<16)
#define AB3100_EVENTA1_ONSWB (0x02<<16)
#define AB3100_EVENTA1_ONSWC (0x04<<16)
#define AB3100_EVENTA1_DCIO (0x08<<16)
#define AB3100_EVENTA1_OVER_TEMP (0x10<<16)
#define AB3100_EVENTA1_SIM_OFF (0x20<<16)
#define AB3100_EVENTA1_VBUS (0x40<<16)
#define AB3100_EVENTA1_VSET_USB (0x80<<16)
#define AB3100_EVENTA2_READY_TX (0x01<<8)
#define AB3100_EVENTA2_READY_RX (0x02<<8)
#define AB3100_EVENTA2_OVERRUN_ERROR (0x04<<8)
#define AB3100_EVENTA2_FRAMING_ERROR (0x08<<8)
#define AB3100_EVENTA2_CHARG_OVERCURRENT (0x10<<8)
#define AB3100_EVENTA2_MIDR (0x20<<8)
#define AB3100_EVENTA2_BATTERY_REM (0x40<<8)
#define AB3100_EVENTA2_ALARM (0x80<<8)
#define AB3100_EVENTA3_ADC_TRIG5 (0x01)
#define AB3100_EVENTA3_ADC_TRIG4 (0x02)
#define AB3100_EVENTA3_ADC_TRIG3 (0x04)
#define AB3100_EVENTA3_ADC_TRIG2 (0x08)
#define AB3100_EVENTA3_ADC_TRIGVBAT (0x10)
#define AB3100_EVENTA3_ADC_TRIGVTX (0x20)
#define AB3100_EVENTA3_ADC_TRIG1 (0x40)
#define AB3100_EVENTA3_ADC_TRIG0 (0x80)
/* AB3100, STR register flags */
#define AB3100_STR_ONSWA (0x01)
#define AB3100_STR_ONSWB (0x02)
#define AB3100_STR_ONSWC (0x04)
#define AB3100_STR_DCIO (0x08)
#define AB3100_STR_BOOT_MODE (0x10)
#define AB3100_STR_SIM_OFF (0x20)
#define AB3100_STR_BATT_REMOVAL (0x40)
#define AB3100_STR_VBUS (0x80)
/*
* AB3100 contains 8 regulators, one external regulator controller
* and a buck converter, further the LDO E and buck converter can
* have separate settings if they are in sleep mode, this is
* modeled as a separate regulator.
*/
#define AB3100_NUM_REGULATORS 10
/**
* struct ab3100
* @access_mutex: lock out concurrent accesses to the AB3100 registers
* @dev: pointer to the containing device
* @i2c_client: I2C client for this chip
* @testreg_client: secondary client for test registers
* @chip_name: name of this chip variant
* @chip_id: 8 bit chip ID for this chip variant
* @event_subscribers: event subscribers are listed here
* @startup_events: a copy of the first reading of the event registers
* @startup_events_read: whether the first events have been read
*
* This struct is PRIVATE and devices using it should NOT
* access ANY fields. It is used as a token for calling the
* AB3100 functions.
*/
struct ab3100 {
struct mutex access_mutex;
struct device *dev;
struct i2c_client *i2c_client;
struct i2c_client *testreg_client;
char chip_name[32];
u8 chip_id;
struct blocking_notifier_head event_subscribers;
u8 startup_events[3];
bool startup_events_read;
};
/**
* struct ab3100_platform_data
* Data supplied to initialize board connections to the AB3100
* @reg_constraints: regulator constraints for target board
* the order of these constraints are: LDO A, C, D, E,
* F, G, H, K, EXT and BUCK.
* @reg_initvals: initial values for the regulator registers
* plus two sleep settings for LDO E and the BUCK converter.
* exactly AB3100_NUM_REGULATORS+2 values must be sent in.
* Order: LDO A, C, E, E sleep, F, G, H, K, EXT, BUCK,
* BUCK sleep, LDO D. (LDO D need to be initialized last.)
* @external_voltage: voltage level of the external regulator.
*/
struct ab3100_platform_data {
struct regulator_init_data reg_constraints[AB3100_NUM_REGULATORS];
u8 reg_initvals[AB3100_NUM_REGULATORS+2];
int external_voltage;
};
int ab3100_event_register(struct ab3100 *ab3100,
struct notifier_block *nb);
int ab3100_event_unregister(struct ab3100 *ab3100,
struct notifier_block *nb);
/**
* struct abx500_init_setting
* Initial value of the registers for driver to use during setup.
*/
struct abx500_init_settings {
u8 bank;
u8 reg;
u8 setting;
};
/* Battery driver related data */
/*
* ADC for the battery thermistor.
* When using the ABx500_ADC_THERM_BATCTRL the battery ID resistor is combined
* with a NTC resistor to both identify the battery and to measure its
* temperature. Different phone manufactures uses different techniques to both
* identify the battery and to read its temperature.
*/
enum abx500_adc_therm {
ABx500_ADC_THERM_BATCTRL,
ABx500_ADC_THERM_BATTEMP,
};
/**
* struct abx500_res_to_temp - defines one point in a temp to res curve. To
* be used in battery packs that combines the identification resistor with a
* NTC resistor.
* @temp: battery pack temperature in Celcius
* @resist: NTC resistor net total resistance
*/
struct abx500_res_to_temp {
int temp;
int resist;
};
/**
* struct abx500_v_to_cap - Table for translating voltage to capacity
* @voltage: Voltage in mV
* @capacity: Capacity in percent
*/
struct abx500_v_to_cap {
int voltage;
int capacity;
};
/* Forward declaration */
struct abx500_fg;
/**
* struct abx500_fg_parameters - Fuel gauge algorithm parameters, in seconds
* if not specified
* @recovery_sleep_timer: Time between measurements while recovering
* @recovery_total_time: Total recovery time
* @init_timer: Measurement interval during startup
* @init_discard_time: Time we discard voltage measurement at startup
* @init_total_time: Total init time during startup
* @high_curr_time: Time current has to be high to go to recovery
* @accu_charging: FG accumulation time while charging
* @accu_high_curr: FG accumulation time in high current mode
* @high_curr_threshold: High current threshold, in mA
* @lowbat_threshold: Low battery threshold, in mV
* @overbat_threshold: Over battery threshold, in mV
* @battok_falling_th_sel0 Threshold in mV for battOk signal sel0
* Resolution in 50 mV step.
* @battok_raising_th_sel1 Threshold in mV for battOk signal sel1
* Resolution in 50 mV step.
* @user_cap_limit Capacity reported from user must be within this
* limit to be considered as sane, in percentage
* points.
* @maint_thres This is the threshold where we stop reporting
* battery full while in maintenance, in per cent
*/
struct abx500_fg_parameters {
int recovery_sleep_timer;
int recovery_total_time;
int init_timer;
int init_discard_time;
int init_total_time;
int high_curr_time;
int accu_charging;
int accu_high_curr;
int high_curr_threshold;
int lowbat_threshold;
int overbat_threshold;
int battok_falling_th_sel0;
int battok_raising_th_sel1;
int user_cap_limit;
int maint_thres;
};
/**
* struct abx500_charger_maximization - struct used by the board config.
* @use_maxi: Enable maximization for this battery type
* @maxi_chg_curr: Maximum charger current allowed
* @maxi_wait_cycles: cycles to wait before setting charger current
* @charger_curr_step delta between two charger current settings (mA)
*/
struct abx500_maxim_parameters {
bool ena_maxi;
int chg_curr;
int wait_cycles;
int charger_curr_step;
};
/**
* struct abx500_battery_type - different batteries supported
* @name: battery technology
* @resis_high: battery upper resistance limit
* @resis_low: battery lower resistance limit
* @charge_full_design: Maximum battery capacity in mAh
* @nominal_voltage: Nominal voltage of the battery in mV
* @termination_vol: max voltage upto which battery can be charged
* @termination_curr battery charging termination current in mA
* @recharge_vol battery voltage limit that will trigger a new
* full charging cycle in the case where maintenan-
* -ce charging has been disabled
* @normal_cur_lvl: charger current in normal state in mA
* @normal_vol_lvl: charger voltage in normal state in mV
* @maint_a_cur_lvl: charger current in maintenance A state in mA
* @maint_a_vol_lvl: charger voltage in maintenance A state in mV
* @maint_a_chg_timer_h: charge time in maintenance A state
* @maint_b_cur_lvl: charger current in maintenance B state in mA
* @maint_b_vol_lvl: charger voltage in maintenance B state in mV
* @maint_b_chg_timer_h: charge time in maintenance B state
* @low_high_cur_lvl: charger current in temp low/high state in mA
* @low_high_vol_lvl: charger voltage in temp low/high state in mV'
* @battery_resistance: battery inner resistance in mOhm.
* @n_r_t_tbl_elements: number of elements in r_to_t_tbl
* @r_to_t_tbl: table containing resistance to temp points
* @n_v_cap_tbl_elements: number of elements in v_to_cap_tbl
* @v_to_cap_tbl: Voltage to capacity (in %) table
* @n_batres_tbl_elements number of elements in the batres_tbl
* @batres_tbl battery internal resistance vs temperature table
*/
struct abx500_battery_type {
int name;
int resis_high;
int resis_low;
int charge_full_design;
int nominal_voltage;
int termination_vol;
int termination_curr;
int recharge_vol;
int normal_cur_lvl;
int normal_vol_lvl;
int maint_a_cur_lvl;
int maint_a_vol_lvl;
int maint_a_chg_timer_h;
int maint_b_cur_lvl;
int maint_b_vol_lvl;
int maint_b_chg_timer_h;
int low_high_cur_lvl;
int low_high_vol_lvl;
int battery_resistance;
int n_temp_tbl_elements;
struct abx500_res_to_temp *r_to_t_tbl;
int n_v_cap_tbl_elements;
struct abx500_v_to_cap *v_to_cap_tbl;
int n_batres_tbl_elements;
struct batres_vs_temp *batres_tbl;
};
/**
* struct abx500_bm_capacity_levels - abx500 capacity level data
* @critical: critical capacity level in percent
* @low: low capacity level in percent
* @normal: normal capacity level in percent
* @high: high capacity level in percent
* @full: full capacity level in percent
*/
struct abx500_bm_capacity_levels {
int critical;
int low;
int normal;
int high;
int full;
};
/**
* struct abx500_bm_charger_parameters - Charger specific parameters
* @usb_volt_max: maximum allowed USB charger voltage in mV
* @usb_curr_max: maximum allowed USB charger current in mA
* @ac_volt_max: maximum allowed AC charger voltage in mV
* @ac_curr_max: maximum allowed AC charger current in mA
*/
struct abx500_bm_charger_parameters {
int usb_volt_max;
int usb_curr_max;
int ac_volt_max;
int ac_curr_max;
};
/**
* struct abx500_bm_data - abx500 battery management data
* @temp_under under this temp, charging is stopped
* @temp_low between this temp and temp_under charging is reduced
* @temp_high between this temp and temp_over charging is reduced
* @temp_over over this temp, charging is stopped
* @temp_now present battery temperature
* @temp_interval_chg temperature measurement interval in s when charging
* @temp_interval_nochg temperature measurement interval in s when not charging
* @main_safety_tmr_h safety timer for main charger
* @usb_safety_tmr_h safety timer for usb charger
* @bkup_bat_v voltage which we charge the backup battery with
* @bkup_bat_i current which we charge the backup battery with
* @no_maintenance indicates that maintenance charging is disabled
* @abx500_adc_therm placement of thermistor, batctrl or battemp adc
* @chg_unknown_bat flag to enable charging of unknown batteries
* @enable_overshoot flag to enable VBAT overshoot control
* @auto_trig flag to enable auto adc trigger
* @fg_res resistance of FG resistor in 0.1mOhm
* @n_btypes number of elements in array bat_type
* @batt_id index of the identified battery in array bat_type
* @interval_charging charge alg cycle period time when charging (sec)
* @interval_not_charging charge alg cycle period time when not charging (sec)
* @temp_hysteresis temperature hysteresis
* @gnd_lift_resistance Battery ground to phone ground resistance (mOhm)
* @maxi: maximization parameters
* @cap_levels capacity in percent for the different capacity levels
* @bat_type table of supported battery types
* @chg_params charger parameters
* @fg_params fuel gauge parameters
*/
struct abx500_bm_data {
int temp_under;
int temp_low;
int temp_high;
int temp_over;
int temp_now;
int temp_interval_chg;
int temp_interval_nochg;
int main_safety_tmr_h;
int usb_safety_tmr_h;
int bkup_bat_v;
int bkup_bat_i;
bool no_maintenance;
bool chg_unknown_bat;
bool enable_overshoot;
bool auto_trig;
enum abx500_adc_therm adc_therm;
int fg_res;
int n_btypes;
int batt_id;
int interval_charging;
int interval_not_charging;
int temp_hysteresis;
int gnd_lift_resistance;
const struct abx500_maxim_parameters *maxi;
const struct abx500_bm_capacity_levels *cap_levels;
const struct abx500_battery_type *bat_type;
const struct abx500_bm_charger_parameters *chg_params;
const struct abx500_fg_parameters *fg_params;
};
struct abx500_chargalg_platform_data {
char **supplied_to;
size_t num_supplicants;
};
struct abx500_charger_platform_data {
char **supplied_to;
size_t num_supplicants;
bool autopower_cfg;
};
struct abx500_btemp_platform_data {
char **supplied_to;
size_t num_supplicants;
};
struct abx500_fg_platform_data {
char **supplied_to;
size_t num_supplicants;
};
struct abx500_bm_plat_data {
struct abx500_bm_data *battery;
struct abx500_charger_platform_data *charger;
struct abx500_btemp_platform_data *btemp;
struct abx500_fg_platform_data *fg;
struct abx500_chargalg_platform_data *chargalg;
};
int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg,
u8 value);
int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg,
u8 *value);
int abx500_get_register_page_interruptible(struct device *dev, u8 bank,
u8 first_reg, u8 *regvals, u8 numregs);
int abx500_set_register_page_interruptible(struct device *dev, u8 bank,
u8 first_reg, u8 *regvals, u8 numregs);
/**
* abx500_mask_and_set_register_inerruptible() - Modifies selected bits of a
* target register
*
* @dev: The AB sub device.
* @bank: The i2c bank number.
* @bitmask: The bit mask to use.
* @bitvalues: The new bit values.
*
* Updates the value of an AB register:
* value -> ((value & ~bitmask) | (bitvalues & bitmask))
*/
int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank,
u8 reg, u8 bitmask, u8 bitvalues);
int abx500_get_chip_id(struct device *dev);
int abx500_event_registers_startup_state_get(struct device *dev, u8 *event);
int abx500_startup_irq_enabled(struct device *dev, unsigned int irq);
struct abx500_ops {
int (*get_chip_id) (struct device *);
int (*get_register) (struct device *, u8, u8, u8 *);
int (*set_register) (struct device *, u8, u8, u8);
int (*get_register_page) (struct device *, u8, u8, u8 *, u8);
int (*set_register_page) (struct device *, u8, u8, u8 *, u8);
int (*mask_and_set_register) (struct device *, u8, u8, u8, u8);
int (*event_registers_startup_state_get) (struct device *, u8 *);
int (*startup_irq_enabled) (struct device *, unsigned int);
};
int abx500_register_ops(struct device *core_dev, struct abx500_ops *ops);
void abx500_remove_ops(struct device *dev);
#endif
kernel/include/linux/mfd/abx500/ab5500.h
+140
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/*
* Copyright (C) ST-Ericsson 2011
*
* License Terms: GNU General Public License v2
*/
#ifndef MFD_AB5500_H
#define MFD_AB5500_H
struct device;
enum ab5500_devid {
AB5500_DEVID_ADC,
AB5500_DEVID_LEDS,
AB5500_DEVID_POWER,
AB5500_DEVID_REGULATORS,
AB5500_DEVID_SIM,
AB5500_DEVID_RTC,
AB5500_DEVID_CHARGER,
AB5500_DEVID_FUELGAUGE,
AB5500_DEVID_VIBRATOR,
AB5500_DEVID_CODEC,
AB5500_DEVID_USB,
AB5500_DEVID_OTP,
AB5500_DEVID_VIDEO,
AB5500_DEVID_DBIECI,
AB5500_DEVID_ONSWA,
AB5500_NUM_DEVICES,
};
enum ab5500_banks {
AB5500_BANK_VIT_IO_I2C_CLK_TST_OTP = 0,
AB5500_BANK_VDDDIG_IO_I2C_CLK_TST = 1,
AB5500_BANK_VDENC = 2,
AB5500_BANK_SIM_USBSIM = 3,
AB5500_BANK_LED = 4,
AB5500_BANK_ADC = 5,
AB5500_BANK_RTC = 6,
AB5500_BANK_STARTUP = 7,
AB5500_BANK_DBI_ECI = 8,
AB5500_BANK_CHG = 9,
AB5500_BANK_FG_BATTCOM_ACC = 10,
AB5500_BANK_USB = 11,
AB5500_BANK_IT = 12,
AB5500_BANK_VIBRA = 13,
AB5500_BANK_AUDIO_HEADSETUSB = 14,
AB5500_NUM_BANKS = 15,
};
enum ab5500_banks_addr {
AB5500_ADDR_VIT_IO_I2C_CLK_TST_OTP = 0x4A,
AB5500_ADDR_VDDDIG_IO_I2C_CLK_TST = 0x4B,
AB5500_ADDR_VDENC = 0x06,
AB5500_ADDR_SIM_USBSIM = 0x04,
AB5500_ADDR_LED = 0x10,
AB5500_ADDR_ADC = 0x0A,
AB5500_ADDR_RTC = 0x0F,
AB5500_ADDR_STARTUP = 0x03,
AB5500_ADDR_DBI_ECI = 0x07,
AB5500_ADDR_CHG = 0x0B,
AB5500_ADDR_FG_BATTCOM_ACC = 0x0C,
AB5500_ADDR_USB = 0x05,
AB5500_ADDR_IT = 0x0E,
AB5500_ADDR_VIBRA = 0x02,
AB5500_ADDR_AUDIO_HEADSETUSB = 0x0D,
};
/*
* Interrupt register offsets
* Bank : 0x0E
*/
#define AB5500_IT_SOURCE0_REG 0x20
#define AB5500_IT_SOURCE1_REG 0x21
#define AB5500_IT_SOURCE2_REG 0x22
#define AB5500_IT_SOURCE3_REG 0x23
#define AB5500_IT_SOURCE4_REG 0x24
#define AB5500_IT_SOURCE5_REG 0x25
#define AB5500_IT_SOURCE6_REG 0x26
#define AB5500_IT_SOURCE7_REG 0x27
#define AB5500_IT_SOURCE8_REG 0x28
#define AB5500_IT_SOURCE9_REG 0x29
#define AB5500_IT_SOURCE10_REG 0x2A
#define AB5500_IT_SOURCE11_REG 0x2B
#define AB5500_IT_SOURCE12_REG 0x2C
#define AB5500_IT_SOURCE13_REG 0x2D
#define AB5500_IT_SOURCE14_REG 0x2E
#define AB5500_IT_SOURCE15_REG 0x2F
#define AB5500_IT_SOURCE16_REG 0x30
#define AB5500_IT_SOURCE17_REG 0x31
#define AB5500_IT_SOURCE18_REG 0x32
#define AB5500_IT_SOURCE19_REG 0x33
#define AB5500_IT_SOURCE20_REG 0x34
#define AB5500_IT_SOURCE21_REG 0x35
#define AB5500_IT_SOURCE22_REG 0x36
#define AB5500_IT_SOURCE23_REG 0x37
#define AB5500_NUM_IRQ_REGS 23
/**
* struct ab5500
* @access_mutex: lock out concurrent accesses to the AB registers
* @dev: a pointer to the device struct for this chip driver
* @ab5500_irq: the analog baseband irq
* @irq_base: the platform configuration irq base for subdevices
* @chip_name: name of this chip variant
* @chip_id: 8 bit chip ID for this chip variant
* @irq_lock: a lock to protect the mask
* @abb_events: a local bit mask of the prcmu wakeup events
* @event_mask: a local copy of the mask event registers
* @last_event_mask: a copy of the last event_mask written to hardware
* @startup_events: a copy of the first reading of the event registers
* @startup_events_read: whether the first events have been read
*/
struct ab5500 {
struct mutex access_mutex;
struct device *dev;
unsigned int ab5500_irq;
unsigned int irq_base;
char chip_name[32];
u8 chip_id;
struct mutex irq_lock;
u32 abb_events;
u8 mask[AB5500_NUM_IRQ_REGS];
u8 oldmask[AB5500_NUM_IRQ_REGS];
u8 startup_events[AB5500_NUM_IRQ_REGS];
bool startup_events_read;
#ifdef CONFIG_DEBUG_FS
unsigned int debug_bank;
unsigned int debug_address;
#endif
};
struct ab5500_platform_data {
struct {unsigned int base; unsigned int count; } irq;
void *dev_data[AB5500_NUM_DEVICES];
struct abx500_init_settings *init_settings;
unsigned int init_settings_sz;
bool pm_power_off;
};
#endif /* MFD_AB5500_H */
kernel/include/linux/mfd/abx500/ab8500-bm.h
+474
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/*
* Copyright ST-Ericsson 2012.
*
* Author: Arun Murthy <arun.murthy@stericsson.com>
* Licensed under GPLv2.
*/
#ifndef _AB8500_BM_H
#define _AB8500_BM_H
#include <linux/kernel.h>
#include <linux/mfd/abx500.h>
/*
* System control 2 register offsets.
* bank = 0x02
*/
#define AB8500_MAIN_WDOG_CTRL_REG 0x01
#define AB8500_LOW_BAT_REG 0x03
#define AB8500_BATT_OK_REG 0x04
/*
* USB/ULPI register offsets
* Bank : 0x5
*/
#define AB8500_USB_LINE_STAT_REG 0x80
/*
* Charger / status register offfsets
* Bank : 0x0B
*/
#define AB8500_CH_STATUS1_REG 0x00
#define AB8500_CH_STATUS2_REG 0x01
#define AB8500_CH_USBCH_STAT1_REG 0x02
#define AB8500_CH_USBCH_STAT2_REG 0x03
#define AB8500_CH_FSM_STAT_REG 0x04
#define AB8500_CH_STAT_REG 0x05
/*
* Charger / control register offfsets
* Bank : 0x0B
*/
#define AB8500_CH_VOLT_LVL_REG 0x40
#define AB8500_CH_VOLT_LVL_MAX_REG 0x41 /*Only in Cut2.0*/
#define AB8500_CH_OPT_CRNTLVL_REG 0x42
#define AB8500_CH_OPT_CRNTLVL_MAX_REG 0x43 /*Only in Cut2.0*/
#define AB8500_CH_WD_TIMER_REG 0x50
#define AB8500_CHARG_WD_CTRL 0x51
#define AB8500_BTEMP_HIGH_TH 0x52
#define AB8500_LED_INDICATOR_PWM_CTRL 0x53
#define AB8500_LED_INDICATOR_PWM_DUTY 0x54
#define AB8500_BATT_OVV 0x55
#define AB8500_CHARGER_CTRL 0x56
#define AB8500_BAT_CTRL_CURRENT_SOURCE 0x60 /*Only in Cut2.0*/
/*
* Charger / main control register offsets
* Bank : 0x0B
*/
#define AB8500_MCH_CTRL1 0x80
#define AB8500_MCH_CTRL2 0x81
#define AB8500_MCH_IPT_CURLVL_REG 0x82
#define AB8500_CH_WD_REG 0x83
/*
* Charger / USB control register offsets
* Bank : 0x0B
*/
#define AB8500_USBCH_CTRL1_REG 0xC0
#define AB8500_USBCH_CTRL2_REG 0xC1
#define AB8500_USBCH_IPT_CRNTLVL_REG 0xC2
/*
* Gas Gauge register offsets
* Bank : 0x0C
*/
#define AB8500_GASG_CC_CTRL_REG 0x00
#define AB8500_GASG_CC_ACCU1_REG 0x01
#define AB8500_GASG_CC_ACCU2_REG 0x02
#define AB8500_GASG_CC_ACCU3_REG 0x03
#define AB8500_GASG_CC_ACCU4_REG 0x04
#define AB8500_GASG_CC_SMPL_CNTRL_REG 0x05
#define AB8500_GASG_CC_SMPL_CNTRH_REG 0x06
#define AB8500_GASG_CC_SMPL_CNVL_REG 0x07
#define AB8500_GASG_CC_SMPL_CNVH_REG 0x08
#define AB8500_GASG_CC_CNTR_AVGOFF_REG 0x09
#define AB8500_GASG_CC_OFFSET_REG 0x0A
#define AB8500_GASG_CC_NCOV_ACCU 0x10
#define AB8500_GASG_CC_NCOV_ACCU_CTRL 0x11
#define AB8500_GASG_CC_NCOV_ACCU_LOW 0x12
#define AB8500_GASG_CC_NCOV_ACCU_MED 0x13
#define AB8500_GASG_CC_NCOV_ACCU_HIGH 0x14
/*
* Interrupt register offsets
* Bank : 0x0E
*/
#define AB8500_IT_SOURCE2_REG 0x01
#define AB8500_IT_SOURCE21_REG 0x14
/*
* RTC register offsets
* Bank: 0x0F
*/
#define AB8500_RTC_BACKUP_CHG_REG 0x0C
#define AB8500_RTC_CC_CONF_REG 0x01
#define AB8500_RTC_CTRL_REG 0x0B
/*
* OTP register offsets
* Bank : 0x15
*/
#define AB8500_OTP_CONF_15 0x0E
/* GPADC constants from AB8500 spec, UM0836 */
#define ADC_RESOLUTION 1024
#define ADC_CH_MAIN_MIN 0
#define ADC_CH_MAIN_MAX 20030
#define ADC_CH_VBUS_MIN 0
#define ADC_CH_VBUS_MAX 20030
#define ADC_CH_VBAT_MIN 2300
#define ADC_CH_VBAT_MAX 4800
#define ADC_CH_BKBAT_MIN 0
#define ADC_CH_BKBAT_MAX 3200
/* Main charge i/p current */
#define MAIN_CH_IP_CUR_0P9A 0x80
#define MAIN_CH_IP_CUR_1P0A 0x90
#define MAIN_CH_IP_CUR_1P1A 0xA0
#define MAIN_CH_IP_CUR_1P2A 0xB0
#define MAIN_CH_IP_CUR_1P3A 0xC0
#define MAIN_CH_IP_CUR_1P4A 0xD0
#define MAIN_CH_IP_CUR_1P5A 0xE0
/* ChVoltLevel */
#define CH_VOL_LVL_3P5 0x00
#define CH_VOL_LVL_4P0 0x14
#define CH_VOL_LVL_4P05 0x16
#define CH_VOL_LVL_4P1 0x1B
#define CH_VOL_LVL_4P15 0x20
#define CH_VOL_LVL_4P2 0x25
#define CH_VOL_LVL_4P6 0x4D
/* ChOutputCurrentLevel */
#define CH_OP_CUR_LVL_0P1 0x00
#define CH_OP_CUR_LVL_0P2 0x01
#define CH_OP_CUR_LVL_0P3 0x02
#define CH_OP_CUR_LVL_0P4 0x03
#define CH_OP_CUR_LVL_0P5 0x04
#define CH_OP_CUR_LVL_0P6 0x05
#define CH_OP_CUR_LVL_0P7 0x06
#define CH_OP_CUR_LVL_0P8 0x07
#define CH_OP_CUR_LVL_0P9 0x08
#define CH_OP_CUR_LVL_1P4 0x0D
#define CH_OP_CUR_LVL_1P5 0x0E
#define CH_OP_CUR_LVL_1P6 0x0F
/* BTEMP High thermal limits */
#define BTEMP_HIGH_TH_57_0 0x00
#define BTEMP_HIGH_TH_52 0x01
#define BTEMP_HIGH_TH_57_1 0x02
#define BTEMP_HIGH_TH_62 0x03
/* current is mA */
#define USB_0P1A 100
#define USB_0P2A 200
#define USB_0P3A 300
#define USB_0P4A 400
#define USB_0P5A 500
#define LOW_BAT_3P1V 0x20
#define LOW_BAT_2P3V 0x00
#define LOW_BAT_RESET 0x01
#define LOW_BAT_ENABLE 0x01
/* Backup battery constants */
#define BUP_ICH_SEL_50UA 0x00
#define BUP_ICH_SEL_150UA 0x04
#define BUP_ICH_SEL_300UA 0x08
#define BUP_ICH_SEL_700UA 0x0C
#define BUP_VCH_SEL_2P5V 0x00
#define BUP_VCH_SEL_2P6V 0x01
#define BUP_VCH_SEL_2P8V 0x02
#define BUP_VCH_SEL_3P1V 0x03
/* Battery OVV constants */
#define BATT_OVV_ENA 0x02
#define BATT_OVV_TH_3P7 0x00
#define BATT_OVV_TH_4P75 0x01
/* A value to indicate over voltage */
#define BATT_OVV_VALUE 4750
/* VBUS OVV constants */
#define VBUS_OVV_SELECT_MASK 0x78
#define VBUS_OVV_SELECT_5P6V 0x00
#define VBUS_OVV_SELECT_5P7V 0x08
#define VBUS_OVV_SELECT_5P8V 0x10
#define VBUS_OVV_SELECT_5P9V 0x18
#define VBUS_OVV_SELECT_6P0V 0x20
#define VBUS_OVV_SELECT_6P1V 0x28
#define VBUS_OVV_SELECT_6P2V 0x30
#define VBUS_OVV_SELECT_6P3V 0x38
#define VBUS_AUTO_IN_CURR_LIM_ENA 0x04
/* Fuel Gauge constants */
#define RESET_ACCU 0x02
#define READ_REQ 0x01
#define CC_DEEP_SLEEP_ENA 0x02
#define CC_PWR_UP_ENA 0x01
#define CC_SAMPLES_40 0x28
#define RD_NCONV_ACCU_REQ 0x01
#define CC_CALIB 0x08
#define CC_INTAVGOFFSET_ENA 0x10
#define CC_MUXOFFSET 0x80
#define CC_INT_CAL_N_AVG_MASK 0x60
#define CC_INT_CAL_SAMPLES_16 0x40
#define CC_INT_CAL_SAMPLES_8 0x20
#define CC_INT_CAL_SAMPLES_4 0x00
/* RTC constants */
#define RTC_BUP_CH_ENA 0x10
/* BatCtrl Current Source Constants */
#define BAT_CTRL_7U_ENA 0x01
#define BAT_CTRL_20U_ENA 0x02
#define BAT_CTRL_CMP_ENA 0x04
#define FORCE_BAT_CTRL_CMP_HIGH 0x08
#define BAT_CTRL_PULL_UP_ENA 0x10
/* Battery type */
#define BATTERY_UNKNOWN 00
/**
* struct res_to_temp - defines one point in a temp to res curve. To
* be used in battery packs that combines the identification resistor with a
* NTC resistor.
* @temp: battery pack temperature in Celcius
* @resist: NTC resistor net total resistance
*/
struct res_to_temp {
int temp;
int resist;
};
/**
* struct batres_vs_temp - defines one point in a temp vs battery internal
* resistance curve.
* @temp: battery pack temperature in Celcius
* @resist: battery internal reistance in mOhm
*/
struct batres_vs_temp {
int temp;
int resist;
};
/* Forward declaration */
struct ab8500_fg;
/**
* struct ab8500_fg_parameters - Fuel gauge algorithm parameters, in seconds
* if not specified
* @recovery_sleep_timer: Time between measurements while recovering
* @recovery_total_time: Total recovery time
* @init_timer: Measurement interval during startup
* @init_discard_time: Time we discard voltage measurement at startup
* @init_total_time: Total init time during startup
* @high_curr_time: Time current has to be high to go to recovery
* @accu_charging: FG accumulation time while charging
* @accu_high_curr: FG accumulation time in high current mode
* @high_curr_threshold: High current threshold, in mA
* @lowbat_threshold: Low battery threshold, in mV
* @battok_falling_th_sel0 Threshold in mV for battOk signal sel0
* Resolution in 50 mV step.
* @battok_raising_th_sel1 Threshold in mV for battOk signal sel1
* Resolution in 50 mV step.
* @user_cap_limit Capacity reported from user must be within this
* limit to be considered as sane, in percentage
* points.
* @maint_thres This is the threshold where we stop reporting
* battery full while in maintenance, in per cent
*/
struct ab8500_fg_parameters {
int recovery_sleep_timer;
int recovery_total_time;
int init_timer;
int init_discard_time;
int init_total_time;
int high_curr_time;
int accu_charging;
int accu_high_curr;
int high_curr_threshold;
int lowbat_threshold;
int battok_falling_th_sel0;
int battok_raising_th_sel1;
int user_cap_limit;
int maint_thres;
};
/**
* struct ab8500_charger_maximization - struct used by the board config.
* @use_maxi: Enable maximization for this battery type
* @maxi_chg_curr: Maximum charger current allowed
* @maxi_wait_cycles: cycles to wait before setting charger current
* @charger_curr_step delta between two charger current settings (mA)
*/
struct ab8500_maxim_parameters {
bool ena_maxi;
int chg_curr;
int wait_cycles;
int charger_curr_step;
};
/**
* struct ab8500_bm_capacity_levels - ab8500 capacity level data
* @critical: critical capacity level in percent
* @low: low capacity level in percent
* @normal: normal capacity level in percent
* @high: high capacity level in percent
* @full: full capacity level in percent
*/
struct ab8500_bm_capacity_levels {
int critical;
int low;
int normal;
int high;
int full;
};
/**
* struct ab8500_bm_charger_parameters - Charger specific parameters
* @usb_volt_max: maximum allowed USB charger voltage in mV
* @usb_curr_max: maximum allowed USB charger current in mA
* @ac_volt_max: maximum allowed AC charger voltage in mV
* @ac_curr_max: maximum allowed AC charger current in mA
*/
struct ab8500_bm_charger_parameters {
int usb_volt_max;
int usb_curr_max;
int ac_volt_max;
int ac_curr_max;
};
/**
* struct ab8500_bm_data - ab8500 battery management data
* @temp_under under this temp, charging is stopped
* @temp_low between this temp and temp_under charging is reduced
* @temp_high between this temp and temp_over charging is reduced
* @temp_over over this temp, charging is stopped
* @temp_interval_chg temperature measurement interval in s when charging
* @temp_interval_nochg temperature measurement interval in s when not charging
* @main_safety_tmr_h safety timer for main charger
* @usb_safety_tmr_h safety timer for usb charger
* @bkup_bat_v voltage which we charge the backup battery with
* @bkup_bat_i current which we charge the backup battery with
* @no_maintenance indicates that maintenance charging is disabled
* @adc_therm placement of thermistor, batctrl or battemp adc
* @chg_unknown_bat flag to enable charging of unknown batteries
* @enable_overshoot flag to enable VBAT overshoot control
* @fg_res resistance of FG resistor in 0.1mOhm
* @n_btypes number of elements in array bat_type
* @batt_id index of the identified battery in array bat_type
* @interval_charging charge alg cycle period time when charging (sec)
* @interval_not_charging charge alg cycle period time when not charging (sec)
* @temp_hysteresis temperature hysteresis
* @gnd_lift_resistance Battery ground to phone ground resistance (mOhm)
* @maxi: maximization parameters
* @cap_levels capacity in percent for the different capacity levels
* @bat_type table of supported battery types
* @chg_params charger parameters
* @fg_params fuel gauge parameters
*/
struct ab8500_bm_data {
int temp_under;
int temp_low;
int temp_high;
int temp_over;
int temp_interval_chg;
int temp_interval_nochg;
int main_safety_tmr_h;
int usb_safety_tmr_h;
int bkup_bat_v;
int bkup_bat_i;
bool no_maintenance;
bool chg_unknown_bat;
bool enable_overshoot;
enum abx500_adc_therm adc_therm;
int fg_res;
int n_btypes;
int batt_id;
int interval_charging;
int interval_not_charging;
int temp_hysteresis;
int gnd_lift_resistance;
const struct ab8500_maxim_parameters *maxi;
const struct ab8500_bm_capacity_levels *cap_levels;
const struct ab8500_bm_charger_parameters *chg_params;
const struct ab8500_fg_parameters *fg_params;
};
struct ab8500_charger_platform_data {
char **supplied_to;
size_t num_supplicants;
bool autopower_cfg;
};
struct ab8500_btemp_platform_data {
char **supplied_to;
size_t num_supplicants;
};
struct ab8500_fg_platform_data {
char **supplied_to;
size_t num_supplicants;
};
struct ab8500_chargalg_platform_data {
char **supplied_to;
size_t num_supplicants;
};
struct ab8500_btemp;
struct ab8500_gpadc;
struct ab8500_fg;
#ifdef CONFIG_AB8500_BM
void ab8500_fg_reinit(void);
void ab8500_charger_usb_state_changed(u8 bm_usb_state, u16 mA);
struct ab8500_btemp *ab8500_btemp_get(void);
int ab8500_btemp_get_batctrl_temp(struct ab8500_btemp *btemp);
struct ab8500_fg *ab8500_fg_get(void);
int ab8500_fg_inst_curr_blocking(struct ab8500_fg *dev);
int ab8500_fg_inst_curr_start(struct ab8500_fg *di);
int ab8500_fg_inst_curr_finalize(struct ab8500_fg *di, int *res);
int ab8500_fg_inst_curr_done(struct ab8500_fg *di);
#else
int ab8500_fg_inst_curr_done(struct ab8500_fg *di)
{
}
static void ab8500_fg_reinit(void)
{
}
static void ab8500_charger_usb_state_changed(u8 bm_usb_state, u16 mA)
{
}
static struct ab8500_btemp *ab8500_btemp_get(void)
{
return NULL;
}
static int ab8500_btemp_get_batctrl_temp(struct ab8500_btemp *btemp)
{
return 0;
}
struct ab8500_fg *ab8500_fg_get(void)
{
return NULL;
}
static int ab8500_fg_inst_curr_blocking(struct ab8500_fg *dev)
{
return -ENODEV;
}
static inline int ab8500_fg_inst_curr_start(struct ab8500_fg *di)
{
return -ENODEV;
}
static inline int ab8500_fg_inst_curr_finalize(struct ab8500_fg *di, int *res)
{
return -ENODEV;
}
#endif
#endif /* _AB8500_BM_H */
kernel/include/linux/mfd/abx500/ab8500-gpadc.h
+35
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@@ -0,0 +1,35 @@
/*
* Copyright (C) 2010 ST-Ericsson SA
* Licensed under GPLv2.
*
* Author: Arun R Murthy <arun.murthy@stericsson.com>
* Author: Daniel Willerud <daniel.willerud@stericsson.com>
*/
#ifndef _AB8500_GPADC_H
#define _AB8500_GPADC_H
/* GPADC source: From datasheet(ADCSwSel[4:0] in GPADCCtrl2) */
#define BAT_CTRL 0x01
#define BTEMP_BALL 0x02
#define MAIN_CHARGER_V 0x03
#define ACC_DETECT1 0x04
#define ACC_DETECT2 0x05
#define ADC_AUX1 0x06
#define ADC_AUX2 0x07
#define MAIN_BAT_V 0x08
#define VBUS_V 0x09
#define MAIN_CHARGER_C 0x0A
#define USB_CHARGER_C 0x0B
#define BK_BAT_V 0x0C
#define DIE_TEMP 0x0D
struct ab8500_gpadc;
struct ab8500_gpadc *ab8500_gpadc_get(char *name);
int ab8500_gpadc_convert(struct ab8500_gpadc *gpadc, u8 channel);
int ab8500_gpadc_read_raw(struct ab8500_gpadc *gpadc, u8 channel);
int ab8500_gpadc_ad_to_voltage(struct ab8500_gpadc *gpadc,
u8 channel, int ad_value);
#endif /* _AB8500_GPADC_H */
kernel/include/linux/mfd/abx500/ab8500-gpio.h
+23
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/*
* Copyright ST-Ericsson 2010.
*
* Author: Bibek Basu <bibek.basu@stericsson.com>
* Licensed under GPLv2.
*/
#ifndef _AB8500_GPIO_H
#define _AB8500_GPIO_H
/*
* Platform data to register a block: only the initial gpio/irq number.
* Array sizes are large enough to contain all AB8500 and AB9540 GPIO
* registers.
*/
struct ab8500_gpio_platform_data {
int gpio_base;
u32 irq_base;
u8 config_reg[8];
};
#endif /* _AB8500_GPIO_H */
kernel/include/linux/mfd/abx500/ab8500-sysctrl.h
+297
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/*
* Copyright (C) ST-Ericsson SA 2010
* Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> for ST Ericsson.
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef __AB8500_SYSCTRL_H
#define __AB8500_SYSCTRL_H
#include <linux/bitops.h>
#ifdef CONFIG_AB8500_CORE
int ab8500_sysctrl_read(u16 reg, u8 *value);
int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value);
#else
static inline int ab8500_sysctrl_read(u16 reg, u8 *value)
{
return 0;
}
static inline int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value)
{
return 0;
}
#endif /* CONFIG_AB8500_CORE */
static inline int ab8500_sysctrl_set(u16 reg, u8 bits)
{
return ab8500_sysctrl_write(reg, bits, bits);
}
static inline int ab8500_sysctrl_clear(u16 reg, u8 bits)
{
return ab8500_sysctrl_write(reg, bits, 0);
}
/* Registers */
#define AB8500_TURNONSTATUS 0x100
#define AB8500_RESETSTATUS 0x101
#define AB8500_PONKEY1PRESSSTATUS 0x102
#define AB8500_SYSCLKREQSTATUS 0x142
#define AB8500_STW4500CTRL1 0x180
#define AB8500_STW4500CTRL2 0x181
#define AB8500_STW4500CTRL3 0x200
#define AB8500_MAINWDOGCTRL 0x201
#define AB8500_MAINWDOGTIMER 0x202
#define AB8500_LOWBAT 0x203
#define AB8500_BATTOK 0x204
#define AB8500_SYSCLKTIMER 0x205
#define AB8500_SMPSCLKCTRL 0x206
#define AB8500_SMPSCLKSEL1 0x207
#define AB8500_SMPSCLKSEL2 0x208
#define AB8500_SMPSCLKSEL3 0x209
#define AB8500_SYSULPCLKCONF 0x20A
#define AB8500_SYSULPCLKCTRL1 0x20B
#define AB8500_SYSCLKCTRL 0x20C
#define AB8500_SYSCLKREQ1VALID 0x20D
#define AB8500_SYSTEMCTRLSUP 0x20F
#define AB8500_SYSCLKREQ1RFCLKBUF 0x210
#define AB8500_SYSCLKREQ2RFCLKBUF 0x211
#define AB8500_SYSCLKREQ3RFCLKBUF 0x212
#define AB8500_SYSCLKREQ4RFCLKBUF 0x213
#define AB8500_SYSCLKREQ5RFCLKBUF 0x214
#define AB8500_SYSCLKREQ6RFCLKBUF 0x215
#define AB8500_SYSCLKREQ7RFCLKBUF 0x216
#define AB8500_SYSCLKREQ8RFCLKBUF 0x217
#define AB8500_DITHERCLKCTRL 0x220
#define AB8500_SWATCTRL 0x230
#define AB8500_HIQCLKCTRL 0x232
#define AB8500_VSIMSYSCLKCTRL 0x233
#define AB9540_SYSCLK12BUFCTRL 0x234
#define AB9540_SYSCLK12CONFCTRL 0x235
#define AB9540_SYSCLK12BUFCTRL2 0x236
#define AB9540_SYSCLK12BUF1VALID 0x237
#define AB9540_SYSCLK12BUF2VALID 0x238
#define AB9540_SYSCLK12BUF3VALID 0x239
#define AB9540_SYSCLK12BUF4VALID 0x23A
/* Bits */
#define AB8500_TURNONSTATUS_PORNVBAT BIT(0)
#define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1)
#define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2)
#define AB8500_TURNONSTATUS_RTCALARM BIT(3)
#define AB8500_TURNONSTATUS_MAINCHDET BIT(4)
#define AB8500_TURNONSTATUS_VBUSDET BIT(5)
#define AB8500_TURNONSTATUS_USBIDDETECT BIT(6)
#define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0)
#define AB8500_RESETSTATUS_SWRESETN4500NSTATUS BIT(2)
#define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_MASK 0x7F
#define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_SHIFT 0
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ1STATUS BIT(0)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ2STATUS BIT(1)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ3STATUS BIT(2)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ4STATUS BIT(3)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ5STATUS BIT(4)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ6STATUS BIT(5)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ7STATUS BIT(6)
#define AB8500_SYSCLKREQSTATUS_SYSCLKREQ8STATUS BIT(7)
#define AB8500_STW4500CTRL1_SWOFF BIT(0)
#define AB8500_STW4500CTRL1_SWRESET4500N BIT(1)
#define AB8500_STW4500CTRL1_THDB8500SWOFF BIT(2)
#define AB8500_STW4500CTRL2_RESETNVAUX1VALID BIT(0)
#define AB8500_STW4500CTRL2_RESETNVAUX2VALID BIT(1)
#define AB8500_STW4500CTRL2_RESETNVAUX3VALID BIT(2)
#define AB8500_STW4500CTRL2_RESETNVMODVALID BIT(3)
#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY1VALID BIT(4)
#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY2VALID BIT(5)
#define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY3VALID BIT(6)
#define AB8500_STW4500CTRL2_RESETNVSMPS1VALID BIT(7)
#define AB8500_STW4500CTRL3_CLK32KOUT2DIS BIT(0)
#define AB8500_STW4500CTRL3_RESETAUDN BIT(1)
#define AB8500_STW4500CTRL3_RESETDENCN BIT(2)
#define AB8500_STW4500CTRL3_THSDENA BIT(3)
#define AB8500_MAINWDOGCTRL_MAINWDOGENA BIT(0)
#define AB8500_MAINWDOGCTRL_MAINWDOGKICK BIT(1)
#define AB8500_MAINWDOGCTRL_WDEXPTURNONVALID BIT(4)
#define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_MASK 0x7F
#define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_SHIFT 0
#define AB8500_LOWBAT_LOWBATENA BIT(0)
#define AB8500_LOWBAT_LOWBAT_MASK 0x7E
#define AB8500_LOWBAT_LOWBAT_SHIFT 1
#define AB8500_BATTOK_BATTOKSEL0THF_MASK 0x0F
#define AB8500_BATTOK_BATTOKSEL0THF_SHIFT 0
#define AB8500_BATTOK_BATTOKSEL1THF_MASK 0xF0
#define AB8500_BATTOK_BATTOKSEL1THF_SHIFT 4
#define AB8500_SYSCLKTIMER_SYSCLKTIMER_MASK 0x0F
#define AB8500_SYSCLKTIMER_SYSCLKTIMER_SHIFT 0
#define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_MASK 0xF0
#define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_SHIFT 4
#define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_MASK 0x03
#define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_SHIFT 0
#define AB8500_SMPSCLKCTRL_3M2CLKINTENA BIT(2)
#define AB8500_SMPSCLKSEL1_VARMCLKSEL_MASK 0x07
#define AB8500_SMPSCLKSEL1_VARMCLKSEL_SHIFT 0
#define AB8500_SMPSCLKSEL1_VAPECLKSEL_MASK 0x38
#define AB8500_SMPSCLKSEL1_VAPECLKSEL_SHIFT 3
#define AB8500_SMPSCLKSEL2_VMODCLKSEL_MASK 0x07
#define AB8500_SMPSCLKSEL2_VMODCLKSEL_SHIFT 0
#define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_MASK 0x38
#define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_SHIFT 3
#define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_MASK 0x07
#define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_SHIFT 0
#define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_MASK 0x38
#define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_SHIFT 3
#define AB8500_SYSULPCLKCONF_ULPCLKCONF_MASK 0x03
#define AB8500_SYSULPCLKCONF_ULPCLKCONF_SHIFT 0
#define AB8500_SYSULPCLKCONF_CLK27MHZSTRE BIT(2)
#define AB8500_SYSULPCLKCONF_TVOUTCLKDELN BIT(3)
#define AB8500_SYSULPCLKCONF_TVOUTCLKINV BIT(4)
#define AB8500_SYSULPCLKCONF_ULPCLKSTRE BIT(5)
#define AB8500_SYSULPCLKCONF_CLK27MHZBUFENA BIT(6)
#define AB8500_SYSULPCLKCONF_CLK27MHZPDENA BIT(7)
#define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK 0x03
#define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT 0
#define AB8500_SYSULPCLKCTRL1_ULPCLKREQ BIT(2)
#define AB8500_SYSULPCLKCTRL1_4500SYSCLKREQ BIT(3)
#define AB8500_SYSULPCLKCTRL1_AUDIOCLKENA BIT(4)
#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ BIT(5)
#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ BIT(6)
#define AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ BIT(7)
#define AB8500_SYSCLKCTRL_TVOUTPLLENA BIT(0)
#define AB8500_SYSCLKCTRL_TVOUTCLKENA BIT(1)
#define AB8500_SYSCLKCTRL_USBCLKENA BIT(2)
#define AB8500_SYSCLKREQ1VALID_SYSCLKREQ1VALID BIT(0)
#define AB8500_SYSCLKREQ1VALID_ULPCLKREQ1VALID BIT(1)
#define AB8500_SYSCLKREQ1VALID_USBSYSCLKREQ1VALID BIT(2)
#define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_MASK 0x03
#define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_SHIFT 0
#define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_MASK 0x0C
#define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_SHIFT 2
#define AB8500_SYSTEMCTRLSUP_INTDB8500NOD BIT(4)
#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF4 BIT(4)
#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF2 BIT(2)
#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF3 BIT(3)
#define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF4 BIT(4)
#define AB8500_DITHERCLKCTRL_VARMDITHERENA BIT(0)
#define AB8500_DITHERCLKCTRL_VSMPS3DITHERENA BIT(1)
#define AB8500_DITHERCLKCTRL_VSMPS1DITHERENA BIT(2)
#define AB8500_DITHERCLKCTRL_VSMPS2DITHERENA BIT(3)
#define AB8500_DITHERCLKCTRL_VMODDITHERENA BIT(4)
#define AB8500_DITHERCLKCTRL_VAPEDITHERENA BIT(5)
#define AB8500_DITHERCLKCTRL_DITHERDEL_MASK 0xC0
#define AB8500_DITHERCLKCTRL_DITHERDEL_SHIFT 6
#define AB8500_SWATCTRL_UPDATERF BIT(0)
#define AB8500_SWATCTRL_SWATENABLE BIT(1)
#define AB8500_SWATCTRL_RFOFFTIMER_MASK 0x1C
#define AB8500_SWATCTRL_RFOFFTIMER_SHIFT 2
#define AB8500_SWATCTRL_SWATBIT5 BIT(6)
#define AB8500_HIQCLKCTRL_SYSCLKREQ1HIQENAVALID BIT(0)
#define AB8500_HIQCLKCTRL_SYSCLKREQ2HIQENAVALID BIT(1)
#define AB8500_HIQCLKCTRL_SYSCLKREQ3HIQENAVALID BIT(2)
#define AB8500_HIQCLKCTRL_SYSCLKREQ4HIQENAVALID BIT(3)
#define AB8500_HIQCLKCTRL_SYSCLKREQ5HIQENAVALID BIT(4)
#define AB8500_HIQCLKCTRL_SYSCLKREQ6HIQENAVALID BIT(5)
#define AB8500_HIQCLKCTRL_SYSCLKREQ7HIQENAVALID BIT(6)
#define AB8500_HIQCLKCTRL_SYSCLKREQ8HIQENAVALID BIT(7)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ1VALID BIT(0)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ2VALID BIT(1)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ3VALID BIT(2)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ4VALID BIT(3)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ5VALID BIT(4)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ6VALID BIT(5)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID BIT(6)
#define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID BIT(7)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1ENA BIT(0)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2ENA BIT(1)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3ENA BIT(2)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4ENA BIT(3)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFENA_MASK 0x0F
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF1STRE BIT(4)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF2STRE BIT(5)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF3STRE BIT(6)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUF4STRE BIT(7)
#define AB9540_SYSCLK12BUFCTRL_SYSCLK12BUFSTRE_MASK 0xF0
#define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0)
#define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1)
#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_MASK 0x0C
#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_SHIFT 2
#define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4)
#define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5)
#define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6)
#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF1PDENA BIT(0)
#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF2PDENA BIT(1)
#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF3PDENA BIT(2)
#define AB9540_SYSCLK12BUFCTRL2_SYSCLK12BUF4PDENA BIT(3)
#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_MASK 0xFF
#define AB9540_SYSCLK12BUF1VALID_SYSCLK12BUF1VALID_SHIFT 0
#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_MASK 0xFF
#define AB9540_SYSCLK12BUF2VALID_SYSCLK12BUF2VALID_SHIFT 0
#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_MASK 0xFF
#define AB9540_SYSCLK12BUF3VALID_SYSCLK12BUF3VALID_SHIFT 0
#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_MASK 0xFF
#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_SHIFT 0
#endif /* __AB8500_SYSCTRL_H */
kernel/include/linux/mfd/abx500/ab8500.h
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/*
* Copyright (C) ST-Ericsson SA 2010
*
* License Terms: GNU General Public License v2
* Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
*/
#ifndef MFD_AB8500_H
#define MFD_AB8500_H
#include <linux/mutex.h>
struct device;
/*
* AB IC versions
*
* AB8500_VERSION_AB8500 should be 0xFF but will never be read as need a
* non-supported multi-byte I2C access via PRCMU. Set to 0x00 to ease the
* print of version string.
*/
enum ab8500_version {
AB8500_VERSION_AB8500 = 0x0,
AB8500_VERSION_AB8505 = 0x1,
AB8500_VERSION_AB9540 = 0x2,
AB8500_VERSION_AB8540 = 0x3,
AB8500_VERSION_UNDEFINED,
};
/* AB8500 CIDs*/
#define AB8500_CUTEARLY 0x00
#define AB8500_CUT1P0 0x10
#define AB8500_CUT1P1 0x11
#define AB8500_CUT2P0 0x20
#define AB8500_CUT3P0 0x30
#define AB8500_CUT3P3 0x33
/*
* AB8500 bank addresses
*/
#define AB8500_SYS_CTRL1_BLOCK 0x1
#define AB8500_SYS_CTRL2_BLOCK 0x2
#define AB8500_REGU_CTRL1 0x3
#define AB8500_REGU_CTRL2 0x4
#define AB8500_USB 0x5
#define AB8500_TVOUT 0x6
#define AB8500_DBI 0x7
#define AB8500_ECI_AV_ACC 0x8
#define AB8500_RESERVED 0x9
#define AB8500_GPADC 0xA
#define AB8500_CHARGER 0xB
#define AB8500_GAS_GAUGE 0xC
#define AB8500_AUDIO 0xD
#define AB8500_INTERRUPT 0xE
#define AB8500_RTC 0xF
#define AB8500_MISC 0x10
#define AB8500_DEVELOPMENT 0x11
#define AB8500_DEBUG 0x12
#define AB8500_PROD_TEST 0x13
#define AB8500_OTP_EMUL 0x15
/*
* Interrupts
* Values used to index into array ab8500_irq_regoffset[] defined in
* drivers/mdf/ab8500-core.c
*/
/* Definitions for AB8500 and AB9540 */
/* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0 /* not 8505/9540 */
#define AB8500_INT_UN_PLUG_TV_DET 1 /* not 8505/9540 */
#define AB8500_INT_PLUG_TV_DET 2 /* not 8505/9540 */
#define AB8500_INT_TEMP_WARM 3
#define AB8500_INT_PON_KEY2DB_F 4
#define AB8500_INT_PON_KEY2DB_R 5
#define AB8500_INT_PON_KEY1DB_F 6
#define AB8500_INT_PON_KEY1DB_R 7
/* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
#define AB8500_INT_BATT_OVV 8
#define AB8500_INT_MAIN_CH_UNPLUG_DET 10 /* not 8505 */
#define AB8500_INT_MAIN_CH_PLUG_DET 11 /* not 8505 */
#define AB8500_INT_VBUS_DET_F 14
#define AB8500_INT_VBUS_DET_R 15
/* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
#define AB8500_INT_VBUS_CH_DROP_END 16
#define AB8500_INT_RTC_60S 17
#define AB8500_INT_RTC_ALARM 18
#define AB8500_INT_BAT_CTRL_INDB 20
#define AB8500_INT_CH_WD_EXP 21
#define AB8500_INT_VBUS_OVV 22
#define AB8500_INT_MAIN_CH_DROP_END 23 /* not 8505/9540 */
/* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
#define AB8500_INT_CCN_CONV_ACC 24
#define AB8500_INT_INT_AUD 25
#define AB8500_INT_CCEOC 26
#define AB8500_INT_CC_INT_CALIB 27
#define AB8500_INT_LOW_BAT_F 28
#define AB8500_INT_LOW_BAT_R 29
#define AB8500_INT_BUP_CHG_NOT_OK 30
#define AB8500_INT_BUP_CHG_OK 31
/* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
#define AB8500_INT_GP_HW_ADC_CONV_END 32 /* not 8505 */
#define AB8500_INT_ACC_DETECT_1DB_F 33
#define AB8500_INT_ACC_DETECT_1DB_R 34
#define AB8500_INT_ACC_DETECT_22DB_F 35
#define AB8500_INT_ACC_DETECT_22DB_R 36
#define AB8500_INT_ACC_DETECT_21DB_F 37
#define AB8500_INT_ACC_DETECT_21DB_R 38
#define AB8500_INT_GP_SW_ADC_CONV_END 39
/* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
#define AB8500_INT_GPIO6R 40 /* not 8505/9540 */
#define AB8500_INT_GPIO7R 41 /* not 8505/9540 */
#define AB8500_INT_GPIO8R 42 /* not 8505/9540 */
#define AB8500_INT_GPIO9R 43 /* not 8505/9540 */
#define AB8500_INT_GPIO10R 44
#define AB8500_INT_GPIO11R 45
#define AB8500_INT_GPIO12R 46 /* not 8505 */
#define AB8500_INT_GPIO13R 47
/* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
#define AB8500_INT_GPIO24R 48 /* not 8505 */
#define AB8500_INT_GPIO25R 49 /* not 8505 */
#define AB8500_INT_GPIO36R 50 /* not 8505/9540 */
#define AB8500_INT_GPIO37R 51 /* not 8505/9540 */
#define AB8500_INT_GPIO38R 52 /* not 8505/9540 */
#define AB8500_INT_GPIO39R 53 /* not 8505/9540 */
#define AB8500_INT_GPIO40R 54
#define AB8500_INT_GPIO41R 55
/* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
#define AB8500_INT_GPIO6F 56 /* not 8505/9540 */
#define AB8500_INT_GPIO7F 57 /* not 8505/9540 */
#define AB8500_INT_GPIO8F 58 /* not 8505/9540 */
#define AB8500_INT_GPIO9F 59 /* not 8505/9540 */
#define AB8500_INT_GPIO10F 60
#define AB8500_INT_GPIO11F 61
#define AB8500_INT_GPIO12F 62 /* not 8505 */
#define AB8500_INT_GPIO13F 63
/* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
#define AB8500_INT_GPIO24F 64 /* not 8505 */
#define AB8500_INT_GPIO25F 65 /* not 8505 */
#define AB8500_INT_GPIO36F 66 /* not 8505/9540 */
#define AB8500_INT_GPIO37F 67 /* not 8505/9540 */
#define AB8500_INT_GPIO38F 68 /* not 8505/9540 */
#define AB8500_INT_GPIO39F 69 /* not 8505/9540 */
#define AB8500_INT_GPIO40F 70
#define AB8500_INT_GPIO41F 71
/* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
#define AB8500_INT_ADP_SOURCE_ERROR 72
#define AB8500_INT_ADP_SINK_ERROR 73
#define AB8500_INT_ADP_PROBE_PLUG 74
#define AB8500_INT_ADP_PROBE_UNPLUG 75
#define AB8500_INT_ADP_SENSE_OFF 76
#define AB8500_INT_USB_PHY_POWER_ERR 78
#define AB8500_INT_USB_LINK_STATUS 79
/* ab8500_irq_regoffset[10] -> IT[Source|Latch|Mask]19 */
#define AB8500_INT_BTEMP_LOW 80
#define AB8500_INT_BTEMP_LOW_MEDIUM 81
#define AB8500_INT_BTEMP_MEDIUM_HIGH 82
#define AB8500_INT_BTEMP_HIGH 83
/* ab8500_irq_regoffset[11] -> IT[Source|Latch|Mask]20 */
#define AB8500_INT_SRP_DETECT 88
#define AB8500_INT_USB_CHARGER_NOT_OKR 89
#define AB8500_INT_ID_WAKEUP_R 90
#define AB8500_INT_ID_DET_R1R 92
#define AB8500_INT_ID_DET_R2R 93
#define AB8500_INT_ID_DET_R3R 94
#define AB8500_INT_ID_DET_R4R 95
/* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */
#define AB8500_INT_ID_WAKEUP_F 96
#define AB8500_INT_ID_DET_R1F 98
#define AB8500_INT_ID_DET_R2F 99
#define AB8500_INT_ID_DET_R3F 100
#define AB8500_INT_ID_DET_R4F 101
#define AB8500_INT_CHAUTORESTARTAFTSEC 102
#define AB8500_INT_CHSTOPBYSEC 103
/* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */
#define AB8500_INT_USB_CH_TH_PROT_F 104
#define AB8500_INT_USB_CH_TH_PROT_R 105
#define AB8500_INT_MAIN_CH_TH_PROT_F 106 /* not 8505/9540 */
#define AB8500_INT_MAIN_CH_TH_PROT_R 107 /* not 8505/9540 */
#define AB8500_INT_CHCURLIMNOHSCHIRP 109
#define AB8500_INT_CHCURLIMHSCHIRP 110
#define AB8500_INT_XTAL32K_KO 111
/* Definitions for AB9540 */
/* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */
#define AB9540_INT_GPIO50R 113
#define AB9540_INT_GPIO51R 114 /* not 8505 */
#define AB9540_INT_GPIO52R 115
#define AB9540_INT_GPIO53R 116
#define AB9540_INT_GPIO54R 117 /* not 8505 */
#define AB9540_INT_IEXT_CH_RF_BFN_R 118
#define AB9540_INT_IEXT_CH_RF_BFN_F 119
/* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */
#define AB9540_INT_GPIO50F 121
#define AB9540_INT_GPIO51F 122 /* not 8505 */
#define AB9540_INT_GPIO52F 123
#define AB9540_INT_GPIO53F 124
#define AB9540_INT_GPIO54F 125 /* not 8505 */
/*
* AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
* entire platform. This is a "compile time" constant so this must be set to
* the largest possible value that may be encountered with different AB SOCs.
* Of the currently supported AB devices, AB8500 and AB9540, it is the AB9540
* which is larger.
*/
#define AB8500_NR_IRQS 112
#define AB8505_NR_IRQS 128
#define AB9540_NR_IRQS 128
/* This is set to the roof of any AB8500 chip variant IRQ counts */
#define AB8500_MAX_NR_IRQS AB9540_NR_IRQS
#define AB8500_NUM_IRQ_REGS 14
#define AB9540_NUM_IRQ_REGS 17
/**
* struct ab8500 - ab8500 internal structure
* @dev: parent device
* @lock: read/write operations lock
* @irq_lock: genirq bus lock
* @irq: irq line
* @version: chip version id (e.g. ab8500 or ab9540)
* @chip_id: chip revision id
* @write: register write
* @write_masked: masked register write
* @read: register read
* @rx_buf: rx buf for SPI
* @tx_buf: tx buf for SPI
* @mask: cache of IRQ regs for bus lock
* @oldmask: cache of previous IRQ regs for bus lock
* @mask_size: Actual number of valid entries in mask[], oldmask[] and
* irq_reg_offset
* @irq_reg_offset: Array of offsets into IRQ registers
*/
struct ab8500 {
struct device *dev;
struct mutex lock;
struct mutex irq_lock;
int irq_base;
int irq;
enum ab8500_version version;
u8 chip_id;
int (*write)(struct ab8500 *ab8500, u16 addr, u8 data);
int (*write_masked)(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data);
int (*read)(struct ab8500 *ab8500, u16 addr);
unsigned long tx_buf[4];
unsigned long rx_buf[4];
u8 *mask;
u8 *oldmask;
int mask_size;
const int *irq_reg_offset;
};
struct regulator_reg_init;
struct regulator_init_data;
struct ab8500_gpio_platform_data;
/**
* struct ab8500_platform_data - AB8500 platform data
* @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
* @init: board-specific initialization after detection of ab8500
* @num_regulator_reg_init: number of regulator init registers
* @regulator_reg_init: regulator init registers
* @num_regulator: number of regulators
* @regulator: machine-specific constraints for regulators
*/
struct ab8500_platform_data {
int irq_base;
void (*init) (struct ab8500 *);
int num_regulator_reg_init;
struct ab8500_regulator_reg_init *regulator_reg_init;
int num_regulator;
struct regulator_init_data *regulator;
struct ab8500_gpio_platform_data *gpio;
};
extern int __devinit ab8500_init(struct ab8500 *ab8500,
enum ab8500_version version);
extern int __devexit ab8500_exit(struct ab8500 *ab8500);
static inline int is_ab8500(struct ab8500 *ab)
{
return ab->version == AB8500_VERSION_AB8500;
}
static inline int is_ab8505(struct ab8500 *ab)
{
return ab->version == AB8500_VERSION_AB8505;
}
static inline int is_ab9540(struct ab8500 *ab)
{
return ab->version == AB8500_VERSION_AB9540;
}
static inline int is_ab8540(struct ab8500 *ab)
{
return ab->version == AB8500_VERSION_AB8540;
}
/* exclude also ab8505, ab9540... */
static inline int is_ab8500_1p0_or_earlier(struct ab8500 *ab)
{
return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P0));
}
/* exclude also ab8505, ab9540... */
static inline int is_ab8500_1p1_or_earlier(struct ab8500 *ab)
{
return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P1));
}
/* exclude also ab8505, ab9540... */
static inline int is_ab8500_2p0_or_earlier(struct ab8500 *ab)
{
return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0));
}
/* exclude also ab8505, ab9540... */
static inline int is_ab8500_2p0(struct ab8500 *ab)
{
return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0));
}
#endif /* MFD_AB8500_H */
kernel/include/linux/mfd/abx500/ux500_chargalg.h
+38
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/*
* Copyright (C) ST-Ericsson SA 2012
* Author: Johan Gardsmark <johan.gardsmark@stericsson.com> for ST-Ericsson.
* License terms: GNU General Public License (GPL), version 2
*/
#ifndef _UX500_CHARGALG_H
#define _UX500_CHARGALG_H
#include <linux/power_supply.h>
#define psy_to_ux500_charger(x) container_of((x), \
struct ux500_charger, psy)
/* Forward declaration */
struct ux500_charger;
struct ux500_charger_ops {
int (*enable) (struct ux500_charger *, int, int, int);
int (*kick_wd) (struct ux500_charger *);
int (*update_curr) (struct ux500_charger *, int);
};
/**
* struct ux500_charger - power supply ux500 charger sub class
* @psy power supply base class
* @ops ux500 charger operations
* @max_out_volt maximum output charger voltage in mV
* @max_out_curr maximum output charger current in mA
*/
struct ux500_charger {
struct power_supply psy;
struct ux500_charger_ops ops;
int max_out_volt;
int max_out_curr;
};
#endif
kernel/include/linux/mfd/adp5520.h
+299
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/*
* Definitions and platform data for Analog Devices
* ADP5520/ADP5501 MFD PMICs (Backlight, LED, GPIO and Keys)
*
* Copyright 2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __LINUX_MFD_ADP5520_H
#define __LINUX_MFD_ADP5520_H
#define ID_ADP5520 5520
#define ID_ADP5501 5501
/*
* ADP5520/ADP5501 Register Map
*/
#define ADP5520_MODE_STATUS 0x00
#define ADP5520_INTERRUPT_ENABLE 0x01
#define ADP5520_BL_CONTROL 0x02
#define ADP5520_BL_TIME 0x03
#define ADP5520_BL_FADE 0x04
#define ADP5520_DAYLIGHT_MAX 0x05
#define ADP5520_DAYLIGHT_DIM 0x06
#define ADP5520_OFFICE_MAX 0x07
#define ADP5520_OFFICE_DIM 0x08
#define ADP5520_DARK_MAX 0x09
#define ADP5520_DARK_DIM 0x0A
#define ADP5520_BL_VALUE 0x0B
#define ADP5520_ALS_CMPR_CFG 0x0C
#define ADP5520_L2_TRIP 0x0D
#define ADP5520_L2_HYS 0x0E
#define ADP5520_L3_TRIP 0x0F
#define ADP5520_L3_HYS 0x10
#define ADP5520_LED_CONTROL 0x11
#define ADP5520_LED_TIME 0x12
#define ADP5520_LED_FADE 0x13
#define ADP5520_LED1_CURRENT 0x14
#define ADP5520_LED2_CURRENT 0x15
#define ADP5520_LED3_CURRENT 0x16
/*
* ADP5520 Register Map
*/
#define ADP5520_GPIO_CFG_1 0x17
#define ADP5520_GPIO_CFG_2 0x18
#define ADP5520_GPIO_IN 0x19
#define ADP5520_GPIO_OUT 0x1A
#define ADP5520_GPIO_INT_EN 0x1B
#define ADP5520_GPIO_INT_STAT 0x1C
#define ADP5520_GPIO_INT_LVL 0x1D
#define ADP5520_GPIO_DEBOUNCE 0x1E
#define ADP5520_GPIO_PULLUP 0x1F
#define ADP5520_KP_INT_STAT_1 0x20
#define ADP5520_KP_INT_STAT_2 0x21
#define ADP5520_KR_INT_STAT_1 0x22
#define ADP5520_KR_INT_STAT_2 0x23
#define ADP5520_KEY_STAT_1 0x24
#define ADP5520_KEY_STAT_2 0x25
/*
* MODE_STATUS bits
*/
#define ADP5520_nSTNBY (1 << 7)
#define ADP5520_BL_EN (1 << 6)
#define ADP5520_DIM_EN (1 << 5)
#define ADP5520_OVP_INT (1 << 4)
#define ADP5520_CMPR_INT (1 << 3)
#define ADP5520_GPI_INT (1 << 2)
#define ADP5520_KR_INT (1 << 1)
#define ADP5520_KP_INT (1 << 0)
/*
* INTERRUPT_ENABLE bits
*/
#define ADP5520_AUTO_LD_EN (1 << 4)
#define ADP5520_CMPR_IEN (1 << 3)
#define ADP5520_OVP_IEN (1 << 2)
#define ADP5520_KR_IEN (1 << 1)
#define ADP5520_KP_IEN (1 << 0)
/*
* BL_CONTROL bits
*/
#define ADP5520_BL_LVL ((x) << 5)
#define ADP5520_BL_LAW ((x) << 4)
#define ADP5520_BL_AUTO_ADJ (1 << 3)
#define ADP5520_OVP_EN (1 << 2)
#define ADP5520_FOVR (1 << 1)
#define ADP5520_KP_BL_EN (1 << 0)
/*
* ALS_CMPR_CFG bits
*/
#define ADP5520_L3_OUT (1 << 3)
#define ADP5520_L2_OUT (1 << 2)
#define ADP5520_L3_EN (1 << 1)
#define ADP5020_MAX_BRIGHTNESS 0x7F
#define FADE_VAL(in, out) ((0xF & (in)) | ((0xF & (out)) << 4))
#define BL_CTRL_VAL(law, auto) (((1 & (auto)) << 3) | ((0x3 & (law)) << 4))
#define ALS_CMPR_CFG_VAL(filt, l3_en) (((0x7 & filt) << 5) | l3_en)
/*
* LEDs subdevice bits and masks
*/
#define ADP5520_01_MAXLEDS 3
#define ADP5520_FLAG_LED_MASK 0x3
#define ADP5520_FLAG_OFFT_SHIFT 8
#define ADP5520_FLAG_OFFT_MASK 0x3
#define ADP5520_R3_MODE (1 << 5)
#define ADP5520_C3_MODE (1 << 4)
#define ADP5520_LED_LAW (1 << 3)
#define ADP5520_LED3_EN (1 << 2)
#define ADP5520_LED2_EN (1 << 1)
#define ADP5520_LED1_EN (1 << 0)
/*
* GPIO subdevice bits and masks
*/
#define ADP5520_MAXGPIOS 8
#define ADP5520_GPIO_C3 (1 << 7) /* LED2 or GPIO7 aka C3 */
#define ADP5520_GPIO_C2 (1 << 6)
#define ADP5520_GPIO_C1 (1 << 5)
#define ADP5520_GPIO_C0 (1 << 4)
#define ADP5520_GPIO_R3 (1 << 3) /* LED3 or GPIO3 aka R3 */
#define ADP5520_GPIO_R2 (1 << 2)
#define ADP5520_GPIO_R1 (1 << 1)
#define ADP5520_GPIO_R0 (1 << 0)
struct adp5520_gpio_platform_data {
unsigned gpio_start;
u8 gpio_en_mask;
u8 gpio_pullup_mask;
};
/*
* Keypad subdevice bits and masks
*/
#define ADP5520_MAXKEYS 16
#define ADP5520_COL_C3 (1 << 7) /* LED2 or GPIO7 aka C3 */
#define ADP5520_COL_C2 (1 << 6)
#define ADP5520_COL_C1 (1 << 5)
#define ADP5520_COL_C0 (1 << 4)
#define ADP5520_ROW_R3 (1 << 3) /* LED3 or GPIO3 aka R3 */
#define ADP5520_ROW_R2 (1 << 2)
#define ADP5520_ROW_R1 (1 << 1)
#define ADP5520_ROW_R0 (1 << 0)
#define ADP5520_KEY(row, col) (col + row * 4)
#define ADP5520_KEYMAPSIZE ADP5520_MAXKEYS
struct adp5520_keys_platform_data {
int rows_en_mask; /* Number of rows */
int cols_en_mask; /* Number of columns */
const unsigned short *keymap; /* Pointer to keymap */
unsigned short keymapsize; /* Keymap size */
unsigned repeat:1; /* Enable key repeat */
};
/*
* LEDs subdevice platform data
*/
#define FLAG_ID_ADP5520_LED1_ADP5501_LED0 1 /* ADP5520 PIN ILED */
#define FLAG_ID_ADP5520_LED2_ADP5501_LED1 2 /* ADP5520 PIN C3 */
#define FLAG_ID_ADP5520_LED3_ADP5501_LED2 3 /* ADP5520 PIN R3 */
#define ADP5520_LED_DIS_BLINK (0 << ADP5520_FLAG_OFFT_SHIFT)
#define ADP5520_LED_OFFT_600ms (1 << ADP5520_FLAG_OFFT_SHIFT)
#define ADP5520_LED_OFFT_800ms (2 << ADP5520_FLAG_OFFT_SHIFT)
#define ADP5520_LED_OFFT_1200ms (3 << ADP5520_FLAG_OFFT_SHIFT)
#define ADP5520_LED_ONT_200ms 0
#define ADP5520_LED_ONT_600ms 1
#define ADP5520_LED_ONT_800ms 2
#define ADP5520_LED_ONT_1200ms 3
struct adp5520_leds_platform_data {
int num_leds;
struct led_info *leds;
u8 fade_in; /* Backlight Fade-In Timer */
u8 fade_out; /* Backlight Fade-Out Timer */
u8 led_on_time;
};
/*
* Backlight subdevice platform data
*/
#define ADP5520_FADE_T_DIS 0 /* Fade Timer Disabled */
#define ADP5520_FADE_T_300ms 1 /* 0.3 Sec */
#define ADP5520_FADE_T_600ms 2
#define ADP5520_FADE_T_900ms 3
#define ADP5520_FADE_T_1200ms 4
#define ADP5520_FADE_T_1500ms 5
#define ADP5520_FADE_T_1800ms 6
#define ADP5520_FADE_T_2100ms 7
#define ADP5520_FADE_T_2400ms 8
#define ADP5520_FADE_T_2700ms 9
#define ADP5520_FADE_T_3000ms 10
#define ADP5520_FADE_T_3500ms 11
#define ADP5520_FADE_T_4000ms 12
#define ADP5520_FADE_T_4500ms 13
#define ADP5520_FADE_T_5000ms 14
#define ADP5520_FADE_T_5500ms 15 /* 5.5 Sec */
#define ADP5520_BL_LAW_LINEAR 0
#define ADP5520_BL_LAW_SQUARE 1
#define ADP5520_BL_LAW_CUBIC1 2
#define ADP5520_BL_LAW_CUBIC2 3
#define ADP5520_BL_AMBL_FILT_80ms 0 /* Light sensor filter time */
#define ADP5520_BL_AMBL_FILT_160ms 1
#define ADP5520_BL_AMBL_FILT_320ms 2
#define ADP5520_BL_AMBL_FILT_640ms 3
#define ADP5520_BL_AMBL_FILT_1280ms 4
#define ADP5520_BL_AMBL_FILT_2560ms 5
#define ADP5520_BL_AMBL_FILT_5120ms 6
#define ADP5520_BL_AMBL_FILT_10240ms 7 /* 10.24 sec */
/*
* Blacklight current 0..30mA
*/
#define ADP5520_BL_CUR_mA(I) ((I * 127) / 30)
/*
* L2 comparator current 0..1000uA
*/
#define ADP5520_L2_COMP_CURR_uA(I) ((I * 255) / 1000)
/*
* L3 comparator current 0..127uA
*/
#define ADP5520_L3_COMP_CURR_uA(I) ((I * 255) / 127)
struct adp5520_backlight_platform_data {
u8 fade_in; /* Backlight Fade-In Timer */
u8 fade_out; /* Backlight Fade-Out Timer */
u8 fade_led_law; /* fade-on/fade-off transfer characteristic */
u8 en_ambl_sens; /* 1 = enable ambient light sensor */
u8 abml_filt; /* Light sensor filter time */
u8 l1_daylight_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l1_daylight_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l2_office_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l2_office_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l3_dark_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l3_dark_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
u8 l2_trip; /* use L2_COMP_CURR_uA(I) 0 <= I <= 1000 uA */
u8 l2_hyst; /* use L2_COMP_CURR_uA(I) 0 <= I <= 1000 uA */
u8 l3_trip; /* use L3_COMP_CURR_uA(I) 0 <= I <= 127 uA */
u8 l3_hyst; /* use L3_COMP_CURR_uA(I) 0 <= I <= 127 uA */
};
/*
* MFD chip platform data
*/
struct adp5520_platform_data {
struct adp5520_keys_platform_data *keys;
struct adp5520_gpio_platform_data *gpio;
struct adp5520_leds_platform_data *leds;
struct adp5520_backlight_platform_data *backlight;
};
/*
* MFD chip functions
*/
extern int adp5520_read(struct device *dev, int reg, uint8_t *val);
extern int adp5520_write(struct device *dev, int reg, u8 val);
extern int adp5520_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
extern int adp5520_set_bits(struct device *dev, int reg, uint8_t bit_mask);
extern int adp5520_register_notifier(struct device *dev,
struct notifier_block *nb, unsigned int events);
extern int adp5520_unregister_notifier(struct device *dev,
struct notifier_block *nb, unsigned int events);
#endif /* __LINUX_MFD_ADP5520_H */
kernel/include/linux/mfd/anatop.h
+40
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/*
* anatop.h - Anatop MFD driver
*
* Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
* Copyright (C) 2012 Linaro
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __LINUX_MFD_ANATOP_H
#define __LINUX_MFD_ANATOP_H
#include <linux/spinlock.h>
/**
* anatop - MFD data
* @ioreg: ioremap register
* @reglock: spinlock for register read/write
*/
struct anatop {
void *ioreg;
spinlock_t reglock;
};
extern u32 anatop_get_bits(struct anatop *, u32, int, int);
extern void anatop_set_bits(struct anatop *, u32, int, int, u32);
#endif /* __LINUX_MFD_ANATOP_H */
kernel/include/linux/mfd/asic3.h
+313
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/*
* include/linux/mfd/asic3.h
*
* Compaq ASIC3 headers.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Copyright 2001 Compaq Computer Corporation.
* Copyright 2007-2008 OpenedHand Ltd.
*/
#ifndef __ASIC3_H__
#define __ASIC3_H__
#include <linux/types.h>
struct led_classdev;
struct asic3_led {
const char *name;
const char *default_trigger;
struct led_classdev *cdev;
};
struct asic3_platform_data {
u16 *gpio_config;
unsigned int gpio_config_num;
unsigned int irq_base;
unsigned int gpio_base;
struct asic3_led *leds;
};
#define ASIC3_NUM_GPIO_BANKS 4
#define ASIC3_GPIOS_PER_BANK 16
#define ASIC3_NUM_GPIOS 64
#define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6
#define ASIC3_IRQ_LED0 64
#define ASIC3_IRQ_LED1 65
#define ASIC3_IRQ_LED2 66
#define ASIC3_IRQ_SPI 67
#define ASIC3_IRQ_SMBUS 68
#define ASIC3_IRQ_OWM 69
#define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio))
#define ASIC3_GPIO_BANK_A 0
#define ASIC3_GPIO_BANK_B 1
#define ASIC3_GPIO_BANK_C 2
#define ASIC3_GPIO_BANK_D 3
#define ASIC3_GPIO(bank, gpio) \
((ASIC3_GPIOS_PER_BANK * ASIC3_GPIO_BANK_##bank) + (gpio))
#define ASIC3_GPIO_bit(gpio) (1 << (gpio & 0xf))
/* All offsets below are specified with this address bus shift */
#define ASIC3_DEFAULT_ADDR_SHIFT 2
#define ASIC3_OFFSET(base, reg) (ASIC3_##base##_BASE + ASIC3_##base##_##reg)
#define ASIC3_GPIO_OFFSET(base, reg) \
(ASIC3_GPIO_##base##_BASE + ASIC3_GPIO_##reg)
#define ASIC3_GPIO_A_BASE 0x0000
#define ASIC3_GPIO_B_BASE 0x0100
#define ASIC3_GPIO_C_BASE 0x0200
#define ASIC3_GPIO_D_BASE 0x0300
#define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4)
#define ASIC3_GPIO_TO_BIT(gpio) ((gpio) - \
(ASIC3_GPIOS_PER_BANK * ((gpio) >> 4)))
#define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio))
#define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_BASE + (((gpio) >> 4) * 0x0100))
#define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_BASE + ((bank) * 0x100))
#define ASIC3_GPIO_MASK 0x00 /* R/W 0:don't mask */
#define ASIC3_GPIO_DIRECTION 0x04 /* R/W 0:input */
#define ASIC3_GPIO_OUT 0x08 /* R/W 0:output low */
#define ASIC3_GPIO_TRIGGER_TYPE 0x0c /* R/W 0:level */
#define ASIC3_GPIO_EDGE_TRIGGER 0x10 /* R/W 0:falling */
#define ASIC3_GPIO_LEVEL_TRIGGER 0x14 /* R/W 0:low level detect */
#define ASIC3_GPIO_SLEEP_MASK 0x18 /* R/W 0:don't mask in sleep mode */
#define ASIC3_GPIO_SLEEP_OUT 0x1c /* R/W level 0:low in sleep mode */
#define ASIC3_GPIO_BAT_FAULT_OUT 0x20 /* R/W level 0:low in batt_fault */
#define ASIC3_GPIO_INT_STATUS 0x24 /* R/W 0:none, 1:detect */
#define ASIC3_GPIO_ALT_FUNCTION 0x28 /* R/W 1:LED register control */
#define ASIC3_GPIO_SLEEP_CONF 0x2c /*
* R/W bit 1: autosleep
* 0: disable gposlpout in normal mode,
* enable gposlpout in sleep mode.
*/
#define ASIC3_GPIO_STATUS 0x30 /* R Pin status */
/*
* ASIC3 GPIO config
*
* Bits 0..6 gpio number
* Bits 7..13 Alternate function
* Bit 14 Direction
* Bit 15 Initial value
*
*/
#define ASIC3_CONFIG_GPIO_PIN(config) ((config) & 0x7f)
#define ASIC3_CONFIG_GPIO_ALT(config) (((config) & (0x7f << 7)) >> 7)
#define ASIC3_CONFIG_GPIO_DIR(config) ((config & (1 << 14)) >> 14)
#define ASIC3_CONFIG_GPIO_INIT(config) ((config & (1 << 15)) >> 15)
#define ASIC3_CONFIG_GPIO(gpio, alt, dir, init) (((gpio) & 0x7f) \
| (((alt) & 0x7f) << 7) | (((dir) & 0x1) << 14) \
| (((init) & 0x1) << 15))
#define ASIC3_CONFIG_GPIO_DEFAULT(gpio, dir, init) \
ASIC3_CONFIG_GPIO((gpio), 0, (dir), (init))
#define ASIC3_CONFIG_GPIO_DEFAULT_OUT(gpio, init) \
ASIC3_CONFIG_GPIO((gpio), 0, 1, (init))
/*
* Alternate functions
*/
#define ASIC3_GPIOA11_PWM0 ASIC3_CONFIG_GPIO(11, 1, 1, 0)
#define ASIC3_GPIOA12_PWM1 ASIC3_CONFIG_GPIO(12, 1, 1, 0)
#define ASIC3_GPIOA15_CONTROL_CX ASIC3_CONFIG_GPIO(15, 1, 1, 0)
#define ASIC3_GPIOC0_LED0 ASIC3_CONFIG_GPIO(32, 1, 0, 0)
#define ASIC3_GPIOC1_LED1 ASIC3_CONFIG_GPIO(33, 1, 0, 0)
#define ASIC3_GPIOC2_LED2 ASIC3_CONFIG_GPIO(34, 1, 0, 0)
#define ASIC3_GPIOC3_SPI_RXD ASIC3_CONFIG_GPIO(35, 1, 0, 0)
#define ASIC3_GPIOC4_CF_nCD ASIC3_CONFIG_GPIO(36, 1, 0, 0)
#define ASIC3_GPIOC4_SPI_TXD ASIC3_CONFIG_GPIO(36, 1, 1, 0)
#define ASIC3_GPIOC5_SPI_CLK ASIC3_CONFIG_GPIO(37, 1, 1, 0)
#define ASIC3_GPIOC5_nCIOW ASIC3_CONFIG_GPIO(37, 1, 1, 0)
#define ASIC3_GPIOC6_nCIOR ASIC3_CONFIG_GPIO(38, 1, 1, 0)
#define ASIC3_GPIOC7_nPCE_1 ASIC3_CONFIG_GPIO(39, 1, 0, 0)
#define ASIC3_GPIOC8_nPCE_2 ASIC3_CONFIG_GPIO(40, 1, 0, 0)
#define ASIC3_GPIOC9_nPOE ASIC3_CONFIG_GPIO(41, 1, 0, 0)
#define ASIC3_GPIOC10_nPWE ASIC3_CONFIG_GPIO(42, 1, 0, 0)
#define ASIC3_GPIOC11_PSKTSEL ASIC3_CONFIG_GPIO(43, 1, 0, 0)
#define ASIC3_GPIOC12_nPREG ASIC3_CONFIG_GPIO(44, 1, 0, 0)
#define ASIC3_GPIOC13_nPWAIT ASIC3_CONFIG_GPIO(45, 1, 1, 0)
#define ASIC3_GPIOC14_nPIOIS16 ASIC3_CONFIG_GPIO(46, 1, 1, 0)
#define ASIC3_GPIOC15_nPIOR ASIC3_CONFIG_GPIO(47, 1, 0, 0)
#define ASIC3_GPIOD11_nCIOIS16 ASIC3_CONFIG_GPIO(59, 1, 0, 0)
#define ASIC3_GPIOD12_nCWAIT ASIC3_CONFIG_GPIO(60, 1, 0, 0)
#define ASIC3_GPIOD15_nPIOW ASIC3_CONFIG_GPIO(63, 1, 0, 0)
#define ASIC3_SPI_Base 0x0400
#define ASIC3_SPI_Control 0x0000
#define ASIC3_SPI_TxData 0x0004
#define ASIC3_SPI_RxData 0x0008
#define ASIC3_SPI_Int 0x000c
#define ASIC3_SPI_Status 0x0010
#define SPI_CONTROL_SPR(clk) ((clk) & 0x0f) /* Clock rate */
#define ASIC3_PWM_0_Base 0x0500
#define ASIC3_PWM_1_Base 0x0600
#define ASIC3_PWM_TimeBase 0x0000
#define ASIC3_PWM_PeriodTime 0x0004
#define ASIC3_PWM_DutyTime 0x0008
#define PWM_TIMEBASE_VALUE(x) ((x)&0xf) /* Low 4 bits sets time base */
#define PWM_TIMEBASE_ENABLE (1 << 4) /* Enable clock */
#define ASIC3_NUM_LEDS 3
#define ASIC3_LED_0_Base 0x0700
#define ASIC3_LED_1_Base 0x0800
#define ASIC3_LED_2_Base 0x0900
#define ASIC3_LED_TimeBase 0x0000 /* R/W 7 bits */
#define ASIC3_LED_PeriodTime 0x0004 /* R/W 12 bits */
#define ASIC3_LED_DutyTime 0x0008 /* R/W 12 bits */
#define ASIC3_LED_AutoStopCount 0x000c /* R/W 16 bits */
/* LED TimeBase bits - match ASIC2 */
#define LED_TBS 0x0f /* Low 4 bits sets time base, max = 13 */
/* Note: max = 5 on hx4700 */
/* 0: maximum time base */
/* 1: maximum time base / 2 */
/* n: maximum time base / 2^n */
#define LED_EN (1 << 4) /* LED ON/OFF 0:off, 1:on */
#define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */
#define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */
#define ASIC3_CLOCK_BASE 0x0A00
#define ASIC3_CLOCK_CDEX 0x00
#define ASIC3_CLOCK_SEL 0x04
#define CLOCK_CDEX_SOURCE (1 << 0) /* 2 bits */
#define CLOCK_CDEX_SOURCE0 (1 << 0)
#define CLOCK_CDEX_SOURCE1 (1 << 1)
#define CLOCK_CDEX_SPI (1 << 2)
#define CLOCK_CDEX_OWM (1 << 3)
#define CLOCK_CDEX_PWM0 (1 << 4)
#define CLOCK_CDEX_PWM1 (1 << 5)
#define CLOCK_CDEX_LED0 (1 << 6)
#define CLOCK_CDEX_LED1 (1 << 7)
#define CLOCK_CDEX_LED2 (1 << 8)
/* Clocks settings: 1 for 24.576 MHz, 0 for 12.288Mhz */
#define CLOCK_CDEX_SD_HOST (1 << 9) /* R/W: SD host clock source */
#define CLOCK_CDEX_SD_BUS (1 << 10) /* R/W: SD bus clock source ctrl */
#define CLOCK_CDEX_SMBUS (1 << 11)
#define CLOCK_CDEX_CONTROL_CX (1 << 12)
#define CLOCK_CDEX_EX0 (1 << 13) /* R/W: 32.768 kHz crystal */
#define CLOCK_CDEX_EX1 (1 << 14) /* R/W: 24.576 MHz crystal */
#define CLOCK_SEL_SD_HCLK_SEL (1 << 0) /* R/W: SDIO host clock select */
#define CLOCK_SEL_SD_BCLK_SEL (1 << 1) /* R/W: SDIO bus clock select */
/* R/W: INT clock source control (32.768 kHz) */
#define CLOCK_SEL_CX (1 << 2)
#define ASIC3_INTR_BASE 0x0B00
#define ASIC3_INTR_INT_MASK 0x00 /* Interrupt mask control */
#define ASIC3_INTR_P_INT_STAT 0x04 /* Peripheral interrupt status */
#define ASIC3_INTR_INT_CPS 0x08 /* Interrupt timer clock pre-scale */
#define ASIC3_INTR_INT_TBS 0x0c /* Interrupt timer set */
#define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */
#define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */
#define ASIC3_INTMASK_MASK0 (1 << 2)
#define ASIC3_INTMASK_MASK1 (1 << 3)
#define ASIC3_INTMASK_MASK2 (1 << 4)
#define ASIC3_INTMASK_MASK3 (1 << 5)
#define ASIC3_INTMASK_MASK4 (1 << 6)
#define ASIC3_INTMASK_MASK5 (1 << 7)
#define ASIC3_INTR_PERIPHERAL_A (1 << 0)
#define ASIC3_INTR_PERIPHERAL_B (1 << 1)
#define ASIC3_INTR_PERIPHERAL_C (1 << 2)
#define ASIC3_INTR_PERIPHERAL_D (1 << 3)
#define ASIC3_INTR_LED0 (1 << 4)
#define ASIC3_INTR_LED1 (1 << 5)
#define ASIC3_INTR_LED2 (1 << 6)
#define ASIC3_INTR_SPI (1 << 7)
#define ASIC3_INTR_SMBUS (1 << 8)
#define ASIC3_INTR_OWM (1 << 9)
#define ASIC3_INTR_CPS(x) ((x)&0x0f) /* 4 bits, max 14 */
#define ASIC3_INTR_CPS_SET (1 << 4) /* Time base enable */
/* Basic control of the SD ASIC */
#define ASIC3_SDHWCTRL_BASE 0x0E00
#define ASIC3_SDHWCTRL_SDCONF 0x00
#define ASIC3_SDHWCTRL_SUSPEND (1 << 0) /* 1=suspend all SD operations */
#define ASIC3_SDHWCTRL_CLKSEL (1 << 1) /* 1=SDICK, 0=HCLK */
#define ASIC3_SDHWCTRL_PCLR (1 << 2) /* All registers of SDIO cleared */
#define ASIC3_SDHWCTRL_LEVCD (1 << 3) /* SD card detection: 0:low */
/* SD card write protection: 0=high */
#define ASIC3_SDHWCTRL_LEVWP (1 << 4)
#define ASIC3_SDHWCTRL_SDLED (1 << 5) /* SD card LED signal 0=disable */
/* SD card power supply ctrl 1=enable */
#define ASIC3_SDHWCTRL_SDPWR (1 << 6)
#define ASIC3_EXTCF_BASE 0x1100
#define ASIC3_EXTCF_SELECT 0x00
#define ASIC3_EXTCF_RESET 0x04
#define ASIC3_EXTCF_SMOD0 (1 << 0) /* slot number of mode 0 */
#define ASIC3_EXTCF_SMOD1 (1 << 1) /* slot number of mode 1 */
#define ASIC3_EXTCF_SMOD2 (1 << 2) /* slot number of mode 2 */
#define ASIC3_EXTCF_OWM_EN (1 << 4) /* enable onewire module */
#define ASIC3_EXTCF_OWM_SMB (1 << 5) /* OWM bus selection */
#define ASIC3_EXTCF_OWM_RESET (1 << 6) /* ?? used by OWM and CF */
#define ASIC3_EXTCF_CF0_SLEEP_MODE (1 << 7) /* CF0 sleep state */
#define ASIC3_EXTCF_CF1_SLEEP_MODE (1 << 8) /* CF1 sleep state */
#define ASIC3_EXTCF_CF0_PWAIT_EN (1 << 10) /* CF0 PWAIT_n control */
#define ASIC3_EXTCF_CF1_PWAIT_EN (1 << 11) /* CF1 PWAIT_n control */
#define ASIC3_EXTCF_CF0_BUF_EN (1 << 12) /* CF0 buffer control */
#define ASIC3_EXTCF_CF1_BUF_EN (1 << 13) /* CF1 buffer control */
#define ASIC3_EXTCF_SD_MEM_ENABLE (1 << 14)
#define ASIC3_EXTCF_CF_SLEEP (1 << 15) /* CF sleep mode control */
/*********************************************
* The Onewire interface (DS1WM) is handled
* by the ds1wm driver.
*
*********************************************/
#define ASIC3_OWM_BASE 0xC00
/*****************************************************************************
* The SD configuration registers are at a completely different location
* in memory. They are divided into three sets of registers:
*
* SD_CONFIG Core configuration register
* SD_CTRL Control registers for SD operations
* SDIO_CTRL Control registers for SDIO operations
*
*****************************************************************************/
#define ASIC3_SD_CONFIG_BASE 0x0400 /* Assumes 32 bit addressing */
#define ASIC3_SD_CONFIG_SIZE 0x0200 /* Assumes 32 bit addressing */
#define ASIC3_SD_CTRL_BASE 0x1000
#define ASIC3_SDIO_CTRL_BASE 0x1200
#define ASIC3_MAP_SIZE_32BIT 0x2000
#define ASIC3_MAP_SIZE_16BIT 0x1000
/* Functions needed by leds-asic3 */
struct asic3;
extern void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 val);
extern u32 asic3_read_register(struct asic3 *asic, unsigned int reg);
#endif /* __ASIC3_H__ */
kernel/include/linux/mfd/core.h
+100
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/*
* drivers/mfd/mfd-core.h
*
* core MFD support
* Copyright (c) 2006 Ian Molton
* Copyright (c) 2007 Dmitry Baryshkov
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef MFD_CORE_H
#define MFD_CORE_H
#include <linux/platform_device.h>
/*
* This struct describes the MFD part ("cell").
* After registration the copy of this structure will become the platform data
* of the resulting platform_device
*/
struct mfd_cell {
const char *name;
int id;
/* refcounting for multiple drivers to use a single cell */
atomic_t *usage_count;
int (*enable)(struct platform_device *dev);
int (*disable)(struct platform_device *dev);
int (*suspend)(struct platform_device *dev);
int (*resume)(struct platform_device *dev);
/* platform data passed to the sub devices drivers */
void *platform_data;
size_t pdata_size;
/*
* These resources can be specified relative to the parent device.
* For accessing hardware you should use resources from the platform dev
*/
int num_resources;
const struct resource *resources;
/* don't check for resource conflicts */
bool ignore_resource_conflicts;
/*
* Disable runtime PM callbacks for this subdevice - see
* pm_runtime_no_callbacks().
*/
bool pm_runtime_no_callbacks;
};
/*
* Convenience functions for clients using shared cells. Refcounting
* happens automatically, with the cell's enable/disable callbacks
* being called only when a device is first being enabled or no other
* clients are making use of it.
*/
extern int mfd_cell_enable(struct platform_device *pdev);
extern int mfd_cell_disable(struct platform_device *pdev);
/*
* "Clone" multiple platform devices for a single cell. This is to be used
* for devices that have multiple users of a cell. For example, if an mfd
* driver wants the cell "foo" to be used by a GPIO driver, an MTD driver,
* and a platform driver, the following bit of code would be use after first
* calling mfd_add_devices():
*
* const char *fclones[] = { "foo-gpio", "foo-mtd" };
* err = mfd_clone_cells("foo", fclones, ARRAY_SIZE(fclones));
*
* Each driver (MTD, GPIO, and platform driver) would then register
* platform_drivers for "foo-mtd", "foo-gpio", and "foo", respectively.
* The cell's .enable/.disable hooks should be used to deal with hardware
* resource contention.
*/
extern int mfd_clone_cell(const char *cell, const char **clones,
size_t n_clones);
/*
* Given a platform device that's been created by mfd_add_devices(), fetch
* the mfd_cell that created it.
*/
static inline const struct mfd_cell *mfd_get_cell(struct platform_device *pdev)
{
return pdev->mfd_cell;
}
extern int mfd_add_devices(struct device *parent, int id,
struct mfd_cell *cells, int n_devs,
struct resource *mem_base,
int irq_base);
extern void mfd_remove_devices(struct device *parent);
#endif
kernel/include/linux/mfd/da903x.h
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#ifndef __LINUX_PMIC_DA903X_H
#define __LINUX_PMIC_DA903X_H
/* Unified sub device IDs for DA9030/DA9034/DA9035 */
enum {
DA9030_ID_LED_1,
DA9030_ID_LED_2,
DA9030_ID_LED_3,
DA9030_ID_LED_4,
DA9030_ID_LED_PC,
DA9030_ID_VIBRA,
DA9030_ID_WLED,
DA9030_ID_BUCK1,
DA9030_ID_BUCK2,
DA9030_ID_LDO1,
DA9030_ID_LDO2,
DA9030_ID_LDO3,
DA9030_ID_LDO4,
DA9030_ID_LDO5,
DA9030_ID_LDO6,
DA9030_ID_LDO7,
DA9030_ID_LDO8,
DA9030_ID_LDO9,
DA9030_ID_LDO10,
DA9030_ID_LDO11,
DA9030_ID_LDO12,
DA9030_ID_LDO13,
DA9030_ID_LDO14,
DA9030_ID_LDO15,
DA9030_ID_LDO16,
DA9030_ID_LDO17,
DA9030_ID_LDO18,
DA9030_ID_LDO19,
DA9030_ID_LDO_INT, /* LDO Internal */
DA9030_ID_BAT, /* battery charger */
DA9034_ID_LED_1,
DA9034_ID_LED_2,
DA9034_ID_VIBRA,
DA9034_ID_WLED,
DA9034_ID_TOUCH,
DA9034_ID_BUCK1,
DA9034_ID_BUCK2,
DA9034_ID_LDO1,
DA9034_ID_LDO2,
DA9034_ID_LDO3,
DA9034_ID_LDO4,
DA9034_ID_LDO5,
DA9034_ID_LDO6,
DA9034_ID_LDO7,
DA9034_ID_LDO8,
DA9034_ID_LDO9,
DA9034_ID_LDO10,
DA9034_ID_LDO11,
DA9034_ID_LDO12,
DA9034_ID_LDO13,
DA9034_ID_LDO14,
DA9034_ID_LDO15,
DA9035_ID_BUCK3,
};
/*
* DA9030/DA9034 LEDs sub-devices uses generic "struct led_info"
* as the platform_data
*/
/* DA9030 flags for "struct led_info"
*/
#define DA9030_LED_RATE_ON (0 << 5)
#define DA9030_LED_RATE_052S (1 << 5)
#define DA9030_LED_DUTY_1_16 (0 << 3)
#define DA9030_LED_DUTY_1_8 (1 << 3)
#define DA9030_LED_DUTY_1_4 (2 << 3)
#define DA9030_LED_DUTY_1_2 (3 << 3)
#define DA9030_VIBRA_MODE_1P3V (0 << 1)
#define DA9030_VIBRA_MODE_2P7V (1 << 1)
#define DA9030_VIBRA_FREQ_1HZ (0 << 2)
#define DA9030_VIBRA_FREQ_2HZ (1 << 2)
#define DA9030_VIBRA_FREQ_4HZ (2 << 2)
#define DA9030_VIBRA_FREQ_8HZ (3 << 2)
#define DA9030_VIBRA_DUTY_ON (0 << 4)
#define DA9030_VIBRA_DUTY_75P (1 << 4)
#define DA9030_VIBRA_DUTY_50P (2 << 4)
#define DA9030_VIBRA_DUTY_25P (3 << 4)
/* DA9034 flags for "struct led_info" */
#define DA9034_LED_RAMP (1 << 7)
/* DA9034 touch screen platform data */
struct da9034_touch_pdata {
int interval_ms; /* sampling interval while pen down */
int x_inverted;
int y_inverted;
};
struct da9034_backlight_pdata {
int output_current; /* output current of WLED, from 0-31 (in mA) */
};
/* DA9030 battery charger data */
struct power_supply_info;
struct da9030_battery_info {
/* battery parameters */
struct power_supply_info *battery_info;
/* current and voltage to use for battery charging */
unsigned int charge_milliamp;
unsigned int charge_millivolt;
/* voltage thresholds (in millivolts) */
int vbat_low;
int vbat_crit;
int vbat_charge_start;
int vbat_charge_stop;
int vbat_charge_restart;
/* battery nominal minimal and maximal voltages in millivolts */
int vcharge_min;
int vcharge_max;
/* Temperature thresholds. These are DA9030 register values
"as is" and should be measured for each battery type */
int tbat_low;
int tbat_high;
int tbat_restart;
/* battery monitor interval (seconds) */
unsigned int batmon_interval;
/* platform callbacks for battery low and critical events */
void (*battery_low)(void);
void (*battery_critical)(void);
};
struct da903x_subdev_info {
int id;
const char *name;
void *platform_data;
};
struct da903x_platform_data {
int num_subdevs;
struct da903x_subdev_info *subdevs;
};
/* bit definitions for DA9030 events */
#define DA9030_EVENT_ONKEY (1 << 0)
#define DA9030_EVENT_PWREN (1 << 1)
#define DA9030_EVENT_EXTON (1 << 2)
#define DA9030_EVENT_CHDET (1 << 3)
#define DA9030_EVENT_TBAT (1 << 4)
#define DA9030_EVENT_VBATMON (1 << 5)
#define DA9030_EVENT_VBATMON_TXON (1 << 6)
#define DA9030_EVENT_CHIOVER (1 << 7)
#define DA9030_EVENT_TCTO (1 << 8)
#define DA9030_EVENT_CCTO (1 << 9)
#define DA9030_EVENT_ADC_READY (1 << 10)
#define DA9030_EVENT_VBUS_4P4 (1 << 11)
#define DA9030_EVENT_VBUS_4P0 (1 << 12)
#define DA9030_EVENT_SESS_VALID (1 << 13)
#define DA9030_EVENT_SRP_DETECT (1 << 14)
#define DA9030_EVENT_WATCHDOG (1 << 15)
#define DA9030_EVENT_LDO15 (1 << 16)
#define DA9030_EVENT_LDO16 (1 << 17)
#define DA9030_EVENT_LDO17 (1 << 18)
#define DA9030_EVENT_LDO18 (1 << 19)
#define DA9030_EVENT_LDO19 (1 << 20)
#define DA9030_EVENT_BUCK2 (1 << 21)
/* bit definitions for DA9034 events */
#define DA9034_EVENT_ONKEY (1 << 0)
#define DA9034_EVENT_EXTON (1 << 2)
#define DA9034_EVENT_CHDET (1 << 3)
#define DA9034_EVENT_TBAT (1 << 4)
#define DA9034_EVENT_VBATMON (1 << 5)
#define DA9034_EVENT_REV_IOVER (1 << 6)
#define DA9034_EVENT_CH_IOVER (1 << 7)
#define DA9034_EVENT_CH_TCTO (1 << 8)
#define DA9034_EVENT_CH_CCTO (1 << 9)
#define DA9034_EVENT_USB_DEV (1 << 10)
#define DA9034_EVENT_OTGCP_IOVER (1 << 11)
#define DA9034_EVENT_VBUS_4P55 (1 << 12)
#define DA9034_EVENT_VBUS_3P8 (1 << 13)
#define DA9034_EVENT_SESS_1P8 (1 << 14)
#define DA9034_EVENT_SRP_READY (1 << 15)
#define DA9034_EVENT_ADC_MAN (1 << 16)
#define DA9034_EVENT_ADC_AUTO4 (1 << 17)
#define DA9034_EVENT_ADC_AUTO5 (1 << 18)
#define DA9034_EVENT_ADC_AUTO6 (1 << 19)
#define DA9034_EVENT_PEN_DOWN (1 << 20)
#define DA9034_EVENT_TSI_READY (1 << 21)
#define DA9034_EVENT_UART_TX (1 << 22)
#define DA9034_EVENT_UART_RX (1 << 23)
#define DA9034_EVENT_HEADSET (1 << 25)
#define DA9034_EVENT_HOOKSWITCH (1 << 26)
#define DA9034_EVENT_WATCHDOG (1 << 27)
extern int da903x_register_notifier(struct device *dev,
struct notifier_block *nb, unsigned int events);
extern int da903x_unregister_notifier(struct device *dev,
struct notifier_block *nb, unsigned int events);
/* Status Query Interface */
#define DA9030_STATUS_ONKEY (1 << 0)
#define DA9030_STATUS_PWREN1 (1 << 1)
#define DA9030_STATUS_EXTON (1 << 2)
#define DA9030_STATUS_CHDET (1 << 3)
#define DA9030_STATUS_TBAT (1 << 4)
#define DA9030_STATUS_VBATMON (1 << 5)
#define DA9030_STATUS_VBATMON_TXON (1 << 6)
#define DA9030_STATUS_MCLKDET (1 << 7)
#define DA9034_STATUS_ONKEY (1 << 0)
#define DA9034_STATUS_EXTON (1 << 2)
#define DA9034_STATUS_CHDET (1 << 3)
#define DA9034_STATUS_TBAT (1 << 4)
#define DA9034_STATUS_VBATMON (1 << 5)
#define DA9034_STATUS_PEN_DOWN (1 << 6)
#define DA9034_STATUS_MCLKDET (1 << 7)
#define DA9034_STATUS_USB_DEV (1 << 8)
#define DA9034_STATUS_HEADSET (1 << 9)
#define DA9034_STATUS_HOOKSWITCH (1 << 10)
#define DA9034_STATUS_REMCON (1 << 11)
#define DA9034_STATUS_VBUS_VALID_4P55 (1 << 12)
#define DA9034_STATUS_VBUS_VALID_3P8 (1 << 13)
#define DA9034_STATUS_SESS_VALID_1P8 (1 << 14)
#define DA9034_STATUS_SRP_READY (1 << 15)
extern int da903x_query_status(struct device *dev, unsigned int status);
/* NOTE: the functions below are not intended for use outside
* of the DA903x sub-device drivers
*/
extern int da903x_write(struct device *dev, int reg, uint8_t val);
extern int da903x_writes(struct device *dev, int reg, int len, uint8_t *val);
extern int da903x_read(struct device *dev, int reg, uint8_t *val);
extern int da903x_reads(struct device *dev, int reg, int len, uint8_t *val);
extern int da903x_update(struct device *dev, int reg, uint8_t val, uint8_t mask);
extern int da903x_set_bits(struct device *dev, int reg, uint8_t bit_mask);
extern int da903x_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
#endif /* __LINUX_PMIC_DA903X_H */
kernel/include/linux/mfd/da9052/da9052.h
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/*
* da9052 declarations for DA9052 PMICs.
*
* Copyright(c) 2011 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <dchen@diasemi.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __MFD_DA9052_DA9052_H
#define __MFD_DA9052_DA9052_H
#include <linux/interrupt.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/completion.h>
#include <linux/list.h>
#include <linux/mfd/core.h>
#include <linux/mfd/da9052/reg.h>
#define DA9052_IRQ_DCIN 0
#define DA9052_IRQ_VBUS 1
#define DA9052_IRQ_DCINREM 2
#define DA9052_IRQ_VBUSREM 3
#define DA9052_IRQ_VDDLOW 4
#define DA9052_IRQ_ALARM 5
#define DA9052_IRQ_SEQRDY 6
#define DA9052_IRQ_COMP1V2 7
#define DA9052_IRQ_NONKEY 8
#define DA9052_IRQ_IDFLOAT 9
#define DA9052_IRQ_IDGND 10
#define DA9052_IRQ_CHGEND 11
#define DA9052_IRQ_TBAT 12
#define DA9052_IRQ_ADC_EOM 13
#define DA9052_IRQ_PENDOWN 14
#define DA9052_IRQ_TSIREADY 15
#define DA9052_IRQ_GPI0 16
#define DA9052_IRQ_GPI1 17
#define DA9052_IRQ_GPI2 18
#define DA9052_IRQ_GPI3 19
#define DA9052_IRQ_GPI4 20
#define DA9052_IRQ_GPI5 21
#define DA9052_IRQ_GPI6 22
#define DA9052_IRQ_GPI7 23
#define DA9052_IRQ_GPI8 24
#define DA9052_IRQ_GPI9 25
#define DA9052_IRQ_GPI10 26
#define DA9052_IRQ_GPI11 27
#define DA9052_IRQ_GPI12 28
#define DA9052_IRQ_GPI13 29
#define DA9052_IRQ_GPI14 30
#define DA9052_IRQ_GPI15 31
enum da9052_chip_id {
DA9052,
DA9053_AA,
DA9053_BA,
DA9053_BB,
};
struct da9052_pdata;
struct da9052 {
struct device *dev;
struct regmap *regmap;
int irq_base;
u8 chip_id;
int chip_irq;
};
/* Device I/O API */
static inline int da9052_reg_read(struct da9052 *da9052, unsigned char reg)
{
int val, ret;
ret = regmap_read(da9052->regmap, reg, &val);
if (ret < 0)
return ret;
return val;
}
static inline int da9052_reg_write(struct da9052 *da9052, unsigned char reg,
unsigned char val)
{
return regmap_write(da9052->regmap, reg, val);
}
static inline int da9052_group_read(struct da9052 *da9052, unsigned char reg,
unsigned reg_cnt, unsigned char *val)
{
return regmap_bulk_read(da9052->regmap, reg, val, reg_cnt);
}
static inline int da9052_group_write(struct da9052 *da9052, unsigned char reg,
unsigned reg_cnt, unsigned char *val)
{
return regmap_raw_write(da9052->regmap, reg, val, reg_cnt);
}
static inline int da9052_reg_update(struct da9052 *da9052, unsigned char reg,
unsigned char bit_mask,
unsigned char reg_val)
{
return regmap_update_bits(da9052->regmap, reg, bit_mask, reg_val);
}
int da9052_device_init(struct da9052 *da9052, u8 chip_id);
void da9052_device_exit(struct da9052 *da9052);
extern struct regmap_config da9052_regmap_config;
#endif /* __MFD_DA9052_DA9052_H */
kernel/include/linux/mfd/da9052/pdata.h
+40
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/*
* Platform data declarations for DA9052 PMICs.
*
* Copyright(c) 2011 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <dchen@diasemi.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __MFD_DA9052_PDATA_H__
#define __MFD_DA9052_PDATA_H__
#define DA9052_MAX_REGULATORS 14
struct da9052;
struct da9052_pdata {
struct led_platform_data *pled;
int (*init) (struct da9052 *da9052);
int irq_base;
int gpio_base;
int use_for_apm;
struct regulator_init_data *regulators[DA9052_MAX_REGULATORS];
};
#endif
kernel/include/linux/mfd/da9052/reg.h
+749
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/*
* Register declarations for DA9052 PMICs.
*
* Copyright(c) 2011 Dialog Semiconductor Ltd.
*
* Author: David Dajun Chen <dchen@diasemi.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __LINUX_MFD_DA9052_REG_H
#define __LINUX_MFD_DA9052_REG_H
/* PAGE REGISTERS */
#define DA9052_PAGE0_CON_REG 0
#define DA9052_PAGE1_CON_REG 128
/* STATUS REGISTERS */
#define DA9052_STATUS_A_REG 1
#define DA9052_STATUS_B_REG 2
#define DA9052_STATUS_C_REG 3
#define DA9052_STATUS_D_REG 4
/* EVENT REGISTERS */
#define DA9052_EVENT_A_REG 5
#define DA9052_EVENT_B_REG 6
#define DA9052_EVENT_C_REG 7
#define DA9052_EVENT_D_REG 8
#define DA9052_FAULTLOG_REG 9
/* IRQ REGISTERS */
#define DA9052_IRQ_MASK_A_REG 10
#define DA9052_IRQ_MASK_B_REG 11
#define DA9052_IRQ_MASK_C_REG 12
#define DA9052_IRQ_MASK_D_REG 13
/* CONTROL REGISTERS */
#define DA9052_CONTROL_A_REG 14
#define DA9052_CONTROL_B_REG 15
#define DA9052_CONTROL_C_REG 16
#define DA9052_CONTROL_D_REG 17
#define DA9052_PDDIS_REG 18
#define DA9052_INTERFACE_REG 19
#define DA9052_RESET_REG 20
/* GPIO REGISTERS */
#define DA9052_GPIO_0_1_REG 21
#define DA9052_GPIO_2_3_REG 22
#define DA9052_GPIO_4_5_REG 23
#define DA9052_GPIO_6_7_REG 24
#define DA9052_GPIO_14_15_REG 28
/* POWER SEQUENCER CONTROL REGISTERS */
#define DA9052_ID_0_1_REG 29
#define DA9052_ID_2_3_REG 30
#define DA9052_ID_4_5_REG 31
#define DA9052_ID_6_7_REG 32
#define DA9052_ID_8_9_REG 33
#define DA9052_ID_10_11_REG 34
#define DA9052_ID_12_13_REG 35
#define DA9052_ID_14_15_REG 36
#define DA9052_ID_16_17_REG 37
#define DA9052_ID_18_19_REG 38
#define DA9052_ID_20_21_REG 39
#define DA9052_SEQ_STATUS_REG 40
#define DA9052_SEQ_A_REG 41
#define DA9052_SEQ_B_REG 42
#define DA9052_SEQ_TIMER_REG 43
/* LDO AND BUCK REGISTERS */
#define DA9052_BUCKA_REG 44
#define DA9052_BUCKB_REG 45
#define DA9052_BUCKCORE_REG 46
#define DA9052_BUCKPRO_REG 47
#define DA9052_BUCKMEM_REG 48
#define DA9052_BUCKPERI_REG 49
#define DA9052_LDO1_REG 50
#define DA9052_LDO2_REG 51
#define DA9052_LDO3_REG 52
#define DA9052_LDO4_REG 53
#define DA9052_LDO5_REG 54
#define DA9052_LDO6_REG 55
#define DA9052_LDO7_REG 56
#define DA9052_LDO8_REG 57
#define DA9052_LDO9_REG 58
#define DA9052_LDO10_REG 59
#define DA9052_SUPPLY_REG 60
#define DA9052_PULLDOWN_REG 61
#define DA9052_CHGBUCK_REG 62
#define DA9052_WAITCONT_REG 63
#define DA9052_ISET_REG 64
#define DA9052_BATCHG_REG 65
/* BATTERY CONTROL REGISTRS */
#define DA9052_CHG_CONT_REG 66
#define DA9052_INPUT_CONT_REG 67
#define DA9052_CHG_TIME_REG 68
#define DA9052_BBAT_CONT_REG 69
/* LED CONTROL REGISTERS */
#define DA9052_BOOST_REG 70
#define DA9052_LED_CONT_REG 71
#define DA9052_LEDMIN123_REG 72
#define DA9052_LED1_CONF_REG 73
#define DA9052_LED2_CONF_REG 74
#define DA9052_LED3_CONF_REG 75
#define DA9052_LED1CONT_REG 76
#define DA9052_LED2CONT_REG 77
#define DA9052_LED3CONT_REG 78
#define DA9052_LED_CONT_4_REG 79
#define DA9052_LED_CONT_5_REG 80
/* ADC CONTROL REGISTERS */
#define DA9052_ADC_MAN_REG 81
#define DA9052_ADC_CONT_REG 82
#define DA9052_ADC_RES_L_REG 83
#define DA9052_ADC_RES_H_REG 84
#define DA9052_VDD_RES_REG 85
#define DA9052_VDD_MON_REG 86
#define DA9052_ICHG_AV_REG 87
#define DA9052_ICHG_THD_REG 88
#define DA9052_ICHG_END_REG 89
#define DA9052_TBAT_RES_REG 90
#define DA9052_TBAT_HIGHP_REG 91
#define DA9052_TBAT_HIGHN_REG 92
#define DA9052_TBAT_LOW_REG 93
#define DA9052_T_OFFSET_REG 94
#define DA9052_ADCIN4_RES_REG 95
#define DA9052_AUTO4_HIGH_REG 96
#define DA9052_AUTO4_LOW_REG 97
#define DA9052_ADCIN5_RES_REG 98
#define DA9052_AUTO5_HIGH_REG 99
#define DA9052_AUTO5_LOW_REG 100
#define DA9052_ADCIN6_RES_REG 101
#define DA9052_AUTO6_HIGH_REG 102
#define DA9052_AUTO6_LOW_REG 103
#define DA9052_TJUNC_RES_REG 104
/* TSI CONTROL REGISTERS */
#define DA9052_TSI_CONT_A_REG 105
#define DA9052_TSI_CONT_B_REG 106
#define DA9052_TSI_X_MSB_REG 107
#define DA9052_TSI_Y_MSB_REG 108
#define DA9052_TSI_LSB_REG 109
#define DA9052_TSI_Z_MSB_REG 110
/* RTC COUNT REGISTERS */
#define DA9052_COUNT_S_REG 111
#define DA9052_COUNT_MI_REG 112
#define DA9052_COUNT_H_REG 113
#define DA9052_COUNT_D_REG 114
#define DA9052_COUNT_MO_REG 115
#define DA9052_COUNT_Y_REG 116
/* RTC CONTROL REGISTERS */
#define DA9052_ALARM_MI_REG 117
#define DA9052_ALARM_H_REG 118
#define DA9052_ALARM_D_REG 119
#define DA9052_ALARM_MO_REG 120
#define DA9052_ALARM_Y_REG 121
#define DA9052_SECOND_A_REG 122
#define DA9052_SECOND_B_REG 123
#define DA9052_SECOND_C_REG 124
#define DA9052_SECOND_D_REG 125
/* PAGE CONFIGURATION BIT */
#define DA9052_PAGE_CONF 0X80
/* STATUS REGISTER A BITS */
#define DA9052_STATUSA_VDATDET 0X80
#define DA9052_STATUSA_VBUSSEL 0X40
#define DA9052_STATUSA_DCINSEL 0X20
#define DA9052_STATUSA_VBUSDET 0X10
#define DA9052_STATUSA_DCINDET 0X08
#define DA9052_STATUSA_IDGND 0X04
#define DA9052_STATUSA_IDFLOAT 0X02
#define DA9052_STATUSA_NONKEY 0X01
/* STATUS REGISTER B BITS */
#define DA9052_STATUSB_COMPDET 0X80
#define DA9052_STATUSB_SEQUENCING 0X40
#define DA9052_STATUSB_GPFB2 0X20
#define DA9052_STATUSB_CHGTO 0X10
#define DA9052_STATUSB_CHGEND 0X08
#define DA9052_STATUSB_CHGLIM 0X04
#define DA9052_STATUSB_CHGPRE 0X02
#define DA9052_STATUSB_CHGATT 0X01
/* STATUS REGISTER C BITS */
#define DA9052_STATUSC_GPI7 0X80
#define DA9052_STATUSC_GPI6 0X40
#define DA9052_STATUSC_GPI5 0X20
#define DA9052_STATUSC_GPI4 0X10
#define DA9052_STATUSC_GPI3 0X08
#define DA9052_STATUSC_GPI2 0X04
#define DA9052_STATUSC_GPI1 0X02
#define DA9052_STATUSC_GPI0 0X01
/* STATUS REGISTER D BITS */
#define DA9052_STATUSD_GPI15 0X80
#define DA9052_STATUSD_GPI14 0X40
#define DA9052_STATUSD_GPI13 0X20
#define DA9052_STATUSD_GPI12 0X10
#define DA9052_STATUSD_GPI11 0X08
#define DA9052_STATUSD_GPI10 0X04
#define DA9052_STATUSD_GPI9 0X02
#define DA9052_STATUSD_GPI8 0X01
/* EVENT REGISTER A BITS */
#define DA9052_EVENTA_ECOMP1V2 0X80
#define DA9052_EVENTA_ESEQRDY 0X40
#define DA9052_EVENTA_EALRAM 0X20
#define DA9052_EVENTA_EVDDLOW 0X10
#define DA9052_EVENTA_EVBUSREM 0X08
#define DA9052_EVENTA_EDCINREM 0X04
#define DA9052_EVENTA_EVBUSDET 0X02
#define DA9052_EVENTA_EDCINDET 0X01
/* EVENT REGISTER B BITS */
#define DA9052_EVENTB_ETSIREADY 0X80
#define DA9052_EVENTB_EPENDOWN 0X40
#define DA9052_EVENTB_EADCEOM 0X20
#define DA9052_EVENTB_ETBAT 0X10
#define DA9052_EVENTB_ECHGEND 0X08
#define DA9052_EVENTB_EIDGND 0X04
#define DA9052_EVENTB_EIDFLOAT 0X02
#define DA9052_EVENTB_ENONKEY 0X01
/* EVENT REGISTER C BITS */
#define DA9052_EVENTC_EGPI7 0X80
#define DA9052_EVENTC_EGPI6 0X40
#define DA9052_EVENTC_EGPI5 0X20
#define DA9052_EVENTC_EGPI4 0X10
#define DA9052_EVENTC_EGPI3 0X08
#define DA9052_EVENTC_EGPI2 0X04
#define DA9052_EVENTC_EGPI1 0X02
#define DA9052_EVENTC_EGPI0 0X01
/* EVENT REGISTER D BITS */
#define DA9052_EVENTD_EGPI15 0X80
#define DA9052_EVENTD_EGPI14 0X40
#define DA9052_EVENTD_EGPI13 0X20
#define DA9052_EVENTD_EGPI12 0X10
#define DA9052_EVENTD_EGPI11 0X08
#define DA9052_EVENTD_EGPI10 0X04
#define DA9052_EVENTD_EGPI9 0X02
#define DA9052_EVENTD_EGPI8 0X01
/* IRQ MASK REGISTERS BITS */
#define DA9052_M_NONKEY 0X0100
/* TSI EVENT REGISTERS BITS */
#define DA9052_E_PEN_DOWN 0X4000
#define DA9052_E_TSI_READY 0X8000
/* FAULT LOG REGISTER BITS */
#define DA9052_FAULTLOG_WAITSET 0X80
#define DA9052_FAULTLOG_NSDSET 0X40
#define DA9052_FAULTLOG_KEYSHUT 0X20
#define DA9052_FAULTLOG_TEMPOVER 0X08
#define DA9052_FAULTLOG_VDDSTART 0X04
#define DA9052_FAULTLOG_VDDFAULT 0X02
#define DA9052_FAULTLOG_TWDERROR 0X01
/* CONTROL REGISTER A BITS */
#define DA9052_CONTROLA_GPIV 0X80
#define DA9052_CONTROLA_PMOTYPE 0X20
#define DA9052_CONTROLA_PMOV 0X10
#define DA9052_CONTROLA_PMIV 0X08
#define DA9052_CONTROLA_PMIFV 0X08
#define DA9052_CONTROLA_PWR1EN 0X04
#define DA9052_CONTROLA_PWREN 0X02
#define DA9052_CONTROLA_SYSEN 0X01
/* CONTROL REGISTER B BITS */
#define DA9052_CONTROLB_SHUTDOWN 0X80
#define DA9052_CONTROLB_DEEPSLEEP 0X40
#define DA9052_CONTROL_B_WRITEMODE 0X20
#define DA9052_CONTROLB_BBATEN 0X10
#define DA9052_CONTROLB_OTPREADEN 0X08
#define DA9052_CONTROLB_AUTOBOOT 0X04
#define DA9052_CONTROLB_ACTDIODE 0X02
#define DA9052_CONTROLB_BUCKMERGE 0X01
/* CONTROL REGISTER C BITS */
#define DA9052_CONTROLC_BLINKDUR 0X80
#define DA9052_CONTROLC_BLINKFRQ 0X60
#define DA9052_CONTROLC_DEBOUNCING 0X1C
#define DA9052_CONTROLC_PMFB2PIN 0X02
#define DA9052_CONTROLC_PMFB1PIN 0X01
/* CONTROL REGISTER D BITS */
#define DA9052_CONTROLD_WATCHDOG 0X80
#define DA9052_CONTROLD_ACCDETEN 0X40
#define DA9052_CONTROLD_GPI1415SD 0X20
#define DA9052_CONTROLD_NONKEYSD 0X10
#define DA9052_CONTROLD_KEEPACTEN 0X08
#define DA9052_CONTROLD_TWDSCALE 0X07
/* POWER DOWN DISABLE REGISTER BITS */
#define DA9052_PDDIS_PMCONTPD 0X80
#define DA9052_PDDIS_OUT32KPD 0X40
#define DA9052_PDDIS_CHGBBATPD 0X20
#define DA9052_PDDIS_CHGPD 0X10
#define DA9052_PDDIS_HS2WIREPD 0X08
#define DA9052_PDDIS_PMIFPD 0X04
#define DA9052_PDDIS_GPADCPD 0X02
#define DA9052_PDDIS_GPIOPD 0X01
/* CONTROL REGISTER D BITS */
#define DA9052_INTERFACE_IFBASEADDR 0XE0
#define DA9052_INTERFACE_NCSPOL 0X10
#define DA9052_INTERFACE_RWPOL 0X08
#define DA9052_INTERFACE_CPHA 0X04
#define DA9052_INTERFACE_CPOL 0X02
#define DA9052_INTERFACE_IFTYPE 0X01
/* CONTROL REGISTER D BITS */
#define DA9052_RESET_RESETEVENT 0XC0
#define DA9052_RESET_RESETTIMER 0X3F
/* GPIO REGISTERS */
/* GPIO CONTROL REGISTER BITS */
#define DA9052_GPIO_EVEN_PORT_PIN 0X03
#define DA9052_GPIO_EVEN_PORT_TYPE 0X04
#define DA9052_GPIO_EVEN_PORT_MODE 0X08
#define DA9052_GPIO_ODD_PORT_PIN 0X30
#define DA9052_GPIO_ODD_PORT_TYPE 0X40
#define DA9052_GPIO_ODD_PORT_MODE 0X80
/*POWER SEQUENCER REGISTER BITS */
/* SEQ CONTROL REGISTER BITS FOR ID 0 AND 1 */
#define DA9052_ID01_LDO1STEP 0XF0
#define DA9052_ID01_SYSPRE 0X04
#define DA9052_ID01_DEFSUPPLY 0X02
#define DA9052_ID01_NRESMODE 0X01
/* SEQ CONTROL REGISTER BITS FOR ID 2 AND 3 */
#define DA9052_ID23_LDO3STEP 0XF0
#define DA9052_ID23_LDO2STEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 4 AND 5 */
#define DA9052_ID45_LDO5STEP 0XF0
#define DA9052_ID45_LDO4STEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 6 AND 7 */
#define DA9052_ID67_LDO7STEP 0XF0
#define DA9052_ID67_LDO6STEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 8 AND 9 */
#define DA9052_ID89_LDO9STEP 0XF0
#define DA9052_ID89_LDO8STEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 10 AND 11 */
#define DA9052_ID1011_PDDISSTEP 0XF0
#define DA9052_ID1011_LDO10STEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 12 AND 13 */
#define DA9052_ID1213_VMEMSWSTEP 0XF0
#define DA9052_ID1213_VPERISWSTEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 14 AND 15 */
#define DA9052_ID1415_BUCKPROSTEP 0XF0
#define DA9052_ID1415_BUCKCORESTEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 16 AND 17 */
#define DA9052_ID1617_BUCKPERISTEP 0XF0
#define DA9052_ID1617_BUCKMEMSTEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 18 AND 19 */
#define DA9052_ID1819_GPRISE2STEP 0XF0
#define DA9052_ID1819_GPRISE1STEP 0X0F
/* SEQ CONTROL REGISTER BITS FOR ID 20 AND 21 */
#define DA9052_ID2021_GPFALL2STEP 0XF0
#define DA9052_ID2021_GPFALL1STEP 0X0F
/* POWER SEQ STATUS REGISTER BITS */
#define DA9052_SEQSTATUS_SEQPOINTER 0XF0
#define DA9052_SEQSTATUS_WAITSTEP 0X0F
/* POWER SEQ A REGISTER BITS */
#define DA9052_SEQA_POWEREND 0XF0
#define DA9052_SEQA_SYSTEMEND 0X0F
/* POWER SEQ B REGISTER BITS */
#define DA9052_SEQB_PARTDOWN 0XF0
#define DA9052_SEQB_MAXCOUNT 0X0F
/* POWER SEQ TIMER REGISTER BITS */
#define DA9052_SEQTIMER_SEQDUMMY 0XF0
#define DA9052_SEQTIMER_SEQTIME 0X0F
/*POWER SUPPLY CONTROL REGISTER BITS */
/* BUCK REGISTER A BITS */
#define DA9052_BUCKA_BPROILIM 0XC0
#define DA9052_BUCKA_BPROMODE 0X30
#define DA9052_BUCKA_BCOREILIM 0X0C
#define DA9052_BUCKA_BCOREMODE 0X03
/* BUCK REGISTER B BITS */
#define DA9052_BUCKB_BERIILIM 0XC0
#define DA9052_BUCKB_BPERIMODE 0X30
#define DA9052_BUCKB_BMEMILIM 0X0C
#define DA9052_BUCKB_BMEMMODE 0X03
/* BUCKCORE REGISTER BITS */
#define DA9052_BUCKCORE_BCORECONF 0X80
#define DA9052_BUCKCORE_BCOREEN 0X40
#define DA9052_BUCKCORE_VBCORE 0X3F
/* BUCKPRO REGISTER BITS */
#define DA9052_BUCKPRO_BPROCONF 0X80
#define DA9052_BUCKPRO_BPROEN 0X40
#define DA9052_BUCKPRO_VBPRO 0X3F
/* BUCKMEM REGISTER BITS */
#define DA9052_BUCKMEM_BMEMCONF 0X80
#define DA9052_BUCKMEM_BMEMEN 0X40
#define DA9052_BUCKMEM_VBMEM 0X3F
/* BUCKPERI REGISTER BITS */
#define DA9052_BUCKPERI_BPERICONF 0X80
#define DA9052_BUCKPERI_BPERIEN 0X40
#define DA9052_BUCKPERI_BPERIHS 0X20
#define DA9052_BUCKPERI_VBPERI 0X1F
/* LDO1 REGISTER BITS */
#define DA9052_LDO1_LDO1CONF 0X80
#define DA9052_LDO1_LDO1EN 0X40
#define DA9052_LDO1_VLDO1 0X1F
/* LDO2 REGISTER BITS */
#define DA9052_LDO2_LDO2CONF 0X80
#define DA9052_LDO2_LDO2EN 0X40
#define DA9052_LDO2_VLDO2 0X3F
/* LDO3 REGISTER BITS */
#define DA9052_LDO3_LDO3CONF 0X80
#define DA9052_LDO3_LDO3EN 0X40
#define DA9052_LDO3_VLDO3 0X3F
/* LDO4 REGISTER BITS */
#define DA9052_LDO4_LDO4CONF 0X80
#define DA9052_LDO4_LDO4EN 0X40
#define DA9052_LDO4_VLDO4 0X3F
/* LDO5 REGISTER BITS */
#define DA9052_LDO5_LDO5CONF 0X80
#define DA9052_LDO5_LDO5EN 0X40
#define DA9052_LDO5_VLDO5 0X3F
/* LDO6 REGISTER BITS */
#define DA9052_LDO6_LDO6CONF 0X80
#define DA9052_LDO6_LDO6EN 0X40
#define DA9052_LDO6_VLDO6 0X3F
/* LDO7 REGISTER BITS */
#define DA9052_LDO7_LDO7CONF 0X80
#define DA9052_LDO7_LDO7EN 0X40
#define DA9052_LDO7_VLDO7 0X3F
/* LDO8 REGISTER BITS */
#define DA9052_LDO8_LDO8CONF 0X80
#define DA9052_LDO8_LDO8EN 0X40
#define DA9052_LDO8_VLDO8 0X3F
/* LDO9 REGISTER BITS */
#define DA9052_LDO9_LDO9CONF 0X80
#define DA9052_LDO9_LDO9EN 0X40
#define DA9052_LDO9_VLDO9 0X3F
/* LDO10 REGISTER BITS */
#define DA9052_LDO10_LDO10CONF 0X80
#define DA9052_LDO10_LDO10EN 0X40
#define DA9052_LDO10_VLDO10 0X3F
/* SUPPLY REGISTER BITS */
#define DA9052_SUPPLY_VLOCK 0X80
#define DA9052_SUPPLY_VMEMSWEN 0X40
#define DA9052_SUPPLY_VPERISWEN 0X20
#define DA9052_SUPPLY_VLDO3GO 0X10
#define DA9052_SUPPLY_VLDO2GO 0X08
#define DA9052_SUPPLY_VBMEMGO 0X04
#define DA9052_SUPPLY_VBPROGO 0X02
#define DA9052_SUPPLY_VBCOREGO 0X01
/* PULLDOWN REGISTER BITS */
#define DA9052_PULLDOWN_LDO5PDDIS 0X20
#define DA9052_PULLDOWN_LDO2PDDIS 0X10
#define DA9052_PULLDOWN_LDO1PDDIS 0X08
#define DA9052_PULLDOWN_MEMPDDIS 0X04
#define DA9052_PULLDOWN_PROPDDIS 0X02
#define DA9052_PULLDOWN_COREPDDIS 0X01
/* BAT CHARGER REGISTER BITS */
/* CHARGER BUCK REGISTER BITS */
#define DA9052_CHGBUCK_CHGTEMP 0X80
#define DA9052_CHGBUCK_CHGUSBILIM 0X40
#define DA9052_CHGBUCK_CHGBUCKLP 0X20
#define DA9052_CHGBUCK_CHGBUCKEN 0X10
#define DA9052_CHGBUCK_ISETBUCK 0X0F
/* WAIT COUNTER REGISTER BITS */
#define DA9052_WAITCONT_WAITDIR 0X80
#define DA9052_WAITCONT_RTCCLOCK 0X40
#define DA9052_WAITCONT_WAITMODE 0X20
#define DA9052_WAITCONT_EN32KOUT 0X10
#define DA9052_WAITCONT_DELAYTIME 0X0F
/* ISET CONTROL REGISTER BITS */
#define DA9052_ISET_ISETDCIN 0XF0
#define DA9052_ISET_ISETVBUS 0X0F
/* BATTERY CHARGER CONTROL REGISTER BITS */
#define DA9052_BATCHG_ICHGPRE 0XC0
#define DA9052_BATCHG_ICHGBAT 0X3F
/* CHARGER COUNTER REGISTER BITS */
#define DA9052_CHG_CONT_VCHG_BAT 0XF8
#define DA9052_CHG_CONT_TCTR 0X07
/* INPUT CONTROL REGISTER BITS */
#define DA9052_INPUT_CONT_TCTR_MODE 0X80
#define DA9052_INPUT_CONT_VBUS_SUSP 0X10
#define DA9052_INPUT_CONT_DCIN_SUSP 0X08
/* CHARGING TIME REGISTER BITS */
#define DA9052_CHGTIME_CHGTIME 0XFF
/* BACKUP BATTERY CONTROL REGISTER BITS */
#define DA9052_BBATCONT_BCHARGERISET 0XF0
#define DA9052_BBATCONT_BCHARGERVSET 0X0F
/* LED REGISTERS BITS */
/* LED BOOST REGISTER BITS */
#define DA9052_BOOST_EBFAULT 0X80
#define DA9052_BOOST_MBFAULT 0X40
#define DA9052_BOOST_BOOSTFRQ 0X20
#define DA9052_BOOST_BOOSTILIM 0X10
#define DA9052_BOOST_LED3INEN 0X08
#define DA9052_BOOST_LED2INEN 0X04
#define DA9052_BOOST_LED1INEN 0X02
#define DA9052_BOOST_BOOSTEN 0X01
/* LED CONTROL REGISTER BITS */
#define DA9052_LEDCONT_SELLEDMODE 0X80
#define DA9052_LEDCONT_LED3ICONT 0X40
#define DA9052_LEDCONT_LED3RAMP 0X20
#define DA9052_LEDCONT_LED3EN 0X10
#define DA9052_LEDCONT_LED2RAMP 0X08
#define DA9052_LEDCONT_LED2EN 0X04
#define DA9052_LEDCONT_LED1RAMP 0X02
#define DA9052_LEDCONT_LED1EN 0X01
/* LEDMIN123 REGISTER BIT */
#define DA9052_LEDMIN123_LEDMINCURRENT 0XFF
/* LED1CONF REGISTER BIT */
#define DA9052_LED1CONF_LED1CURRENT 0XFF
/* LED2CONF REGISTER BIT */
#define DA9052_LED2CONF_LED2CURRENT 0XFF
/* LED3CONF REGISTER BIT */
#define DA9052_LED3CONF_LED3CURRENT 0XFF
/* LED COUNT REGISTER BIT */
#define DA9052_LED_CONT_DIM 0X80
/* ADC MAN REGISTERS BITS */
#define DA9052_ADC_MAN_MAN_CONV 0X10
#define DA9052_ADC_MAN_MUXSEL_VDDOUT 0X00
#define DA9052_ADC_MAN_MUXSEL_ICH 0X01
#define DA9052_ADC_MAN_MUXSEL_TBAT 0X02
#define DA9052_ADC_MAN_MUXSEL_VBAT 0X03
#define DA9052_ADC_MAN_MUXSEL_AD4 0X04
#define DA9052_ADC_MAN_MUXSEL_AD5 0X05
#define DA9052_ADC_MAN_MUXSEL_AD6 0X06
#define DA9052_ADC_MAN_MUXSEL_VBBAT 0X09
/* ADC CONTROL REGSISTERS BITS */
#define DA9052_ADCCONT_COMP1V2EN 0X80
#define DA9052_ADCCONT_ADCMODE 0X40
#define DA9052_ADCCONT_TBATISRCEN 0X20
#define DA9052_ADCCONT_AD4ISRCEN 0X10
#define DA9052_ADCCONT_AUTOAD6EN 0X08
#define DA9052_ADCCONT_AUTOAD5EN 0X04
#define DA9052_ADCCONT_AUTOAD4EN 0X02
#define DA9052_ADCCONT_AUTOVDDEN 0X01
/* ADC 10 BIT MANUAL CONVERSION RESULT LOW REGISTER */
#define DA9052_ADC_RES_LSB 0X03
/* ADC 10 BIT MANUAL CONVERSION RESULT HIGH REGISTER */
#define DA9052_ADCRESH_ADCRESMSB 0XFF
/* VDD RES REGSISTER BIT*/
#define DA9052_VDDRES_VDDOUTRES 0XFF
/* VDD MON REGSISTER BIT */
#define DA9052_VDDMON_VDDOUTMON 0XFF
/* ICHG_AV REGSISTER BIT */
#define DA9052_ICHGAV_ICHGAV 0XFF
/* ICHG_THD REGSISTER BIT */
#define DA9052_ICHGTHD_ICHGTHD 0XFF
/* ICHG_END REGSISTER BIT */
#define DA9052_ICHGEND_ICHGEND 0XFF
/* TBAT_RES REGSISTER BIT */
#define DA9052_TBATRES_TBATRES 0XFF
/* TBAT_HIGHP REGSISTER BIT */
#define DA9052_TBATHIGHP_TBATHIGHP 0XFF
/* TBAT_HIGHN REGSISTER BIT */
#define DA9052_TBATHIGHN_TBATHIGHN 0XFF
/* TBAT_LOW REGSISTER BIT */
#define DA9052_TBATLOW_TBATLOW 0XFF
/* T_OFFSET REGSISTER BIT */
#define DA9052_TOFFSET_TOFFSET 0XFF
/* ADCIN4_RES REGSISTER BIT */
#define DA9052_ADCIN4RES_ADCIN4RES 0XFF
/* ADCIN4_HIGH REGSISTER BIT */
#define DA9052_AUTO4HIGH_AUTO4HIGH 0XFF
/* ADCIN4_LOW REGSISTER BIT */
#define DA9052_AUTO4LOW_AUTO4LOW 0XFF
/* ADCIN5_RES REGSISTER BIT */
#define DA9052_ADCIN5RES_ADCIN5RES 0XFF
/* ADCIN5_HIGH REGSISTER BIT */
#define DA9052_AUTO5HIGH_AUTOHIGH 0XFF
/* ADCIN5_LOW REGSISTER BIT */
#define DA9052_AUTO5LOW_AUTO5LOW 0XFF
/* ADCIN6_RES REGSISTER BIT */
#define DA9052_ADCIN6RES_ADCIN6RES 0XFF
/* ADCIN6_HIGH REGSISTER BIT */
#define DA9052_AUTO6HIGH_AUTO6HIGH 0XFF
/* ADCIN6_LOW REGSISTER BIT */
#define DA9052_AUTO6LOW_AUTO6LOW 0XFF
/* TJUNC_RES REGSISTER BIT*/
#define DA9052_TJUNCRES_TJUNCRES 0XFF
/* TSI REGISTER */
/* TSI CONTROL REGISTER A BITS */
#define DA9052_TSICONTA_TSIDELAY 0XC0
#define DA9052_TSICONTA_TSISKIP 0X38
#define DA9052_TSICONTA_TSIMODE 0X04
#define DA9052_TSICONTA_PENDETEN 0X02
#define DA9052_TSICONTA_AUTOTSIEN 0X01
/* TSI CONTROL REGISTER B BITS */
#define DA9052_TSICONTB_ADCREF 0X80
#define DA9052_TSICONTB_TSIMAN 0X40
#define DA9052_TSICONTB_TSIMUX 0X30
#define DA9052_TSICONTB_TSISEL3 0X08
#define DA9052_TSICONTB_TSISEL2 0X04
#define DA9052_TSICONTB_TSISEL1 0X02
#define DA9052_TSICONTB_TSISEL0 0X01
/* TSI X CO-ORDINATE MSB RESULT REGISTER BITS */
#define DA9052_TSIXMSB_TSIXM 0XFF
/* TSI Y CO-ORDINATE MSB RESULT REGISTER BITS */
#define DA9052_TSIYMSB_TSIYM 0XFF
/* TSI CO-ORDINATE LSB RESULT REGISTER BITS */
#define DA9052_TSILSB_PENDOWN 0X40
#define DA9052_TSILSB_TSIZL 0X30
#define DA9052_TSILSB_TSIYL 0X0C
#define DA9052_TSILSB_TSIXL 0X03
/* TSI Z MEASUREMENT MSB RESULT REGISTER BIT */
#define DA9052_TSIZMSB_TSIZM 0XFF
/* RTC REGISTER */
/* RTC TIMER SECONDS REGISTER BITS */
#define DA9052_COUNTS_MONITOR 0X40
#define DA9052_RTC_SEC 0X3F
/* RTC TIMER MINUTES REGISTER BIT */
#define DA9052_RTC_MIN 0X3F
/* RTC TIMER HOUR REGISTER BIT */
#define DA9052_RTC_HOUR 0X1F
/* RTC TIMER DAYS REGISTER BIT */
#define DA9052_RTC_DAY 0X1F
/* RTC TIMER MONTHS REGISTER BIT */
#define DA9052_RTC_MONTH 0X0F
/* RTC TIMER YEARS REGISTER BIT */
#define DA9052_RTC_YEAR 0X3F
/* RTC ALARM MINUTES REGISTER BITS */
#define DA9052_ALARMM_I_TICK_TYPE 0X80
#define DA9052_ALARMMI_ALARMTYPE 0X40
/* RTC ALARM YEARS REGISTER BITS */
#define DA9052_ALARM_Y_TICK_ON 0X80
#define DA9052_ALARM_Y_ALARM_ON 0X40
/* RTC SECONDS REGISTER A BITS */
#define DA9052_SECONDA_SECONDSA 0XFF
/* RTC SECONDS REGISTER B BITS */
#define DA9052_SECONDB_SECONDSB 0XFF
/* RTC SECONDS REGISTER C BITS */
#define DA9052_SECONDC_SECONDSC 0XFF
/* RTC SECONDS REGISTER D BITS */
#define DA9052_SECONDD_SECONDSD 0XFF
#endif
/* __LINUX_MFD_DA9052_REG_H */
kernel/include/linux/mfd/davinci_voicecodec.h
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/*
* DaVinci Voice Codec Core Interface for TI platforms
*
* Copyright (C) 2010 Texas Instruments, Inc
*
* Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __LINUX_MFD_DAVINCI_VOICECODEC_H_
#define __LINUX_MFD_DAVINIC_VOICECODEC_H_
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mfd/core.h>
#include <mach/edma.h>
/*
* Register values.
*/
#define DAVINCI_VC_PID 0x00
#define DAVINCI_VC_CTRL 0x04
#define DAVINCI_VC_INTEN 0x08
#define DAVINCI_VC_INTSTATUS 0x0c
#define DAVINCI_VC_INTCLR 0x10
#define DAVINCI_VC_EMUL_CTRL 0x14
#define DAVINCI_VC_RFIFO 0x20
#define DAVINCI_VC_WFIFO 0x24
#define DAVINCI_VC_FIFOSTAT 0x28
#define DAVINCI_VC_TST_CTRL 0x2C
#define DAVINCI_VC_REG05 0x94
#define DAVINCI_VC_REG09 0xA4
#define DAVINCI_VC_REG12 0xB0
/* DAVINCI_VC_CTRL bit fields */
#define DAVINCI_VC_CTRL_MASK 0x5500
#define DAVINCI_VC_CTRL_RSTADC BIT(0)
#define DAVINCI_VC_CTRL_RSTDAC BIT(1)
#define DAVINCI_VC_CTRL_RD_BITS_8 BIT(4)
#define DAVINCI_VC_CTRL_RD_UNSIGNED BIT(5)
#define DAVINCI_VC_CTRL_WD_BITS_8 BIT(6)
#define DAVINCI_VC_CTRL_WD_UNSIGNED BIT(7)
#define DAVINCI_VC_CTRL_RFIFOEN BIT(8)
#define DAVINCI_VC_CTRL_RFIFOCL BIT(9)
#define DAVINCI_VC_CTRL_RFIFOMD_WORD_1 BIT(10)
#define DAVINCI_VC_CTRL_WFIFOEN BIT(12)
#define DAVINCI_VC_CTRL_WFIFOCL BIT(13)
#define DAVINCI_VC_CTRL_WFIFOMD_WORD_1 BIT(14)
/* DAVINCI_VC_INT bit fields */
#define DAVINCI_VC_INT_MASK 0x3F
#define DAVINCI_VC_INT_RDRDY_MASK BIT(0)
#define DAVINCI_VC_INT_RERROVF_MASK BIT(1)
#define DAVINCI_VC_INT_RERRUDR_MASK BIT(2)
#define DAVINCI_VC_INT_WDREQ_MASK BIT(3)
#define DAVINCI_VC_INT_WERROVF_MASKBIT BIT(4)
#define DAVINCI_VC_INT_WERRUDR_MASK BIT(5)
/* DAVINCI_VC_REG05 bit fields */
#define DAVINCI_VC_REG05_PGA_GAIN 0x07
/* DAVINCI_VC_REG09 bit fields */
#define DAVINCI_VC_REG09_MUTE 0x40
#define DAVINCI_VC_REG09_DIG_ATTEN 0x3F
/* DAVINCI_VC_REG12 bit fields */
#define DAVINCI_VC_REG12_POWER_ALL_ON 0xFD
#define DAVINCI_VC_REG12_POWER_ALL_OFF 0x00
#define DAVINCI_VC_CELLS 2
enum davinci_vc_cells {
DAVINCI_VC_VCIF_CELL,
DAVINCI_VC_CQ93VC_CELL,
};
struct davinci_vcif {
struct platform_device *pdev;
u32 dma_tx_channel;
u32 dma_rx_channel;
dma_addr_t dma_tx_addr;
dma_addr_t dma_rx_addr;
};
struct cq93vc {
struct platform_device *pdev;
struct snd_soc_codec *codec;
u32 sysclk;
};
struct davinci_vc;
struct davinci_vc {
/* Device data */
struct device *dev;
struct platform_device *pdev;
struct clk *clk;
/* Memory resources */
void __iomem *base;
resource_size_t pbase;
size_t base_size;
/* MFD cells */
struct mfd_cell cells[DAVINCI_VC_CELLS];
/* Client devices */
struct davinci_vcif davinci_vcif;
struct cq93vc cq93vc;
};
#endif
kernel/include/linux/mfd/db5500-prcmu.h
+105
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/*
* Copyright (C) ST-Ericsson SA 2010
*
* License Terms: GNU General Public License v2
*
* U5500 PRCMU API.
*/
#ifndef __MFD_DB5500_PRCMU_H
#define __MFD_DB5500_PRCMU_H
static inline int prcmu_resetout(u8 resoutn, u8 state)
{
return 0;
}
static inline int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state)
{
return 0;
}
static inline int db5500_prcmu_request_clock(u8 clock, bool enable)
{
return 0;
}
static inline int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
bool keep_ap_pll)
{
return 0;
}
static inline int db5500_prcmu_config_esram0_deep_sleep(u8 state)
{
return 0;
}
static inline u16 db5500_prcmu_get_reset_code(void)
{
return 0;
}
static inline bool db5500_prcmu_is_ac_wake_requested(void)
{
return 0;
}
static inline int db5500_prcmu_set_arm_opp(u8 opp)
{
return 0;
}
static inline int db5500_prcmu_get_arm_opp(void)
{
return 0;
}
static inline void db5500_prcmu_config_abb_event_readout(u32 abb_events) {}
static inline void db5500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
static inline void db5500_prcmu_system_reset(u16 reset_code) {}
static inline void db5500_prcmu_enable_wakeups(u32 wakeups) {}
#ifdef CONFIG_MFD_DB5500_PRCMU
void db5500_prcmu_early_init(void);
int db5500_prcmu_set_display_clocks(void);
int db5500_prcmu_disable_dsipll(void);
int db5500_prcmu_enable_dsipll(void);
int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
#else /* !CONFIG_UX500_SOC_DB5500 */
static inline void db5500_prcmu_early_init(void) {}
static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
{
return -ENOSYS;
}
static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
{
return -ENOSYS;
}
static inline int db5500_prcmu_set_display_clocks(void)
{
return 0;
}
static inline int db5500_prcmu_disable_dsipll(void)
{
return 0;
}
static inline int db5500_prcmu_enable_dsipll(void)
{
return 0;
}
#endif /* CONFIG_MFD_DB5500_PRCMU */
#endif /* __MFD_DB5500_PRCMU_H */
kernel/include/linux/mfd/db8500-prcmu.h
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/*
* Copyright (C) STMicroelectronics 2009
* Copyright (C) ST-Ericsson SA 2010
*
* License Terms: GNU General Public License v2
* Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
*
* PRCMU f/w APIs
*/
#ifndef __MFD_DB8500_PRCMU_H
#define __MFD_DB8500_PRCMU_H
#include <linux/interrupt.h>
#include <linux/bitops.h>
/*
* Registers
*/
#define DB8500_PRCM_GPIOCR 0x138
#define DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0 BIT(0)
#define DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD BIT(9)
#define DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 BIT(11)
#define DB8500_PRCM_GPIOCR_SPI2_SELECT BIT(23)
#define DB8500_PRCM_LINE_VALUE 0x170
#define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0 BIT(3)
#define DB8500_PRCM_DSI_SW_RESET 0x324
#define DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0)
#define DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)
#define DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)
/* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
/**
* enum state - ON/OFF state definition
* @OFF: State is ON
* @ON: State is OFF
*
*/
enum state {
OFF = 0x0,
ON = 0x1,
};
/**
* enum ret_state - general purpose On/Off/Retention states
*
*/
enum ret_state {
OFFST = 0,
ONST = 1,
RETST = 2
};
/**
* enum clk_arm - ARM Cortex A9 clock schemes
* @A9_OFF:
* @A9_BOOT:
* @A9_OPPT1:
* @A9_OPPT2:
* @A9_EXTCLK:
*/
enum clk_arm {
A9_OFF,
A9_BOOT,
A9_OPPT1,
A9_OPPT2,
A9_EXTCLK
};
/**
* enum clk_gen - GEN#0/GEN#1 clock schemes
* @GEN_OFF:
* @GEN_BOOT:
* @GEN_OPPT1:
*/
enum clk_gen {
GEN_OFF,
GEN_BOOT,
GEN_OPPT1,
};
/* some information between arm and xp70 */
/**
* enum romcode_write - Romcode message written by A9 AND read by XP70
* @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70
* @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the
* romcode. The xp70 will go into self-reset
*/
enum romcode_write {
RDY_2_DS = 0x09,
RDY_2_XP70_RST = 0x10
};
/**
* enum romcode_read - Romcode message written by XP70 and read by A9
* @INIT: Init value when romcode field is not used
* @FS_2_DS: Value set when power state is going from ApExecute to
* ApDeepSleep
* @END_DS: Value set when ApDeepSleep power state is reached coming from
* ApExecute state
* @DS_TO_FS: Value set when power state is going from ApDeepSleep to
* ApExecute
* @END_FS: Value set when ApExecute power state is reached coming from
* ApDeepSleep state
* @SWR: Value set when power state is going to ApReset
* @END_SWR: Value set when the xp70 finished executing ApReset actions and
* waits for romcode acknowledgment to go to self-reset
*/
enum romcode_read {
INIT = 0x00,
FS_2_DS = 0x0A,
END_DS = 0x0B,
DS_TO_FS = 0x0C,
END_FS = 0x0D,
SWR = 0x0E,
END_SWR = 0x0F
};
/**
* enum ap_pwrst - current power states defined in PRCMU firmware
* @NO_PWRST: Current power state init
* @AP_BOOT: Current power state is apBoot
* @AP_EXECUTE: Current power state is apExecute
* @AP_DEEP_SLEEP: Current power state is apDeepSleep
* @AP_SLEEP: Current power state is apSleep
* @AP_IDLE: Current power state is apIdle
* @AP_RESET: Current power state is apReset
*/
enum ap_pwrst {
NO_PWRST = 0x00,
AP_BOOT = 0x01,
AP_EXECUTE = 0x02,
AP_DEEP_SLEEP = 0x03,
AP_SLEEP = 0x04,
AP_IDLE = 0x05,
AP_RESET = 0x06
};
/**
* enum ap_pwrst_trans - Transition states defined in PRCMU firmware
* @NO_TRANSITION: No power state transition
* @APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep
* @APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep
* @APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute
* @APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to
* ApDeepSleep
* @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle
*/
enum ap_pwrst_trans {
PRCMU_AP_NO_CHANGE = 0x00,
APEXECUTE_TO_APSLEEP = 0x01,
APIDLE_TO_APSLEEP = 0x02, /* To be removed */
PRCMU_AP_SLEEP = 0x01,
APBOOT_TO_APEXECUTE = 0x03,
APEXECUTE_TO_APDEEPSLEEP = 0x04, /* To be removed */
PRCMU_AP_DEEP_SLEEP = 0x04,
APEXECUTE_TO_APIDLE = 0x05, /* To be removed */
PRCMU_AP_IDLE = 0x05,
PRCMU_AP_DEEP_IDLE = 0x07,
};
/**
* enum hw_acc_state - State definition for hardware accelerator
* @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
* @HW_OFF: The hardware accelerator must be switched off
* @HW_OFF_RAMRET: The hardware accelerator must be switched off with its
* internal RAM in retention
* @HW_ON: The hwa hardware accelerator hwa must be switched on
*
* NOTE! Deprecated, to be removed when all users switched over to use the
* regulator API.
*/
enum hw_acc_state {
HW_NO_CHANGE = 0x00,
HW_OFF = 0x01,
HW_OFF_RAMRET = 0x02,
HW_ON = 0x04
};
/**
* enum mbox_2_arm_stat - Status messages definition for mbox_arm
* @BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been
* completed
* @DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been
* completed
* @SLEEPOK: The apExecute to apSleep state transition has been completed
* @IDLEOK: The apExecute to apIdle state transition has been completed
* @SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed
* @SOFTRESETGO : The A9 watchdog/SoftReset state is on going
* @BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going
* @EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on
* going
* @DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on
* going
* @DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has
* been completed
* @EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going
* @SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going
* @SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been
* completed
* @EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going
* @IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going
* @IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been
* completed
* @INIT_STATUS: Status init
*/
enum ap_pwrsttr_status {
BOOT_TO_EXECUTEOK = 0xFF,
DEEPSLEEPOK = 0xFE,
SLEEPOK = 0xFD,
IDLEOK = 0xFC,
SOFTRESETOK = 0xFB,
SOFTRESETGO = 0xFA,
BOOT_TO_EXECUTE = 0xF9,
EXECUTE_TO_DEEPSLEEP = 0xF8,
DEEPSLEEP_TO_EXECUTE = 0xF7,
DEEPSLEEP_TO_EXECUTEOK = 0xF6,
EXECUTE_TO_SLEEP = 0xF5,
SLEEP_TO_EXECUTE = 0xF4,
SLEEP_TO_EXECUTEOK = 0xF3,
EXECUTE_TO_IDLE = 0xF2,
IDLE_TO_EXECUTE = 0xF1,
IDLE_TO_EXECUTEOK = 0xF0,
RDYTODS_RETURNTOEXE = 0xEF,
NORDYTODS_RETURNTOEXE = 0xEE,
EXETOSLEEP_RETURNTOEXE = 0xED,
EXETOIDLE_RETURNTOEXE = 0xEC,
INIT_STATUS = 0xEB,
/*error messages */
INITERROR = 0x00,
PLLARMLOCKP_ER = 0x01,
PLLDDRLOCKP_ER = 0x02,
PLLSOCLOCKP_ER = 0x03,
PLLSOCK1LOCKP_ER = 0x04,
ARMWFI_ER = 0x05,
SYSCLKOK_ER = 0x06,
I2C_NACK_DATA_ER = 0x07,
BOOT_ER = 0x08,
I2C_STATUS_ALWAYS_1 = 0x0A,
I2C_NACK_REG_ADDR_ER = 0x0B,
I2C_NACK_DATA0123_ER = 0x1B,
I2C_NACK_ADDR_ER = 0x1F,
CURAPPWRSTISNOT_BOOT = 0x20,
CURAPPWRSTISNOT_EXECUTE = 0x21,
CURAPPWRSTISNOT_SLEEPMODE = 0x22,
CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23,
FIFO4500WUISNOT_WUPEVENT = 0x24,
PLL32KLOCKP_ER = 0x29,
DDRDEEPSLEEPOK_ER = 0x2A,
ROMCODEREADY_ER = 0x50,
WUPBEFOREDS = 0x51,
DDRCONFIG_ER = 0x52,
WUPBEFORESLEEP = 0x53,
WUPBEFOREIDLE = 0x54
}; /* earlier called as mbox_2_arm_stat */
/**
* enum dvfs_stat - DVFS status messages definition
* @DVFS_GO: A state transition DVFS is on going
* @DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP
* @DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP
* @DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK
* @DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for
* NOCHGCLK
* @DVFS_INITSTATUS: Value init
*/
enum dvfs_stat {
DVFS_GO = 0xFF,
DVFS_ARM100OPPOK = 0xFE,
DVFS_ARM50OPPOK = 0xFD,
DVFS_ARMEXTCLKOK = 0xFC,
DVFS_NOCHGTCLKOK = 0xFB,
DVFS_INITSTATUS = 0x00
};
/**
* enum sva_mmdsp_stat - SVA MMDSP status messages
* @SVA_MMDSP_GO: SVAMMDSP interrupt has happened
* @SVA_MMDSP_INIT: Status init
*/
enum sva_mmdsp_stat {
SVA_MMDSP_GO = 0xFF,
SVA_MMDSP_INIT = 0x00
};
/**
* enum sia_mmdsp_stat - SIA MMDSP status messages
* @SIA_MMDSP_GO: SIAMMDSP interrupt has happened
* @SIA_MMDSP_INIT: Status init
*/
enum sia_mmdsp_stat {
SIA_MMDSP_GO = 0xFF,
SIA_MMDSP_INIT = 0x00
};
/**
* enum mbox_to_arm_err - Error messages definition
* @INIT_ERR: Init value
* @PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time
* @PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time
* @PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time
* @PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time
* @ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time
* @SYSCLKOK_ERR: The SYSCLK is not available in the given time
* @BOOT_ERR: Romcode has not validated the XP70 self reset in the given time
* @ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context
* @VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered
* through I2C has not been correctly executed in the given time
* @VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered
* through I2C has not been correctly executed in the given time
* @VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through
* I2C has not been correctly executed in the given time
* @VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered
* through I2C has not been correctly executed in the given time
* @VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through
* I2C has not been correctly executed in the given time
* @VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered
* through I2C has not been correctly executed in the given time
* @VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through
* I2C has not been correctly executed in the given time
* @VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C
* has not been correctly executed in the given time
* @VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has
* not been correctly executed in the given time
* @VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has
* not been correctly executed in the given time
* @VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through
* I2C has not been correctly executed in the given time
* @VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through
* I2C has not been correctly executed in the given time
* @VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered
* through I2C has not been correctly executed in the given time
* @CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition
* ApBoot to ApExecute but the power current state is not Apboot
* @CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state
* transition from ApExecute to others power state but the
* power current state is not ApExecute
* @CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted
* but the power current state is not ApDeepSleep/ApSleep/ApIdle
* @CURAPPWRSTISNOTCORRECTDBG: Generated when wake up events are transmitted
* but the power current state is not correct
* @ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not
* been correctly executed in the given time
* @ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not
* been correctly executed in the given time
* @VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not
* been correctly executed in the given time
* @VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not
* been correctly executed in the given time
* @VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not
* been correctly executed in the given time
*/
enum mbox_to_arm_err {
INIT_ERR = 0x00,
PLLARMLOCKP_ERR = 0x01,
PLLDDRLOCKP_ERR = 0x02,
PLLSOC0LOCKP_ERR = 0x03,
PLLSOC1LOCKP_ERR = 0x04,
ARMWFI_ERR = 0x05,
SYSCLKOK_ERR = 0x06,
BOOT_ERR = 0x07,
ROMCODESAVECONTEXT = 0x08,
VARMHIGHSPEEDVALTO_ERR = 0x10,
VARMHIGHSPEEDACCESS_ERR = 0x11,
VARMLOWSPEEDVALTO_ERR = 0x12,
VARMLOWSPEEDACCESS_ERR = 0x13,
VARMRETENTIONVALTO_ERR = 0x14,
VARMRETENTIONACCESS_ERR = 0x15,
VAPEHIGHSPEEDVALTO_ERR = 0x16,
VSAFEHPVALTO_ERR = 0x17,
VMODSEL1VALTO_ERR = 0x18,
VMODSEL2VALTO_ERR = 0x19,
VARMOFFACCESS_ERR = 0x1A,
VAPEOFFACCESS_ERR = 0x1B,
VARMRETACCES_ERR = 0x1C,
CURAPPWRSTISNOTBOOT = 0x20,
CURAPPWRSTISNOTEXECUTE = 0x21,
CURAPPWRSTISNOTSLEEPMODE = 0x22,
CURAPPWRSTISNOTCORRECTDBG = 0x23,
ARMREGU1VALTO_ERR = 0x24,
ARMREGU2VALTO_ERR = 0x25,
VAPEREGUVALTO_ERR = 0x26,
VSMPS3REGUVALTO_ERR = 0x27,
VMODREGUVALTO_ERR = 0x28
};
enum hw_acc {
SVAMMDSP = 0,
SVAPIPE = 1,
SIAMMDSP = 2,
SIAPIPE = 3,
SGA = 4,
B2R2MCDE = 5,
ESRAM12 = 6,
ESRAM34 = 7,
};
enum cs_pwrmgt {
PWRDNCS0 = 0,
WKUPCS0 = 1,
PWRDNCS1 = 2,
WKUPCS1 = 3
};
/* Defs related to autonomous power management */
/**
* enum sia_sva_pwr_policy - Power policy
* @NO_CHGT: No change
* @DSPOFF_HWPOFF:
* @DSPOFFRAMRET_HWPOFF:
* @DSPCLKOFF_HWPOFF:
* @DSPCLKOFF_HWPCLKOFF:
*
*/
enum sia_sva_pwr_policy {
NO_CHGT = 0x0,
DSPOFF_HWPOFF = 0x1,
DSPOFFRAMRET_HWPOFF = 0x2,
DSPCLKOFF_HWPOFF = 0x3,
DSPCLKOFF_HWPCLKOFF = 0x4,
};
/**
* enum auto_enable - Auto Power enable
* @AUTO_OFF:
* @AUTO_ON:
*
*/
enum auto_enable {
AUTO_OFF = 0x0,
AUTO_ON = 0x1,
};
/* End of file previously known as prcmu-fw-defs_v1.h */
/**
* enum prcmu_power_status - results from set_power_state
* @PRCMU_SLEEP_OK: Sleep went ok
* @PRCMU_DEEP_SLEEP_OK: DeepSleep went ok
* @PRCMU_IDLE_OK: Idle went ok
* @PRCMU_DEEPIDLE_OK: DeepIdle went ok
* @PRCMU_PRCMU2ARMPENDINGIT_ER: Pending interrupt detected
* @PRCMU_ARMPENDINGIT_ER: Pending interrupt detected
*
*/
enum prcmu_power_status {
PRCMU_SLEEP_OK = 0xf3,
PRCMU_DEEP_SLEEP_OK = 0xf6,
PRCMU_IDLE_OK = 0xf0,
PRCMU_DEEPIDLE_OK = 0xe3,
PRCMU_PRCMU2ARMPENDINGIT_ER = 0x91,
PRCMU_ARMPENDINGIT_ER = 0x93,
};
/*
* Definitions for autonomous power management configuration.
*/
#define PRCMU_AUTO_PM_OFF 0
#define PRCMU_AUTO_PM_ON 1
#define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0)
#define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1)
enum prcmu_auto_pm_policy {
PRCMU_AUTO_PM_POLICY_NO_CHANGE,
PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF,
PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF,
PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF,
PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF,
};
/**
* struct prcmu_auto_pm_config - Autonomous power management configuration.
* @sia_auto_pm_enable: SIA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
* @sia_power_on: SIA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
* @sia_policy: SIA power policy. (enum prcmu_auto_pm_policy)
* @sva_auto_pm_enable: SVA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
* @sva_power_on: SVA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
* @sva_policy: SVA power policy. (enum prcmu_auto_pm_policy)
*/
struct prcmu_auto_pm_config {
u8 sia_auto_pm_enable;
u8 sia_power_on;
u8 sia_policy;
u8 sva_auto_pm_enable;
u8 sva_power_on;
u8 sva_policy;
};
#define PRCMU_FW_PROJECT_U8500 2
#define PRCMU_FW_PROJECT_U9500 4
#define PRCMU_FW_PROJECT_U8500_C2 7
#define PRCMU_FW_PROJECT_U9500_C2 11
#define PRCMU_FW_PROJECT_U8520 13
#define PRCMU_FW_PROJECT_U8420 14
struct prcmu_fw_version {
u8 project;
u8 api_version;
u8 func_version;
u8 errata;
};
#ifdef CONFIG_MFD_DB8500_PRCMU
void db8500_prcmu_early_init(void);
int prcmu_set_rc_a2p(enum romcode_write);
enum romcode_read prcmu_get_rc_p2a(void);
enum ap_pwrst prcmu_get_xp70_current_state(void);
bool prcmu_has_arm_maxopp(void);
struct prcmu_fw_version *prcmu_get_fw_version(void);
int prcmu_request_ape_opp_100_voltage(bool enable);
int prcmu_release_usb_wakeup_state(void);
void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
struct prcmu_auto_pm_config *idle);
bool prcmu_is_auto_pm_enabled(void);
int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
int prcmu_set_clock_divider(u8 clock, u8 divider);
int db8500_prcmu_config_hotdog(u8 threshold);
int db8500_prcmu_config_hotmon(u8 low, u8 high);
int db8500_prcmu_start_temp_sense(u16 cycles32k);
int db8500_prcmu_stop_temp_sense(void);
int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
void prcmu_ac_wake_req(void);
void prcmu_ac_sleep_req(void);
void db8500_prcmu_modem_reset(void);
int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
int db8500_prcmu_enable_a9wdog(u8 id);
int db8500_prcmu_disable_a9wdog(u8 id);
int db8500_prcmu_kick_a9wdog(u8 id);
int db8500_prcmu_load_a9wdog(u8 id, u32 val);
void db8500_prcmu_system_reset(u16 reset_code);
int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
u8 db8500_prcmu_get_power_state_result(void);
int db8500_prcmu_gic_decouple(void);
int db8500_prcmu_gic_recouple(void);
int db8500_prcmu_copy_gic_settings(void);
bool db8500_prcmu_gic_pending_irq(void);
bool db8500_prcmu_pending_irq(void);
bool db8500_prcmu_is_cpu_in_wfi(int cpu);
void db8500_prcmu_enable_wakeups(u32 wakeups);
int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
int db8500_prcmu_request_clock(u8 clock, bool enable);
int db8500_prcmu_set_display_clocks(void);
int db8500_prcmu_disable_dsipll(void);
int db8500_prcmu_enable_dsipll(void);
void db8500_prcmu_config_abb_event_readout(u32 abb_events);
void db8500_prcmu_get_abb_event_buffer(void __iomem **buf);
int db8500_prcmu_config_esram0_deep_sleep(u8 state);
u16 db8500_prcmu_get_reset_code(void);
bool db8500_prcmu_is_ac_wake_requested(void);
int db8500_prcmu_set_arm_opp(u8 opp);
int db8500_prcmu_get_arm_opp(void);
int db8500_prcmu_set_ape_opp(u8 opp);
int db8500_prcmu_get_ape_opp(void);
int db8500_prcmu_set_ddr_opp(u8 opp);
int db8500_prcmu_get_ddr_opp(void);
u32 db8500_prcmu_read(unsigned int reg);
void db8500_prcmu_write(unsigned int reg, u32 value);
void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value);
#else /* !CONFIG_MFD_DB8500_PRCMU */
static inline void db8500_prcmu_early_init(void) {}
static inline int prcmu_set_rc_a2p(enum romcode_write code)
{
return 0;
}
static inline enum romcode_read prcmu_get_rc_p2a(void)
{
return INIT;
}
static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
{
return AP_EXECUTE;
}
static inline bool prcmu_has_arm_maxopp(void)
{
return false;
}
static inline struct prcmu_fw_version *prcmu_get_fw_version(void)
{
return NULL;
}
static inline int db8500_prcmu_set_ape_opp(u8 opp)
{
return 0;
}
static inline int db8500_prcmu_get_ape_opp(void)
{
return APE_100_OPP;
}
static inline int prcmu_request_ape_opp_100_voltage(bool enable)
{
return 0;
}
static inline int prcmu_release_usb_wakeup_state(void)
{
return 0;
}
static inline int db8500_prcmu_set_ddr_opp(u8 opp)
{
return 0;
}
static inline int db8500_prcmu_get_ddr_opp(void)
{
return DDR_100_OPP;
}
static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
struct prcmu_auto_pm_config *idle)
{
}
static inline bool prcmu_is_auto_pm_enabled(void)
{
return false;
}
static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
{
return 0;
}
static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
{
return 0;
}
static inline int db8500_prcmu_config_hotdog(u8 threshold)
{
return 0;
}
static inline int db8500_prcmu_config_hotmon(u8 low, u8 high)
{
return 0;
}
static inline int db8500_prcmu_start_temp_sense(u16 cycles32k)
{
return 0;
}
static inline int db8500_prcmu_stop_temp_sense(void)
{
return 0;
}
static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
{
return -ENOSYS;
}
static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
{
return -ENOSYS;
}
static inline void prcmu_ac_wake_req(void) {}
static inline void prcmu_ac_sleep_req(void) {}
static inline void db8500_prcmu_modem_reset(void) {}
static inline void db8500_prcmu_system_reset(u16 reset_code) {}
static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
bool keep_ap_pll)
{
return 0;
}
static inline u8 db8500_prcmu_get_power_state_result(void)
{
return 0;
}
static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
{
return 0;
}
static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
{
return 0;
}
static inline int db8500_prcmu_set_display_clocks(void)
{
return 0;
}
static inline int db8500_prcmu_disable_dsipll(void)
{
return 0;
}
static inline int db8500_prcmu_enable_dsipll(void)
{
return 0;
}
static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state)
{
return 0;
}
static inline void db8500_prcmu_config_abb_event_readout(u32 abb_events) {}
static inline void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
static inline u16 db8500_prcmu_get_reset_code(void)
{
return 0;
}
static inline int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
{
return 0;
}
static inline int db8500_prcmu_enable_a9wdog(u8 id)
{
return 0;
}
static inline int db8500_prcmu_disable_a9wdog(u8 id)
{
return 0;
}
static inline int db8500_prcmu_kick_a9wdog(u8 id)
{
return 0;
}
static inline int db8500_prcmu_load_a9wdog(u8 id, u32 val)
{
return 0;
}
static inline bool db8500_prcmu_is_ac_wake_requested(void)
{
return 0;
}
static inline int db8500_prcmu_set_arm_opp(u8 opp)
{
return 0;
}
static inline int db8500_prcmu_get_arm_opp(void)
{
return 0;
}
static inline u32 db8500_prcmu_read(unsigned int reg)
{
return 0;
}
static inline void db8500_prcmu_write(unsigned int reg, u32 value) {}
static inline void db8500_prcmu_write_masked(unsigned int reg, u32 mask,
u32 value) {}
#endif /* !CONFIG_MFD_DB8500_PRCMU */
#endif /* __MFD_DB8500_PRCMU_H */
kernel/include/linux/mfd/dbx500-prcmu.h
+915
View File
@@ -0,0 +1,915 @@
/*
* Copyright (C) ST Ericsson SA 2011
*
* License Terms: GNU General Public License v2
*
* STE Ux500 PRCMU API
*/
#ifndef __MACH_PRCMU_H
#define __MACH_PRCMU_H
#include <linux/interrupt.h>
#include <linux/notifier.h>
#include <linux/err.h>
/* PRCMU Wakeup defines */
enum prcmu_wakeup_index {
PRCMU_WAKEUP_INDEX_RTC,
PRCMU_WAKEUP_INDEX_RTT0,
PRCMU_WAKEUP_INDEX_RTT1,
PRCMU_WAKEUP_INDEX_HSI0,
PRCMU_WAKEUP_INDEX_HSI1,
PRCMU_WAKEUP_INDEX_USB,
PRCMU_WAKEUP_INDEX_ABB,
PRCMU_WAKEUP_INDEX_ABB_FIFO,
PRCMU_WAKEUP_INDEX_ARM,
PRCMU_WAKEUP_INDEX_CD_IRQ,
NUM_PRCMU_WAKEUP_INDICES
};
#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
/* EPOD (power domain) IDs */
/*
* DB8500 EPODs
* - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
* - EPOD_ID_SVAPIPE: power domain for SVA pipe
* - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
* - EPOD_ID_SIAPIPE: power domain for SIA pipe
* - EPOD_ID_SGA: power domain for SGA
* - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
* - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
* - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
* - NUM_EPOD_ID: number of power domains
*
* TODO: These should be prefixed.
*/
#define EPOD_ID_SVAMMDSP 0
#define EPOD_ID_SVAPIPE 1
#define EPOD_ID_SIAMMDSP 2
#define EPOD_ID_SIAPIPE 3
#define EPOD_ID_SGA 4
#define EPOD_ID_B2R2_MCDE 5
#define EPOD_ID_ESRAM12 6
#define EPOD_ID_ESRAM34 7
#define NUM_EPOD_ID 8
/*
* DB5500 EPODs
*/
#define DB5500_EPOD_ID_BASE 0x0100
#define DB5500_EPOD_ID_SGA (DB5500_EPOD_ID_BASE + 0)
#define DB5500_EPOD_ID_HVA (DB5500_EPOD_ID_BASE + 1)
#define DB5500_EPOD_ID_SIA (DB5500_EPOD_ID_BASE + 2)
#define DB5500_EPOD_ID_DISP (DB5500_EPOD_ID_BASE + 3)
#define DB5500_EPOD_ID_ESRAM12 (DB5500_EPOD_ID_BASE + 6)
#define DB5500_NUM_EPOD_ID 7
/*
* state definition for EPOD (power domain)
* - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
* - EPOD_STATE_OFF: The EPOD is switched off
* - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
* retention
* - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
* - EPOD_STATE_ON: Same as above, but with clock enabled
*/
#define EPOD_STATE_NO_CHANGE 0x00
#define EPOD_STATE_OFF 0x01
#define EPOD_STATE_RAMRET 0x02
#define EPOD_STATE_ON_CLK_OFF 0x03
#define EPOD_STATE_ON 0x04
/* DB5500 CLKOUT IDs */
enum {
DB5500_CLKOUT0 = 0,
DB5500_CLKOUT1,
};
/* DB5500 CLKOUTx sources */
enum {
DB5500_CLKOUT_REF_CLK_SEL0,
DB5500_CLKOUT_RTC_CLK0_SEL0,
DB5500_CLKOUT_ULP_CLK_SEL0,
DB5500_CLKOUT_STATIC0,
DB5500_CLKOUT_REFCLK,
DB5500_CLKOUT_ULPCLK,
DB5500_CLKOUT_ARMCLK,
DB5500_CLKOUT_SYSACC0CLK,
DB5500_CLKOUT_SOC0PLLCLK,
DB5500_CLKOUT_SOC1PLLCLK,
DB5500_CLKOUT_DDRPLLCLK,
DB5500_CLKOUT_TVCLK,
DB5500_CLKOUT_IRDACLK,
};
/*
* CLKOUT sources
*/
#define PRCMU_CLKSRC_CLK38M 0x00
#define PRCMU_CLKSRC_ACLK 0x01
#define PRCMU_CLKSRC_SYSCLK 0x02
#define PRCMU_CLKSRC_LCDCLK 0x03
#define PRCMU_CLKSRC_SDMMCCLK 0x04
#define PRCMU_CLKSRC_TVCLK 0x05
#define PRCMU_CLKSRC_TIMCLK 0x06
#define PRCMU_CLKSRC_CLK009 0x07
/* These are only valid for CLKOUT1: */
#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
#define PRCMU_CLKSRC_I2CCLK 0x41
#define PRCMU_CLKSRC_MSP02CLK 0x42
#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
#define PRCMU_CLKSRC_HSIRXCLK 0x44
#define PRCMU_CLKSRC_HSITXCLK 0x45
#define PRCMU_CLKSRC_ARMCLKFIX 0x46
#define PRCMU_CLKSRC_HDMICLK 0x47
/*
* Clock identifiers.
*/
enum prcmu_clock {
PRCMU_SGACLK,
PRCMU_UARTCLK,
PRCMU_MSP02CLK,
PRCMU_MSP1CLK,
PRCMU_I2CCLK,
PRCMU_SDMMCCLK,
PRCMU_SPARE1CLK,
PRCMU_SLIMCLK,
PRCMU_PER1CLK,
PRCMU_PER2CLK,
PRCMU_PER3CLK,
PRCMU_PER5CLK,
PRCMU_PER6CLK,
PRCMU_PER7CLK,
PRCMU_LCDCLK,
PRCMU_BMLCLK,
PRCMU_HSITXCLK,
PRCMU_HSIRXCLK,
PRCMU_HDMICLK,
PRCMU_APEATCLK,
PRCMU_APETRACECLK,
PRCMU_MCDECLK,
PRCMU_IPI2CCLK,
PRCMU_DSIALTCLK,
PRCMU_DMACLK,
PRCMU_B2R2CLK,
PRCMU_TVCLK,
PRCMU_SSPCLK,
PRCMU_RNGCLK,
PRCMU_UICCCLK,
PRCMU_PWMCLK,
PRCMU_IRDACLK,
PRCMU_IRRCCLK,
PRCMU_SIACLK,
PRCMU_SVACLK,
PRCMU_ACLK,
PRCMU_NUM_REG_CLOCKS,
PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
PRCMU_CDCLK,
PRCMU_TIMCLK,
PRCMU_PLLSOC0,
PRCMU_PLLSOC1,
PRCMU_PLLDDR,
PRCMU_PLLDSI,
PRCMU_DSI0CLK,
PRCMU_DSI1CLK,
PRCMU_DSI0ESCCLK,
PRCMU_DSI1ESCCLK,
PRCMU_DSI2ESCCLK,
};
/**
* enum ape_opp - APE OPP states definition
* @APE_OPP_INIT:
* @APE_NO_CHANGE: The APE operating point is unchanged
* @APE_100_OPP: The new APE operating point is ape100opp
* @APE_50_OPP: 50%
* @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
*/
enum ape_opp {
APE_OPP_INIT = 0x00,
APE_NO_CHANGE = 0x01,
APE_100_OPP = 0x02,
APE_50_OPP = 0x03,
APE_50_PARTLY_25_OPP = 0xFF,
};
/**
* enum arm_opp - ARM OPP states definition
* @ARM_OPP_INIT:
* @ARM_NO_CHANGE: The ARM operating point is unchanged
* @ARM_100_OPP: The new ARM operating point is arm100opp
* @ARM_50_OPP: The new ARM operating point is arm50opp
* @ARM_MAX_OPP: Operating point is "max" (more than 100)
* @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
* @ARM_EXTCLK: The new ARM operating point is armExtClk
*/
enum arm_opp {
ARM_OPP_INIT = 0x00,
ARM_NO_CHANGE = 0x01,
ARM_100_OPP = 0x02,
ARM_50_OPP = 0x03,
ARM_MAX_OPP = 0x04,
ARM_MAX_FREQ100OPP = 0x05,
ARM_EXTCLK = 0x07
};
/**
* enum ddr_opp - DDR OPP states definition
* @DDR_100_OPP: The new DDR operating point is ddr100opp
* @DDR_50_OPP: The new DDR operating point is ddr50opp
* @DDR_25_OPP: The new DDR operating point is ddr25opp
*/
enum ddr_opp {
DDR_100_OPP = 0x00,
DDR_50_OPP = 0x01,
DDR_25_OPP = 0x02,
};
/*
* Definitions for controlling ESRAM0 in deep sleep.
*/
#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
#define ESRAM0_DEEP_SLEEP_STATE_RET 2
/**
* enum ddr_pwrst - DDR power states definition
* @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
* @DDR_PWR_STATE_ON:
* @DDR_PWR_STATE_OFFLOWLAT:
* @DDR_PWR_STATE_OFFHIGHLAT:
*/
enum ddr_pwrst {
DDR_PWR_STATE_UNCHANGED = 0x00,
DDR_PWR_STATE_ON = 0x01,
DDR_PWR_STATE_OFFLOWLAT = 0x02,
DDR_PWR_STATE_OFFHIGHLAT = 0x03
};
#include <linux/mfd/db8500-prcmu.h>
#include <linux/mfd/db5500-prcmu.h>
#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
#include <mach/id.h>
static inline void __init prcmu_early_init(void)
{
if (cpu_is_u5500())
return db5500_prcmu_early_init();
else
return db8500_prcmu_early_init();
}
static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
bool keep_ap_pll)
{
if (cpu_is_u5500())
return db5500_prcmu_set_power_state(state, keep_ulp_clk,
keep_ap_pll);
else
return db8500_prcmu_set_power_state(state, keep_ulp_clk,
keep_ap_pll);
}
static inline u8 prcmu_get_power_state_result(void)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_get_power_state_result();
}
static inline int prcmu_gic_decouple(void)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_gic_decouple();
}
static inline int prcmu_gic_recouple(void)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_gic_recouple();
}
static inline bool prcmu_gic_pending_irq(void)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_gic_pending_irq();
}
static inline bool prcmu_is_cpu_in_wfi(int cpu)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_is_cpu_in_wfi(cpu);
}
static inline int prcmu_copy_gic_settings(void)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_copy_gic_settings();
}
static inline bool prcmu_pending_irq(void)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_pending_irq();
}
static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_set_epod(epod_id, epod_state);
}
static inline void prcmu_enable_wakeups(u32 wakeups)
{
if (cpu_is_u5500())
db5500_prcmu_enable_wakeups(wakeups);
else
db8500_prcmu_enable_wakeups(wakeups);
}
static inline void prcmu_disable_wakeups(void)
{
prcmu_enable_wakeups(0);
}
static inline void prcmu_config_abb_event_readout(u32 abb_events)
{
if (cpu_is_u5500())
db5500_prcmu_config_abb_event_readout(abb_events);
else
db8500_prcmu_config_abb_event_readout(abb_events);
}
static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
{
if (cpu_is_u5500())
db5500_prcmu_get_abb_event_buffer(buf);
else
db8500_prcmu_get_abb_event_buffer(buf);
}
int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size);
int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
static inline int prcmu_request_clock(u8 clock, bool enable)
{
if (cpu_is_u5500())
return db5500_prcmu_request_clock(clock, enable);
else
return db8500_prcmu_request_clock(clock, enable);
}
unsigned long prcmu_clock_rate(u8 clock);
long prcmu_round_clock_rate(u8 clock, unsigned long rate);
int prcmu_set_clock_rate(u8 clock, unsigned long rate);
static inline int prcmu_set_ddr_opp(u8 opp)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_set_ddr_opp(opp);
}
static inline int prcmu_get_ddr_opp(void)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_get_ddr_opp();
}
static inline int prcmu_set_arm_opp(u8 opp)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_set_arm_opp(opp);
}
static inline int prcmu_get_arm_opp(void)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_get_arm_opp();
}
static inline int prcmu_set_ape_opp(u8 opp)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_set_ape_opp(opp);
}
static inline int prcmu_get_ape_opp(void)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_get_ape_opp();
}
static inline void prcmu_system_reset(u16 reset_code)
{
if (cpu_is_u5500())
return db5500_prcmu_system_reset(reset_code);
else
return db8500_prcmu_system_reset(reset_code);
}
static inline u16 prcmu_get_reset_code(void)
{
if (cpu_is_u5500())
return db5500_prcmu_get_reset_code();
else
return db8500_prcmu_get_reset_code();
}
void prcmu_ac_wake_req(void);
void prcmu_ac_sleep_req(void);
static inline void prcmu_modem_reset(void)
{
if (cpu_is_u5500())
return;
else
return db8500_prcmu_modem_reset();
}
static inline bool prcmu_is_ac_wake_requested(void)
{
if (cpu_is_u5500())
return db5500_prcmu_is_ac_wake_requested();
else
return db8500_prcmu_is_ac_wake_requested();
}
static inline int prcmu_set_display_clocks(void)
{
if (cpu_is_u5500())
return db5500_prcmu_set_display_clocks();
else
return db8500_prcmu_set_display_clocks();
}
static inline int prcmu_disable_dsipll(void)
{
if (cpu_is_u5500())
return db5500_prcmu_disable_dsipll();
else
return db8500_prcmu_disable_dsipll();
}
static inline int prcmu_enable_dsipll(void)
{
if (cpu_is_u5500())
return db5500_prcmu_enable_dsipll();
else
return db8500_prcmu_enable_dsipll();
}
static inline int prcmu_config_esram0_deep_sleep(u8 state)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_config_esram0_deep_sleep(state);
}
static inline int prcmu_config_hotdog(u8 threshold)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_config_hotdog(threshold);
}
static inline int prcmu_config_hotmon(u8 low, u8 high)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_config_hotmon(low, high);
}
static inline int prcmu_start_temp_sense(u16 cycles32k)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_start_temp_sense(cycles32k);
}
static inline int prcmu_stop_temp_sense(void)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_stop_temp_sense();
}
static inline u32 prcmu_read(unsigned int reg)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_read(reg);
}
static inline void prcmu_write(unsigned int reg, u32 value)
{
if (cpu_is_u5500())
return;
else
db8500_prcmu_write(reg, value);
}
static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
{
if (cpu_is_u5500())
return;
else
db8500_prcmu_write_masked(reg, mask, value);
}
static inline int prcmu_enable_a9wdog(u8 id)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_enable_a9wdog(id);
}
static inline int prcmu_disable_a9wdog(u8 id)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_disable_a9wdog(id);
}
static inline int prcmu_kick_a9wdog(u8 id)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_kick_a9wdog(id);
}
static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_load_a9wdog(id, timeout);
}
static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
{
if (cpu_is_u5500())
return -EINVAL;
else
return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
}
#else
static inline void __init prcmu_early_init(void) {}
static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
bool keep_ap_pll)
{
return 0;
}
static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
{
return 0;
}
static inline void prcmu_enable_wakeups(u32 wakeups) {}
static inline void prcmu_disable_wakeups(void) {}
static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
{
return -ENOSYS;
}
static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
{
return -ENOSYS;
}
static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
u8 size)
{
return -ENOSYS;
}
static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
{
return 0;
}
static inline int prcmu_request_clock(u8 clock, bool enable)
{
return 0;
}
static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
{
return 0;
}
static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
{
return 0;
}
static inline unsigned long prcmu_clock_rate(u8 clock)
{
return 0;
}
static inline int prcmu_set_ape_opp(u8 opp)
{
return 0;
}
static inline int prcmu_get_ape_opp(void)
{
return APE_100_OPP;
}
static inline int prcmu_set_arm_opp(u8 opp)
{
return 0;
}
static inline int prcmu_get_arm_opp(void)
{
return ARM_100_OPP;
}
static inline int prcmu_set_ddr_opp(u8 opp)
{
return 0;
}
static inline int prcmu_get_ddr_opp(void)
{
return DDR_100_OPP;
}
static inline void prcmu_system_reset(u16 reset_code) {}
static inline u16 prcmu_get_reset_code(void)
{
return 0;
}
static inline void prcmu_ac_wake_req(void) {}
static inline void prcmu_ac_sleep_req(void) {}
static inline void prcmu_modem_reset(void) {}
static inline bool prcmu_is_ac_wake_requested(void)
{
return false;
}
static inline int prcmu_set_display_clocks(void)
{
return 0;
}
static inline int prcmu_disable_dsipll(void)
{
return 0;
}
static inline int prcmu_enable_dsipll(void)
{
return 0;
}
static inline int prcmu_config_esram0_deep_sleep(u8 state)
{
return 0;
}
static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
{
*buf = NULL;
}
static inline int prcmu_config_hotdog(u8 threshold)
{
return 0;
}
static inline int prcmu_config_hotmon(u8 low, u8 high)
{
return 0;
}
static inline int prcmu_start_temp_sense(u16 cycles32k)
{
return 0;
}
static inline int prcmu_stop_temp_sense(void)
{
return 0;
}
static inline u32 prcmu_read(unsigned int reg)
{
return 0;
}
static inline void prcmu_write(unsigned int reg, u32 value) {}
static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
#endif
static inline void prcmu_set(unsigned int reg, u32 bits)
{
prcmu_write_masked(reg, bits, bits);
}
static inline void prcmu_clear(unsigned int reg, u32 bits)
{
prcmu_write_masked(reg, bits, 0);
}
#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
/**
* prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.
*/
static inline void prcmu_enable_spi2(void)
{
if (cpu_is_u8500())
prcmu_set(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
}
/**
* prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1.
*/
static inline void prcmu_disable_spi2(void)
{
if (cpu_is_u8500())
prcmu_clear(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT);
}
/**
* prcmu_enable_stm_mod_uart - Enables pin muxing for STMMOD
* and UARTMOD on OtherAlternateC3.
*/
static inline void prcmu_enable_stm_mod_uart(void)
{
if (cpu_is_u8500()) {
prcmu_set(DB8500_PRCM_GPIOCR,
(DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
}
}
/**
* prcmu_disable_stm_mod_uart - Disables pin muxing for STMMOD
* and UARTMOD on OtherAlternateC3.
*/
static inline void prcmu_disable_stm_mod_uart(void)
{
if (cpu_is_u8500()) {
prcmu_clear(DB8500_PRCM_GPIOCR,
(DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 |
DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0));
}
}
/**
* prcmu_enable_stm_ape - Enables pin muxing for STM APE on OtherAlternateC1.
*/
static inline void prcmu_enable_stm_ape(void)
{
if (cpu_is_u8500()) {
prcmu_set(DB8500_PRCM_GPIOCR,
DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
}
}
/**
* prcmu_disable_stm_ape - Disables pin muxing for STM APE on OtherAlternateC1.
*/
static inline void prcmu_disable_stm_ape(void)
{
if (cpu_is_u8500()) {
prcmu_clear(DB8500_PRCM_GPIOCR,
DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD);
}
}
#else
static inline void prcmu_enable_spi2(void) {}
static inline void prcmu_disable_spi2(void) {}
static inline void prcmu_enable_stm_mod_uart(void) {}
static inline void prcmu_disable_stm_mod_uart(void) {}
static inline void prcmu_enable_stm_ape(void) {}
static inline void prcmu_disable_stm_ape(void) {}
#endif
/* PRCMU QoS APE OPP class */
#define PRCMU_QOS_APE_OPP 1
#define PRCMU_QOS_DDR_OPP 2
#define PRCMU_QOS_ARM_OPP 3
#define PRCMU_QOS_DEFAULT_VALUE -1
#ifdef CONFIG_DBX500_PRCMU_QOS_POWER
unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
void prcmu_qos_force_opp(int, s32);
int prcmu_qos_requirement(int pm_qos_class);
int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
int prcmu_qos_add_notifier(int prcmu_qos_class,
struct notifier_block *notifier);
int prcmu_qos_remove_notifier(int prcmu_qos_class,
struct notifier_block *notifier);
#else
static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
{
return 0;
}
static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
static inline int prcmu_qos_requirement(int prcmu_qos_class)
{
return 0;
}
static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
char *name, s32 value)
{
return 0;
}
static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
char *name, s32 new_value)
{
return 0;
}
static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
{
}
static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
struct notifier_block *notifier)
{
return 0;
}
static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
struct notifier_block *notifier)
{
return 0;
}
#endif
#endif /* __MACH_PRCMU_H */
kernel/include/linux/mfd/ds1wm.h
+13
View File
@@ -0,0 +1,13 @@
/* MFD cell driver data for the DS1WM driver */
struct ds1wm_driver_data {
int active_high;
int clock_rate;
/* in milliseconds, the amount of time to */
/* sleep following a reset pulse. Zero */
/* should work if your bus devices recover*/
/* time respects the 1-wire spec since the*/
/* ds1wm implements the precise timings of*/
/* a reset pulse/presence detect sequence.*/
unsigned int reset_recover_delay;
};
kernel/include/linux/mfd/ezx-pcap.h
+252
View File
@@ -0,0 +1,252 @@
/*
* Copyright 2009 Daniel Ribeiro <drwyrm@gmail.com>
*
* For further information, please see http://wiki.openezx.org/PCAP2
*/
#ifndef EZX_PCAP_H
#define EZX_PCAP_H
struct pcap_subdev {
int id;
const char *name;
void *platform_data;
};
struct pcap_platform_data {
unsigned int irq_base;
unsigned int config;
void (*init) (void *); /* board specific init */
int num_subdevs;
struct pcap_subdev *subdevs;
};
struct pcap_chip;
int ezx_pcap_write(struct pcap_chip *, u8, u32);
int ezx_pcap_read(struct pcap_chip *, u8, u32 *);
int ezx_pcap_set_bits(struct pcap_chip *, u8, u32, u32);
int pcap_to_irq(struct pcap_chip *, int);
int irq_to_pcap(struct pcap_chip *, int);
int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *);
int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]);
void pcap_set_ts_bits(struct pcap_chip *, u32);
#define PCAP_SECOND_PORT 1
#define PCAP_CS_AH 2
#define PCAP_REGISTER_WRITE_OP_BIT 0x80000000
#define PCAP_REGISTER_READ_OP_BIT 0x00000000
#define PCAP_REGISTER_VALUE_MASK 0x01ffffff
#define PCAP_REGISTER_ADDRESS_MASK 0x7c000000
#define PCAP_REGISTER_ADDRESS_SHIFT 26
#define PCAP_REGISTER_NUMBER 32
#define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff
#define PCAP_MASK_ALL_INTERRUPT 0x01ffffff
/* registers accessible by both pcap ports */
#define PCAP_REG_ISR 0x0 /* Interrupt Status */
#define PCAP_REG_MSR 0x1 /* Interrupt Mask */
#define PCAP_REG_PSTAT 0x2 /* Processor Status */
#define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
#define PCAP_REG_AUXVREG 0x7 /* Auxiliary Regulator Control */
#define PCAP_REG_BATT 0x8 /* Battery Control */
#define PCAP_REG_ADC 0x9 /* AD Control */
#define PCAP_REG_ADR 0xa /* AD Result */
#define PCAP_REG_CODEC 0xb /* Audio Codec Control */
#define PCAP_REG_RX_AMPS 0xc /* RX Audio Amplifiers Control */
#define PCAP_REG_ST_DAC 0xd /* Stereo DAC Control */
#define PCAP_REG_BUSCTRL 0x14 /* Connectivity Control */
#define PCAP_REG_PERIPH 0x15 /* Peripheral Control */
#define PCAP_REG_LOWPWR 0x18 /* Regulator Low Power Control */
#define PCAP_REG_TX_AMPS 0x1a /* TX Audio Amplifiers Control */
#define PCAP_REG_GP 0x1b /* General Purpose */
#define PCAP_REG_TEST1 0x1c
#define PCAP_REG_TEST2 0x1d
#define PCAP_REG_VENDOR_TEST1 0x1e
#define PCAP_REG_VENDOR_TEST2 0x1f
/* registers accessible by pcap port 1 only (a1200, e2 & e6) */
#define PCAP_REG_INT_SEL 0x3 /* Interrupt Select */
#define PCAP_REG_SWCTRL 0x4 /* Switching Regulator Control */
#define PCAP_REG_VREG1 0x5 /* Regulator Bank 1 Control */
#define PCAP_REG_RTC_TOD 0xe /* RTC Time of Day */
#define PCAP_REG_RTC_TODA 0xf /* RTC Time of Day Alarm */
#define PCAP_REG_RTC_DAY 0x10 /* RTC Day */
#define PCAP_REG_RTC_DAYA 0x11 /* RTC Day Alarm */
#define PCAP_REG_MTRTMR 0x12 /* AD Monitor Timer */
#define PCAP_REG_PWR 0x13 /* Power Control */
#define PCAP_REG_AUXVREG_MASK 0x16 /* Auxiliary Regulator Mask */
#define PCAP_REG_VENDOR_REV 0x17
#define PCAP_REG_PERIPH_MASK 0x19 /* Peripheral Mask */
/* PCAP2 Interrupts */
#define PCAP_NIRQS 23
#define PCAP_IRQ_ADCDONE 0 /* ADC done port 1 */
#define PCAP_IRQ_TS 1 /* Touch Screen */
#define PCAP_IRQ_1HZ 2 /* 1HZ timer */
#define PCAP_IRQ_WH 3 /* ADC above high limit */
#define PCAP_IRQ_WL 4 /* ADC below low limit */
#define PCAP_IRQ_TODA 5 /* Time of day alarm */
#define PCAP_IRQ_USB4V 6 /* USB above 4V */
#define PCAP_IRQ_ONOFF 7 /* On/Off button */
#define PCAP_IRQ_ONOFF2 8 /* On/Off button 2 */
#define PCAP_IRQ_USB1V 9 /* USB above 1V */
#define PCAP_IRQ_MOBPORT 10
#define PCAP_IRQ_MIC 11 /* Mic attach/HS button */
#define PCAP_IRQ_HS 12 /* Headset attach */
#define PCAP_IRQ_ST 13
#define PCAP_IRQ_PC 14 /* Power Cut */
#define PCAP_IRQ_WARM 15
#define PCAP_IRQ_EOL 16 /* Battery End Of Life */
#define PCAP_IRQ_CLK 17
#define PCAP_IRQ_SYSRST 18 /* System Reset */
#define PCAP_IRQ_DUMMY 19
#define PCAP_IRQ_ADCDONE2 20 /* ADC done port 2 */
#define PCAP_IRQ_SOFTRESET 21
#define PCAP_IRQ_MNEXB 22
/* voltage regulators */
#define V1 0
#define V2 1
#define V3 2
#define V4 3
#define V5 4
#define V6 5
#define V7 6
#define V8 7
#define V9 8
#define V10 9
#define VAUX1 10
#define VAUX2 11
#define VAUX3 12
#define VAUX4 13
#define VSIM 14
#define VSIM2 15
#define VVIB 16
#define SW1 17
#define SW2 18
#define SW3 19
#define SW1S 20
#define SW2S 21
#define PCAP_BATT_DAC_MASK 0x000000ff
#define PCAP_BATT_DAC_SHIFT 0
#define PCAP_BATT_B_FDBK (1 << 8)
#define PCAP_BATT_EXT_ISENSE (1 << 9)
#define PCAP_BATT_V_COIN_MASK 0x00003c00
#define PCAP_BATT_V_COIN_SHIFT 10
#define PCAP_BATT_I_COIN (1 << 14)
#define PCAP_BATT_COIN_CH_EN (1 << 15)
#define PCAP_BATT_EOL_SEL_MASK 0x000e0000
#define PCAP_BATT_EOL_SEL_SHIFT 17
#define PCAP_BATT_EOL_CMP_EN (1 << 20)
#define PCAP_BATT_BATT_DET_EN (1 << 21)
#define PCAP_BATT_THERMBIAS_CTRL (1 << 22)
#define PCAP_ADC_ADEN (1 << 0)
#define PCAP_ADC_RAND (1 << 1)
#define PCAP_ADC_AD_SEL1 (1 << 2)
#define PCAP_ADC_AD_SEL2 (1 << 3)
#define PCAP_ADC_ADA1_MASK 0x00000070
#define PCAP_ADC_ADA1_SHIFT 4
#define PCAP_ADC_ADA2_MASK 0x00000380
#define PCAP_ADC_ADA2_SHIFT 7
#define PCAP_ADC_ATO_MASK 0x00003c00
#define PCAP_ADC_ATO_SHIFT 10
#define PCAP_ADC_ATOX (1 << 14)
#define PCAP_ADC_MTR1 (1 << 15)
#define PCAP_ADC_MTR2 (1 << 16)
#define PCAP_ADC_TS_M_MASK 0x000e0000
#define PCAP_ADC_TS_M_SHIFT 17
#define PCAP_ADC_TS_REF_LOWPWR (1 << 20)
#define PCAP_ADC_TS_REFENB (1 << 21)
#define PCAP_ADC_BATT_I_POLARITY (1 << 22)
#define PCAP_ADC_BATT_I_ADC (1 << 23)
#define PCAP_ADC_BANK_0 0
#define PCAP_ADC_BANK_1 1
/* ADC bank 0 */
#define PCAP_ADC_CH_COIN 0
#define PCAP_ADC_CH_BATT 1
#define PCAP_ADC_CH_BPLUS 2
#define PCAP_ADC_CH_MOBPORTB 3
#define PCAP_ADC_CH_TEMPERATURE 4
#define PCAP_ADC_CH_CHARGER_ID 5
#define PCAP_ADC_CH_AD6 6
/* ADC bank 1 */
#define PCAP_ADC_CH_AD7 0
#define PCAP_ADC_CH_AD8 1
#define PCAP_ADC_CH_AD9 2
#define PCAP_ADC_CH_TS_X1 3
#define PCAP_ADC_CH_TS_X2 4
#define PCAP_ADC_CH_TS_Y1 5
#define PCAP_ADC_CH_TS_Y2 6
#define PCAP_ADC_T_NOW 0
#define PCAP_ADC_T_IN_BURST 1
#define PCAP_ADC_T_OUT_BURST 2
#define PCAP_ADC_ATO_IN_BURST 6
#define PCAP_ADC_ATO_OUT_BURST 0
#define PCAP_ADC_TS_M_XY 1
#define PCAP_ADC_TS_M_PRESSURE 2
#define PCAP_ADC_TS_M_PLATE_X 3
#define PCAP_ADC_TS_M_PLATE_Y 4
#define PCAP_ADC_TS_M_STANDBY 5
#define PCAP_ADC_TS_M_NONTS 6
#define PCAP_ADR_ADD1_MASK 0x000003ff
#define PCAP_ADR_ADD1_SHIFT 0
#define PCAP_ADR_ADD2_MASK 0x000ffc00
#define PCAP_ADR_ADD2_SHIFT 10
#define PCAP_ADR_ADINC1 (1 << 20)
#define PCAP_ADR_ADINC2 (1 << 21)
#define PCAP_ADR_ASC (1 << 22)
#define PCAP_ADR_ONESHOT (1 << 23)
#define PCAP_BUSCTRL_FSENB (1 << 0)
#define PCAP_BUSCTRL_USB_SUSPEND (1 << 1)
#define PCAP_BUSCTRL_USB_PU (1 << 2)
#define PCAP_BUSCTRL_USB_PD (1 << 3)
#define PCAP_BUSCTRL_VUSB_EN (1 << 4)
#define PCAP_BUSCTRL_USB_PS (1 << 5)
#define PCAP_BUSCTRL_VUSB_MSTR_EN (1 << 6)
#define PCAP_BUSCTRL_VBUS_PD_ENB (1 << 7)
#define PCAP_BUSCTRL_CURRLIM (1 << 8)
#define PCAP_BUSCTRL_RS232ENB (1 << 9)
#define PCAP_BUSCTRL_RS232_DIR (1 << 10)
#define PCAP_BUSCTRL_SE0_CONN (1 << 11)
#define PCAP_BUSCTRL_USB_PDM (1 << 12)
#define PCAP_BUSCTRL_BUS_PRI_ADJ (1 << 24)
/* leds */
#define PCAP_LED0 0
#define PCAP_LED1 1
#define PCAP_BL0 2
#define PCAP_BL1 3
#define PCAP_LED_3MA 0
#define PCAP_LED_4MA 1
#define PCAP_LED_5MA 2
#define PCAP_LED_9MA 3
#define PCAP_LED_T_MASK 0xf
#define PCAP_LED_C_MASK 0x3
#define PCAP_BL_MASK 0x1f
#define PCAP_BL0_SHIFT 0
#define PCAP_LED0_EN (1 << 5)
#define PCAP_LED1_EN (1 << 6)
#define PCAP_LED0_T_SHIFT 7
#define PCAP_LED1_T_SHIFT 11
#define PCAP_LED0_C_SHIFT 15
#define PCAP_LED1_C_SHIFT 17
#define PCAP_BL1_SHIFT 20
/* RTC */
#define PCAP_RTC_DAY_MASK 0x3fff
#define PCAP_RTC_TOD_MASK 0xffff
#define PCAP_RTC_PC_MASK 0x7
#define SEC_PER_DAY 86400
#endif
kernel/include/linux/mfd/htc-egpio.h
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/*
* HTC simple EGPIO irq and gpio extender
*/
#ifndef __HTC_EGPIO_H__
#define __HTC_EGPIO_H__
#include <linux/gpio.h>
/* Descriptive values for all-in or all-out htc_egpio_chip descriptors. */
#define HTC_EGPIO_OUTPUT (~0)
#define HTC_EGPIO_INPUT 0
/**
* struct htc_egpio_chip - descriptor to create gpio_chip for register range
* @reg_start: index of first register
* @gpio_base: gpio number of first pin in this register range
* @num_gpios: number of gpios in this register range, max BITS_PER_LONG
* (number of registers = DIV_ROUND_UP(num_gpios, reg_width))
* @direction: bitfield, '0' = input, '1' = output,
*/
struct htc_egpio_chip {
int reg_start;
int gpio_base;
int num_gpios;
unsigned long direction;
unsigned long initial_values;
};
/**
* struct htc_egpio_platform_data - description provided by the arch
* @irq_base: beginning of available IRQs (eg, IRQ_BOARD_START)
* @num_irqs: number of irqs
* @reg_width: number of bits per register, either 8 or 16 bit
* @bus_width: alignment of the registers, either 16 or 32 bit
* @invert_acks: set if chip requires writing '0' to ack an irq, instead of '1'
* @ack_register: location of the irq/ack register
* @chip: pointer to array of htc_egpio_chip descriptors
* @num_chips: number of egpio chip descriptors
*/
struct htc_egpio_platform_data {
int bus_width;
int reg_width;
int irq_base;
int num_irqs;
int invert_acks;
int ack_register;
struct htc_egpio_chip *chip;
int num_chips;
};
/* Determine the wakeup irq, to be called during early resume */
extern int htc_egpio_get_wakeup_irq(struct device *dev);
#endif
kernel/include/linux/mfd/htc-pasic3.h
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/*
* HTC PASIC3 driver - LEDs and DS1WM
*
* Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
*/
#ifndef __PASIC3_H
#define __PASIC3_H
#include <linux/platform_device.h>
#include <linux/leds.h>
extern void pasic3_write_register(struct device *dev, u32 reg, u8 val);
extern u8 pasic3_read_register(struct device *dev, u32 reg);
/*
* mask for registers 0x20,0x21,0x22
*/
#define PASIC3_MASK_LED0 0x04
#define PASIC3_MASK_LED1 0x08
#define PASIC3_MASK_LED2 0x40
/*
* bits in register 0x06
*/
#define PASIC3_BIT2_LED0 0x08
#define PASIC3_BIT2_LED1 0x10
#define PASIC3_BIT2_LED2 0x20
struct pasic3_led {
struct led_classdev led;
unsigned int hw_num;
unsigned int bit2;
unsigned int mask;
struct pasic3_leds_machinfo *pdata;
};
struct pasic3_leds_machinfo {
unsigned int num_leds;
unsigned int power_gpio;
struct pasic3_led *leds;
};
struct pasic3_platform_data {
struct pasic3_leds_machinfo *led_pdata;
unsigned int clock_rate;
};
#endif
kernel/include/linux/mfd/intel_msic.h
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/*
* include/linux/mfd/intel_msic.h - Core interface for Intel MSIC
*
* Copyright (C) 2011, Intel Corporation
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_MFD_INTEL_MSIC_H__
#define __LINUX_MFD_INTEL_MSIC_H__
/* ID */
#define INTEL_MSIC_ID0 0x000 /* RO */
#define INTEL_MSIC_ID1 0x001 /* RO */
/* IRQ */
#define INTEL_MSIC_IRQLVL1 0x002
#define INTEL_MSIC_ADC1INT 0x003
#define INTEL_MSIC_CCINT 0x004
#define INTEL_MSIC_PWRSRCINT 0x005
#define INTEL_MSIC_PWRSRCINT1 0x006
#define INTEL_MSIC_CHRINT 0x007
#define INTEL_MSIC_CHRINT1 0x008
#define INTEL_MSIC_RTCIRQ 0x009
#define INTEL_MSIC_GPIO0LVIRQ 0x00a
#define INTEL_MSIC_GPIO1LVIRQ 0x00b
#define INTEL_MSIC_GPIOHVIRQ 0x00c
#define INTEL_MSIC_VRINT 0x00d
#define INTEL_MSIC_OCAUDIO 0x00e
#define INTEL_MSIC_ACCDET 0x00f
#define INTEL_MSIC_RESETIRQ1 0x010
#define INTEL_MSIC_RESETIRQ2 0x011
#define INTEL_MSIC_MADC1INT 0x012
#define INTEL_MSIC_MCCINT 0x013
#define INTEL_MSIC_MPWRSRCINT 0x014
#define INTEL_MSIC_MPWRSRCINT1 0x015
#define INTEL_MSIC_MCHRINT 0x016
#define INTEL_MSIC_MCHRINT1 0x017
#define INTEL_MSIC_RTCIRQMASK 0x018
#define INTEL_MSIC_GPIO0LVIRQMASK 0x019
#define INTEL_MSIC_GPIO1LVIRQMASK 0x01a
#define INTEL_MSIC_GPIOHVIRQMASK 0x01b
#define INTEL_MSIC_VRINTMASK 0x01c
#define INTEL_MSIC_OCAUDIOMASK 0x01d
#define INTEL_MSIC_ACCDETMASK 0x01e
#define INTEL_MSIC_RESETIRQ1MASK 0x01f
#define INTEL_MSIC_RESETIRQ2MASK 0x020
#define INTEL_MSIC_IRQLVL1MSK 0x021
#define INTEL_MSIC_PBCONFIG 0x03e
#define INTEL_MSIC_PBSTATUS 0x03f /* RO */
/* GPIO */
#define INTEL_MSIC_GPIO0LV7CTLO 0x040
#define INTEL_MSIC_GPIO0LV6CTLO 0x041
#define INTEL_MSIC_GPIO0LV5CTLO 0x042
#define INTEL_MSIC_GPIO0LV4CTLO 0x043
#define INTEL_MSIC_GPIO0LV3CTLO 0x044
#define INTEL_MSIC_GPIO0LV2CTLO 0x045
#define INTEL_MSIC_GPIO0LV1CTLO 0x046
#define INTEL_MSIC_GPIO0LV0CTLO 0x047
#define INTEL_MSIC_GPIO1LV7CTLOS 0x048
#define INTEL_MSIC_GPIO1LV6CTLO 0x049
#define INTEL_MSIC_GPIO1LV5CTLO 0x04a
#define INTEL_MSIC_GPIO1LV4CTLO 0x04b
#define INTEL_MSIC_GPIO1LV3CTLO 0x04c
#define INTEL_MSIC_GPIO1LV2CTLO 0x04d
#define INTEL_MSIC_GPIO1LV1CTLO 0x04e
#define INTEL_MSIC_GPIO1LV0CTLO 0x04f
#define INTEL_MSIC_GPIO0LV7CTLI 0x050
#define INTEL_MSIC_GPIO0LV6CTLI 0x051
#define INTEL_MSIC_GPIO0LV5CTLI 0x052
#define INTEL_MSIC_GPIO0LV4CTLI 0x053
#define INTEL_MSIC_GPIO0LV3CTLI 0x054
#define INTEL_MSIC_GPIO0LV2CTLI 0x055
#define INTEL_MSIC_GPIO0LV1CTLI 0x056
#define INTEL_MSIC_GPIO0LV0CTLI 0x057
#define INTEL_MSIC_GPIO1LV7CTLIS 0x058
#define INTEL_MSIC_GPIO1LV6CTLI 0x059
#define INTEL_MSIC_GPIO1LV5CTLI 0x05a
#define INTEL_MSIC_GPIO1LV4CTLI 0x05b
#define INTEL_MSIC_GPIO1LV3CTLI 0x05c
#define INTEL_MSIC_GPIO1LV2CTLI 0x05d
#define INTEL_MSIC_GPIO1LV1CTLI 0x05e
#define INTEL_MSIC_GPIO1LV0CTLI 0x05f
#define INTEL_MSIC_PWM0CLKDIV1 0x061
#define INTEL_MSIC_PWM0CLKDIV0 0x062
#define INTEL_MSIC_PWM1CLKDIV1 0x063
#define INTEL_MSIC_PWM1CLKDIV0 0x064
#define INTEL_MSIC_PWM2CLKDIV1 0x065
#define INTEL_MSIC_PWM2CLKDIV0 0x066
#define INTEL_MSIC_PWM0DUTYCYCLE 0x067
#define INTEL_MSIC_PWM1DUTYCYCLE 0x068
#define INTEL_MSIC_PWM2DUTYCYCLE 0x069
#define INTEL_MSIC_GPIO0HV3CTLO 0x06d
#define INTEL_MSIC_GPIO0HV2CTLO 0x06e
#define INTEL_MSIC_GPIO0HV1CTLO 0x06f
#define INTEL_MSIC_GPIO0HV0CTLO 0x070
#define INTEL_MSIC_GPIO1HV3CTLO 0x071
#define INTEL_MSIC_GPIO1HV2CTLO 0x072
#define INTEL_MSIC_GPIO1HV1CTLO 0x073
#define INTEL_MSIC_GPIO1HV0CTLO 0x074
#define INTEL_MSIC_GPIO0HV3CTLI 0x075
#define INTEL_MSIC_GPIO0HV2CTLI 0x076
#define INTEL_MSIC_GPIO0HV1CTLI 0x077
#define INTEL_MSIC_GPIO0HV0CTLI 0x078
#define INTEL_MSIC_GPIO1HV3CTLI 0x079
#define INTEL_MSIC_GPIO1HV2CTLI 0x07a
#define INTEL_MSIC_GPIO1HV1CTLI 0x07b
#define INTEL_MSIC_GPIO1HV0CTLI 0x07c
/* SVID */
#define INTEL_MSIC_SVIDCTRL0 0x080
#define INTEL_MSIC_SVIDCTRL1 0x081
#define INTEL_MSIC_SVIDCTRL2 0x082
#define INTEL_MSIC_SVIDTXLASTPKT3 0x083 /* RO */
#define INTEL_MSIC_SVIDTXLASTPKT2 0x084 /* RO */
#define INTEL_MSIC_SVIDTXLASTPKT1 0x085 /* RO */
#define INTEL_MSIC_SVIDTXLASTPKT0 0x086 /* RO */
#define INTEL_MSIC_SVIDPKTOUTBYTE3 0x087
#define INTEL_MSIC_SVIDPKTOUTBYTE2 0x088
#define INTEL_MSIC_SVIDPKTOUTBYTE1 0x089
#define INTEL_MSIC_SVIDPKTOUTBYTE0 0x08a
#define INTEL_MSIC_SVIDRXVPDEBUG1 0x08b
#define INTEL_MSIC_SVIDRXVPDEBUG0 0x08c
#define INTEL_MSIC_SVIDRXLASTPKT3 0x08d /* RO */
#define INTEL_MSIC_SVIDRXLASTPKT2 0x08e /* RO */
#define INTEL_MSIC_SVIDRXLASTPKT1 0x08f /* RO */
#define INTEL_MSIC_SVIDRXLASTPKT0 0x090 /* RO */
#define INTEL_MSIC_SVIDRXCHKSTATUS3 0x091 /* RO */
#define INTEL_MSIC_SVIDRXCHKSTATUS2 0x092 /* RO */
#define INTEL_MSIC_SVIDRXCHKSTATUS1 0x093 /* RO */
#define INTEL_MSIC_SVIDRXCHKSTATUS0 0x094 /* RO */
/* VREG */
#define INTEL_MSIC_VCCLATCH 0x0c0
#define INTEL_MSIC_VNNLATCH 0x0c1
#define INTEL_MSIC_VCCCNT 0x0c2
#define INTEL_MSIC_SMPSRAMP 0x0c3
#define INTEL_MSIC_VNNCNT 0x0c4
#define INTEL_MSIC_VNNAONCNT 0x0c5
#define INTEL_MSIC_VCC122AONCNT 0x0c6
#define INTEL_MSIC_V180AONCNT 0x0c7
#define INTEL_MSIC_V500CNT 0x0c8
#define INTEL_MSIC_VIHFCNT 0x0c9
#define INTEL_MSIC_LDORAMP1 0x0ca
#define INTEL_MSIC_LDORAMP2 0x0cb
#define INTEL_MSIC_VCC108AONCNT 0x0cc
#define INTEL_MSIC_VCC108ASCNT 0x0cd
#define INTEL_MSIC_VCC108CNT 0x0ce
#define INTEL_MSIC_VCCA100ASCNT 0x0cf
#define INTEL_MSIC_VCCA100CNT 0x0d0
#define INTEL_MSIC_VCC180AONCNT 0x0d1
#define INTEL_MSIC_VCC180CNT 0x0d2
#define INTEL_MSIC_VCC330CNT 0x0d3
#define INTEL_MSIC_VUSB330CNT 0x0d4
#define INTEL_MSIC_VCCSDIOCNT 0x0d5
#define INTEL_MSIC_VPROG1CNT 0x0d6
#define INTEL_MSIC_VPROG2CNT 0x0d7
#define INTEL_MSIC_VEMMCSCNT 0x0d8
#define INTEL_MSIC_VEMMC1CNT 0x0d9
#define INTEL_MSIC_VEMMC2CNT 0x0da
#define INTEL_MSIC_VAUDACNT 0x0db
#define INTEL_MSIC_VHSPCNT 0x0dc
#define INTEL_MSIC_VHSNCNT 0x0dd
#define INTEL_MSIC_VHDMICNT 0x0de
#define INTEL_MSIC_VOTGCNT 0x0df
#define INTEL_MSIC_V1P35CNT 0x0e0
#define INTEL_MSIC_V330AONCNT 0x0e1
/* RESET */
#define INTEL_MSIC_CHIPCNTRL 0x100 /* WO */
#define INTEL_MSIC_ERCONFIG 0x101
/* BURST */
#define INTEL_MSIC_BATCURRENTLIMIT12 0x102
#define INTEL_MSIC_BATTIMELIMIT12 0x103
#define INTEL_MSIC_BATTIMELIMIT3 0x104
#define INTEL_MSIC_BATTIMEDB 0x105
#define INTEL_MSIC_BRSTCONFIGOUTPUTS 0x106
#define INTEL_MSIC_BRSTCONFIGACTIONS 0x107
#define INTEL_MSIC_BURSTCONTROLSTATUS 0x108
/* RTC */
#define INTEL_MSIC_RTCB1 0x140 /* RO */
#define INTEL_MSIC_RTCB2 0x141 /* RO */
#define INTEL_MSIC_RTCB3 0x142 /* RO */
#define INTEL_MSIC_RTCB4 0x143 /* RO */
#define INTEL_MSIC_RTCOB1 0x144
#define INTEL_MSIC_RTCOB2 0x145
#define INTEL_MSIC_RTCOB3 0x146
#define INTEL_MSIC_RTCOB4 0x147
#define INTEL_MSIC_RTCAB1 0x148
#define INTEL_MSIC_RTCAB2 0x149
#define INTEL_MSIC_RTCAB3 0x14a
#define INTEL_MSIC_RTCAB4 0x14b
#define INTEL_MSIC_RTCWAB1 0x14c
#define INTEL_MSIC_RTCWAB2 0x14d
#define INTEL_MSIC_RTCWAB3 0x14e
#define INTEL_MSIC_RTCWAB4 0x14f
#define INTEL_MSIC_RTCSC1 0x150
#define INTEL_MSIC_RTCSC2 0x151
#define INTEL_MSIC_RTCSC3 0x152
#define INTEL_MSIC_RTCSC4 0x153
#define INTEL_MSIC_RTCSTATUS 0x154 /* RO */
#define INTEL_MSIC_RTCCONFIG1 0x155
#define INTEL_MSIC_RTCCONFIG2 0x156
/* CHARGER */
#define INTEL_MSIC_BDTIMER 0x180
#define INTEL_MSIC_BATTRMV 0x181
#define INTEL_MSIC_VBUSDET 0x182
#define INTEL_MSIC_VBUSDET1 0x183
#define INTEL_MSIC_ADPHVDET 0x184
#define INTEL_MSIC_ADPLVDET 0x185
#define INTEL_MSIC_ADPDETDBDM 0x186
#define INTEL_MSIC_LOWBATTDET 0x187
#define INTEL_MSIC_CHRCTRL 0x188
#define INTEL_MSIC_CHRCVOLTAGE 0x189
#define INTEL_MSIC_CHRCCURRENT 0x18a
#define INTEL_MSIC_SPCHARGER 0x18b
#define INTEL_MSIC_CHRTTIME 0x18c
#define INTEL_MSIC_CHRCTRL1 0x18d
#define INTEL_MSIC_PWRSRCLMT 0x18e
#define INTEL_MSIC_CHRSTWDT 0x18f
#define INTEL_MSIC_WDTWRITE 0x190 /* WO */
#define INTEL_MSIC_CHRSAFELMT 0x191
#define INTEL_MSIC_SPWRSRCINT 0x192 /* RO */
#define INTEL_MSIC_SPWRSRCINT1 0x193 /* RO */
#define INTEL_MSIC_CHRLEDPWM 0x194
#define INTEL_MSIC_CHRLEDCTRL 0x195
/* ADC */
#define INTEL_MSIC_ADC1CNTL1 0x1c0
#define INTEL_MSIC_ADC1CNTL2 0x1c1
#define INTEL_MSIC_ADC1CNTL3 0x1c2
#define INTEL_MSIC_ADC1OFFSETH 0x1c3 /* RO */
#define INTEL_MSIC_ADC1OFFSETL 0x1c4 /* RO */
#define INTEL_MSIC_ADC1ADDR0 0x1c5
#define INTEL_MSIC_ADC1ADDR1 0x1c6
#define INTEL_MSIC_ADC1ADDR2 0x1c7
#define INTEL_MSIC_ADC1ADDR3 0x1c8
#define INTEL_MSIC_ADC1ADDR4 0x1c9
#define INTEL_MSIC_ADC1ADDR5 0x1ca
#define INTEL_MSIC_ADC1ADDR6 0x1cb
#define INTEL_MSIC_ADC1ADDR7 0x1cc
#define INTEL_MSIC_ADC1ADDR8 0x1cd
#define INTEL_MSIC_ADC1ADDR9 0x1ce
#define INTEL_MSIC_ADC1ADDR10 0x1cf
#define INTEL_MSIC_ADC1ADDR11 0x1d0
#define INTEL_MSIC_ADC1ADDR12 0x1d1
#define INTEL_MSIC_ADC1ADDR13 0x1d2
#define INTEL_MSIC_ADC1ADDR14 0x1d3
#define INTEL_MSIC_ADC1SNS0H 0x1d4 /* RO */
#define INTEL_MSIC_ADC1SNS0L 0x1d5 /* RO */
#define INTEL_MSIC_ADC1SNS1H 0x1d6 /* RO */
#define INTEL_MSIC_ADC1SNS1L 0x1d7 /* RO */
#define INTEL_MSIC_ADC1SNS2H 0x1d8 /* RO */
#define INTEL_MSIC_ADC1SNS2L 0x1d9 /* RO */
#define INTEL_MSIC_ADC1SNS3H 0x1da /* RO */
#define INTEL_MSIC_ADC1SNS3L 0x1db /* RO */
#define INTEL_MSIC_ADC1SNS4H 0x1dc /* RO */
#define INTEL_MSIC_ADC1SNS4L 0x1dd /* RO */
#define INTEL_MSIC_ADC1SNS5H 0x1de /* RO */
#define INTEL_MSIC_ADC1SNS5L 0x1df /* RO */
#define INTEL_MSIC_ADC1SNS6H 0x1e0 /* RO */
#define INTEL_MSIC_ADC1SNS6L 0x1e1 /* RO */
#define INTEL_MSIC_ADC1SNS7H 0x1e2 /* RO */
#define INTEL_MSIC_ADC1SNS7L 0x1e3 /* RO */
#define INTEL_MSIC_ADC1SNS8H 0x1e4 /* RO */
#define INTEL_MSIC_ADC1SNS8L 0x1e5 /* RO */
#define INTEL_MSIC_ADC1SNS9H 0x1e6 /* RO */
#define INTEL_MSIC_ADC1SNS9L 0x1e7 /* RO */
#define INTEL_MSIC_ADC1SNS10H 0x1e8 /* RO */
#define INTEL_MSIC_ADC1SNS10L 0x1e9 /* RO */
#define INTEL_MSIC_ADC1SNS11H 0x1ea /* RO */
#define INTEL_MSIC_ADC1SNS11L 0x1eb /* RO */
#define INTEL_MSIC_ADC1SNS12H 0x1ec /* RO */
#define INTEL_MSIC_ADC1SNS12L 0x1ed /* RO */
#define INTEL_MSIC_ADC1SNS13H 0x1ee /* RO */
#define INTEL_MSIC_ADC1SNS13L 0x1ef /* RO */
#define INTEL_MSIC_ADC1SNS14H 0x1f0 /* RO */
#define INTEL_MSIC_ADC1SNS14L 0x1f1 /* RO */
#define INTEL_MSIC_ADC1BV0H 0x1f2 /* RO */
#define INTEL_MSIC_ADC1BV0L 0x1f3 /* RO */
#define INTEL_MSIC_ADC1BV1H 0x1f4 /* RO */
#define INTEL_MSIC_ADC1BV1L 0x1f5 /* RO */
#define INTEL_MSIC_ADC1BV2H 0x1f6 /* RO */
#define INTEL_MSIC_ADC1BV2L 0x1f7 /* RO */
#define INTEL_MSIC_ADC1BV3H 0x1f8 /* RO */
#define INTEL_MSIC_ADC1BV3L 0x1f9 /* RO */
#define INTEL_MSIC_ADC1BI0H 0x1fa /* RO */
#define INTEL_MSIC_ADC1BI0L 0x1fb /* RO */
#define INTEL_MSIC_ADC1BI1H 0x1fc /* RO */
#define INTEL_MSIC_ADC1BI1L 0x1fd /* RO */
#define INTEL_MSIC_ADC1BI2H 0x1fe /* RO */
#define INTEL_MSIC_ADC1BI2L 0x1ff /* RO */
#define INTEL_MSIC_ADC1BI3H 0x200 /* RO */
#define INTEL_MSIC_ADC1BI3L 0x201 /* RO */
#define INTEL_MSIC_CCCNTL 0x202
#define INTEL_MSIC_CCOFFSETH 0x203 /* RO */
#define INTEL_MSIC_CCOFFSETL 0x204 /* RO */
#define INTEL_MSIC_CCADCHA 0x205 /* RO */
#define INTEL_MSIC_CCADCLA 0x206 /* RO */
/* AUDIO */
#define INTEL_MSIC_AUDPLLCTRL 0x240
#define INTEL_MSIC_DMICBUF0123 0x241
#define INTEL_MSIC_DMICBUF45 0x242
#define INTEL_MSIC_DMICGPO 0x244
#define INTEL_MSIC_DMICMUX 0x245
#define INTEL_MSIC_DMICCLK 0x246
#define INTEL_MSIC_MICBIAS 0x247
#define INTEL_MSIC_ADCCONFIG 0x248
#define INTEL_MSIC_MICAMP1 0x249
#define INTEL_MSIC_MICAMP2 0x24a
#define INTEL_MSIC_NOISEMUX 0x24b
#define INTEL_MSIC_AUDIOMUX12 0x24c
#define INTEL_MSIC_AUDIOMUX34 0x24d
#define INTEL_MSIC_AUDIOSINC 0x24e
#define INTEL_MSIC_AUDIOTXEN 0x24f
#define INTEL_MSIC_HSEPRXCTRL 0x250
#define INTEL_MSIC_IHFRXCTRL 0x251
#define INTEL_MSIC_VOICETXVOL 0x252
#define INTEL_MSIC_SIDETONEVOL 0x253
#define INTEL_MSIC_MUSICSHARVOL 0x254
#define INTEL_MSIC_VOICETXCTRL 0x255
#define INTEL_MSIC_HSMIXER 0x256
#define INTEL_MSIC_DACCONFIG 0x257
#define INTEL_MSIC_SOFTMUTE 0x258
#define INTEL_MSIC_HSLVOLCTRL 0x259
#define INTEL_MSIC_HSRVOLCTRL 0x25a
#define INTEL_MSIC_IHFLVOLCTRL 0x25b
#define INTEL_MSIC_IHFRVOLCTRL 0x25c
#define INTEL_MSIC_DRIVEREN 0x25d
#define INTEL_MSIC_LINEOUTCTRL 0x25e
#define INTEL_MSIC_VIB1CTRL1 0x25f
#define INTEL_MSIC_VIB1CTRL2 0x260
#define INTEL_MSIC_VIB1CTRL3 0x261
#define INTEL_MSIC_VIB1SPIPCM_1 0x262
#define INTEL_MSIC_VIB1SPIPCM_2 0x263
#define INTEL_MSIC_VIB1CTRL5 0x264
#define INTEL_MSIC_VIB2CTRL1 0x265
#define INTEL_MSIC_VIB2CTRL2 0x266
#define INTEL_MSIC_VIB2CTRL3 0x267
#define INTEL_MSIC_VIB2SPIPCM_1 0x268
#define INTEL_MSIC_VIB2SPIPCM_2 0x269
#define INTEL_MSIC_VIB2CTRL5 0x26a
#define INTEL_MSIC_BTNCTRL1 0x26b
#define INTEL_MSIC_BTNCTRL2 0x26c
#define INTEL_MSIC_PCM1TXSLOT01 0x26d
#define INTEL_MSIC_PCM1TXSLOT23 0x26e
#define INTEL_MSIC_PCM1TXSLOT45 0x26f
#define INTEL_MSIC_PCM1RXSLOT0123 0x270
#define INTEL_MSIC_PCM1RXSLOT045 0x271
#define INTEL_MSIC_PCM2TXSLOT01 0x272
#define INTEL_MSIC_PCM2TXSLOT23 0x273
#define INTEL_MSIC_PCM2TXSLOT45 0x274
#define INTEL_MSIC_PCM2RXSLOT01 0x275
#define INTEL_MSIC_PCM2RXSLOT23 0x276
#define INTEL_MSIC_PCM2RXSLOT45 0x277
#define INTEL_MSIC_PCM1CTRL1 0x278
#define INTEL_MSIC_PCM1CTRL2 0x279
#define INTEL_MSIC_PCM1CTRL3 0x27a
#define INTEL_MSIC_PCM2CTRL1 0x27b
#define INTEL_MSIC_PCM2CTRL2 0x27c
/* HDMI */
#define INTEL_MSIC_HDMIPUEN 0x280
#define INTEL_MSIC_HDMISTATUS 0x281 /* RO */
/* Physical address of the start of the MSIC interrupt tree in SRAM */
#define INTEL_MSIC_IRQ_PHYS_BASE 0xffff7fc0
/**
* struct intel_msic_gpio_pdata - platform data for the MSIC GPIO driver
* @gpio_base: base number for the GPIOs
*/
struct intel_msic_gpio_pdata {
unsigned gpio_base;
};
/**
* struct intel_msic_ocd_pdata - platform data for the MSIC OCD driver
* @gpio: GPIO number used for OCD interrupts
*
* The MSIC MFD driver converts @gpio into an IRQ number and passes it to
* the OCD driver as %IORESOURCE_IRQ.
*/
struct intel_msic_ocd_pdata {
unsigned gpio;
};
/* MSIC embedded blocks (subdevices) */
enum intel_msic_block {
INTEL_MSIC_BLOCK_TOUCH,
INTEL_MSIC_BLOCK_ADC,
INTEL_MSIC_BLOCK_BATTERY,
INTEL_MSIC_BLOCK_GPIO,
INTEL_MSIC_BLOCK_AUDIO,
INTEL_MSIC_BLOCK_HDMI,
INTEL_MSIC_BLOCK_THERMAL,
INTEL_MSIC_BLOCK_POWER_BTN,
INTEL_MSIC_BLOCK_OCD,
INTEL_MSIC_BLOCK_LAST,
};
/**
* struct intel_msic_platform_data - platform data for the MSIC driver
* @irq: array of interrupt numbers, one per device. If @irq is set to %0
* for a given block, the corresponding platform device is not
* created. For devices which don't have an interrupt, use %0xff
* (this is same as in SFI spec).
* @gpio: platform data for the MSIC GPIO driver
* @ocd: platform data for the MSIC OCD driver
*
* Once the MSIC driver is initialized, the register interface is ready to
* use. All the platform devices for subdevices are created after the
* register interface is ready so that we can guarantee its availability to
* the subdevice drivers.
*
* Interrupt numbers are passed to the subdevices via %IORESOURCE_IRQ
* resources of the created platform device.
*/
struct intel_msic_platform_data {
int irq[INTEL_MSIC_BLOCK_LAST];
struct intel_msic_gpio_pdata *gpio;
struct intel_msic_ocd_pdata *ocd;
};
struct intel_msic;
extern int intel_msic_reg_read(unsigned short reg, u8 *val);
extern int intel_msic_reg_write(unsigned short reg, u8 val);
extern int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask);
extern int intel_msic_bulk_read(unsigned short *reg, u8 *buf, size_t count);
extern int intel_msic_bulk_write(unsigned short *reg, u8 *buf, size_t count);
/*
* pdev_to_intel_msic - gets an MSIC instance from the platform device
* @pdev: platform device pointer
*
* The client drivers need to have pointer to the MSIC instance if they
* want to call intel_msic_irq_read(). This macro can be used for
* convenience to get the MSIC pointer from @pdev where needed. This is
* _only_ valid for devices which are managed by the MSIC.
*/
#define pdev_to_intel_msic(pdev) (dev_get_drvdata(pdev->dev.parent))
extern int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg,
u8 *val);
#endif /* __LINUX_MFD_INTEL_MSIC_H__ */
kernel/include/linux/mfd/janz.h
+54
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/*
* Common Definitions for Janz MODULbus devices
*
* Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef JANZ_H
#define JANZ_H
struct janz_platform_data {
/* MODULbus Module Number */
unsigned int modno;
};
/* PLX bridge chip onboard registers */
struct janz_cmodio_onboard_regs {
u8 unused1;
/*
* Read access: interrupt status
* Write access: interrupt disable
*/
u8 int_disable;
u8 unused2;
/*
* Read access: MODULbus number (hex switch)
* Write access: interrupt enable
*/
u8 int_enable;
u8 unused3;
/* write-only */
u8 reset_assert;
u8 unused4;
/* write-only */
u8 reset_deassert;
u8 unused5;
/* read-write access to serial EEPROM */
u8 eep;
u8 unused6;
/* write-only access to EEPROM chip select */
u8 enid;
};
#endif /* JANZ_H */
kernel/include/linux/mfd/marimba-codec.h
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/* Copyright (c) 2009, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __LINUX_MFD_MSM_MARIMBA_CODEC_H
#define __LINUX_MFD_MSM_MARIMBA_CODEC_H
#include <mach/qdsp5v2/adie_marimba.h>
struct adie_codec_register {
u8 reg;
u8 mask;
u8 val;
};
struct adie_codec_register_image {
struct adie_codec_register *regs;
u32 img_sz;
};
struct adie_codec_path {
struct adie_codec_dev_profile *profile;
struct adie_codec_register_image img;
u32 hwsetting_idx;
u32 stage_idx;
u32 curr_stage;
};
int adie_codec_open(struct adie_codec_dev_profile *profile,
struct adie_codec_path **path_pptr);
int adie_codec_setpath(struct adie_codec_path *path_ptr,
u32 freq_plan, u32 osr);
int adie_codec_proceed_stage(struct adie_codec_path *path_ptr, u32 state);
int adie_codec_close(struct adie_codec_path *path_ptr);
u32 adie_codec_freq_supported(struct adie_codec_dev_profile *profile,
u32 requested_freq);
int adie_codec_enable_sidetone(struct adie_codec_path *rx_path_ptr, u32 enable);
int adie_codec_set_device_digital_volume(struct adie_codec_path *path_ptr,
u32 num_channels, u32 vol_percentage /* in percentage */);
int adie_codec_set_device_analog_volume(struct adie_codec_path *path_ptr,
u32 num_channels, u32 volume /* in percentage */);
#endif
kernel/include/linux/mfd/marimba-tsadc.h
+29
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/* Copyright (c) 2009, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _MARIMBA_TSADC_H_
#define _MARIMBA_TSADC_H_
struct marimba_tsadc_client;
#define TSSC_SUSPEND_LEVEL 1
#define TSADC_SUSPEND_LEVEL 2
int marimba_tsadc_start(struct marimba_tsadc_client *client);
struct marimba_tsadc_client *
marimba_tsadc_register(struct platform_device *pdev, unsigned int is_ts);
void marimba_tsadc_unregister(struct marimba_tsadc_client *client);
#endif /* _MARIMBA_TSADC_H_ */
kernel/include/linux/mfd/marimba.h
+191
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/* Copyright (c) 2009-2011, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
/*
* Qualcomm Marimba Core Driver header file
*/
#ifndef _MARIMBA_H
#define _MARIMBA_H_
#include <linux/types.h>
#include <linux/i2c.h>
#include <linux/input/msm_ts.h>
#include <mach/vreg.h>
#define MARIMBA_NUM_CHILD 4
#define MARIMBA_SLAVE_ID_MARIMBA 0x00
#define MARIMBA_SLAVE_ID_FM 0x01
#define MARIMBA_SLAVE_ID_CDC 0x02
#define MARIMBA_SLAVE_ID_QMEMBIST 0x03
#define MARIMBA_ID_TSADC 0x04
#define BAHAMA_SLAVE_ID_FM_ID 0x02
#define SLAVE_ID_BAHAMA 0x05
#define SLAVE_ID_BAHAMA_FM 0x07
#define SLAVE_ID_BAHAMA_QMEMBIST 0x08
#if defined(CONFIG_ARCH_MSM7X30)
#define MARIMBA_SSBI_ADAP 0x7
#elif defined(CONFIG_ARCH_MSM8X60)
#define MARIMBA_SSBI_ADAP 0X8
#endif
enum chip_id {
MARIMBA_ID = 0,
TIMPANI_ID,
BAHAMA_ID,
CHIP_ID_MAX
};
enum bahama_version {
BAHAMA_VER_1_0,
BAHAMA_VER_2_0,
BAHAMA_VER_UNSUPPORTED = 0xFF
};
enum {
BT_PCM_ON,
BT_PCM_OFF,
FM_I2S_ON,
FM_I2S_OFF,
};
struct marimba {
struct i2c_client *client;
struct i2c_msg xfer_msg[2];
struct mutex xfer_lock;
int mod_id;
};
struct marimba_top_level_platform_data {
int slave_id; /* Member added for eg. */
};
struct marimba_fm_platform_data {
int irq;
int (*fm_setup)(struct marimba_fm_platform_data *pdata);
void (*fm_shutdown)(struct marimba_fm_platform_data *pdata);
struct vreg *vreg_s2;
struct vreg *vreg_xo_out;
/*
This is to indicate whether Fm SoC is I2S master/slave
false - FM SoC is I2S slave
true - FM SoC is I2S master
*/
bool is_fm_soc_i2s_master;
int (*config_i2s_gpio)(int mode);
};
struct marimba_codec_platform_data {
int (*marimba_codec_power)(int vreg_on);
void (*snddev_profile_init) (void);
};
struct marimba_tsadc_setup_params {
bool pen_irq_en;
bool tsadc_en;
};
enum sample_period {
TSADC_CLK_3 = 0,
TSADC_CLK_24,
TSADC_CLK_36,
TSADC_CLK_48,
TSADC_CLK_1,
TSADC_CLK_2,
TSADC_CLK_6,
TSADC_CLK_12,
TSADC_CLOCK_MAX
};
struct marimba_tsadc_config_params2 {
unsigned long input_clk_khz;
enum sample_period sample_prd;
};
struct marimba_tsadc_config_params3 {
unsigned long prechg_time_nsecs;
unsigned long stable_time_nsecs;
unsigned long tsadc_test_mode;
};
struct marimba_tsadc_platform_data {
int (*marimba_tsadc_power)(int vreg_on);
int (*init)(void);
int (*exit)(void);
int (*level_vote)(int vote_on);
bool tsadc_prechg_en;
bool can_wakeup;
struct marimba_tsadc_setup_params setup;
struct marimba_tsadc_config_params2 params2;
struct marimba_tsadc_config_params3 params3;
struct msm_ts_platform_data *tssc_data;
};
/*
* Marimba Platform Data
* */
struct marimba_platform_data {
struct marimba_top_level_platform_data *marimba_tp_level;
struct marimba_fm_platform_data *fm;
struct marimba_codec_platform_data *codec;
struct marimba_tsadc_platform_data *tsadc;
u8 slave_id[(MARIMBA_NUM_CHILD + 1) * CHIP_ID_MAX];
u32 (*marimba_setup) (void);
void (*marimba_shutdown) (void);
u32 (*bahama_setup) (void);
u32 (*bahama_shutdown) (int);
u32 (*marimba_gpio_config) (int);
u32 (*bahama_core_config) (int type);
u32 tsadc_ssbi_adap;
};
/*
* Read and Write to register
* */
int marimba_read(struct marimba *, u8 reg, u8 *value, unsigned num_bytes);
int marimba_write(struct marimba *, u8 reg, u8 *value, unsigned num_bytes);
/*
* Read and Write single 8 bit register with bit mask
* */
int marimba_read_bit_mask(struct marimba *, u8 reg, u8 *value,
unsigned num_bytes, u8 mask);
int marimba_write_bit_mask(struct marimba *, u8 reg, u8 *value,
unsigned num_bytes, u8 mask);
/*
* Read and Write to TSADC registers across the SSBI
* * */
int marimba_ssbi_read(struct marimba *, u16 reg, u8 *value, int len);
int marimba_ssbi_write(struct marimba *, u16 reg , u8 *value, int len);
/* Read and write to Timpani */
int timpani_read(struct marimba*, u8 reg, u8 *value, unsigned num_bytes);
int timpani_write(struct marimba*, u8 reg, u8 *value,
unsigned num_bytes);
/* Get the detected codec type */
int adie_get_detected_codec_type(void);
int adie_get_detected_connectivity_type(void);
int marimba_gpio_config(int gpio_value);
bool marimba_get_fm_status(struct marimba *);
bool marimba_get_bt_status(struct marimba *);
void marimba_set_fm_status(struct marimba *, bool);
void marimba_set_bt_status(struct marimba *, bool);
int marimba_read_bahama_ver(struct marimba *);
#endif
kernel/include/linux/mfd/max8925.h
+256
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/*
* Maxim8925 Interface
*
* Copyright (C) 2009 Marvell International Ltd.
* Haojian Zhuang <haojian.zhuang@marvell.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_MFD_MAX8925_H
#define __LINUX_MFD_MAX8925_H
#include <linux/mutex.h>
#include <linux/interrupt.h>
/* Unified sub device IDs for MAX8925 */
enum {
MAX8925_ID_SD1,
MAX8925_ID_SD2,
MAX8925_ID_SD3,
MAX8925_ID_LDO1,
MAX8925_ID_LDO2,
MAX8925_ID_LDO3,
MAX8925_ID_LDO4,
MAX8925_ID_LDO5,
MAX8925_ID_LDO6,
MAX8925_ID_LDO7,
MAX8925_ID_LDO8,
MAX8925_ID_LDO9,
MAX8925_ID_LDO10,
MAX8925_ID_LDO11,
MAX8925_ID_LDO12,
MAX8925_ID_LDO13,
MAX8925_ID_LDO14,
MAX8925_ID_LDO15,
MAX8925_ID_LDO16,
MAX8925_ID_LDO17,
MAX8925_ID_LDO18,
MAX8925_ID_LDO19,
MAX8925_ID_LDO20,
MAX8925_ID_MAX,
};
enum {
/*
* Charging current threshold trigger going from fast charge
* to TOPOFF charge. From 5% to 20% of fasting charging current.
*/
MAX8925_TOPOFF_THR_5PER,
MAX8925_TOPOFF_THR_10PER,
MAX8925_TOPOFF_THR_15PER,
MAX8925_TOPOFF_THR_20PER,
};
enum {
/* Fast charging current */
MAX8925_FCHG_85MA,
MAX8925_FCHG_300MA,
MAX8925_FCHG_460MA,
MAX8925_FCHG_600MA,
MAX8925_FCHG_700MA,
MAX8925_FCHG_800MA,
MAX8925_FCHG_900MA,
MAX8925_FCHG_1000MA,
};
/* Charger registers */
#define MAX8925_CHG_IRQ1 (0x7e)
#define MAX8925_CHG_IRQ2 (0x7f)
#define MAX8925_CHG_IRQ1_MASK (0x80)
#define MAX8925_CHG_IRQ2_MASK (0x81)
#define MAX8925_CHG_STATUS (0x82)
/* GPM registers */
#define MAX8925_SYSENSEL (0x00)
#define MAX8925_ON_OFF_IRQ1 (0x01)
#define MAX8925_ON_OFF_IRQ1_MASK (0x02)
#define MAX8925_ON_OFF_STATUS (0x03)
#define MAX8925_ON_OFF_IRQ2 (0x0d)
#define MAX8925_ON_OFF_IRQ2_MASK (0x0e)
#define MAX8925_RESET_CNFG (0x0f)
/* Touch registers */
#define MAX8925_TSC_IRQ (0x00)
#define MAX8925_TSC_IRQ_MASK (0x01)
#define MAX8925_TSC_CNFG1 (0x02)
#define MAX8925_ADC_SCHED (0x10)
#define MAX8925_ADC_RES_END (0x6f)
#define MAX8925_NREF_OK (1 << 4)
/* RTC registers */
#define MAX8925_ALARM0_CNTL (0x18)
#define MAX8925_ALARM1_CNTL (0x19)
#define MAX8925_RTC_IRQ (0x1c)
#define MAX8925_RTC_IRQ_MASK (0x1d)
#define MAX8925_MPL_CNTL (0x1e)
/* WLED registers */
#define MAX8925_WLED_MODE_CNTL (0x84)
#define MAX8925_WLED_CNTL (0x85)
/* MAX8925 Registers */
#define MAX8925_SDCTL1 (0x04)
#define MAX8925_SDCTL2 (0x07)
#define MAX8925_SDCTL3 (0x0A)
#define MAX8925_SDV1 (0x06)
#define MAX8925_SDV2 (0x09)
#define MAX8925_SDV3 (0x0C)
#define MAX8925_LDOCTL1 (0x18)
#define MAX8925_LDOCTL2 (0x1C)
#define MAX8925_LDOCTL3 (0x20)
#define MAX8925_LDOCTL4 (0x24)
#define MAX8925_LDOCTL5 (0x28)
#define MAX8925_LDOCTL6 (0x2C)
#define MAX8925_LDOCTL7 (0x30)
#define MAX8925_LDOCTL8 (0x34)
#define MAX8925_LDOCTL9 (0x38)
#define MAX8925_LDOCTL10 (0x3C)
#define MAX8925_LDOCTL11 (0x40)
#define MAX8925_LDOCTL12 (0x44)
#define MAX8925_LDOCTL13 (0x48)
#define MAX8925_LDOCTL14 (0x4C)
#define MAX8925_LDOCTL15 (0x50)
#define MAX8925_LDOCTL16 (0x10)
#define MAX8925_LDOCTL17 (0x14)
#define MAX8925_LDOCTL18 (0x72)
#define MAX8925_LDOCTL19 (0x5C)
#define MAX8925_LDOCTL20 (0x9C)
#define MAX8925_LDOVOUT1 (0x1A)
#define MAX8925_LDOVOUT2 (0x1E)
#define MAX8925_LDOVOUT3 (0x22)
#define MAX8925_LDOVOUT4 (0x26)
#define MAX8925_LDOVOUT5 (0x2A)
#define MAX8925_LDOVOUT6 (0x2E)
#define MAX8925_LDOVOUT7 (0x32)
#define MAX8925_LDOVOUT8 (0x36)
#define MAX8925_LDOVOUT9 (0x3A)
#define MAX8925_LDOVOUT10 (0x3E)
#define MAX8925_LDOVOUT11 (0x42)
#define MAX8925_LDOVOUT12 (0x46)
#define MAX8925_LDOVOUT13 (0x4A)
#define MAX8925_LDOVOUT14 (0x4E)
#define MAX8925_LDOVOUT15 (0x52)
#define MAX8925_LDOVOUT16 (0x12)
#define MAX8925_LDOVOUT17 (0x16)
#define MAX8925_LDOVOUT18 (0x74)
#define MAX8925_LDOVOUT19 (0x5E)
#define MAX8925_LDOVOUT20 (0x9E)
/* bit definitions */
#define CHG_IRQ1_MASK (0x07)
#define CHG_IRQ2_MASK (0xff)
#define ON_OFF_IRQ1_MASK (0xff)
#define ON_OFF_IRQ2_MASK (0x03)
#define TSC_IRQ_MASK (0x03)
#define RTC_IRQ_MASK (0x0c)
#define MAX8925_MAX_REGULATOR (23)
#define MAX8925_NAME_SIZE (32)
/* IRQ definitions */
enum {
MAX8925_IRQ_VCHG_DC_OVP,
MAX8925_IRQ_VCHG_DC_F,
MAX8925_IRQ_VCHG_DC_R,
MAX8925_IRQ_VCHG_THM_OK_R,
MAX8925_IRQ_VCHG_THM_OK_F,
MAX8925_IRQ_VCHG_SYSLOW_F,
MAX8925_IRQ_VCHG_SYSLOW_R,
MAX8925_IRQ_VCHG_RST,
MAX8925_IRQ_VCHG_DONE,
MAX8925_IRQ_VCHG_TOPOFF,
MAX8925_IRQ_VCHG_TMR_FAULT,
MAX8925_IRQ_GPM_RSTIN,
MAX8925_IRQ_GPM_MPL,
MAX8925_IRQ_GPM_SW_3SEC,
MAX8925_IRQ_GPM_EXTON_F,
MAX8925_IRQ_GPM_EXTON_R,
MAX8925_IRQ_GPM_SW_1SEC,
MAX8925_IRQ_GPM_SW_F,
MAX8925_IRQ_GPM_SW_R,
MAX8925_IRQ_GPM_SYSCKEN_F,
MAX8925_IRQ_GPM_SYSCKEN_R,
MAX8925_IRQ_RTC_ALARM1,
MAX8925_IRQ_RTC_ALARM0,
MAX8925_IRQ_TSC_STICK,
MAX8925_IRQ_TSC_NSTICK,
MAX8925_NR_IRQS,
};
struct max8925_chip {
struct device *dev;
struct i2c_client *i2c;
struct i2c_client *adc;
struct i2c_client *rtc;
struct mutex io_lock;
struct mutex irq_lock;
int irq_base;
int core_irq;
int tsc_irq;
unsigned int wakeup_flag;
};
struct max8925_backlight_pdata {
int lxw_scl; /* 0/1 -- 0.8Ohm/0.4Ohm */
int lxw_freq; /* 700KHz ~ 1400KHz */
int dual_string; /* 0/1 -- single/dual string */
};
struct max8925_touch_pdata {
unsigned int flags;
};
struct max8925_power_pdata {
int (*set_charger)(int);
unsigned batt_detect:1;
unsigned topoff_threshold:2;
unsigned fast_charge:3; /* charge current */
unsigned no_temp_support:1; /* set if no temperature detect */
unsigned no_insert_detect:1; /* set if no ac insert detect */
char **supplied_to;
int num_supplicants;
};
/*
* irq_base: stores IRQ base number of MAX8925 in platform
* tsc_irq: stores IRQ number of MAX8925 TSC
*/
struct max8925_platform_data {
struct max8925_backlight_pdata *backlight;
struct max8925_touch_pdata *touch;
struct max8925_power_pdata *power;
struct regulator_init_data *regulator[MAX8925_MAX_REGULATOR];
int irq_base;
int tsc_irq;
};
extern int max8925_reg_read(struct i2c_client *, int);
extern int max8925_reg_write(struct i2c_client *, int, unsigned char);
extern int max8925_bulk_read(struct i2c_client *, int, int, unsigned char *);
extern int max8925_bulk_write(struct i2c_client *, int, int, unsigned char *);
extern int max8925_set_bits(struct i2c_client *, int, unsigned char,
unsigned char);
extern int max8925_device_init(struct max8925_chip *,
struct max8925_platform_data *);
extern void max8925_device_exit(struct max8925_chip *);
#endif /* __LINUX_MFD_MAX8925_H */
kernel/include/linux/mfd/max8997-private.h
+363
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/*
* max8997.h - Voltage regulator driver for the Maxim 8997
*
* Copyright (C) 2010 Samsung Electrnoics
* MyungJoo Ham <myungjoo.ham@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __LINUX_MFD_MAX8997_PRIV_H
#define __LINUX_MFD_MAX8997_PRIV_H
#include <linux/i2c.h>
#define MAX8997_REG_INVALID (0xff)
enum max8997_pmic_reg {
MAX8997_REG_PMIC_ID0 = 0x00,
MAX8997_REG_PMIC_ID1 = 0x01,
MAX8997_REG_INTSRC = 0x02,
MAX8997_REG_INT1 = 0x03,
MAX8997_REG_INT2 = 0x04,
MAX8997_REG_INT3 = 0x05,
MAX8997_REG_INT4 = 0x06,
MAX8997_REG_INT1MSK = 0x08,
MAX8997_REG_INT2MSK = 0x09,
MAX8997_REG_INT3MSK = 0x0a,
MAX8997_REG_INT4MSK = 0x0b,
MAX8997_REG_STATUS1 = 0x0d,
MAX8997_REG_STATUS2 = 0x0e,
MAX8997_REG_STATUS3 = 0x0f,
MAX8997_REG_STATUS4 = 0x10,
MAX8997_REG_MAINCON1 = 0x13,
MAX8997_REG_MAINCON2 = 0x14,
MAX8997_REG_BUCKRAMP = 0x15,
MAX8997_REG_BUCK1CTRL = 0x18,
MAX8997_REG_BUCK1DVS1 = 0x19,
MAX8997_REG_BUCK1DVS2 = 0x1a,
MAX8997_REG_BUCK1DVS3 = 0x1b,
MAX8997_REG_BUCK1DVS4 = 0x1c,
MAX8997_REG_BUCK1DVS5 = 0x1d,
MAX8997_REG_BUCK1DVS6 = 0x1e,
MAX8997_REG_BUCK1DVS7 = 0x1f,
MAX8997_REG_BUCK1DVS8 = 0x20,
MAX8997_REG_BUCK2CTRL = 0x21,
MAX8997_REG_BUCK2DVS1 = 0x22,
MAX8997_REG_BUCK2DVS2 = 0x23,
MAX8997_REG_BUCK2DVS3 = 0x24,
MAX8997_REG_BUCK2DVS4 = 0x25,
MAX8997_REG_BUCK2DVS5 = 0x26,
MAX8997_REG_BUCK2DVS6 = 0x27,
MAX8997_REG_BUCK2DVS7 = 0x28,
MAX8997_REG_BUCK2DVS8 = 0x29,
MAX8997_REG_BUCK3CTRL = 0x2a,
MAX8997_REG_BUCK3DVS = 0x2b,
MAX8997_REG_BUCK4CTRL = 0x2c,
MAX8997_REG_BUCK4DVS = 0x2d,
MAX8997_REG_BUCK5CTRL = 0x2e,
MAX8997_REG_BUCK5DVS1 = 0x2f,
MAX8997_REG_BUCK5DVS2 = 0x30,
MAX8997_REG_BUCK5DVS3 = 0x31,
MAX8997_REG_BUCK5DVS4 = 0x32,
MAX8997_REG_BUCK5DVS5 = 0x33,
MAX8997_REG_BUCK5DVS6 = 0x34,
MAX8997_REG_BUCK5DVS7 = 0x35,
MAX8997_REG_BUCK5DVS8 = 0x36,
MAX8997_REG_BUCK6CTRL = 0x37,
MAX8997_REG_BUCK6BPSKIPCTRL = 0x38,
MAX8997_REG_BUCK7CTRL = 0x39,
MAX8997_REG_BUCK7DVS = 0x3a,
MAX8997_REG_LDO1CTRL = 0x3b,
MAX8997_REG_LDO2CTRL = 0x3c,
MAX8997_REG_LDO3CTRL = 0x3d,
MAX8997_REG_LDO4CTRL = 0x3e,
MAX8997_REG_LDO5CTRL = 0x3f,
MAX8997_REG_LDO6CTRL = 0x40,
MAX8997_REG_LDO7CTRL = 0x41,
MAX8997_REG_LDO8CTRL = 0x42,
MAX8997_REG_LDO9CTRL = 0x43,
MAX8997_REG_LDO10CTRL = 0x44,
MAX8997_REG_LDO11CTRL = 0x45,
MAX8997_REG_LDO12CTRL = 0x46,
MAX8997_REG_LDO13CTRL = 0x47,
MAX8997_REG_LDO14CTRL = 0x48,
MAX8997_REG_LDO15CTRL = 0x49,
MAX8997_REG_LDO16CTRL = 0x4a,
MAX8997_REG_LDO17CTRL = 0x4b,
MAX8997_REG_LDO18CTRL = 0x4c,
MAX8997_REG_LDO21CTRL = 0x4d,
MAX8997_REG_MBCCTRL1 = 0x50,
MAX8997_REG_MBCCTRL2 = 0x51,
MAX8997_REG_MBCCTRL3 = 0x52,
MAX8997_REG_MBCCTRL4 = 0x53,
MAX8997_REG_MBCCTRL5 = 0x54,
MAX8997_REG_MBCCTRL6 = 0x55,
MAX8997_REG_OTPCGHCVS = 0x56,
MAX8997_REG_SAFEOUTCTRL = 0x5a,
MAX8997_REG_LBCNFG1 = 0x5e,
MAX8997_REG_LBCNFG2 = 0x5f,
MAX8997_REG_BBCCTRL = 0x60,
MAX8997_REG_FLASH1_CUR = 0x63, /* 0x63 ~ 0x6e for FLASH */
MAX8997_REG_FLASH2_CUR = 0x64,
MAX8997_REG_MOVIE_CUR = 0x65,
MAX8997_REG_GSMB_CUR = 0x66,
MAX8997_REG_BOOST_CNTL = 0x67,
MAX8997_REG_LEN_CNTL = 0x68,
MAX8997_REG_FLASH_CNTL = 0x69,
MAX8997_REG_WDT_CNTL = 0x6a,
MAX8997_REG_MAXFLASH1 = 0x6b,
MAX8997_REG_MAXFLASH2 = 0x6c,
MAX8997_REG_FLASHSTATUS = 0x6d,
MAX8997_REG_FLASHSTATUSMASK = 0x6e,
MAX8997_REG_GPIOCNTL1 = 0x70,
MAX8997_REG_GPIOCNTL2 = 0x71,
MAX8997_REG_GPIOCNTL3 = 0x72,
MAX8997_REG_GPIOCNTL4 = 0x73,
MAX8997_REG_GPIOCNTL5 = 0x74,
MAX8997_REG_GPIOCNTL6 = 0x75,
MAX8997_REG_GPIOCNTL7 = 0x76,
MAX8997_REG_GPIOCNTL8 = 0x77,
MAX8997_REG_GPIOCNTL9 = 0x78,
MAX8997_REG_GPIOCNTL10 = 0x79,
MAX8997_REG_GPIOCNTL11 = 0x7a,
MAX8997_REG_GPIOCNTL12 = 0x7b,
MAX8997_REG_LDO1CONFIG = 0x80,
MAX8997_REG_LDO2CONFIG = 0x81,
MAX8997_REG_LDO3CONFIG = 0x82,
MAX8997_REG_LDO4CONFIG = 0x83,
MAX8997_REG_LDO5CONFIG = 0x84,
MAX8997_REG_LDO6CONFIG = 0x85,
MAX8997_REG_LDO7CONFIG = 0x86,
MAX8997_REG_LDO8CONFIG = 0x87,
MAX8997_REG_LDO9CONFIG = 0x88,
MAX8997_REG_LDO10CONFIG = 0x89,
MAX8997_REG_LDO11CONFIG = 0x8a,
MAX8997_REG_LDO12CONFIG = 0x8b,
MAX8997_REG_LDO13CONFIG = 0x8c,
MAX8997_REG_LDO14CONFIG = 0x8d,
MAX8997_REG_LDO15CONFIG = 0x8e,
MAX8997_REG_LDO16CONFIG = 0x8f,
MAX8997_REG_LDO17CONFIG = 0x90,
MAX8997_REG_LDO18CONFIG = 0x91,
MAX8997_REG_LDO21CONFIG = 0x92,
MAX8997_REG_DVSOKTIMER1 = 0x97,
MAX8997_REG_DVSOKTIMER2 = 0x98,
MAX8997_REG_DVSOKTIMER4 = 0x99,
MAX8997_REG_DVSOKTIMER5 = 0x9a,
MAX8997_REG_PMIC_END = 0x9b,
};
enum max8997_muic_reg {
MAX8997_MUIC_REG_ID = 0x0,
MAX8997_MUIC_REG_INT1 = 0x1,
MAX8997_MUIC_REG_INT2 = 0x2,
MAX8997_MUIC_REG_INT3 = 0x3,
MAX8997_MUIC_REG_STATUS1 = 0x4,
MAX8997_MUIC_REG_STATUS2 = 0x5,
MAX8997_MUIC_REG_STATUS3 = 0x6,
MAX8997_MUIC_REG_INTMASK1 = 0x7,
MAX8997_MUIC_REG_INTMASK2 = 0x8,
MAX8997_MUIC_REG_INTMASK3 = 0x9,
MAX8997_MUIC_REG_CDETCTRL = 0xa,
MAX8997_MUIC_REG_CONTROL1 = 0xc,
MAX8997_MUIC_REG_CONTROL2 = 0xd,
MAX8997_MUIC_REG_CONTROL3 = 0xe,
MAX8997_MUIC_REG_END = 0xf,
};
enum max8997_haptic_reg {
MAX8997_HAPTIC_REG_GENERAL = 0x00,
MAX8997_HAPTIC_REG_CONF1 = 0x01,
MAX8997_HAPTIC_REG_CONF2 = 0x02,
MAX8997_HAPTIC_REG_DRVCONF = 0x03,
MAX8997_HAPTIC_REG_CYCLECONF1 = 0x04,
MAX8997_HAPTIC_REG_CYCLECONF2 = 0x05,
MAX8997_HAPTIC_REG_SIGCONF1 = 0x06,
MAX8997_HAPTIC_REG_SIGCONF2 = 0x07,
MAX8997_HAPTIC_REG_SIGCONF3 = 0x08,
MAX8997_HAPTIC_REG_SIGCONF4 = 0x09,
MAX8997_HAPTIC_REG_SIGDC1 = 0x0a,
MAX8997_HAPTIC_REG_SIGDC2 = 0x0b,
MAX8997_HAPTIC_REG_SIGPWMDC1 = 0x0c,
MAX8997_HAPTIC_REG_SIGPWMDC2 = 0x0d,
MAX8997_HAPTIC_REG_SIGPWMDC3 = 0x0e,
MAX8997_HAPTIC_REG_SIGPWMDC4 = 0x0f,
MAX8997_HAPTIC_REG_MTR_REV = 0x10,
MAX8997_HAPTIC_REG_END = 0x11,
};
/* slave addr = 0x0c: using "2nd part" of rev4 datasheet */
enum max8997_rtc_reg {
MAX8997_RTC_CTRLMASK = 0x02,
MAX8997_RTC_CTRL = 0x03,
MAX8997_RTC_UPDATE1 = 0x04,
MAX8997_RTC_UPDATE2 = 0x05,
MAX8997_RTC_WTSR_SMPL = 0x06,
MAX8997_RTC_SEC = 0x10,
MAX8997_RTC_MIN = 0x11,
MAX8997_RTC_HOUR = 0x12,
MAX8997_RTC_DAY_OF_WEEK = 0x13,
MAX8997_RTC_MONTH = 0x14,
MAX8997_RTC_YEAR = 0x15,
MAX8997_RTC_DAY_OF_MONTH = 0x16,
MAX8997_RTC_ALARM1_SEC = 0x17,
MAX8997_RTC_ALARM1_MIN = 0x18,
MAX8997_RTC_ALARM1_HOUR = 0x19,
MAX8997_RTC_ALARM1_DAY_OF_WEEK = 0x1a,
MAX8997_RTC_ALARM1_MONTH = 0x1b,
MAX8997_RTC_ALARM1_YEAR = 0x1c,
MAX8997_RTC_ALARM1_DAY_OF_MONTH = 0x1d,
MAX8997_RTC_ALARM2_SEC = 0x1e,
MAX8997_RTC_ALARM2_MIN = 0x1f,
MAX8997_RTC_ALARM2_HOUR = 0x20,
MAX8997_RTC_ALARM2_DAY_OF_WEEK = 0x21,
MAX8997_RTC_ALARM2_MONTH = 0x22,
MAX8997_RTC_ALARM2_YEAR = 0x23,
MAX8997_RTC_ALARM2_DAY_OF_MONTH = 0x24,
};
enum max8997_irq_source {
PMIC_INT1 = 0,
PMIC_INT2,
PMIC_INT3,
PMIC_INT4,
FUEL_GAUGE, /* Ignored (MAX17042 driver handles) */
MUIC_INT1,
MUIC_INT2,
MUIC_INT3,
GPIO_LOW, /* Not implemented */
GPIO_HI, /* Not implemented */
FLASH_STATUS, /* Not implemented */
MAX8997_IRQ_GROUP_NR,
};
enum max8997_irq {
MAX8997_PMICIRQ_PWRONR,
MAX8997_PMICIRQ_PWRONF,
MAX8997_PMICIRQ_PWRON1SEC,
MAX8997_PMICIRQ_JIGONR,
MAX8997_PMICIRQ_JIGONF,
MAX8997_PMICIRQ_LOWBAT2,
MAX8997_PMICIRQ_LOWBAT1,
MAX8997_PMICIRQ_JIGR,
MAX8997_PMICIRQ_JIGF,
MAX8997_PMICIRQ_MR,
MAX8997_PMICIRQ_DVS1OK,
MAX8997_PMICIRQ_DVS2OK,
MAX8997_PMICIRQ_DVS3OK,
MAX8997_PMICIRQ_DVS4OK,
MAX8997_PMICIRQ_CHGINS,
MAX8997_PMICIRQ_CHGRM,
MAX8997_PMICIRQ_DCINOVP,
MAX8997_PMICIRQ_TOPOFFR,
MAX8997_PMICIRQ_CHGRSTF,
MAX8997_PMICIRQ_MBCHGTMEXPD,
MAX8997_PMICIRQ_RTC60S,
MAX8997_PMICIRQ_RTCA1,
MAX8997_PMICIRQ_RTCA2,
MAX8997_PMICIRQ_SMPL_INT,
MAX8997_PMICIRQ_RTC1S,
MAX8997_PMICIRQ_WTSR,
MAX8997_MUICIRQ_ADCError,
MAX8997_MUICIRQ_ADCLow,
MAX8997_MUICIRQ_ADC,
MAX8997_MUICIRQ_VBVolt,
MAX8997_MUICIRQ_DBChg,
MAX8997_MUICIRQ_DCDTmr,
MAX8997_MUICIRQ_ChgDetRun,
MAX8997_MUICIRQ_ChgTyp,
MAX8997_MUICIRQ_OVP,
MAX8997_IRQ_NR,
};
#define MAX8997_NUM_GPIO 12
struct max8997_dev {
struct device *dev;
struct i2c_client *i2c; /* 0xcc / PMIC, Battery Control, and FLASH */
struct i2c_client *rtc; /* slave addr 0x0c */
struct i2c_client *haptic; /* slave addr 0x90 */
struct i2c_client *muic; /* slave addr 0x4a */
struct mutex iolock;
int type;
struct platform_device *battery; /* battery control (not fuel gauge) */
int irq;
int ono;
int irq_base;
struct mutex irqlock;
int irq_masks_cur[MAX8997_IRQ_GROUP_NR];
int irq_masks_cache[MAX8997_IRQ_GROUP_NR];
/* For hibernation */
u8 reg_dump[MAX8997_REG_PMIC_END + MAX8997_MUIC_REG_END +
MAX8997_HAPTIC_REG_END];
bool gpio_status[MAX8997_NUM_GPIO];
};
enum max8997_types {
TYPE_MAX8997,
TYPE_MAX8966,
};
extern int max8997_irq_init(struct max8997_dev *max8997);
extern void max8997_irq_exit(struct max8997_dev *max8997);
extern int max8997_irq_resume(struct max8997_dev *max8997);
extern int max8997_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
extern int max8997_bulk_read(struct i2c_client *i2c, u8 reg, int count,
u8 *buf);
extern int max8997_write_reg(struct i2c_client *i2c, u8 reg, u8 value);
extern int max8997_bulk_write(struct i2c_client *i2c, u8 reg, int count,
u8 *buf);
extern int max8997_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask);
#define MAX8997_GPIO_INT_BOTH (0x3 << 4)
#define MAX8997_GPIO_INT_RISE (0x2 << 4)
#define MAX8997_GPIO_INT_FALL (0x1 << 4)
#define MAX8997_GPIO_INT_MASK (0x3 << 4)
#define MAX8997_GPIO_DATA_MASK (0x1 << 2)
#endif /* __LINUX_MFD_MAX8997_PRIV_H */
kernel/include/linux/mfd/max8997.h
+252
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/*
* max8997.h - Driver for the Maxim 8997/8966
*
* Copyright (C) 2009-2010 Samsung Electrnoics
* MyungJoo Ham <myungjoo.ham@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* This driver is based on max8998.h
*
* MAX8997 has PMIC, MUIC, HAPTIC, RTC, FLASH, and Fuel Gauge devices.
* Except Fuel Gauge, every device shares the same I2C bus and included in
* this mfd driver. Although the fuel gauge is included in the chip, it is
* excluded from the driver because a) it has a different I2C bus from
* others and b) it can be enabled simply by using MAX17042 driver.
*/
#ifndef __LINUX_MFD_MAX8998_H
#define __LINUX_MFD_MAX8998_H
#include <linux/regulator/consumer.h>
/* MAX8997/8966 regulator IDs */
enum max8998_regulators {
MAX8997_LDO1 = 0,
MAX8997_LDO2,
MAX8997_LDO3,
MAX8997_LDO4,
MAX8997_LDO5,
MAX8997_LDO6,
MAX8997_LDO7,
MAX8997_LDO8,
MAX8997_LDO9,
MAX8997_LDO10,
MAX8997_LDO11,
MAX8997_LDO12,
MAX8997_LDO13,
MAX8997_LDO14,
MAX8997_LDO15,
MAX8997_LDO16,
MAX8997_LDO17,
MAX8997_LDO18,
MAX8997_LDO21,
MAX8997_BUCK1,
MAX8997_BUCK2,
MAX8997_BUCK3,
MAX8997_BUCK4,
MAX8997_BUCK5,
MAX8997_BUCK6,
MAX8997_BUCK7,
MAX8997_EN32KHZ_AP,
MAX8997_EN32KHZ_CP,
MAX8997_ENVICHG,
MAX8997_ESAFEOUT1,
MAX8997_ESAFEOUT2,
MAX8997_CHARGER_CV, /* control MBCCV of MBCCTRL3 */
MAX8997_CHARGER, /* charger current, MBCCTRL4 */
MAX8997_CHARGER_TOPOFF, /* MBCCTRL5 */
MAX8997_REG_MAX,
};
struct max8997_regulator_data {
int id;
struct regulator_init_data *initdata;
};
enum max8997_muic_usb_type {
MAX8997_USB_HOST,
MAX8997_USB_DEVICE,
};
enum max8997_muic_charger_type {
MAX8997_CHARGER_TYPE_NONE = 0,
MAX8997_CHARGER_TYPE_USB,
MAX8997_CHARGER_TYPE_DOWNSTREAM_PORT,
MAX8997_CHARGER_TYPE_DEDICATED_CHG,
MAX8997_CHARGER_TYPE_500MA,
MAX8997_CHARGER_TYPE_1A,
MAX8997_CHARGER_TYPE_DEAD_BATTERY = 7,
};
struct max8997_muic_reg_data {
u8 addr;
u8 data;
};
/**
* struct max8997_muic_platform_data
* @usb_callback: callback function for USB
* inform callee of USB type (HOST or DEVICE)
* and attached state(true or false)
* @charger_callback: callback function for charger
* inform callee of charger_type
* and attached state(true or false)
* @deskdock_callback: callback function for desk dock
* inform callee of attached state(true or false)
* @cardock_callback: callback function for car dock
* inform callee of attached state(true or false)
* @mhl_callback: callback function for MHL (Mobile High-definition Link)
* inform callee of attached state(true or false)
* @uart_callback: callback function for JIG UART
* inform callee of attached state(true or false)
* @init_data: array of max8997_muic_reg_data
* used for initializing registers of MAX8997 MUIC device
* @num_init_data: array size of init_data
*/
struct max8997_muic_platform_data {
void (*usb_callback)(enum max8997_muic_usb_type usb_type,
bool attached);
void (*charger_callback)(bool attached,
enum max8997_muic_charger_type charger_type);
void (*deskdock_callback) (bool attached);
void (*cardock_callback) (bool attached);
void (*mhl_callback) (bool attached);
void (*uart_callback) (bool attached);
struct max8997_muic_reg_data *init_data;
int num_init_data;
};
enum max8997_haptic_motor_type {
MAX8997_HAPTIC_ERM,
MAX8997_HAPTIC_LRA,
};
enum max8997_haptic_pulse_mode {
MAX8997_EXTERNAL_MODE,
MAX8997_INTERNAL_MODE,
};
enum max8997_haptic_pwm_divisor {
MAX8997_PWM_DIVISOR_32,
MAX8997_PWM_DIVISOR_64,
MAX8997_PWM_DIVISOR_128,
MAX8997_PWM_DIVISOR_256,
};
/**
* max8997_haptic_platform_data
* @pwm_channel_id: channel number of PWM device
* valid for MAX8997_EXTERNAL_MODE
* @pwm_period: period in nano second for PWM device
* valid for MAX8997_EXTERNAL_MODE
* @type: motor type
* @mode: pulse mode
* MAX8997_EXTERNAL_MODE: external PWM device is used to control motor
* MAX8997_INTERNAL_MODE: internal pulse generator is used to control motor
* @pwm_divisor: divisor for external PWM device
* @internal_mode_pattern: internal mode pattern for internal mode
* [0 - 3]: valid pattern number
* @pattern_cycle: the number of cycles of the waveform
* for the internal mode pattern
* [0 - 15]: available cycles
* @pattern_signal_period: period of the waveform for the internal mode pattern
* [0 - 255]: available period
*/
struct max8997_haptic_platform_data {
unsigned int pwm_channel_id;
unsigned int pwm_period;
enum max8997_haptic_motor_type type;
enum max8997_haptic_pulse_mode mode;
enum max8997_haptic_pwm_divisor pwm_divisor;
unsigned int internal_mode_pattern;
unsigned int pattern_cycle;
unsigned int pattern_signal_period;
};
enum max8997_led_mode {
MAX8997_NONE,
MAX8997_FLASH_MODE,
MAX8997_MOVIE_MODE,
MAX8997_FLASH_PIN_CONTROL_MODE,
MAX8997_MOVIE_PIN_CONTROL_MODE,
};
/**
* struct max8997_led_platform_data
* The number of LED devices for MAX8997 is two
* @mode: LED mode for each LED device
* @brightness: initial brightness for each LED device
* range:
* [0 - 31]: MAX8997_FLASH_MODE and MAX8997_FLASH_PIN_CONTROL_MODE
* [0 - 15]: MAX8997_MOVIE_MODE and MAX8997_MOVIE_PIN_CONTROL_MODE
*/
struct max8997_led_platform_data {
enum max8997_led_mode mode[2];
u8 brightness[2];
};
struct max8997_platform_data {
/* IRQ */
int irq_base;
int ono;
int wakeup;
/* ---- PMIC ---- */
struct max8997_regulator_data *regulators;
int num_regulators;
/*
* SET1~3 DVS GPIOs control Buck1, 2, and 5 simultaneously. Therefore,
* With buckx_gpiodvs enabled, the buckx cannot be controlled
* independently. To control buckx (of 1, 2, and 5) independently,
* disable buckx_gpiodvs and control with BUCKxDVS1 register.
*
* When buckx_gpiodvs and bucky_gpiodvs are both enabled, set_voltage
* on buckx will change the voltage of bucky at the same time.
*
*/
bool ignore_gpiodvs_side_effect;
int buck125_gpios[3]; /* GPIO of [0]SET1, [1]SET2, [2]SET3 */
int buck125_default_idx; /* Default value of SET1, 2, 3 */
unsigned int buck1_voltage[8]; /* buckx_voltage in uV */
bool buck1_gpiodvs;
unsigned int buck2_voltage[8];
bool buck2_gpiodvs;
unsigned int buck5_voltage[8];
bool buck5_gpiodvs;
/* ---- Charger control ---- */
/* eoc stands for 'end of charge' */
int eoc_mA; /* 50 ~ 200mA by 10mA step */
/* charge Full Timeout */
int timeout; /* 0 (no timeout), 5, 6, 7 hours */
/* ---- MUIC ---- */
struct max8997_muic_platform_data *muic_pdata;
/* ---- HAPTIC ---- */
struct max8997_haptic_platform_data *haptic_pdata;
/* RTC: Not implemented */
/* ---- LED ---- */
struct max8997_led_platform_data *led_pdata;
};
#endif /* __LINUX_MFD_MAX8998_H */
kernel/include/linux/mfd/max8998-private.h
+177
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/*
* max8998.h - Voltage regulator driver for the Maxim 8998
*
* Copyright (C) 2009-2010 Samsung Electrnoics
* Kyungmin Park <kyungmin.park@samsung.com>
* Marek Szyprowski <m.szyprowski@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __LINUX_MFD_MAX8998_PRIV_H
#define __LINUX_MFD_MAX8998_PRIV_H
#define MAX8998_NUM_IRQ_REGS 4
/* MAX 8998 registers */
enum {
MAX8998_REG_IRQ1,
MAX8998_REG_IRQ2,
MAX8998_REG_IRQ3,
MAX8998_REG_IRQ4,
MAX8998_REG_IRQM1,
MAX8998_REG_IRQM2,
MAX8998_REG_IRQM3,
MAX8998_REG_IRQM4,
MAX8998_REG_STATUS1,
MAX8998_REG_STATUS2,
MAX8998_REG_STATUSM1,
MAX8998_REG_STATUSM2,
MAX8998_REG_CHGR1,
MAX8998_REG_CHGR2,
MAX8998_REG_LDO_ACTIVE_DISCHARGE1,
MAX8998_REG_LDO_ACTIVE_DISCHARGE2,
MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
MAX8998_REG_ONOFF1,
MAX8998_REG_ONOFF2,
MAX8998_REG_ONOFF3,
MAX8998_REG_ONOFF4,
MAX8998_REG_BUCK1_VOLTAGE1,
MAX8998_REG_BUCK1_VOLTAGE2,
MAX8998_REG_BUCK1_VOLTAGE3,
MAX8998_REG_BUCK1_VOLTAGE4,
MAX8998_REG_BUCK2_VOLTAGE1,
MAX8998_REG_BUCK2_VOLTAGE2,
MAX8998_REG_BUCK3,
MAX8998_REG_BUCK4,
MAX8998_REG_LDO2_LDO3,
MAX8998_REG_LDO4,
MAX8998_REG_LDO5,
MAX8998_REG_LDO6,
MAX8998_REG_LDO7,
MAX8998_REG_LDO8_LDO9,
MAX8998_REG_LDO10_LDO11,
MAX8998_REG_LDO12,
MAX8998_REG_LDO13,
MAX8998_REG_LDO14,
MAX8998_REG_LDO15,
MAX8998_REG_LDO16,
MAX8998_REG_LDO17,
MAX8998_REG_BKCHR,
MAX8998_REG_LBCNFG1,
MAX8998_REG_LBCNFG2,
};
/* IRQ definitions */
enum {
MAX8998_IRQ_DCINF,
MAX8998_IRQ_DCINR,
MAX8998_IRQ_JIGF,
MAX8998_IRQ_JIGR,
MAX8998_IRQ_PWRONF,
MAX8998_IRQ_PWRONR,
MAX8998_IRQ_WTSREVNT,
MAX8998_IRQ_SMPLEVNT,
MAX8998_IRQ_ALARM1,
MAX8998_IRQ_ALARM0,
MAX8998_IRQ_ONKEY1S,
MAX8998_IRQ_TOPOFFR,
MAX8998_IRQ_DCINOVPR,
MAX8998_IRQ_CHGRSTF,
MAX8998_IRQ_DONER,
MAX8998_IRQ_CHGFAULT,
MAX8998_IRQ_LOBAT1,
MAX8998_IRQ_LOBAT2,
MAX8998_IRQ_NR,
};
/* MAX8998 various variants */
enum {
TYPE_MAX8998 = 0, /* Default */
TYPE_LP3974, /* National version of MAX8998 */
TYPE_LP3979, /* Added AVS */
};
#define MAX8998_IRQ_DCINF_MASK (1 << 2)
#define MAX8998_IRQ_DCINR_MASK (1 << 3)
#define MAX8998_IRQ_JIGF_MASK (1 << 4)
#define MAX8998_IRQ_JIGR_MASK (1 << 5)
#define MAX8998_IRQ_PWRONF_MASK (1 << 6)
#define MAX8998_IRQ_PWRONR_MASK (1 << 7)
#define MAX8998_IRQ_WTSREVNT_MASK (1 << 0)
#define MAX8998_IRQ_SMPLEVNT_MASK (1 << 1)
#define MAX8998_IRQ_ALARM1_MASK (1 << 2)
#define MAX8998_IRQ_ALARM0_MASK (1 << 3)
#define MAX8998_IRQ_ONKEY1S_MASK (1 << 0)
#define MAX8998_IRQ_TOPOFFR_MASK (1 << 2)
#define MAX8998_IRQ_DCINOVPR_MASK (1 << 3)
#define MAX8998_IRQ_CHGRSTF_MASK (1 << 4)
#define MAX8998_IRQ_DONER_MASK (1 << 5)
#define MAX8998_IRQ_CHGFAULT_MASK (1 << 7)
#define MAX8998_IRQ_LOBAT1_MASK (1 << 0)
#define MAX8998_IRQ_LOBAT2_MASK (1 << 1)
#define MAX8998_ENRAMP (1 << 4)
/**
* struct max8998_dev - max8998 master device for sub-drivers
* @dev: master device of the chip (can be used to access platform data)
* @i2c: i2c client private data for regulator
* @rtc: i2c client private data for rtc
* @iolock: mutex for serializing io access
* @irqlock: mutex for buslock
* @irq_base: base IRQ number for max8998, required for IRQs
* @irq: generic IRQ number for max8998
* @ono: power onoff IRQ number for max8998
* @irq_masks_cur: currently active value
* @irq_masks_cache: cached hardware value
* @type: indicate which max8998 "variant" is used
*/
struct max8998_dev {
struct device *dev;
struct i2c_client *i2c;
struct i2c_client *rtc;
struct mutex iolock;
struct mutex irqlock;
int irq_base;
int irq;
int ono;
u8 irq_masks_cur[MAX8998_NUM_IRQ_REGS];
u8 irq_masks_cache[MAX8998_NUM_IRQ_REGS];
int type;
bool wakeup;
};
int max8998_irq_init(struct max8998_dev *max8998);
void max8998_irq_exit(struct max8998_dev *max8998);
int max8998_irq_resume(struct max8998_dev *max8998);
extern int max8998_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
extern int max8998_bulk_read(struct i2c_client *i2c, u8 reg, int count,
u8 *buf);
extern int max8998_write_reg(struct i2c_client *i2c, u8 reg, u8 value);
extern int max8998_bulk_write(struct i2c_client *i2c, u8 reg, int count,
u8 *buf);
extern int max8998_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask);
#endif /* __LINUX_MFD_MAX8998_PRIV_H */
kernel/include/linux/mfd/max8998.h
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/*
* max8998.h - Voltage regulator driver for the Maxim 8998
*
* Copyright (C) 2009-2010 Samsung Electrnoics
* Kyungmin Park <kyungmin.park@samsung.com>
* Marek Szyprowski <m.szyprowski@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __LINUX_MFD_MAX8998_H
#define __LINUX_MFD_MAX8998_H
#include <linux/regulator/machine.h>
/* MAX 8998 regulator ids */
enum {
MAX8998_LDO2 = 2,
MAX8998_LDO3,
MAX8998_LDO4,
MAX8998_LDO5,
MAX8998_LDO6,
MAX8998_LDO7,
MAX8998_LDO8,
MAX8998_LDO9,
MAX8998_LDO10,
MAX8998_LDO11,
MAX8998_LDO12,
MAX8998_LDO13,
MAX8998_LDO14,
MAX8998_LDO15,
MAX8998_LDO16,
MAX8998_LDO17,
MAX8998_BUCK1,
MAX8998_BUCK2,
MAX8998_BUCK3,
MAX8998_BUCK4,
MAX8998_EN32KHZ_AP,
MAX8998_EN32KHZ_CP,
MAX8998_ENVICHG,
MAX8998_ESAFEOUT1,
MAX8998_ESAFEOUT2,
};
/**
* max8998_regulator_data - regulator data
* @id: regulator id
* @initdata: regulator init data (contraints, supplies, ...)
*/
struct max8998_regulator_data {
int id;
struct regulator_init_data *initdata;
};
/**
* struct max8998_board - packages regulator init data
* @regulators: array of defined regulators
* @num_regulators: number of regultors used
* @irq_base: base IRQ number for max8998, required for IRQs
* @ono: power onoff IRQ number for max8998
* @buck_voltage_lock: Do NOT change the values of the following six
* registers set by buck?_voltage?. The voltage of BUCK1/2 cannot
* be other than the preset values.
* @buck1_voltage1: BUCK1 DVS mode 1 voltage register
* @buck1_voltage2: BUCK1 DVS mode 2 voltage register
* @buck1_voltage3: BUCK1 DVS mode 3 voltage register
* @buck1_voltage4: BUCK1 DVS mode 4 voltage register
* @buck2_voltage1: BUCK2 DVS mode 1 voltage register
* @buck2_voltage2: BUCK2 DVS mode 2 voltage register
* @buck1_set1: BUCK1 gpio pin 1 to set output voltage
* @buck1_set2: BUCK1 gpio pin 2 to set output voltage
* @buck1_default_idx: Default for BUCK1 gpio pin 1, 2
* @buck2_set3: BUCK2 gpio pin to set output voltage
* @buck2_default_idx: Default for BUCK2 gpio pin.
* @wakeup: Allow to wake up from suspend
* @rtc_delay: LP3974 RTC chip bug that requires delay after a register
* write before reading it.
* @eoc: End of Charge Level in percent: 10% ~ 45% by 5% step
* If it equals 0, leave it unchanged.
* Otherwise, it is a invalid value.
* @restart: Restart Level in mV: 100, 150, 200, and -1 for disable.
* If it equals 0, leave it unchanged.
* Otherwise, it is a invalid value.
* @timeout: Full Timeout in hours: 5, 6, 7, and -1 for disable.
* If it equals 0, leave it unchanged.
* Otherwise, leave it unchanged.
*/
struct max8998_platform_data {
struct max8998_regulator_data *regulators;
int num_regulators;
int irq_base;
int ono;
bool buck_voltage_lock;
int buck1_voltage1;
int buck1_voltage2;
int buck1_voltage3;
int buck1_voltage4;
int buck2_voltage1;
int buck2_voltage2;
int buck1_set1;
int buck1_set2;
int buck1_default_idx;
int buck2_set3;
int buck2_default_idx;
bool wakeup;
bool rtc_delay;
int eoc;
int restart;
int timeout;
};
#endif /* __LINUX_MFD_MAX8998_H */
kernel/include/linux/mfd/mc13783.h
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/*
* Copyright 2010 Yong Shen <yong.shen@linaro.org>
* Copyright 2009-2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#ifndef __LINUX_MFD_MC13783_H
#define __LINUX_MFD_MC13783_H
#include <linux/mfd/mc13xxx.h>
#define MC13783_REG_SW1A 0
#define MC13783_REG_SW1B 1
#define MC13783_REG_SW2A 2
#define MC13783_REG_SW2B 3
#define MC13783_REG_SW3 4
#define MC13783_REG_PLL 5
#define MC13783_REG_VAUDIO 6
#define MC13783_REG_VIOHI 7
#define MC13783_REG_VIOLO 8
#define MC13783_REG_VDIG 9
#define MC13783_REG_VGEN 10
#define MC13783_REG_VRFDIG 11
#define MC13783_REG_VRFREF 12
#define MC13783_REG_VRFCP 13
#define MC13783_REG_VSIM 14
#define MC13783_REG_VESIM 15
#define MC13783_REG_VCAM 16
#define MC13783_REG_VRFBG 17
#define MC13783_REG_VVIB 18
#define MC13783_REG_VRF1 19
#define MC13783_REG_VRF2 20
#define MC13783_REG_VMMC1 21
#define MC13783_REG_VMMC2 22
#define MC13783_REG_GPO1 23
#define MC13783_REG_GPO2 24
#define MC13783_REG_GPO3 25
#define MC13783_REG_GPO4 26
#define MC13783_REG_V1 27
#define MC13783_REG_V2 28
#define MC13783_REG_V3 29
#define MC13783_REG_V4 30
#define MC13783_REG_PWGT1SPI 31
#define MC13783_REG_PWGT2SPI 32
#define MC13783_IRQ_ADCDONE MC13XXX_IRQ_ADCDONE
#define MC13783_IRQ_ADCBISDONE MC13XXX_IRQ_ADCBISDONE
#define MC13783_IRQ_TS MC13XXX_IRQ_TS
#define MC13783_IRQ_WHIGH 3
#define MC13783_IRQ_WLOW 4
#define MC13783_IRQ_CHGDET MC13XXX_IRQ_CHGDET
#define MC13783_IRQ_CHGOV 7
#define MC13783_IRQ_CHGREV MC13XXX_IRQ_CHGREV
#define MC13783_IRQ_CHGSHORT MC13XXX_IRQ_CHGSHORT
#define MC13783_IRQ_CCCV MC13XXX_IRQ_CCCV
#define MC13783_IRQ_CHGCURR MC13XXX_IRQ_CHGCURR
#define MC13783_IRQ_BPON MC13XXX_IRQ_BPON
#define MC13783_IRQ_LOBATL MC13XXX_IRQ_LOBATL
#define MC13783_IRQ_LOBATH MC13XXX_IRQ_LOBATH
#define MC13783_IRQ_UDP 15
#define MC13783_IRQ_USB 16
#define MC13783_IRQ_ID 19
#define MC13783_IRQ_SE1 21
#define MC13783_IRQ_CKDET 22
#define MC13783_IRQ_UDM 23
#define MC13783_IRQ_1HZ MC13XXX_IRQ_1HZ
#define MC13783_IRQ_TODA MC13XXX_IRQ_TODA
#define MC13783_IRQ_ONOFD1 27
#define MC13783_IRQ_ONOFD2 28
#define MC13783_IRQ_ONOFD3 29
#define MC13783_IRQ_SYSRST MC13XXX_IRQ_SYSRST
#define MC13783_IRQ_RTCRST MC13XXX_IRQ_RTCRST
#define MC13783_IRQ_PC MC13XXX_IRQ_PC
#define MC13783_IRQ_WARM MC13XXX_IRQ_WARM
#define MC13783_IRQ_MEMHLD MC13XXX_IRQ_MEMHLD
#define MC13783_IRQ_PWRRDY 35
#define MC13783_IRQ_THWARNL MC13XXX_IRQ_THWARNL
#define MC13783_IRQ_THWARNH MC13XXX_IRQ_THWARNH
#define MC13783_IRQ_CLK MC13XXX_IRQ_CLK
#define MC13783_IRQ_SEMAF 39
#define MC13783_IRQ_MC2B 41
#define MC13783_IRQ_HSDET 42
#define MC13783_IRQ_HSL 43
#define MC13783_IRQ_ALSPTH 44
#define MC13783_IRQ_AHSSHORT 45
#define MC13783_NUM_IRQ MC13XXX_NUM_IRQ
#endif /* ifndef __LINUX_MFD_MC13783_H */
kernel/include/linux/mfd/mc13892.h
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/*
* Copyright 2010 Yong Shen <yong.shen@linaro.org>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#ifndef __LINUX_MFD_MC13892_H
#define __LINUX_MFD_MC13892_H
#include <linux/mfd/mc13xxx.h>
#define MC13892_SW1 0
#define MC13892_SW2 1
#define MC13892_SW3 2
#define MC13892_SW4 3
#define MC13892_SWBST 4
#define MC13892_VIOHI 5
#define MC13892_VPLL 6
#define MC13892_VDIG 7
#define MC13892_VSD 8
#define MC13892_VUSB2 9
#define MC13892_VVIDEO 10
#define MC13892_VAUDIO 11
#define MC13892_VCAM 12
#define MC13892_VGEN1 13
#define MC13892_VGEN2 14
#define MC13892_VGEN3 15
#define MC13892_VUSB 16
#define MC13892_GPO1 17
#define MC13892_GPO2 18
#define MC13892_GPO3 19
#define MC13892_GPO4 20
#define MC13892_PWGT1SPI 21
#define MC13892_PWGT2SPI 22
#define MC13892_VCOINCELL 23
#endif
kernel/include/linux/mfd/mc13xxx.h
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/*
* Copyright 2009-2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#ifndef __LINUX_MFD_MC13XXX_H
#define __LINUX_MFD_MC13XXX_H
#include <linux/interrupt.h>
struct mc13xxx;
void mc13xxx_lock(struct mc13xxx *mc13xxx);
void mc13xxx_unlock(struct mc13xxx *mc13xxx);
int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val);
int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val);
int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
u32 mask, u32 val);
int mc13xxx_get_flags(struct mc13xxx *mc13xxx);
int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
irq_handler_t handler, const char *name, void *dev);
int mc13xxx_irq_request_nounmask(struct mc13xxx *mc13xxx, int irq,
irq_handler_t handler, const char *name, void *dev);
int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev);
int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq);
int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq);
int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
int *enabled, int *pending);
int mc13xxx_irq_ack(struct mc13xxx *mc13xxx, int irq);
int mc13xxx_get_flags(struct mc13xxx *mc13xxx);
int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx,
unsigned int mode, unsigned int channel,
u8 ato, bool atox, unsigned int *sample);
#define MC13XXX_IRQ_ADCDONE 0
#define MC13XXX_IRQ_ADCBISDONE 1
#define MC13XXX_IRQ_TS 2
#define MC13XXX_IRQ_CHGDET 6
#define MC13XXX_IRQ_CHGREV 8
#define MC13XXX_IRQ_CHGSHORT 9
#define MC13XXX_IRQ_CCCV 10
#define MC13XXX_IRQ_CHGCURR 11
#define MC13XXX_IRQ_BPON 12
#define MC13XXX_IRQ_LOBATL 13
#define MC13XXX_IRQ_LOBATH 14
#define MC13XXX_IRQ_1HZ 24
#define MC13XXX_IRQ_TODA 25
#define MC13XXX_IRQ_SYSRST 30
#define MC13XXX_IRQ_RTCRST 31
#define MC13XXX_IRQ_PC 32
#define MC13XXX_IRQ_WARM 33
#define MC13XXX_IRQ_MEMHLD 34
#define MC13XXX_IRQ_THWARNL 36
#define MC13XXX_IRQ_THWARNH 37
#define MC13XXX_IRQ_CLK 38
#define MC13XXX_NUM_IRQ 46
struct regulator_init_data;
struct mc13xxx_regulator_init_data {
int id;
struct regulator_init_data *init_data;
struct device_node *node;
};
struct mc13xxx_regulator_platform_data {
int num_regulators;
struct mc13xxx_regulator_init_data *regulators;
};
struct mc13xxx_led_platform_data {
#define MC13783_LED_MD 0
#define MC13783_LED_AD 1
#define MC13783_LED_KP 2
#define MC13783_LED_R1 3
#define MC13783_LED_G1 4
#define MC13783_LED_B1 5
#define MC13783_LED_R2 6
#define MC13783_LED_G2 7
#define MC13783_LED_B2 8
#define MC13783_LED_R3 9
#define MC13783_LED_G3 10
#define MC13783_LED_B3 11
#define MC13783_LED_MAX MC13783_LED_B3
int id;
const char *name;
const char *default_trigger;
/* Three or two bits current selection depending on the led */
char max_current;
};
struct mc13xxx_leds_platform_data {
int num_leds;
struct mc13xxx_led_platform_data *led;
#define MC13783_LED_TRIODE_MD (1 << 0)
#define MC13783_LED_TRIODE_AD (1 << 1)
#define MC13783_LED_TRIODE_KP (1 << 2)
#define MC13783_LED_BOOST_EN (1 << 3)
#define MC13783_LED_TC1HALF (1 << 4)
#define MC13783_LED_SLEWLIMTC (1 << 5)
#define MC13783_LED_SLEWLIMBL (1 << 6)
#define MC13783_LED_TRIODE_TC1 (1 << 7)
#define MC13783_LED_TRIODE_TC2 (1 << 8)
#define MC13783_LED_TRIODE_TC3 (1 << 9)
int flags;
#define MC13783_LED_AB_DISABLED 0
#define MC13783_LED_AB_MD1 1
#define MC13783_LED_AB_MD12 2
#define MC13783_LED_AB_MD123 3
#define MC13783_LED_AB_MD1234 4
#define MC13783_LED_AB_MD1234_AD1 5
#define MC13783_LED_AB_MD1234_AD12 6
#define MC13783_LED_AB_MD1_AD 7
char abmode;
#define MC13783_LED_ABREF_200MV 0
#define MC13783_LED_ABREF_400MV 1
#define MC13783_LED_ABREF_600MV 2
#define MC13783_LED_ABREF_800MV 3
char abref;
#define MC13783_LED_PERIOD_10MS 0
#define MC13783_LED_PERIOD_100MS 1
#define MC13783_LED_PERIOD_500MS 2
#define MC13783_LED_PERIOD_2S 3
char bl_period;
char tc1_period;
char tc2_period;
char tc3_period;
};
struct mc13xxx_buttons_platform_data {
#define MC13783_BUTTON_DBNC_0MS 0
#define MC13783_BUTTON_DBNC_30MS 1
#define MC13783_BUTTON_DBNC_150MS 2
#define MC13783_BUTTON_DBNC_750MS 3
#define MC13783_BUTTON_ENABLE (1 << 2)
#define MC13783_BUTTON_POL_INVERT (1 << 3)
#define MC13783_BUTTON_RESET_EN (1 << 4)
int b1on_flags;
unsigned short b1on_key;
int b2on_flags;
unsigned short b2on_key;
int b3on_flags;
unsigned short b3on_key;
};
struct mc13xxx_ts_platform_data {
/* Delay between Touchscreen polarization and ADC Conversion.
* Given in clock ticks of a 32 kHz clock which gives a granularity of
* about 30.5ms */
u8 ato;
#define MC13783_TS_ATO_FIRST false
#define MC13783_TS_ATO_EACH true
/* Use the ATO delay only for the first conversion or for each one */
bool atox;
};
struct mc13xxx_platform_data {
#define MC13XXX_USE_TOUCHSCREEN (1 << 0)
#define MC13XXX_USE_CODEC (1 << 1)
#define MC13XXX_USE_ADC (1 << 2)
#define MC13XXX_USE_RTC (1 << 3)
unsigned int flags;
struct mc13xxx_regulator_platform_data regulators;
struct mc13xxx_leds_platform_data *leds;
struct mc13xxx_buttons_platform_data *buttons;
struct mc13xxx_ts_platform_data touch;
};
#define MC13XXX_ADC_MODE_TS 1
#define MC13XXX_ADC_MODE_SINGLE_CHAN 2
#define MC13XXX_ADC_MODE_MULT_CHAN 3
#define MC13XXX_ADC0 43
#define MC13XXX_ADC0_LICELLCON (1 << 0)
#define MC13XXX_ADC0_CHRGICON (1 << 1)
#define MC13XXX_ADC0_BATICON (1 << 2)
#define MC13XXX_ADC0_ADREFEN (1 << 10)
#define MC13XXX_ADC0_TSMOD0 (1 << 12)
#define MC13XXX_ADC0_TSMOD1 (1 << 13)
#define MC13XXX_ADC0_TSMOD2 (1 << 14)
#define MC13XXX_ADC0_ADINC1 (1 << 16)
#define MC13XXX_ADC0_ADINC2 (1 << 17)
#define MC13XXX_ADC0_TSMOD_MASK (MC13XXX_ADC0_TSMOD0 | \
MC13XXX_ADC0_TSMOD1 | \
MC13XXX_ADC0_TSMOD2)
#define MC13XXX_ADC0_CONFIG_MASK (MC13XXX_ADC0_TSMOD_MASK | \
MC13XXX_ADC0_LICELLCON | \
MC13XXX_ADC0_CHRGICON | \
MC13XXX_ADC0_BATICON)
#endif /* ifndef __LINUX_MFD_MC13XXX_H */
kernel/include/linux/mfd/mcp.h
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/*
* linux/drivers/mfd/mcp.h
*
* Copyright (C) 2001 Russell King, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
*/
#ifndef MCP_H
#define MCP_H
struct mcp_ops;
struct mcp {
struct module *owner;
struct mcp_ops *ops;
spinlock_t lock;
int use_count;
unsigned int sclk_rate;
unsigned int rw_timeout;
struct device attached_device;
};
struct mcp_ops {
void (*set_telecom_divisor)(struct mcp *, unsigned int);
void (*set_audio_divisor)(struct mcp *, unsigned int);
void (*reg_write)(struct mcp *, unsigned int, unsigned int);
unsigned int (*reg_read)(struct mcp *, unsigned int);
void (*enable)(struct mcp *);
void (*disable)(struct mcp *);
};
void mcp_set_telecom_divisor(struct mcp *, unsigned int);
void mcp_set_audio_divisor(struct mcp *, unsigned int);
void mcp_reg_write(struct mcp *, unsigned int, unsigned int);
unsigned int mcp_reg_read(struct mcp *, unsigned int);
void mcp_enable(struct mcp *);
void mcp_disable(struct mcp *);
#define mcp_get_sclk_rate(mcp) ((mcp)->sclk_rate)
struct mcp *mcp_host_alloc(struct device *, size_t);
int mcp_host_add(struct mcp *, void *);
void mcp_host_del(struct mcp *);
void mcp_host_free(struct mcp *);
struct mcp_driver {
struct device_driver drv;
int (*probe)(struct mcp *);
void (*remove)(struct mcp *);
};
int mcp_driver_register(struct mcp_driver *);
void mcp_driver_unregister(struct mcp_driver *);
#define mcp_get_drvdata(mcp) dev_get_drvdata(&(mcp)->attached_device)
#define mcp_set_drvdata(mcp,d) dev_set_drvdata(&(mcp)->attached_device, d)
static inline void *mcp_priv(struct mcp *mcp)
{
return mcp + 1;
}
#endif
kernel/include/linux/mfd/msm-adie-codec.h
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#ifndef __LINUX_MFD_MSM_ADIE_CODEC_H
#define __LINUX_MFD_MSM_ADIE_CODEC_H
#include <linux/types.h>
/* Value Represents a entry */
#define ADIE_CODEC_ACTION_ENTRY 0x1
/* Value representing a delay wait */
#define ADIE_CODEC_ACTION_DELAY_WAIT 0x2
/* Value representing a stage reached */
#define ADIE_CODEC_ACTION_STAGE_REACHED 0x3
/* This value is the state after the client sets the path */
#define ADIE_CODEC_PATH_OFF 0x0050
/* State to which client asks the drv to proceed to where it can
* set up the clocks and 0-fill PCM buffers
*/
#define ADIE_CODEC_DIGITAL_READY 0x0100
/* State to which client asks the drv to proceed to where it can
* start sending data after internal steady state delay
*/
#define ADIE_CODEC_DIGITAL_ANALOG_READY 0x1000
/* Client Asks adie to switch off the Analog portion of the
* the internal codec. After the use of this path
*/
#define ADIE_CODEC_ANALOG_OFF 0x0750
/* Client Asks adie to switch off the digital portion of the
* the internal codec. After switching off the analog portion.
*
* 0-fill PCM may or maynot be sent at this point
*
*/
#define ADIE_CODEC_DIGITAL_OFF 0x0600
/* State to which client asks the drv to write the default values
* to the registers */
#define ADIE_CODEC_FLASH_IMAGE 0x0001
/* Path type */
#define ADIE_CODEC_RX 0
#define ADIE_CODEC_TX 1
#define ADIE_CODEC_LB 3
#define ADIE_CODEC_MAX 4
#define ADIE_CODEC_PACK_ENTRY(reg, mask, val) ((val)|(mask << 8)|(reg << 16))
#define ADIE_CODEC_UNPACK_ENTRY(packed, reg, mask, val) \
do { \
((reg) = ((packed >> 16) & (0xff))); \
((mask) = ((packed >> 8) & (0xff))); \
((val) = ((packed) & (0xff))); \
} while (0);
struct adie_codec_action_unit {
u32 type;
u32 action;
};
struct adie_codec_hwsetting_entry{
struct adie_codec_action_unit *actions;
u32 action_sz;
u32 freq_plan;
u32 osr;
/* u32 VolMask;
* u32 SidetoneMask;
*/
};
struct adie_codec_dev_profile {
u32 path_type; /* RX or TX */
u32 setting_sz;
struct adie_codec_hwsetting_entry *settings;
};
struct adie_codec_register {
u8 reg;
u8 mask;
u8 val;
};
struct adie_codec_register_image {
struct adie_codec_register *regs;
u32 img_sz;
};
struct adie_codec_path;
struct adie_codec_anc_data {
u32 size;
u32 writes[];
};
struct adie_codec_operations {
int codec_id;
int (*codec_open) (struct adie_codec_dev_profile *profile,
struct adie_codec_path **path_pptr);
int (*codec_close) (struct adie_codec_path *path_ptr);
int (*codec_setpath) (struct adie_codec_path *path_ptr,
u32 freq_plan, u32 osr);
int (*codec_proceed_stage) (struct adie_codec_path *path_ptr,
u32 state);
u32 (*codec_freq_supported) (struct adie_codec_dev_profile *profile,
u32 requested_freq);
int (*codec_enable_sidetone) (struct adie_codec_path *rx_path_ptr,
u32 enable);
int (*codec_enable_anc) (struct adie_codec_path *rx_path_ptr,
u32 enable, struct adie_codec_anc_data *calibration_writes);
int (*codec_set_device_digital_volume) (
struct adie_codec_path *path_ptr,
u32 num_channels,
u32 vol_percentage);
int (*codec_set_device_analog_volume) (struct adie_codec_path *path_ptr,
u32 num_channels,
u32 volume);
int (*codec_set_master_mode) (struct adie_codec_path *path_ptr,
u8 master);
};
int adie_codec_register_codec_operations(
const struct adie_codec_operations *codec_ops);
int adie_codec_open(struct adie_codec_dev_profile *profile,
struct adie_codec_path **path_pptr);
int adie_codec_setpath(struct adie_codec_path *path_ptr,
u32 freq_plan, u32 osr);
int adie_codec_proceed_stage(struct adie_codec_path *path_ptr, u32 state);
int adie_codec_close(struct adie_codec_path *path_ptr);
u32 adie_codec_freq_supported(struct adie_codec_dev_profile *profile,
u32 requested_freq);
int adie_codec_enable_sidetone(struct adie_codec_path *rx_path_ptr, u32 enable);
int adie_codec_enable_anc(struct adie_codec_path *rx_path_ptr, u32 enable,
struct adie_codec_anc_data *calibration_writes);
int adie_codec_set_device_digital_volume(struct adie_codec_path *path_ptr,
u32 num_channels, u32 vol_percentage /* in percentage */);
int adie_codec_set_device_analog_volume(struct adie_codec_path *path_ptr,
u32 num_channels, u32 volume /* in percentage */);
int adie_codec_set_master_mode(struct adie_codec_path *path_ptr, u8 master);
#endif
kernel/include/linux/mfd/pcf50633/adc.h
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/*
* adc.h -- Driver for NXP PCF50633 ADC
*
* (C) 2006-2008 by Openmoko, Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __LINUX_MFD_PCF50633_ADC_H
#define __LINUX_MFD_PCF50633_ADC_H
#include <linux/mfd/pcf50633/core.h>
#include <linux/platform_device.h>
/* ADC Registers */
#define PCF50633_REG_ADCC3 0x52
#define PCF50633_REG_ADCC2 0x53
#define PCF50633_REG_ADCC1 0x54
#define PCF50633_REG_ADCS1 0x55
#define PCF50633_REG_ADCS2 0x56
#define PCF50633_REG_ADCS3 0x57
#define PCF50633_ADCC1_ADCSTART 0x01
#define PCF50633_ADCC1_RES_8BIT 0x02
#define PCF50633_ADCC1_RES_10BIT 0x00
#define PCF50633_ADCC1_AVERAGE_NO 0x00
#define PCF50633_ADCC1_AVERAGE_4 0x04
#define PCF50633_ADCC1_AVERAGE_8 0x08
#define PCF50633_ADCC1_AVERAGE_16 0x0c
#define PCF50633_ADCC1_MUX_BATSNS_RES 0x00
#define PCF50633_ADCC1_MUX_BATSNS_SUBTR 0x10
#define PCF50633_ADCC1_MUX_ADCIN2_RES 0x20
#define PCF50633_ADCC1_MUX_ADCIN2_SUBTR 0x30
#define PCF50633_ADCC1_MUX_BATTEMP 0x60
#define PCF50633_ADCC1_MUX_ADCIN1 0x70
#define PCF50633_ADCC1_AVERAGE_MASK 0x0c
#define PCF50633_ADCC1_ADCMUX_MASK 0xf0
#define PCF50633_ADCC2_RATIO_NONE 0x00
#define PCF50633_ADCC2_RATIO_BATTEMP 0x01
#define PCF50633_ADCC2_RATIO_ADCIN1 0x02
#define PCF50633_ADCC2_RATIO_BOTH 0x03
#define PCF50633_ADCC2_RATIOSETTL_100US 0x04
#define PCF50633_ADCC3_ACCSW_EN 0x01
#define PCF50633_ADCC3_NTCSW_EN 0x04
#define PCF50633_ADCC3_RES_DIV_TWO 0x10
#define PCF50633_ADCC3_RES_DIV_THREE 0x00
#define PCF50633_ADCS3_REF_NTCSW 0x00
#define PCF50633_ADCS3_REF_ACCSW 0x10
#define PCF50633_ADCS3_REF_2V0 0x20
#define PCF50633_ADCS3_REF_VISA 0x30
#define PCF50633_ADCS3_REF_2V0_2 0x70
#define PCF50633_ADCS3_ADCRDY 0x80
#define PCF50633_ADCS3_ADCDAT1L_MASK 0x03
#define PCF50633_ADCS3_ADCDAT2L_MASK 0x0c
#define PCF50633_ADCS3_ADCDAT2L_SHIFT 2
#define PCF50633_ASCS3_REF_MASK 0x70
extern int
pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg,
void (*callback)(struct pcf50633 *, void *, int),
void *callback_param);
extern int
pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg);
#endif /* __LINUX_PCF50633_ADC_H */
kernel/include/linux/mfd/pcf50633/backlight.h
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/*
* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
* PCF50633 backlight device driver
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
*/
#ifndef __LINUX_MFD_PCF50633_BACKLIGHT
#define __LINUX_MFD_PCF50633_BACKLIGHT
/*
* @default_brightness: Backlight brightness is initialized to this value
*
* Brightness to be used after the driver has been probed.
* Valid range 0-63.
*
* @default_brightness_limit: The actual brightness is limited by this value
*
* Brightness limit to be used after the driver has been probed. This is useful
* when it is not known how much power is available for the backlight during
* probe.
* Valid range 0-63. Can be changed later with pcf50633_bl_set_brightness_limit.
*
* @ramp_time: Display ramp time when changing brightness
*
* When changing the backlights brightness the change is not instant, instead
* it fades smooth from one state to another. This value specifies how long
* the fade should take. The lower the value the higher the fade time.
* Valid range 0-255
*/
struct pcf50633_bl_platform_data {
unsigned int default_brightness;
unsigned int default_brightness_limit;
uint8_t ramp_time;
};
struct pcf50633;
int pcf50633_bl_set_brightness_limit(struct pcf50633 *pcf, unsigned int limit);
#endif
kernel/include/linux/mfd/pcf50633/core.h
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/*
* core.h -- Core driver for NXP PCF50633
*
* (C) 2006-2008 by Openmoko, Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __LINUX_MFD_PCF50633_CORE_H
#define __LINUX_MFD_PCF50633_CORE_H
#include <linux/i2c.h>
#include <linux/workqueue.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
#include <linux/power_supply.h>
#include <linux/mfd/pcf50633/backlight.h>
struct pcf50633;
struct regmap;
#define PCF50633_NUM_REGULATORS 11
struct pcf50633_platform_data {
struct regulator_init_data reg_init_data[PCF50633_NUM_REGULATORS];
char **batteries;
int num_batteries;
/*
* Should be set accordingly to the reference resistor used, see
* I_{ch(ref)} charger reference current in the pcf50633 User
* Manual.
*/
int charger_reference_current_ma;
/* Callbacks */
void (*probe_done)(struct pcf50633 *);
void (*mbc_event_callback)(struct pcf50633 *, int);
void (*regulator_registered)(struct pcf50633 *, int);
void (*force_shutdown)(struct pcf50633 *);
u8 resumers[5];
struct pcf50633_bl_platform_data *backlight_data;
};
struct pcf50633_irq {
void (*handler) (int, void *);
void *data;
};
int pcf50633_register_irq(struct pcf50633 *pcf, int irq,
void (*handler) (int, void *), void *data);
int pcf50633_free_irq(struct pcf50633 *pcf, int irq);
int pcf50633_irq_mask(struct pcf50633 *pcf, int irq);
int pcf50633_irq_unmask(struct pcf50633 *pcf, int irq);
int pcf50633_irq_mask_get(struct pcf50633 *pcf, int irq);
int pcf50633_read_block(struct pcf50633 *, u8 reg,
int nr_regs, u8 *data);
int pcf50633_write_block(struct pcf50633 *pcf, u8 reg,
int nr_regs, u8 *data);
u8 pcf50633_reg_read(struct pcf50633 *, u8 reg);
int pcf50633_reg_write(struct pcf50633 *pcf, u8 reg, u8 val);
int pcf50633_reg_set_bit_mask(struct pcf50633 *pcf, u8 reg, u8 mask, u8 val);
int pcf50633_reg_clear_bits(struct pcf50633 *pcf, u8 reg, u8 bits);
/* Interrupt registers */
#define PCF50633_REG_INT1 0x02
#define PCF50633_REG_INT2 0x03
#define PCF50633_REG_INT3 0x04
#define PCF50633_REG_INT4 0x05
#define PCF50633_REG_INT5 0x06
#define PCF50633_REG_INT1M 0x07
#define PCF50633_REG_INT2M 0x08
#define PCF50633_REG_INT3M 0x09
#define PCF50633_REG_INT4M 0x0a
#define PCF50633_REG_INT5M 0x0b
enum {
/* Chip IRQs */
PCF50633_IRQ_ADPINS,
PCF50633_IRQ_ADPREM,
PCF50633_IRQ_USBINS,
PCF50633_IRQ_USBREM,
PCF50633_IRQ_RESERVED1,
PCF50633_IRQ_RESERVED2,
PCF50633_IRQ_ALARM,
PCF50633_IRQ_SECOND,
PCF50633_IRQ_ONKEYR,
PCF50633_IRQ_ONKEYF,
PCF50633_IRQ_EXTON1R,
PCF50633_IRQ_EXTON1F,
PCF50633_IRQ_EXTON2R,
PCF50633_IRQ_EXTON2F,
PCF50633_IRQ_EXTON3R,
PCF50633_IRQ_EXTON3F,
PCF50633_IRQ_BATFULL,
PCF50633_IRQ_CHGHALT,
PCF50633_IRQ_THLIMON,
PCF50633_IRQ_THLIMOFF,
PCF50633_IRQ_USBLIMON,
PCF50633_IRQ_USBLIMOFF,
PCF50633_IRQ_ADCRDY,
PCF50633_IRQ_ONKEY1S,
PCF50633_IRQ_LOWSYS,
PCF50633_IRQ_LOWBAT,
PCF50633_IRQ_HIGHTMP,
PCF50633_IRQ_AUTOPWRFAIL,
PCF50633_IRQ_DWN1PWRFAIL,
PCF50633_IRQ_DWN2PWRFAIL,
PCF50633_IRQ_LEDPWRFAIL,
PCF50633_IRQ_LEDOVP,
PCF50633_IRQ_LDO1PWRFAIL,
PCF50633_IRQ_LDO2PWRFAIL,
PCF50633_IRQ_LDO3PWRFAIL,
PCF50633_IRQ_LDO4PWRFAIL,
PCF50633_IRQ_LDO5PWRFAIL,
PCF50633_IRQ_LDO6PWRFAIL,
PCF50633_IRQ_HCLDOPWRFAIL,
PCF50633_IRQ_HCLDOOVL,
/* Always last */
PCF50633_NUM_IRQ,
};
struct pcf50633 {
struct device *dev;
struct regmap *regmap;
struct pcf50633_platform_data *pdata;
int irq;
struct pcf50633_irq irq_handler[PCF50633_NUM_IRQ];
struct work_struct irq_work;
struct workqueue_struct *work_queue;
struct mutex lock;
u8 mask_regs[5];
u8 suspend_irq_masks[5];
u8 resume_reason[5];
int is_suspended;
int onkey1s_held;
struct platform_device *rtc_pdev;
struct platform_device *mbc_pdev;
struct platform_device *adc_pdev;
struct platform_device *input_pdev;
struct platform_device *bl_pdev;
struct platform_device *regulator_pdev[PCF50633_NUM_REGULATORS];
};
enum pcf50633_reg_int1 {
PCF50633_INT1_ADPINS = 0x01, /* Adapter inserted */
PCF50633_INT1_ADPREM = 0x02, /* Adapter removed */
PCF50633_INT1_USBINS = 0x04, /* USB inserted */
PCF50633_INT1_USBREM = 0x08, /* USB removed */
/* reserved */
PCF50633_INT1_ALARM = 0x40, /* RTC alarm time is reached */
PCF50633_INT1_SECOND = 0x80, /* RTC periodic second interrupt */
};
enum pcf50633_reg_int2 {
PCF50633_INT2_ONKEYR = 0x01, /* ONKEY rising edge */
PCF50633_INT2_ONKEYF = 0x02, /* ONKEY falling edge */
PCF50633_INT2_EXTON1R = 0x04, /* EXTON1 rising edge */
PCF50633_INT2_EXTON1F = 0x08, /* EXTON1 falling edge */
PCF50633_INT2_EXTON2R = 0x10, /* EXTON2 rising edge */
PCF50633_INT2_EXTON2F = 0x20, /* EXTON2 falling edge */
PCF50633_INT2_EXTON3R = 0x40, /* EXTON3 rising edge */
PCF50633_INT2_EXTON3F = 0x80, /* EXTON3 falling edge */
};
enum pcf50633_reg_int3 {
PCF50633_INT3_BATFULL = 0x01, /* Battery full */
PCF50633_INT3_CHGHALT = 0x02, /* Charger halt */
PCF50633_INT3_THLIMON = 0x04,
PCF50633_INT3_THLIMOFF = 0x08,
PCF50633_INT3_USBLIMON = 0x10,
PCF50633_INT3_USBLIMOFF = 0x20,
PCF50633_INT3_ADCRDY = 0x40, /* ADC result ready */
PCF50633_INT3_ONKEY1S = 0x80, /* ONKEY pressed 1 second */
};
enum pcf50633_reg_int4 {
PCF50633_INT4_LOWSYS = 0x01,
PCF50633_INT4_LOWBAT = 0x02,
PCF50633_INT4_HIGHTMP = 0x04,
PCF50633_INT4_AUTOPWRFAIL = 0x08,
PCF50633_INT4_DWN1PWRFAIL = 0x10,
PCF50633_INT4_DWN2PWRFAIL = 0x20,
PCF50633_INT4_LEDPWRFAIL = 0x40,
PCF50633_INT4_LEDOVP = 0x80,
};
enum pcf50633_reg_int5 {
PCF50633_INT5_LDO1PWRFAIL = 0x01,
PCF50633_INT5_LDO2PWRFAIL = 0x02,
PCF50633_INT5_LDO3PWRFAIL = 0x04,
PCF50633_INT5_LDO4PWRFAIL = 0x08,
PCF50633_INT5_LDO5PWRFAIL = 0x10,
PCF50633_INT5_LDO6PWRFAIL = 0x20,
PCF50633_INT5_HCLDOPWRFAIL = 0x40,
PCF50633_INT5_HCLDOOVL = 0x80,
};
/* misc. registers */
#define PCF50633_REG_OOCSHDWN 0x0c
/* LED registers */
#define PCF50633_REG_LEDOUT 0x28
#define PCF50633_REG_LEDENA 0x29
#define PCF50633_REG_LEDCTL 0x2a
#define PCF50633_REG_LEDDIM 0x2b
static inline struct pcf50633 *dev_to_pcf50633(struct device *dev)
{
return dev_get_drvdata(dev);
}
int pcf50633_irq_init(struct pcf50633 *pcf, int irq);
void pcf50633_irq_free(struct pcf50633 *pcf);
#ifdef CONFIG_PM
int pcf50633_irq_suspend(struct pcf50633 *pcf);
int pcf50633_irq_resume(struct pcf50633 *pcf);
#endif
#endif
kernel/include/linux/mfd/pcf50633/gpio.h
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/*
* gpio.h -- GPIO driver for NXP PCF50633
*
* (C) 2006-2008 by Openmoko, Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __LINUX_MFD_PCF50633_GPIO_H
#define __LINUX_MFD_PCF50633_GPIO_H
#include <linux/mfd/pcf50633/core.h>
#define PCF50633_GPIO1 1
#define PCF50633_GPIO2 2
#define PCF50633_GPIO3 3
#define PCF50633_GPO 4
#define PCF50633_REG_GPIO1CFG 0x14
#define PCF50633_REG_GPIO2CFG 0x15
#define PCF50633_REG_GPIO3CFG 0x16
#define PCF50633_REG_GPOCFG 0x17
#define PCF50633_GPOCFG_GPOSEL_MASK 0x07
enum pcf50633_reg_gpocfg {
PCF50633_GPOCFG_GPOSEL_0 = 0x00,
PCF50633_GPOCFG_GPOSEL_LED_NFET = 0x01,
PCF50633_GPOCFG_GPOSEL_SYSxOK = 0x02,
PCF50633_GPOCFG_GPOSEL_CLK32K = 0x03,
PCF50633_GPOCFG_GPOSEL_ADAPUSB = 0x04,
PCF50633_GPOCFG_GPOSEL_USBxOK = 0x05,
PCF50633_GPOCFG_GPOSEL_ACTPH4 = 0x06,
PCF50633_GPOCFG_GPOSEL_1 = 0x07,
PCF50633_GPOCFG_GPOSEL_INVERSE = 0x08,
};
int pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, u8 val);
u8 pcf50633_gpio_get(struct pcf50633 *pcf, int gpio);
int pcf50633_gpio_invert_set(struct pcf50633 *, int gpio, int invert);
int pcf50633_gpio_invert_get(struct pcf50633 *pcf, int gpio);
int pcf50633_gpio_power_supply_set(struct pcf50633 *,
int gpio, int regulator, int on);
#endif /* __LINUX_MFD_PCF50633_GPIO_H */
kernel/include/linux/mfd/pcf50633/mbc.h
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/*
* mbc.h -- Driver for NXP PCF50633 Main Battery Charger
*
* (C) 2006-2008 by Openmoko, Inc.
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __LINUX_MFD_PCF50633_MBC_H
#define __LINUX_MFD_PCF50633_MBC_H
#include <linux/mfd/pcf50633/core.h>
#include <linux/platform_device.h>
#define PCF50633_REG_MBCC1 0x43
#define PCF50633_REG_MBCC2 0x44
#define PCF50633_REG_MBCC3 0x45
#define PCF50633_REG_MBCC4 0x46
#define PCF50633_REG_MBCC5 0x47
#define PCF50633_REG_MBCC6 0x48
#define PCF50633_REG_MBCC7 0x49
#define PCF50633_REG_MBCC8 0x4a
#define PCF50633_REG_MBCS1 0x4b
#define PCF50633_REG_MBCS2 0x4c
#define PCF50633_REG_MBCS3 0x4d
enum pcf50633_reg_mbcc1 {
PCF50633_MBCC1_CHGENA = 0x01, /* Charger enable */
PCF50633_MBCC1_AUTOSTOP = 0x02,
PCF50633_MBCC1_AUTORES = 0x04, /* automatic resume */
PCF50633_MBCC1_RESUME = 0x08, /* explicit resume cmd */
PCF50633_MBCC1_RESTART = 0x10, /* restart charging */
PCF50633_MBCC1_PREWDTIME_60M = 0x20, /* max. precharging time */
PCF50633_MBCC1_WDTIME_1H = 0x00,
PCF50633_MBCC1_WDTIME_2H = 0x40,
PCF50633_MBCC1_WDTIME_4H = 0x80,
PCF50633_MBCC1_WDTIME_6H = 0xc0,
};
#define PCF50633_MBCC1_WDTIME_MASK 0xc0
enum pcf50633_reg_mbcc2 {
PCF50633_MBCC2_VBATCOND_2V7 = 0x00,
PCF50633_MBCC2_VBATCOND_2V85 = 0x01,
PCF50633_MBCC2_VBATCOND_3V0 = 0x02,
PCF50633_MBCC2_VBATCOND_3V15 = 0x03,
PCF50633_MBCC2_VMAX_4V = 0x00,
PCF50633_MBCC2_VMAX_4V20 = 0x28,
PCF50633_MBCC2_VRESDEBTIME_64S = 0x80, /* debounce time (32/64sec) */
};
enum pcf50633_reg_mbcc7 {
PCF50633_MBCC7_USB_100mA = 0x00,
PCF50633_MBCC7_USB_500mA = 0x01,
PCF50633_MBCC7_USB_1000mA = 0x02,
PCF50633_MBCC7_USB_SUSPEND = 0x03,
PCF50633_MBCC7_BATTEMP_EN = 0x04,
PCF50633_MBCC7_BATSYSIMAX_1A6 = 0x00,
PCF50633_MBCC7_BATSYSIMAX_1A8 = 0x40,
PCF50633_MBCC7_BATSYSIMAX_2A0 = 0x80,
PCF50633_MBCC7_BATSYSIMAX_2A2 = 0xc0,
};
#define PCF50633_MBCC7_USB_MASK 0x03
enum pcf50633_reg_mbcc8 {
PCF50633_MBCC8_USBENASUS = 0x10,
};
enum pcf50633_reg_mbcs1 {
PCF50633_MBCS1_USBPRES = 0x01,
PCF50633_MBCS1_USBOK = 0x02,
PCF50633_MBCS1_ADAPTPRES = 0x04,
PCF50633_MBCS1_ADAPTOK = 0x08,
PCF50633_MBCS1_TBAT_OK = 0x00,
PCF50633_MBCS1_TBAT_ABOVE = 0x10,
PCF50633_MBCS1_TBAT_BELOW = 0x20,
PCF50633_MBCS1_TBAT_UNDEF = 0x30,
PCF50633_MBCS1_PREWDTEXP = 0x40,
PCF50633_MBCS1_WDTEXP = 0x80,
};
enum pcf50633_reg_mbcs2_mbcmod {
PCF50633_MBCS2_MBC_PLAY = 0x00,
PCF50633_MBCS2_MBC_USB_PRE = 0x01,
PCF50633_MBCS2_MBC_USB_PRE_WAIT = 0x02,
PCF50633_MBCS2_MBC_USB_FAST = 0x03,
PCF50633_MBCS2_MBC_USB_FAST_WAIT = 0x04,
PCF50633_MBCS2_MBC_USB_SUSPEND = 0x05,
PCF50633_MBCS2_MBC_ADP_PRE = 0x06,
PCF50633_MBCS2_MBC_ADP_PRE_WAIT = 0x07,
PCF50633_MBCS2_MBC_ADP_FAST = 0x08,
PCF50633_MBCS2_MBC_ADP_FAST_WAIT = 0x09,
PCF50633_MBCS2_MBC_BAT_FULL = 0x0a,
PCF50633_MBCS2_MBC_HALT = 0x0b,
};
#define PCF50633_MBCS2_MBC_MASK 0x0f
enum pcf50633_reg_mbcs2_chgstat {
PCF50633_MBCS2_CHGS_NONE = 0x00,
PCF50633_MBCS2_CHGS_ADAPTER = 0x10,
PCF50633_MBCS2_CHGS_USB = 0x20,
PCF50633_MBCS2_CHGS_BOTH = 0x30,
};
#define PCF50633_MBCS2_RESSTAT_AUTO 0x40
enum pcf50633_reg_mbcs3 {
PCF50633_MBCS3_USBLIM_PLAY = 0x01,
PCF50633_MBCS3_USBLIM_CGH = 0x02,
PCF50633_MBCS3_TLIM_PLAY = 0x04,
PCF50633_MBCS3_TLIM_CHG = 0x08,
PCF50633_MBCS3_ILIM = 0x10, /* 1: Ibat > Icutoff */
PCF50633_MBCS3_VLIM = 0x20, /* 1: Vbat == Vmax */
PCF50633_MBCS3_VBATSTAT = 0x40, /* 1: Vbat > Vbatcond */
PCF50633_MBCS3_VRES = 0x80, /* 1: Vbat > Vth(RES) */
};
#define PCF50633_MBCC2_VBATCOND_MASK 0x03
#define PCF50633_MBCC2_VMAX_MASK 0x3c
/* Charger status */
#define PCF50633_MBC_USB_ONLINE 0x01
#define PCF50633_MBC_USB_ACTIVE 0x02
#define PCF50633_MBC_ADAPTER_ONLINE 0x04
#define PCF50633_MBC_ADAPTER_ACTIVE 0x08
int pcf50633_mbc_usb_curlim_set(struct pcf50633 *pcf, int ma);
int pcf50633_mbc_get_status(struct pcf50633 *);
int pcf50633_mbc_get_usb_online_status(struct pcf50633 *);
#endif
kernel/include/linux/mfd/pcf50633/pmic.h
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#ifndef __LINUX_MFD_PCF50633_PMIC_H
#define __LINUX_MFD_PCF50633_PMIC_H
#include <linux/mfd/pcf50633/core.h>
#include <linux/platform_device.h>
#define PCF50633_REG_AUTOOUT 0x1a
#define PCF50633_REG_AUTOENA 0x1b
#define PCF50633_REG_AUTOCTL 0x1c
#define PCF50633_REG_AUTOMXC 0x1d
#define PCF50633_REG_DOWN1OUT 0x1e
#define PCF50633_REG_DOWN1ENA 0x1f
#define PCF50633_REG_DOWN1CTL 0x20
#define PCF50633_REG_DOWN1MXC 0x21
#define PCF50633_REG_DOWN2OUT 0x22
#define PCF50633_REG_DOWN2ENA 0x23
#define PCF50633_REG_DOWN2CTL 0x24
#define PCF50633_REG_DOWN2MXC 0x25
#define PCF50633_REG_MEMLDOOUT 0x26
#define PCF50633_REG_MEMLDOENA 0x27
#define PCF50633_REG_LDO1OUT 0x2d
#define PCF50633_REG_LDO1ENA 0x2e
#define PCF50633_REG_LDO2OUT 0x2f
#define PCF50633_REG_LDO2ENA 0x30
#define PCF50633_REG_LDO3OUT 0x31
#define PCF50633_REG_LDO3ENA 0x32
#define PCF50633_REG_LDO4OUT 0x33
#define PCF50633_REG_LDO4ENA 0x34
#define PCF50633_REG_LDO5OUT 0x35
#define PCF50633_REG_LDO5ENA 0x36
#define PCF50633_REG_LDO6OUT 0x37
#define PCF50633_REG_LDO6ENA 0x38
#define PCF50633_REG_HCLDOOUT 0x39
#define PCF50633_REG_HCLDOENA 0x3a
#define PCF50633_REG_HCLDOOVL 0x40
enum pcf50633_regulator_enable {
PCF50633_REGULATOR_ON = 0x01,
PCF50633_REGULATOR_ON_GPIO1 = 0x02,
PCF50633_REGULATOR_ON_GPIO2 = 0x04,
PCF50633_REGULATOR_ON_GPIO3 = 0x08,
};
#define PCF50633_REGULATOR_ON_MASK 0x0f
enum pcf50633_regulator_phase {
PCF50633_REGULATOR_ACTPH1 = 0x00,
PCF50633_REGULATOR_ACTPH2 = 0x10,
PCF50633_REGULATOR_ACTPH3 = 0x20,
PCF50633_REGULATOR_ACTPH4 = 0x30,
};
#define PCF50633_REGULATOR_ACTPH_MASK 0x30
enum pcf50633_regulator_id {
PCF50633_REGULATOR_AUTO,
PCF50633_REGULATOR_DOWN1,
PCF50633_REGULATOR_DOWN2,
PCF50633_REGULATOR_LDO1,
PCF50633_REGULATOR_LDO2,
PCF50633_REGULATOR_LDO3,
PCF50633_REGULATOR_LDO4,
PCF50633_REGULATOR_LDO5,
PCF50633_REGULATOR_LDO6,
PCF50633_REGULATOR_HCLDO,
PCF50633_REGULATOR_MEMLDO,
};
#endif
kernel/include/linux/mfd/pm8xxx/batt-alarm.h
+201
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/* Copyright (c) 2011, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Qualcomm PMIC PM8xxx Battery Alarm driver
*
*/
#ifndef __MFD_PM8XXX_BATT_ALARM_H__
#define __MFD_PM8XXX_BATT_ALARM_H__
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/notifier.h>
#define PM8XXX_BATT_ALARM_DEV_NAME "pm8xxx-batt-alarm"
/**
* enum pm8xxx_batt_alarm_core_data - PMIC core specific core passed into the
* batter alarm driver as platform data
* @irq_name:
* @reg_addr_batt_alarm_threshold: PMIC threshold register address
* @reg_addr_batt_alarm_ctrl1: PMIC control 1 register address
* @reg_addr_batt_alarm_ctrl2: PMIC control 2 register address
* @reg_addr_batt_alarm_pwm_ctrl: PMIC PWM control register address
*/
struct pm8xxx_batt_alarm_core_data {
char *irq_name;
u16 reg_addr_threshold;
u16 reg_addr_ctrl1;
u16 reg_addr_ctrl2;
u16 reg_addr_pwm_ctrl;
};
/**
* enum pm8xxx_batt_alarm_comparator - battery alarm comparator ID values
*/
enum pm8xxx_batt_alarm_comparator {
PM8XXX_BATT_ALARM_LOWER_COMPARATOR,
PM8XXX_BATT_ALARM_UPPER_COMPARATOR,
};
/**
* enum pm8xxx_batt_alarm_hold_time - hold time required for out of range
* battery voltage needed to trigger a status change. Enum names denote
* hold time in milliseconds.
*/
enum pm8xxx_batt_alarm_hold_time {
PM8XXX_BATT_ALARM_HOLD_TIME_0p125_MS = 0,
PM8XXX_BATT_ALARM_HOLD_TIME_0p25_MS,
PM8XXX_BATT_ALARM_HOLD_TIME_0p5_MS,
PM8XXX_BATT_ALARM_HOLD_TIME_1_MS,
PM8XXX_BATT_ALARM_HOLD_TIME_2_MS,
PM8XXX_BATT_ALARM_HOLD_TIME_4_MS,
PM8XXX_BATT_ALARM_HOLD_TIME_8_MS,
PM8XXX_BATT_ALARM_HOLD_TIME_16_MS,
};
/*
* Bits that are set in the return value of pm8xxx_batt_alarm_status_read
* to indicate crossing of the upper or lower threshold.
*/
#define PM8XXX_BATT_ALARM_STATUS_BELOW_LOWER BIT(0)
#define PM8XXX_BATT_ALARM_STATUS_ABOVE_UPPER BIT(1)
#if defined(CONFIG_MFD_PM8XXX_BATT_ALARM) \
|| defined(CONFIG_MFD_PM8XXX_BATT_ALARM_MODULE)
/**
* pm8xxx_batt_alarm_enable - enable one of the battery voltage threshold
* comparators
* @comparator: selects which comparator to enable
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_batt_alarm_enable(enum pm8xxx_batt_alarm_comparator comparator);
/**
* pm8xxx_batt_alarm_disable - disable one of the battery voltage threshold
* comparators
* @comparator: selects which comparator to disable
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_batt_alarm_disable(enum pm8xxx_batt_alarm_comparator comparator);
/**
* pm8xxx_batt_alarm_threshold_set - set the lower and upper alarm thresholds
* @comparator: selects which comparator to set the threshold of
* @threshold_mV: battery voltage threshold in millivolts
* set points = 2500-5675 mV in 25 mV steps
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_batt_alarm_threshold_set(
enum pm8xxx_batt_alarm_comparator comparator, int threshold_mV);
/**
* pm8xxx_batt_alarm_status_read - get status of both threshold comparators
*
* RETURNS: < 0 = error
* 0 = battery voltage ok
* BIT(0) set = battery voltage below lower threshold
* BIT(1) set = battery voltage above upper threshold
*/
int pm8xxx_batt_alarm_status_read(void);
/**
* pm8xxx_batt_alarm_register_notifier - register a notifier to run when a
* battery voltage change interrupt fires
* @nb: notifier block containing callback function to register
*
* nb->notifier_call must point to a function of this form -
* int (*notifier_call)(struct notifier_block *nb, unsigned long status,
* void *unused);
* "status" will receive the battery alarm status; "unused" will be NULL.
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_batt_alarm_register_notifier(struct notifier_block *nb);
/**
* pm8xxx_batt_alarm_unregister_notifier - unregister a notifier that is run
* when a battery voltage change interrupt fires
* @nb: notifier block containing callback function to unregister
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_batt_alarm_unregister_notifier(struct notifier_block *nb);
/**
* pm8xxx_batt_alarm_hold_time_set - set hold time of interrupt output *
* @hold_time: amount of time that battery voltage must remain outside of the
* threshold range before the battery alarm interrupt triggers
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_batt_alarm_hold_time_set(enum pm8xxx_batt_alarm_hold_time hold_time);
/**
* pm8xxx_batt_alarm_pwm_rate_set - set battery alarm update rate *
* @use_pwm: 1 = use PWM update rate, 0 = comparators always active
* @clock_scaler: PWM clock scaler = 2 to 9
* @clock_divider: PWM clock divider = 2 to 8
*
* This function sets the rate at which the battery alarm module enables
* the threshold comparators. The rate is determined by the following equation:
*
* f_update = (1024 Hz) / (clock_divider * (2 ^ clock_scaler))
*
* Thus, the update rate can range from 0.25 Hz to 128 Hz.
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_batt_alarm_pwm_rate_set(int use_pwm, int clock_scaler,
int clock_divider);
#else
static inline int
pm8xxx_batt_alarm_enable(enum pm8xxx_batt_alarm_comparator comparator)
{ return -ENODEV; }
static inline int
pm8xxx_batt_alarm_disable(enum pm8xxx_batt_alarm_comparator comparator)
{ return -ENODEV; }
static inline int
pm8xxx_batt_alarm_threshold_set(enum pm8xxx_batt_alarm_comparator comparator,
int threshold_mV)
{ return -ENODEV; }
static inline int pm8xxx_batt_alarm_status_read(void)
{ return -ENODEV; }
static inline int pm8xxx_batt_alarm_register_notifier(struct notifier_block *nb)
{ return -ENODEV; }
static inline int
pm8xxx_batt_alarm_unregister_notifier(struct notifier_block *nb)
{ return -ENODEV; }
static inline int
pm8xxx_batt_alarm_hold_time_set(enum pm8xxx_batt_alarm_hold_time hold_time)
{ return -ENODEV; }
static inline int
pm8xxx_batt_alarm_pwm_rate_set(int use_pwm, int clock_scaler, int clock_divider)
{ return -ENODEV; }
#endif
#endif /* __MFD_PM8XXX_BATT_ALARM_H__ */
kernel/include/linux/mfd/pm8xxx/batterydata-lib.h
+166
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/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __PM8XXX_BMS_BATTERYDATA_H
#define __PM8XXX_BMS_BATTERYDATA_H
#include <linux/errno.h>
#define FCC_CC_COLS 5
#define FCC_TEMP_COLS 8
#define PC_CC_ROWS 31
#define PC_CC_COLS 13
#define PC_TEMP_ROWS 31
#define PC_TEMP_COLS 8
#define MAX_SINGLE_LUT_COLS 20
struct single_row_lut {
int x[MAX_SINGLE_LUT_COLS];
int y[MAX_SINGLE_LUT_COLS];
int cols;
};
/**
* struct sf_lut -
* @rows: number of percent charge entries should be <= PC_CC_ROWS
* @cols: number of charge cycle entries should be <= PC_CC_COLS
* @row_entries: the charge cycles/temperature at which sf data
* is available in the table.
* The charge cycles must be in increasing order from 0 to rows.
* @percent: the percent charge at which sf data is available in the table
* The percentcharge must be in decreasing order from 0 to cols.
* @sf: the scaling factor data
*/
struct sf_lut {
int rows;
int cols;
int row_entries[PC_CC_COLS];
int percent[PC_CC_ROWS];
int sf[PC_CC_ROWS][PC_CC_COLS];
};
/**
* struct pc_temp_ocv_lut -
* @rows: number of percent charge entries should be <= PC_TEMP_ROWS
* @cols: number of temperature entries should be <= PC_TEMP_COLS
* @temp: the temperatures at which ocv data is available in the table
* The temperatures must be in increasing order from 0 to rows.
* @percent: the percent charge at which ocv data is available in the table
* The percentcharge must be in decreasing order from 0 to cols.
* @ocv: the open circuit voltage
*/
struct pc_temp_ocv_lut {
int rows;
int cols;
int temp[PC_TEMP_COLS];
int percent[PC_TEMP_ROWS];
int ocv[PC_TEMP_ROWS][PC_TEMP_COLS];
};
enum battery_type {
BATT_UNKNOWN = 0,
BATT_PALLADIUM,
BATT_DESAY,
BATT_OEM,
BATT_QRD_4V35_2000MAH,
};
/**
* struct bms_battery_data -
* @fcc: full charge capacity (mAmpHour)
* @fcc_temp_lut: table to get fcc at a given temp
* @pc_temp_ocv_lut: table to get percent charge given batt temp and cycles
* @pc_sf_lut: table to get percent charge scaling factor given cycles
* and percent charge
* @rbatt_sf_lut: table to get battery resistance scaling factor given
* temperature and percent charge
* @default_rbatt_mohm: the default value of battery resistance to use when
* readings from bms are not available.
* @delta_rbatt_mohm: the resistance to be added towards lower soc to
* compensate for battery capacitance.
* @rbatt_capacitve_mohm: the resistance to be added to compensate for
* battery capacitance
* @flat_ocv_threshold_uv: the voltage where the battery's discharge curve
* starts flattening out.
*/
struct bms_battery_data {
unsigned int fcc;
struct single_row_lut *fcc_temp_lut;
struct single_row_lut *fcc_sf_lut;
struct pc_temp_ocv_lut *pc_temp_ocv_lut;
struct sf_lut *pc_sf_lut;
struct sf_lut *rbatt_sf_lut;
int default_rbatt_mohm;
int delta_rbatt_mohm;
int rbatt_capacitive_mohm;
int flat_ocv_threshold_uv;
};
#if defined(CONFIG_PM8921_BMS) || \
defined(CONFIG_PM8921_BMS_MODULE) || \
defined(CONFIG_QPNP_BMS)
extern struct bms_battery_data palladium_1500_data;
extern struct bms_battery_data desay_5200_data;
extern struct bms_battery_data oem_batt_data;
extern struct bms_battery_data QRD_4v35_2000mAh_data;
int interpolate_fcc(struct single_row_lut *fcc_temp_lut, int batt_temp);
int interpolate_scalingfactor(struct sf_lut *sf_lut, int row_entry, int pc);
int interpolate_scalingfactor_fcc(struct single_row_lut *fcc_sf_lut,
int cycles);
int interpolate_pc(struct pc_temp_ocv_lut *pc_temp_ocv,
int batt_temp_degc, int ocv);
int interpolate_ocv(struct pc_temp_ocv_lut *pc_temp_ocv,
int batt_temp_degc, int pc);
int linear_interpolate(int y0, int x0, int y1, int x1, int x);
int is_between(int left, int right, int value);
#else
static inline int interpolate_fcc(struct single_row_lut *fcc_temp_lut,
int batt_temp)
{
return -EINVAL;
}
static inline int interpolate_scalingfactor(struct sf_lut *sf_lut,
int row_entry, int pc)
{
return -EINVAL;
}
static inline int interpolate_scalingfactor_fcc(
struct single_row_lut *fcc_sf_lut, int cycles)
{
return -EINVAL;
}
static inline int interpolate_pc(struct pc_temp_ocv_lut *pc_temp_ocv,
int batt_temp_degc, int ocv)
{
return -EINVAL;
}
static inline int interpolate_ocv(struct pc_temp_ocv_lut *pc_temp_ocv,
int batt_temp_degc, int pc)
{
return -EINVAL;
}
static inline int linear_interpolate(int y0, int x0, int y1, int x1, int x)
{
return -EINVAL;
}
static inline int is_between(int left, int right, int value)
{
return -EINVAL;
}
#endif
#endif
kernel/include/linux/mfd/pm8xxx/ccadc.h
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/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __PMIC8XXX_CCADC_H__
#define __PMIC8XXX_CCADC_H__
#include <linux/mfd/pm8xxx/core.h>
#define PM8XXX_CCADC_DEV_NAME "pm8xxx-ccadc"
struct pm8xxx_ccadc_core_data {
unsigned int batt_temp_channel;
};
/**
* struct pm8xxx_ccadc_platform_data -
* @ccadc_cdata: core data for the ccadc driver containing channel info
* @r_sense_uohm: sense resistor value in (micro Ohms)
* @calib_delay_ms: how often should the adc calculate gain and offset
* @periodic_wakeup: a flag to indicate that this system wakeups periodically
* for calibration/other housekeeping activities. The ccadc
* does a quick calibration while resuming
*/
struct pm8xxx_ccadc_platform_data {
struct pm8xxx_ccadc_core_data ccadc_cdata;
int r_sense_uohm;
unsigned int calib_delay_ms;
bool periodic_wakeup;
};
#define CCADC_READING_RESOLUTION_N 542535
#define CCADC_READING_RESOLUTION_D 100000
static inline s64 pm8xxx_ccadc_reading_to_microvolt(int revision, s64 cc)
{
return div_s64(cc * CCADC_READING_RESOLUTION_N,
CCADC_READING_RESOLUTION_D);
}
#if defined(CONFIG_PM8XXX_CCADC) || defined(CONFIG_PM8XXX_CCADC_MODULE)
/**
* pm8xxx_cc_adjust_for_gain - the function to adjust the voltage read from
* ccadc for gain compensation
* @v: the voltage which needs to be gain compensated in microVolts
*
*
* RETURNS: gain compensated voltage
*/
s64 pm8xxx_cc_adjust_for_gain(s64 uv);
/**
* pm8xxx_calib_ccadc - calibration for ccadc. This will calculate gain
* and offset and reprogram them in the appropriate
* registers
*/
void pm8xxx_calib_ccadc(void);
/**
* pm8xxx_ccadc_get_battery_current - return the battery current based on vsense
* resitor in microamperes
* @result: The pointer where the voltage will be updated. A -ve
* result means that the current is flowing in
* the battery - during battery charging
*
* RETURNS: Error code if there was a problem reading vsense, Zero otherwise
* The result won't be updated in case of an error.
*
*/
int pm8xxx_ccadc_get_battery_current(int *bat_current);
#else
static inline s64 pm8xxx_cc_adjust_for_gain(s64 uv)
{
return -ENXIO;
}
static inline void pm8xxx_calib_ccadc(void)
{
}
static inline int pm8xxx_ccadc_get_battery_current(int *bat_current)
{
return -ENXIO;
}
#endif
#endif /* __PMIC8XXX_CCADC_H__ */
kernel/include/linux/mfd/pm8xxx/core.h
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/*
* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Qualcomm PMIC 8xxx driver header file
*
*/
#ifndef __MFD_PM8XXX_CORE_H
#define __MFD_PM8XXX_CORE_H
#include <linux/mfd/core.h>
enum pm8xxx_version {
PM8XXX_VERSION_8058,
PM8XXX_VERSION_8901,
PM8XXX_VERSION_8921,
PM8XXX_VERSION_8821,
PM8XXX_VERSION_8018,
PM8XXX_VERSION_8922,
PM8XXX_VERSION_8038,
PM8XXX_VERSION_8917,
};
/* PMIC version specific silicon revisions */
#define PM8XXX_REVISION_8058_TEST 0
#define PM8XXX_REVISION_8058_1p0 1
#define PM8XXX_REVISION_8058_2p0 2
#define PM8XXX_REVISION_8058_2p1 3
#define PM8XXX_REVISION_8901_TEST 0
#define PM8XXX_REVISION_8901_1p0 1
#define PM8XXX_REVISION_8901_1p1 2
#define PM8XXX_REVISION_8901_2p0 3
#define PM8XXX_REVISION_8901_2p1 4
#define PM8XXX_REVISION_8901_2p2 5
#define PM8XXX_REVISION_8901_2p3 6
#define PM8XXX_REVISION_8921_TEST 0
#define PM8XXX_REVISION_8921_1p0 1
#define PM8XXX_REVISION_8921_1p1 2
#define PM8XXX_REVISION_8921_2p0 3
#define PM8XXX_REVISION_8921_3p0 4
#define PM8XXX_REVISION_8921_3p1 5
#define PM8XXX_REVISION_8821_TEST 0
#define PM8XXX_REVISION_8821_1p0 1
#define PM8XXX_REVISION_8821_2p0 2
#define PM8XXX_REVISION_8821_2p1 3
#define PM8XXX_REVISION_8018_TEST 0
#define PM8XXX_REVISION_8018_1p0 1
#define PM8XXX_REVISION_8018_2p0 2
#define PM8XXX_REVISION_8018_2p1 3
#define PM8XXX_REVISION_8922_TEST 0
#define PM8XXX_REVISION_8922_1p0 1
#define PM8XXX_REVISION_8922_1p1 2
#define PM8XXX_REVISION_8922_2p0 3
#define PM8XXX_REVISION_8038_TEST 0
#define PM8XXX_REVISION_8038_1p0 1
#define PM8XXX_REVISION_8038_2p0 2
#define PM8XXX_REVISION_8038_2p1 3
#define PM8XXX_REVISION_8917_TEST 0
#define PM8XXX_REVISION_8917_1p0 1
#define PM8XXX_RESTART_UNKNOWN 0
#define PM8XXX_RESTART_CBL 1
#define PM8XXX_RESTART_KPD 2
#define PM8XXX_RESTART_CHG 3
#define PM8XXX_RESTART_SMPL 4
#define PM8XXX_RESTART_RTC 5
#define PM8XXX_RESTART_HARD_RESET 6
#define PM8XXX_RESTART_GEN_PURPOSE 7
#define PM8XXX_RESTART_REASON_MASK 0x07
static const char * const pm8xxx_restart_reason_str[] = {
[0] = "Unknown",
[1] = "Triggered from CBL (external charger)",
[2] = "Triggered from KPD (power key press)",
[3] = "Triggered from CHG (usb charger insertion)",
[4] = "Triggered from SMPL (sudden momentary power loss)",
[5] = "Triggered from RTC (real time clock)",
[6] = "Triggered by Hard Reset",
[7] = "Triggered by General Purpose Trigger",
};
struct pm8xxx_drvdata {
int (*pmic_readb) (const struct device *dev,
u16 addr, u8 *val);
int (*pmic_writeb) (const struct device *dev,
u16 addr, u8 val);
int (*pmic_read_buf) (const struct device *dev,
u16 addr, u8 *buf, int n);
int (*pmic_write_buf) (const struct device *dev,
u16 addr, u8 *buf, int n);
int (*pmic_read_irq_stat) (const struct device *dev,
int irq);
enum pm8xxx_version (*pmic_get_version) (const struct device *dev);
int (*pmic_get_revision) (const struct device *dev);
u8 (*pmic_restart_reason)
(const struct device *dev);
void *pm_chip_data;
};
static inline int pm8xxx_readb(const struct device *dev, u16 addr, u8 *val)
{
struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
if (!dd)
return -EINVAL;
return dd->pmic_readb(dev, addr, val);
}
static inline int pm8xxx_writeb(const struct device *dev, u16 addr, u8 val)
{
struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
if (!dd)
return -EINVAL;
return dd->pmic_writeb(dev, addr, val);
}
static inline int pm8xxx_read_buf(const struct device *dev, u16 addr, u8 *buf,
int n)
{
struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
if (!dd)
return -EINVAL;
return dd->pmic_read_buf(dev, addr, buf, n);
}
static inline int pm8xxx_write_buf(const struct device *dev, u16 addr, u8 *buf,
int n)
{
struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
if (!dd)
return -EINVAL;
return dd->pmic_write_buf(dev, addr, buf, n);
}
static inline int pm8xxx_read_irq_stat(const struct device *dev, int irq)
{
struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
if (!dd)
return -EINVAL;
return dd->pmic_read_irq_stat(dev, irq);
}
static inline enum pm8xxx_version pm8xxx_get_version(const struct device *dev)
{
struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
if (!dd)
return -EINVAL;
return dd->pmic_get_version(dev);
}
static inline int pm8xxx_get_revision(const struct device *dev)
{
struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
if (!dd)
return -EINVAL;
return dd->pmic_get_revision(dev);
}
static inline u8 pm8xxx_restart_reason(const struct device *dev)
{
struct pm8xxx_drvdata *dd = dev_get_drvdata(dev);
if (!dd)
return -EINVAL;
return dd->pmic_restart_reason(dev);
}
#endif
kernel/include/linux/mfd/pm8xxx/gpio.h
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/*
* Copyright (c) 2011, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Qualcomm PMIC8XXX gpio driver header file
*
*/
#ifndef __PM8XXX_GPIO_H
#define __PM8XXX_GPIO_H
#include <linux/errno.h>
#define PM8XXX_GPIO_DEV_NAME "pm8xxx-gpio"
struct pm8xxx_gpio_core_data {
int ngpios;
};
struct pm8xxx_gpio_platform_data {
struct pm8xxx_gpio_core_data gpio_cdata;
int gpio_base;
};
/* GPIO parameters */
/* direction */
#define PM_GPIO_DIR_OUT 0x01
#define PM_GPIO_DIR_IN 0x02
#define PM_GPIO_DIR_BOTH (PM_GPIO_DIR_OUT | PM_GPIO_DIR_IN)
/* output_buffer */
#define PM_GPIO_OUT_BUF_OPEN_DRAIN 1
#define PM_GPIO_OUT_BUF_CMOS 0
/* pull */
#define PM_GPIO_PULL_UP_30 0
#define PM_GPIO_PULL_UP_1P5 1
#define PM_GPIO_PULL_UP_31P5 2
#define PM_GPIO_PULL_UP_1P5_30 3
#define PM_GPIO_PULL_DN 4
#define PM_GPIO_PULL_NO 5
/* vin_sel: Voltage Input Select */
#define PM_GPIO_VIN_VPH 0 /* 3v ~ 4.4v */
#define PM_GPIO_VIN_BB 1 /* ~3.3v */
#define PM_GPIO_VIN_S4 2 /* 1.8v */
#define PM_GPIO_VIN_L15 3
#define PM_GPIO_VIN_L4 4
#define PM_GPIO_VIN_L3 5
#define PM_GPIO_VIN_L17 6
/* vin_sel: Voltage Input select on PM8058 */
#define PM8058_GPIO_VIN_VPH 0
#define PM8058_GPIO_VIN_BB 1
#define PM8058_GPIO_VIN_S3 2
#define PM8058_GPIO_VIN_L3 3
#define PM8058_GPIO_VIN_L7 4
#define PM8058_GPIO_VIN_L6 5
#define PM8058_GPIO_VIN_L5 6
#define PM8058_GPIO_VIN_L2 7
/* vin_sel: Voltage Input Select on PM8038*/
#define PM8038_GPIO_VIN_VPH 0
#define PM8038_GPIO_VIN_BB 1
#define PM8038_GPIO_VIN_L11 2
#define PM8038_GPIO_VIN_L15 3
#define PM8038_GPIO_VIN_L4 4
#define PM8038_GPIO_VIN_L3 5
#define PM8038_GPIO_VIN_L17 6
/* vin_sel: Voltage Input Select on PM8018*/
#define PM8018_GPIO_VIN_L4 0
#define PM8018_GPIO_VIN_L14 1
#define PM8018_GPIO_VIN_S3 2
#define PM8018_GPIO_VIN_L6 3
#define PM8018_GPIO_VIN_L2 4
#define PM8018_GPIO_VIN_L5 5
#define PM8018_GPIO_VIN_L8 6
#define PM8018_GPIO_VIN_VPH 7
/* out_strength */
#define PM_GPIO_STRENGTH_NO 0
#define PM_GPIO_STRENGTH_HIGH 1
#define PM_GPIO_STRENGTH_MED 2
#define PM_GPIO_STRENGTH_LOW 3
/* function */
#define PM_GPIO_FUNC_NORMAL 0
#define PM_GPIO_FUNC_PAIRED 1
#define PM_GPIO_FUNC_1 2
#define PM_GPIO_FUNC_2 3
#define PM_GPIO_DTEST1 4
#define PM_GPIO_DTEST2 5
#define PM_GPIO_DTEST3 6
#define PM_GPIO_DTEST4 7
/**
* struct pm_gpio - structure to specify gpio configurtion values
* @direction: indicates whether the gpio should be input, output, or
* both. Should be of the type PM_GPIO_DIR_*
* @output_buffer: indicates gpio should be configured as CMOS or open
* drain. Should be of the type PM_GPIO_OUT_BUF_*
* @output_value: The gpio output value of the gpio line - 0 or 1
* @pull: Indicates whether a pull up or pull down should be
* applied. If a pullup is required the current strength
* needs to be specified. Current values of 30uA, 1.5uA,
* 31.5uA, 1.5uA with 30uA boost are supported. This value
* should be one of the PM_GPIO_PULL_*
* @vin_sel: specifies the voltage level when the output is set to 1.
* For an input gpio specifies the voltage level at which
* the input is interpreted as a logical 1.
* @out_strength: the amount of current supplied for an output gpio,
* should be of the type PM_GPIO_STRENGTH_*
* @function: choose alternate function for the gpio. Certain gpios
* can be paired (shorted) with each other. Some gpio pin
* can act as alternate functions. This parameter should
* be of type PM_GPIO_FUNC_*
* @inv_int_pol: Invert polarity before feeding the line to the interrupt
* module in pmic. This feature will almost be never used
* since the pm8xxx interrupt block can detect both edges
* and both levels.
* @disable_pin: Disable the gpio by configuring it as high impedance.
*/
struct pm_gpio {
int direction;
int output_buffer;
int output_value;
int pull;
int vin_sel;
int out_strength;
int function;
int inv_int_pol;
int disable_pin;
};
#if defined(CONFIG_GPIO_PM8XXX) || defined(CONFIG_GPIO_PM8XXX_MODULE)
/**
* pm8xxx_gpio_config - configure a gpio controlled by a pm8xxx chip
* @gpio: gpio number to configure
* @param: configuration values
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_gpio_config(int gpio, struct pm_gpio *param);
#else
static inline int pm8xxx_gpio_config(int gpio, struct pm_gpio *param)
{
return -ENXIO;
}
#endif
#endif
kernel/include/linux/mfd/pm8xxx/irq.h
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/*
* Copyright (c) 2011, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Qualcomm PMIC irq 8xxx driver header file
*
*/
#ifndef __MFD_PM8XXX_IRQ_H
#define __MFD_PM8XXX_IRQ_H
#include <linux/errno.h>
#include <linux/err.h>
struct pm8xxx_irq_core_data {
u32 rev;
int nirqs;
unsigned int base_addr;
};
struct pm8xxx_irq_platform_data {
int irq_base;
struct pm8xxx_irq_core_data irq_cdata;
int devirq;
int irq_trigger_flag;
int dev_id;
};
struct pm_irq_chip;
#ifdef CONFIG_MFD_PM8XXX_IRQ
int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq);
struct pm_irq_chip *pm8xxx_irq_init(struct device *dev,
const struct pm8xxx_irq_platform_data *pdata);
int pm8xxx_irq_exit(struct pm_irq_chip *chip);
#else
static inline int pm8xxx_get_irq_stat(struct pm_irq_chip *chip, int irq)
{
return -ENXIO;
}
static inline struct pm_irq_chip *pm8xxx_irq_init(const struct device *dev,
const struct pm8xxx_irq_platform_data *pdata)
{
return ERR_PTR(-ENXIO);
}
static inline int pm8xxx_irq_exit(struct pm_irq_chip *chip)
{
return -ENXIO;
}
#endif /* CONFIG_MFD_PM8XXX_IRQ */
#endif /* __MFD_PM8XXX_IRQ_H */
kernel/include/linux/mfd/pm8xxx/misc.h
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/*
* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MFD_PM8XXX_MISC_H__
#define __MFD_PM8XXX_MISC_H__
#include <linux/err.h>
#define PM8XXX_MISC_DEV_NAME "pm8xxx-misc"
/**
* struct pm8xxx_misc_platform_data - PM8xxx misc driver platform data
* @priority: PMIC prority level in a multi-PMIC system. Lower value means
* greater priority. Actions are performed from highest to lowest
* priority PMIC.
*/
struct pm8xxx_misc_platform_data {
int priority;
};
enum pm8xxx_uart_path_sel {
UART_NONE,
UART_TX1_RX1,
UART_TX2_RX2,
UART_TX3_RX3,
};
enum pm8xxx_coincell_chg_voltage {
PM8XXX_COINCELL_VOLTAGE_3p2V = 1,
PM8XXX_COINCELL_VOLTAGE_3p1V,
PM8XXX_COINCELL_VOLTAGE_3p0V,
PM8XXX_COINCELL_VOLTAGE_2p5V = 16
};
enum pm8xxx_coincell_chg_resistor {
PM8XXX_COINCELL_RESISTOR_2100_OHMS,
PM8XXX_COINCELL_RESISTOR_1700_OHMS,
PM8XXX_COINCELL_RESISTOR_1200_OHMS,
PM8XXX_COINCELL_RESISTOR_800_OHMS
};
enum pm8xxx_coincell_chg_state {
PM8XXX_COINCELL_CHG_DISABLE,
PM8XXX_COINCELL_CHG_ENABLE
};
struct pm8xxx_coincell_chg {
enum pm8xxx_coincell_chg_state state;
enum pm8xxx_coincell_chg_voltage voltage;
enum pm8xxx_coincell_chg_resistor resistor;
};
enum pm8xxx_smpl_delay {
PM8XXX_SMPL_DELAY_0p5,
PM8XXX_SMPL_DELAY_1p0,
PM8XXX_SMPL_DELAY_1p5,
PM8XXX_SMPL_DELAY_2p0,
};
enum pm8xxx_pon_config {
PM8XXX_DISABLE_HARD_RESET = 0,
PM8XXX_SHUTDOWN_ON_HARD_RESET,
PM8XXX_RESTART_ON_HARD_RESET,
};
enum pm8xxx_aux_clk_id {
CLK_MP3_1,
CLK_MP3_2,
};
enum pm8xxx_aux_clk_div {
XO_DIV_NONE,
XO_DIV_1,
XO_DIV_2,
XO_DIV_4,
XO_DIV_8,
XO_DIV_16,
XO_DIV_32,
XO_DIV_64,
};
enum pm8xxx_hsed_bias {
PM8XXX_HSED_BIAS0,
PM8XXX_HSED_BIAS1,
PM8XXX_HSED_BIAS2,
};
#if defined(CONFIG_MFD_PM8XXX_MISC) || defined(CONFIG_MFD_PM8XXX_MISC_MODULE)
/**
* pm8xxx_reset_pwr_off - switch all PM8XXX PMIC chips attached to the system to
* either reset or shutdown when they are turned off
* @reset: 0 = shudown the PMICs, 1 = shutdown and then restart the PMICs
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_reset_pwr_off(int reset);
int pm8xxx_uart_gpio_mux_ctrl(enum pm8xxx_uart_path_sel uart_path_sel);
/**
* pm8xxx_coincell_chg_config - Disables or enables the coincell charger, and
* configures its voltage and resistor settings.
* @chg_config: Holds both voltage and resistor values, and a
* switch to change the state of charger.
* If state is to disable the charger then
* both voltage and resistor are disregarded.
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_coincell_chg_config(struct pm8xxx_coincell_chg *chg_config);
/**
* pm8xxx_smpl_control - enables/disables SMPL detection
* @enable: 0 = shutdown PMIC on power loss, 1 = reset PMIC on power loss
*
* This function enables or disables the Sudden Momentary Power Loss detection
* module. If SMPL detection is enabled, then when a sufficiently long power
* loss event occurs, the PMIC will automatically reset itself. If SMPL
* detection is disabled, then the PMIC will shutdown when power loss occurs.
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_smpl_control(int enable);
/**
* pm8xxx_smpl_set_delay - sets the SMPL detection time delay
* @delay: enum value corresponding to delay time
*
* This function sets the time delay of the SMPL detection module. If power
* is reapplied within this interval, then the PMIC reset automatically. The
* SMPL detection module must be enabled for this delay time to take effect.
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_smpl_set_delay(enum pm8xxx_smpl_delay delay);
/**
* pm8xxx_watchdog_reset_control - enables/disables watchdog reset detection
* @enable: 0 = shutdown when PS_HOLD goes low, 1 = reset when PS_HOLD goes low
*
* This function enables or disables the PMIC watchdog reset detection feature.
* If watchdog reset detection is enabled, then the PMIC will reset itself
* when PS_HOLD goes low. If it is not enabled, then the PMIC will shutdown
* when PS_HOLD goes low.
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_watchdog_reset_control(int enable);
/**
* pm8xxx_hard_reset_config - Allows different reset configurations
*
* config = DISABLE_HARD_RESET to disable hard reset
* = SHUTDOWN_ON_HARD_RESET to turn off the system on hard reset
* = RESTART_ON_HARD_RESET to restart the system on hard reset
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_hard_reset_config(enum pm8xxx_pon_config config);
/**
* pm8xxx_stay_on - enables stay_on feature
*
* PMIC stay-on feature allows PMIC to ignore MSM PS_HOLD=low
* signal so that some special functions like debugging could be
* performed.
*
* This feature should not be used in any product release.
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_stay_on(void);
/**
* pm8xxx_preload_dVdd - preload the dVdd regulator during off state.
*
* This can help to reduce fluctuations in the dVdd voltage during startup
* at the cost of additional off state current draw.
*
* This API should only be called if dVdd startup issues are suspected.
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_preload_dVdd(void);
/**
* pm8xxx_usb_id_pullup - Control a pullup for USB ID
*
* @enable: enable (1) or disable (0) the pullup
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_usb_id_pullup(int enable);
/**
* pm8xxx_aux_clk_control - Control an auxiliary clock
* @clk_id: ID of clock to be programmed, registers of XO_CNTRL2
* @divider: divisor to use when configuring desired clock
* @enable: enable (1) the designated clock with the supplied division,
* or disable (0) the designated clock
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_aux_clk_control(enum pm8xxx_aux_clk_id clk_id,
enum pm8xxx_aux_clk_div divider,
bool enable);
/**
* pm8xxx_hsed_bias_control - Control the HSED_BIAS signal
* @bias: the bias line to be controlled (of the 3)
* @enable: enable/disable the bias line
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_hsed_bias_control(enum pm8xxx_hsed_bias bias, bool enable);
/**
* pm8xxx_read_register - Read a PMIC register
* @addr: PMIC register address
* @value: Output parameter which gets the value of the register read.
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_read_register(u16 addr, u8 *value);
#else
static inline int pm8xxx_reset_pwr_off(int reset)
{
return -ENODEV;
}
static inline int
pm8xxx_uart_gpio_mux_ctrl(enum pm8xxx_uart_path_sel uart_path_sel)
{
return -ENODEV;
}
static inline int
pm8xxx_coincell_chg_config(struct pm8xxx_coincell_chg *chg_config)
{
return -ENODEV;
}
static inline int pm8xxx_smpl_set_delay(enum pm8xxx_smpl_delay delay)
{
return -ENODEV;
}
static inline int pm8xxx_smpl_control(int enable)
{
return -ENODEV;
}
static inline int pm8xxx_watchdog_reset_control(int enable)
{
return -ENODEV;
}
static inline int pm8xxx_hard_reset_config(enum pm8xxx_pon_config config)
{
return -ENODEV;
}
static inline int pm8xxx_stay_on(void)
{
return -ENODEV;
}
static inline int pm8xxx_preload_dVdd(void)
{
return -ENODEV;
}
static inline int pm8xxx_usb_id_pullup(int enable)
{
return -ENODEV;
}
static inline int pm8xxx_aux_clk_control(enum pm8xxx_aux_clk_id clk_id,
enum pm8xxx_aux_clk_div divider, bool enable)
{
return -ENODEV;
}
static inline int pm8xxx_hsed_bias_control(enum pm8xxx_hsed_bias bias,
bool enable)
{
return -ENODEV;
}
static inline int pm8xxx_read_register(u16 addr, u8 *value)
{
return -ENODEV;
}
#endif
#endif
kernel/include/linux/mfd/pm8xxx/mpp.h
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/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __PM8XXX_MPP_H
#define __PM8XXX_MPP_H
#include <linux/errno.h>
#define PM8XXX_MPP_DEV_NAME "pm8xxx-mpp"
struct pm8xxx_mpp_core_data {
int base_addr;
int nmpps;
};
struct pm8xxx_mpp_platform_data {
struct pm8xxx_mpp_core_data core_data;
int mpp_base;
};
/**
* struct pm8xxx_mpp_config_data - structure to specify mpp configuration values
* @type: MPP type which determines the overall MPP function (i.e. digital
* in/out/bi, analog in/out, current sink, or test). It should be
* set to the value of one of PM8XXX_MPP_TYPE_D_*.
* @level: meaning depends upon MPP type specified
* @control: meaning depends upon MPP type specified
*
* Usage of level argument:
* 1. type = PM8XXX_MPP_TYPE_D_INPUT, PM8XXX_MPP_TYPE_D_OUTPUT,
* PM8XXX_MPP_TYPE_D_BI_DIR, or PM8XXX_MPP_TYPE_DTEST_OUTPUT -
*
* level specifies that digital logic level to use for the MPP. It should
* be set to the value of one of PM8XXX_MPP_DIG_LEVEL_*. Actual regulator
* connections for these level choices are PMIC chip specific.
*
* 2. type = PM8XXX_MPP_TYPE_A_INPUT -
*
* level specifies where in the PMIC chip the analog input value should
* be routed to. It should be set to the value of one of
* PM8XXX_MPP_AIN_AMUX_*.
*
* 3. type = PM8XXX_MPP_TYPE_A_OUTPUT -
*
* level specifies the output analog voltage reference level. It should
* be set to the value of one of PM8XXX_MPP_AOUT_LVL_*.
*
* 4. type = PM8XXX_MPP_TYPE_SINK or PM8XXX_MPP_TYPE_DTEST_SINK -
*
* level specifies the output current level. It should be set to the value
* of one of PM8XXX_MPP_CS_OUT_*.
*
* Usage of control argument:
* 1. type = PM8XXX_MPP_TYPE_D_INPUT -
*
* control specifies how the digital input should be routed in the chip.
* It should be set to the value of one of PM8XXX_MPP_DIN_TO_*.
*
* 2. type = PM8XXX_MPP_TYPE_D_OUTPUT -
*
* control specifies the digital output value. It should be set to the
* value of one of PM8XXX_MPP_DOUT_CTRL_*.
*
* 3. type = PM8XXX_MPP_TYPE_D_BI_DIR -
*
* control specifies the pullup resistor value. It should be set to the
* value of one of PM8XXX_MPP_BI_PULLUP_*.
*
* 4. type = PM8XXX_MPP_TYPE_A_INPUT -
*
* control is unused; a value of 0 is sufficient.
*
* 5. type = PM8XXX_MPP_TYPE_A_OUTPUT -
*
* control specifies if analog output is enabled. It should be set to the
* value of one of PM8XXX_MPP_AOUT_CTRL_*.
*
* 6. type = PM8XXX_MPP_TYPE_SINK -
*
* control specifies if current sinking is enabled. It should be set to
* the value of one of PM8XXX_MPP_CS_CTRL_*.
*
* 7. type = PM8XXX_MPP_TYPE_DTEST_SINK -
*
* control specifies if current sinking is enabled. It should be set to
* the value of one of PM8XXX_MPP_DTEST_CS_CTRL_*.
*
* 8. type = PM8XXX_MPP_TYPE_DTEST_OUTPUT -
*
* control specifies which DTEST bus value to output. It should be set to
* the value of one of PM8XXX_MPP_DTEST_*.
*/
struct pm8xxx_mpp_config_data {
unsigned type;
unsigned level;
unsigned control;
};
/* API */
#if defined(CONFIG_GPIO_PM8XXX_MPP) || defined(CONFIG_GPIO_PM8XXX_MPP_MODULE)
/**
* pm8xxx_mpp_config() - configure control options of a multi-purpose pin (MPP)
* @mpp: global GPIO number corresponding to the MPP
* @config: configuration to set for this MPP
* Context: can sleep
*
* RETURNS: an appropriate -ERRNO error value on error, or zero for success.
*/
int pm8xxx_mpp_config(unsigned mpp, struct pm8xxx_mpp_config_data *config);
#else
static inline int pm8xxx_mpp_config(unsigned mpp,
struct pm8xxx_mpp_config_data *config)
{
return -ENXIO;
}
#endif
/* MPP Type: type */
#define PM8XXX_MPP_TYPE_D_INPUT 0
#define PM8XXX_MPP_TYPE_D_OUTPUT 1
#define PM8XXX_MPP_TYPE_D_BI_DIR 2
#define PM8XXX_MPP_TYPE_A_INPUT 3
#define PM8XXX_MPP_TYPE_A_OUTPUT 4
#define PM8XXX_MPP_TYPE_SINK 5
#define PM8XXX_MPP_TYPE_DTEST_SINK 6
#define PM8XXX_MPP_TYPE_DTEST_OUTPUT 7
/* Digital Input/Output: level */
#define PM8XXX_MPP_DIG_LEVEL_VIO_0 0
#define PM8XXX_MPP_DIG_LEVEL_VIO_1 1
#define PM8XXX_MPP_DIG_LEVEL_VIO_2 2
#define PM8XXX_MPP_DIG_LEVEL_VIO_3 3
#define PM8XXX_MPP_DIG_LEVEL_VIO_4 4
#define PM8XXX_MPP_DIG_LEVEL_VIO_5 5
#define PM8XXX_MPP_DIG_LEVEL_VIO_6 6
#define PM8XXX_MPP_DIG_LEVEL_VIO_7 7
/* Digital Input/Output: level [PM8058] */
#define PM8058_MPP_DIG_LEVEL_VPH 0
#define PM8058_MPP_DIG_LEVEL_S3 1
#define PM8058_MPP_DIG_LEVEL_L2 2
#define PM8058_MPP_DIG_LEVEL_L3 3
/* Digital Input/Output: level [PM8901] */
#define PM8901_MPP_DIG_LEVEL_MSMIO 0
#define PM8901_MPP_DIG_LEVEL_DIG 1
#define PM8901_MPP_DIG_LEVEL_L5 2
#define PM8901_MPP_DIG_LEVEL_S4 3
#define PM8901_MPP_DIG_LEVEL_VPH 4
/* Digital Input/Output: level [PM8921] */
#define PM8921_MPP_DIG_LEVEL_S4 1
#define PM8921_MPP_DIG_LEVEL_L15 3
#define PM8921_MPP_DIG_LEVEL_L17 4
#define PM8921_MPP_DIG_LEVEL_VPH 7
/* Digital Input/Output: level [PM8821] */
#define PM8821_MPP_DIG_LEVEL_1P8 0
#define PM8821_MPP_DIG_LEVEL_VPH 7
/* Digital Input/Output: level [PM8018] */
#define PM8018_MPP_DIG_LEVEL_L4 0
#define PM8018_MPP_DIG_LEVEL_L14 1
#define PM8018_MPP_DIG_LEVEL_S3 2
#define PM8018_MPP_DIG_LEVEL_L6 3
#define PM8018_MPP_DIG_LEVEL_L2 4
#define PM8018_MPP_DIG_LEVEL_L5 5
#define PM8018_MPP_DIG_LEVEL_VPH 7
/* Digital Input/Output: level [PM8038] */
#define PM8038_MPP_DIG_LEVEL_L20 0
#define PM8038_MPP_DIG_LEVEL_L11 1
#define PM8038_MPP_DIG_LEVEL_L5 2
#define PM8038_MPP_DIG_LEVEL_L15 3
#define PM8038_MPP_DIG_LEVEL_L17 4
#define PM8038_MPP_DIG_LEVEL_VPH 7
/* Digital Input: control */
#define PM8XXX_MPP_DIN_TO_INT 0
#define PM8XXX_MPP_DIN_TO_DBUS1 1
#define PM8XXX_MPP_DIN_TO_DBUS2 2
#define PM8XXX_MPP_DIN_TO_DBUS3 3
/* Digital Output: control */
#define PM8XXX_MPP_DOUT_CTRL_LOW 0
#define PM8XXX_MPP_DOUT_CTRL_HIGH 1
#define PM8XXX_MPP_DOUT_CTRL_MPP 2
#define PM8XXX_MPP_DOUT_CTRL_INV_MPP 3
/* Bidirectional: control */
#define PM8XXX_MPP_BI_PULLUP_1KOHM 0
#define PM8XXX_MPP_BI_PULLUP_OPEN 1
#define PM8XXX_MPP_BI_PULLUP_10KOHM 2
#define PM8XXX_MPP_BI_PULLUP_30KOHM 3
/* Analog Input: level */
#define PM8XXX_MPP_AIN_AMUX_CH5 0
#define PM8XXX_MPP_AIN_AMUX_CH6 1
#define PM8XXX_MPP_AIN_AMUX_CH7 2
#define PM8XXX_MPP_AIN_AMUX_CH8 3
#define PM8XXX_MPP_AIN_AMUX_CH9 4
#define PM8XXX_MPP_AIN_AMUX_ABUS1 5
#define PM8XXX_MPP_AIN_AMUX_ABUS2 6
#define PM8XXX_MPP_AIN_AMUX_ABUS3 7
/* Analog Output: level */
#define PM8XXX_MPP_AOUT_LVL_1V25 0
#define PM8XXX_MPP_AOUT_LVL_1V25_2 1
#define PM8XXX_MPP_AOUT_LVL_0V625 2
#define PM8XXX_MPP_AOUT_LVL_0V3125 3
#define PM8XXX_MPP_AOUT_LVL_MPP 4
#define PM8XXX_MPP_AOUT_LVL_ABUS1 5
#define PM8XXX_MPP_AOUT_LVL_ABUS2 6
#define PM8XXX_MPP_AOUT_LVL_ABUS3 7
/* Analog Output: control */
#define PM8XXX_MPP_AOUT_CTRL_DISABLE 0
#define PM8XXX_MPP_AOUT_CTRL_ENABLE 1
#define PM8XXX_MPP_AOUT_CTRL_MPP_HIGH_EN 2
#define PM8XXX_MPP_AOUT_CTRL_MPP_LOW_EN 3
/* Current Sink: level */
#define PM8XXX_MPP_CS_OUT_5MA 0
#define PM8XXX_MPP_CS_OUT_10MA 1
#define PM8XXX_MPP_CS_OUT_15MA 2
#define PM8XXX_MPP_CS_OUT_20MA 3
#define PM8XXX_MPP_CS_OUT_25MA 4
#define PM8XXX_MPP_CS_OUT_30MA 5
#define PM8XXX_MPP_CS_OUT_35MA 6
#define PM8XXX_MPP_CS_OUT_40MA 7
/* Current Sink: control */
#define PM8XXX_MPP_CS_CTRL_DISABLE 0
#define PM8XXX_MPP_CS_CTRL_ENABLE 1
#define PM8XXX_MPP_CS_CTRL_MPP_HIGH_EN 2
#define PM8XXX_MPP_CS_CTRL_MPP_LOW_EN 3
/* DTEST Current Sink: control */
#define PM8XXX_MPP_DTEST_CS_CTRL_EN1 0
#define PM8XXX_MPP_DTEST_CS_CTRL_EN2 1
#define PM8XXX_MPP_DTEST_CS_CTRL_EN3 2
#define PM8XXX_MPP_DTEST_CS_CTRL_EN4 3
/* DTEST Digital Output: control */
#define PM8XXX_MPP_DTEST_DBUS1 0
#define PM8XXX_MPP_DTEST_DBUS2 1
#define PM8XXX_MPP_DTEST_DBUS3 2
#define PM8XXX_MPP_DTEST_DBUS4 3
#endif
kernel/include/linux/mfd/pm8xxx/nfc.h
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/* Copyright (c) 2010,2011 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __PM8XXX_NFC_H__
#define __PM8XXX_NFC_H__
struct pm8xxx_nfc_device;
#define PM8XXX_NFC_DEV_NAME "pm8xxx-nfc"
/* masks, flags and status */
#define PM_NFC_VDDLDO_MON_LEVEL 0x0003
#define PM_NFC_VPH_PWR_EN 0x0008
#define PM_NFC_EXT_VDDLDO_EN 0x0010
#define PM_NFC_EN 0x0020
#define PM_NFC_LDO_EN 0x0040
#define PM_NFC_SUPPORT_EN 0x0080
#define PM_NFC_EXT_EN_HIGH 0x0100
#define PM_NFC_MBG_EN_HIGH 0x0200
#define PM_NFC_VDDLDO_OK_HIGH 0x0400
#define PM_NFC_DTEST1_MODE 0x2000
#define PM_NFC_ATEST_EN 0x4000
#define PM_NFC_VDDLDO_MON_EN 0x8000
#define PM_NFC_CTRL_REQ (PM_NFC_SUPPORT_EN |\
PM_NFC_LDO_EN |\
PM_NFC_EN |\
PM_NFC_EXT_VDDLDO_EN |\
PM_NFC_VPH_PWR_EN |\
PM_NFC_VDDLDO_MON_LEVEL)
#define PM_NFC_TEST_REQ (PM_NFC_VDDLDO_MON_EN |\
PM_NFC_DTEST1_MODE |\
PM_NFC_ATEST_EN)
#define PM_NFC_TEST_STATUS (PM_NFC_EXT_EN_HIGH |\
PM_NFC_MBG_EN_HIGH |\
PM_NFC_VDDLDO_OK_HIGH)
/*
* pm8xxx_nfc_request - request a handle to access NFC device
*/
struct pm8xxx_nfc_device *pm8xxx_nfc_request(void);
/*
* pm8xxx_nfc_config - configure NFC signals
*
* @nfcdev: the NFC device
* @mask: signal mask to configure
* @flags: control flags
*/
int pm8xxx_nfc_config(struct pm8xxx_nfc_device *nfcdev, u32 mask, u32 flags);
/*
* pm8xxx_nfc_get_status - get NFC status
*
* @nfcdev: the NFC device
* @mask: of status mask to read
* @status: pointer to the status variable
*/
int pm8xxx_nfc_get_status(struct pm8xxx_nfc_device *nfcdev,
u32 mask, u32 *status);
/*
* pm8xxx_nfc_free - free the NFC device
*/
void pm8xxx_nfc_free(struct pm8xxx_nfc_device *nfcdev);
#endif /* __PM8XXX_NFC_H__ */
kernel/include/linux/mfd/pm8xxx/pm8018.h
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/*
* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Qualcomm PMIC 8018 driver header file
*
*/
#ifndef __MFD_PM8018_H
#define __MFD_PM8018_H
#include <linux/device.h>
#include <linux/mfd/pm8xxx/irq.h>
#include <linux/mfd/pm8xxx/gpio.h>
#include <linux/mfd/pm8xxx/mpp.h>
#include <linux/mfd/pm8xxx/rtc.h>
#include <linux/mfd/pm8xxx/tm.h>
#include <linux/input/pmic8xxx-pwrkey.h>
#include <linux/mfd/pm8xxx/misc.h>
#include <linux/regulator/pm8xxx-regulator.h>
#include <linux/mfd/pm8xxx/pm8xxx-adc.h>
#include <linux/mfd/pm8xxx/pwm.h>
#include <linux/leds-pm8xxx.h>
#define PM8018_CORE_DEV_NAME "pm8018-core"
#define PM8018_NR_IRQS 256
#define PM8018_NR_GPIOS 6
#define PM8018_NR_MPPS 6
#define PM8018_GPIO_BLOCK_START 24
#define PM8018_MPP_BLOCK_START 16
#define PM8018_IRQ_BLOCK_BIT(block, bit) ((block) * 8 + (bit))
/* GPIOs and MPPs [1,N] */
#define PM8018_GPIO_IRQ(base, gpio) ((base) + \
PM8018_IRQ_BLOCK_BIT(PM8018_GPIO_BLOCK_START, (gpio)-1))
#define PM8018_MPP_IRQ(base, mpp) ((base) + \
PM8018_IRQ_BLOCK_BIT(PM8018_MPP_BLOCK_START, (mpp)-1))
/* PMIC Interrupts */
#define PM8018_RTC_ALARM_IRQ PM8018_IRQ_BLOCK_BIT(4, 7)
#define PM8018_PWRKEY_REL_IRQ PM8018_IRQ_BLOCK_BIT(6, 2)
#define PM8018_PWRKEY_PRESS_IRQ PM8018_IRQ_BLOCK_BIT(6, 3)
#define PM8018_ADC_EOC_USR_IRQ PM8018_IRQ_BLOCK_BIT(9, 6)
#define PM8018_ADC_BATT_TEMP_WARM_IRQ PM8018_IRQ_BLOCK_BIT(9, 1)
#define PM8018_ADC_BATT_TEMP_COLD_IRQ PM8018_IRQ_BLOCK_BIT(9, 0)
#define PM8018_OVERTEMP_IRQ PM8018_IRQ_BLOCK_BIT(4, 2)
#define PM8018_TEMPSTAT_IRQ PM8018_IRQ_BLOCK_BIT(6, 7)
#define PM8018_LVS1_OCP_IRQ PM8921_IRQ_BLOCK_BIT(13, 0)
struct pm8018_platform_data {
struct pm8xxx_irq_platform_data *irq_pdata;
struct pm8xxx_gpio_platform_data *gpio_pdata;
struct pm8xxx_mpp_platform_data *mpp_pdata;
struct pm8xxx_rtc_platform_data *rtc_pdata;
struct pm8xxx_pwrkey_platform_data *pwrkey_pdata;
struct pm8xxx_misc_platform_data *misc_pdata;
struct pm8xxx_regulator_platform_data *regulator_pdatas;
struct pm8xxx_adc_platform_data *adc_pdata;
int num_regulators;
struct pm8xxx_led_platform_data *leds_pdata;
};
#endif
kernel/include/linux/mfd/pm8xxx/pm8038.h
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/*
* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Qualcomm PMIC 8038 driver header file
*
*/
#ifndef __MFD_PM8038_H
#define __MFD_PM8038_H
#include <linux/device.h>
#include <linux/mfd/pm8xxx/irq.h>
#include <linux/mfd/pm8xxx/gpio.h>
#include <linux/mfd/pm8xxx/mpp.h>
#include <linux/mfd/pm8xxx/pwm.h>
#include <linux/mfd/pm8xxx/rtc.h>
#include <linux/input/pmic8xxx-pwrkey.h>
#include <linux/mfd/pm8xxx/misc.h>
#include <linux/regulator/pm8xxx-regulator.h>
#include <linux/mfd/pm8xxx/pm8xxx-adc.h>
#include <linux/mfd/pm8xxx/pm8921-charger.h>
#include <linux/mfd/pm8xxx/pm8921-bms.h>
#include <linux/leds-pm8xxx.h>
#include <linux/mfd/pm8xxx/ccadc.h>
#include <linux/mfd/pm8xxx/spk.h>
#include <linux/mfd/pm8xxx/tm.h>
#define PM8038_CORE_DEV_NAME "pm8038-core"
#define PM8038_NR_IRQS 256
#define PM8038_NR_GPIOS 12
#define PM8038_NR_MPPS 6
#define PM8038_GPIO_BLOCK_START 24
#define PM8038_MPP_BLOCK_START 16
#define PM8038_IRQ_BLOCK_BIT(block, bit) ((block) * 8 + (bit))
/* GPIO and MPPs [1,N] */
#define PM8038_GPIO_IRQ(base, gpio) ((base) + \
PM8038_IRQ_BLOCK_BIT(PM8038_GPIO_BLOCK_START, (gpio)-1))
#define PM8038_MPP_IRQ(base, mpp) ((base) + \
PM8038_IRQ_BLOCK_BIT(PM8038_MPP_BLOCK_START, (mpp)-1))
/* PMIC Interrupts */
#define PM8038_RTC_ALARM_IRQ PM8038_IRQ_BLOCK_BIT(4, 7)
#define PM8038_BATT_ALARM_IRQ PM8921_IRQ_BLOCK_BIT(5, 6)
#define PM8038_PWRKEY_REL_IRQ PM8038_IRQ_BLOCK_BIT(6, 2)
#define PM8038_PWRKEY_PRESS_IRQ PM8038_IRQ_BLOCK_BIT(6, 3)
#define PM8038_KEYPAD_IRQ PM8038_IRQ_BLOCK_BIT(9, 2)
#define PM8038_KEYSTUCK_IRQ PM8038_IRQ_BLOCK_BIT(9, 3)
#define PM8038_ADC_EOC_USR_IRQ PM8038_IRQ_BLOCK_BIT(9, 6)
#define PM8038_ADC_BATT_TEMP_WARM_IRQ PM8038_IRQ_BLOCK_BIT(9, 1)
#define PM8038_ADC_BATT_TEMP_COLD_IRQ PM8038_IRQ_BLOCK_BIT(9, 0)
#define PM8038_USB_ID_IN_IRQ(base) (base + PM8921_IRQ_BLOCK_BIT(6, 1))
#define PM8038_RESOUT_IRQ PM8038_IRQ_BLOCK_BIT(6, 4)
#define PM8038_OVERTEMP_IRQ PM8038_IRQ_BLOCK_BIT(4, 2)
#define PM8038_TEMPSTAT_IRQ PM8038_IRQ_BLOCK_BIT(6, 7)
struct pm8038_platform_data {
int irq_base;
struct pm8xxx_gpio_platform_data *gpio_pdata;
struct pm8xxx_irq_platform_data *irq_pdata;
struct pm8xxx_mpp_platform_data *mpp_pdata;
struct pm8xxx_rtc_platform_data *rtc_pdata;
struct pm8xxx_pwrkey_platform_data *pwrkey_pdata;
struct pm8xxx_misc_platform_data *misc_pdata;
struct pm8xxx_regulator_platform_data *regulator_pdatas;
int num_regulators;
struct pm8921_charger_platform_data *charger_pdata;
struct pm8921_bms_platform_data *bms_pdata;
struct pm8xxx_adc_platform_data *adc_pdata;
struct pm8xxx_led_platform_data *leds_pdata;
struct pm8xxx_vibrator_platform_data *vibrator_pdata;
struct pm8xxx_ccadc_platform_data *ccadc_pdata;
struct pm8xxx_spk_platform_data *spk_pdata;
};
#endif
kernel/include/linux/mfd/pm8xxx/pm8821-irq.h
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/*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Qualcomm PMIC irq 8821 driver header file
*
*/
#ifndef __MFD_PM8821_IRQ_H
#define __MFD_PM8821_IRQ_H
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/mfd/pm8xxx/irq.h>
#ifdef CONFIG_MFD_PM8821_IRQ
int pm8821_get_irq_stat(struct pm_irq_chip *chip, int irq);
struct pm_irq_chip *pm8821_irq_init(struct device *dev,
const struct pm8xxx_irq_platform_data *pdata);
int pm8821_irq_exit(struct pm_irq_chip *chip);
#else
static inline int pm8821_get_irq_stat(struct pm_irq_chip *chip, int irq)
{
return -ENXIO;
}
static inline struct pm_irq_chip *pm8821_irq_init(const struct device *dev,
const struct pm8xxx_irq_platform_data *pdata)
{
return ERR_PTR(-ENXIO);
}
static inline int pm8821_irq_exit(struct pm_irq_chip *chip)
{
return -ENXIO;
}
#endif /* CONFIG_MFD_PM8821_IRQ */
#endif /* __MFD_PM8821_IRQ_H */
kernel/include/linux/mfd/pm8xxx/pm8821.h
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/*
* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Qualcomm PMIC 8821 driver header file
*
*/
#ifndef __MFD_PM8821_H
#define __MFD_PM8821_H
#include <linux/device.h>
#include <linux/mfd/pm8xxx/pm8821-irq.h>
#include <linux/mfd/pm8xxx/mpp.h>
#include <linux/mfd/pm8xxx/tm.h>
#define PM8821_NR_IRQS (112)
#define PM8821_NR_MPPS (4)
#define PM8821_MPP_BLOCK_START (4)
/*
* Block 0 does not exist in PM8821 IRQ SSBI address space,
* IRQ0 is assigned to bit0 of block1
*/
#define PM8821_IRQ_BLOCK_BIT(block, bit) ((block-1) * 8 + (bit))
/* MPPs [1,N] */
#define PM8821_MPP_IRQ(base, mpp) ((base) + \
PM8821_IRQ_BLOCK_BIT(PM8821_MPP_BLOCK_START, (mpp)-1))
/* PMIC Interrupts */
#define PM8821_OVERTEMP_IRQ PM8821_IRQ_BLOCK_BIT(5, 2)
#define PM8821_TEMPSTAT_IRQ PM8821_IRQ_BLOCK_BIT(5, 7)
struct pm8821_platform_data {
int irq_base;
struct pm8xxx_irq_platform_data *irq_pdata;
struct pm8xxx_mpp_platform_data *mpp_pdata;
};
#endif
kernel/include/linux/mfd/pm8xxx/pm8921-bms.h
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/* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __PM8XXX_BMS_H
#define __PM8XXX_BMS_H
#include <linux/errno.h>
#include <linux/mfd/pm8xxx/batterydata-lib.h>
#define PM8921_BMS_DEV_NAME "pm8921-bms"
struct pm8xxx_bms_core_data {
unsigned int batt_temp_channel;
unsigned int vbat_channel;
unsigned int ref625mv_channel;
unsigned int ref1p25v_channel;
unsigned int batt_id_channel;
};
/**
* struct pm8921_bms_platform_data -
* @batt_type: allows to force chose battery calibration data
* @r_sense_uohm: sense resistor value in (micro Ohms)
* @i_test: current at which the unusable charger cutoff is to be
* calculated or the peak system current (mA)
* @v_cutoff: the loaded voltage at which the battery
* is considered empty(mV)
* @enable_fcc_learning: if set the driver will learn full charge
* capacity of the battery upon end of charge
* @min_fcc_learning_soc: minimum SOC as which CC counting for FCC
* learning can start
* @min_fcc_ocv_pc: minimum PC (lookup(OCV)) at which CC counting
* for FCC learning can start
* @max_fcc_learning_samples: Maximum number of FCC measurement cycles to be
* used for FCC update
* @normal_voltage_calc_ms: The period of soc calculation in ms when battery
* voltage higher than cutoff voltage
* @low_voltage_calc_ms: The period of soc calculation in ms when battery
* voltage is near cutoff voltage
* @disable_flat_portion_ocv: feature to disable ocv updates while in sleep
* @ocv_dis_high_soc: the high soc percent when ocv should be disabled
* @ocv_dis_low_soc: the low soc percent when ocv should be enabled
* @low_voltage_detect: feature to enable 0 SOC reporting on low volatge
* @vbatt_cutoff_retries: number of tries before we report a 0 SOC
* @high_ocv_correction_limit_uv: the max amount of OCV corrections
* allowed when ocv is high
* (higher than 3.8V)
* @low_ocv_correction_limit_uv: the max amount of OCV corrections
* allowed when ocv is low
* (lower or equal to 3.8V)
* @hold_soc_est: the min est soc below which the calculated soc
* is allowed to go to 0%
*/
struct pm8921_bms_platform_data {
struct pm8xxx_bms_core_data bms_cdata;
enum battery_type battery_type;
int r_sense_uohm;
unsigned int i_test;
unsigned int v_cutoff;
unsigned int max_voltage_uv;
unsigned int rconn_mohm;
unsigned int alarm_low_mv;
unsigned int alarm_high_mv;
int enable_fcc_learning;
int min_fcc_learning_soc;
int min_fcc_ocv_pc;
int max_fcc_learning_samples;
int shutdown_soc_valid_limit;
int ignore_shutdown_soc;
int adjust_soc_low_threshold;
int chg_term_ua;
int normal_voltage_calc_ms;
int low_voltage_calc_ms;
int disable_flat_portion_ocv;
int ocv_dis_high_soc;
int ocv_dis_low_soc;
int low_voltage_detect;
int vbatt_cutoff_retries;
int high_ocv_correction_limit_uv;
int low_ocv_correction_limit_uv;
int hold_soc_est;
};
#if defined(CONFIG_PM8921_BMS) || defined(CONFIG_PM8921_BMS_MODULE)
/**
* pm8921_bms_get_vsense_avg - return the voltage across the sense
* resitor in microvolts
* @result: The pointer where the voltage will be updated. A -ve
* result means that the current is flowing in
* the battery - during battery charging
*
* RETURNS: Error code if there was a problem reading vsense, Zero otherwise
* The result won't be updated in case of an error.
*
*
*/
int pm8921_bms_get_vsense_avg(int *result);
/**
* pm8921_bms_get_battery_current - return the battery current based on vsense
* resitor in microamperes
* @result: The pointer where the voltage will be updated. A -ve
* result means that the current is flowing in
* the battery - during battery charging
*
* RETURNS: Error code if there was a problem reading vsense, Zero otherwise
* The result won't be updated in case of an error.
*
*/
int pm8921_bms_get_battery_current(int *result);
/**
* pm8921_bms_get_percent_charge - returns the current battery charge in percent
*
*/
int pm8921_bms_get_percent_charge(void);
/**
* pm8921_bms_get_fcc - returns fcc in mAh of the battery depending on its age
* and temperature
*
*/
int pm8921_bms_get_fcc(void);
/**
* pm8921_bms_charging_began - function to notify the bms driver that charging
* has started. Used by the bms driver to keep
* track of chargecycles
*/
void pm8921_bms_charging_began(void);
/**
* pm8921_bms_charging_end - function to notify the bms driver that charging
* has stopped. Used by the bms driver to keep
* track of chargecycles
*/
void pm8921_bms_charging_end(int is_battery_full);
void pm8921_bms_calibrate_hkadc(void);
/**
* pm8921_bms_get_simultaneous_battery_voltage_and_current
* - function to take simultaneous vbat and vsense readings
* this puts the bms in override mode but keeps coulumb couting
* on. Useful when ir compensation needs to be implemented
*/
int pm8921_bms_get_simultaneous_battery_voltage_and_current(int *ibat_ua,
int *vbat_uv);
/**
* pm8921_bms_get_current_max
* - function to get the max current that can be drawn from
* the battery before it dips below the min allowed voltage
*/
int pm8921_bms_get_current_max(void);
/**
* pm8921_bms_invalidate_shutdown_soc - function to notify the bms driver that
* the battery was replaced between reboot
* and so it should not use the shutdown
* soc stored in a coincell backed register
*/
void pm8921_bms_invalidate_shutdown_soc(void);
/**
* pm8921_bms_cc_uah - function to get the coulomb counter based charge. Note
* that the coulomb counter are reset when the current
* consumption is low (below 8mA for more than 5 minutes),
* This will lead in a very low coulomb counter charge
* value upon wakeup from sleep.
*/
int pm8921_bms_cc_uah(int *cc_uah);
/**
* pm8921_bms_battery_removed - function to be called to tell the bms that
* the battery is removed. The bms resets its internal
* history data used to report soc.
*/
void pm8921_bms_battery_removed(void);
/**
* pm8921_bms_battery_inseted - function to be called to tell the bms that
* the battery was inserted. The bms initiates calculations
* for reporting soc.
*/
void pm8921_bms_battery_inserted(void);
#else
static inline int pm8921_bms_get_vsense_avg(int *result)
{
return -ENXIO;
}
static inline int pm8921_bms_get_battery_current(int *result)
{
return -ENXIO;
}
static inline int pm8921_bms_get_percent_charge(void)
{
return -ENXIO;
}
static inline int pm8921_bms_get_fcc(void)
{
return -ENXIO;
}
static inline void pm8921_bms_charging_began(void)
{
}
static inline void pm8921_bms_charging_end(int is_battery_full)
{
}
static inline void pm8921_bms_calibrate_hkadc(void)
{
}
static inline int pm8921_bms_get_simultaneous_battery_voltage_and_current(
int *ibat_ua, int *vbat_uv)
{
return -ENXIO;
}
static inline int pm8921_bms_get_rbatt(void)
{
return -EINVAL;
}
static inline void pm8921_bms_invalidate_shutdown_soc(void)
{
}
static inline int pm8921_bms_cc_uah(int *cc_uah)
{
return -ENXIO;
}
static inline int pm8921_bms_get_current_max(void)
{
return -ENXIO;
}
static inline void pm8921_bms_battery_removed(void) {}
static inline void pm8921_bms_battery_inserted(void) {}
#endif
#endif
kernel/include/linux/mfd/pm8xxx/pm8921-charger.h
+393
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/* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __PM8XXX_CHARGER_H
#define __PM8XXX_CHARGER_H
#include <linux/errno.h>
#include <linux/power_supply.h>
#define PM8921_CHARGER_DEV_NAME "pm8921-charger"
struct pm8xxx_charger_core_data {
unsigned int vbat_channel;
unsigned int batt_temp_channel;
unsigned int batt_id_channel;
};
enum pm8921_chg_cold_thr {
PM_SMBC_BATT_TEMP_COLD_THR__LOW,
PM_SMBC_BATT_TEMP_COLD_THR__HIGH
};
enum pm8921_chg_hot_thr {
PM_SMBC_BATT_TEMP_HOT_THR__LOW,
PM_SMBC_BATT_TEMP_HOT_THR__HIGH
};
enum pm8921_usb_ov_threshold {
PM_USB_OV_5P5V,
PM_USB_OV_6V,
PM_USB_OV_6P5V,
PM_USB_OV_7V,
};
enum pm8921_usb_debounce_time {
PM_USB_BYPASS_DEBOUNCER,
PM_USB_DEBOUNCE_20P5MS,
PM_USB_DEBOUNCE_40P5MS,
PM_USB_DEBOUNCE_80P5MS,
};
enum pm8921_chg_led_src_config {
LED_SRC_GND,
LED_SRC_VPH_PWR,
LED_SRC_5V,
LED_SRC_MIN_VPH_5V,
LED_SRC_BYPASS,
};
/**
* struct pm8921_charger_platform_data -
* valid range 4 to 512 min. PON default 120 min
* @ttrkl_time: max trckl charging time in minutes
* valid range 1 to 64 mins. PON default 15 min
* @update_time: how often the userland be updated of the charging (msec)
* @alarm_low_mv: the voltage (mV) when low battery alarm is triggered
* @alarm_high_mv: the voltage (mV) when high battery alarm is triggered
* @max_voltage: the max voltage (mV) the battery should be charged up to
* @min_voltage: the voltage (mV) where charging method switches from
* trickle to fast. This is also the minimum voltage the
* system operates at
* @uvd_thresh_voltage: the USB falling UVD threshold (mV) (PM8917 only)
* @safe_current_ma: The upper limit of current allowed to be pushed in
* battery. This ends up writing in a one time
* programmable register.
* @resume_voltage_delta: the (mV) drop to wait for before resume charging
* after the battery has been fully charged
* @resume_charge_percent: the % SOC the charger will drop to after the
* battery is fully charged before resuming
* charging.
* @term_current: the charger current (mA) at which EOC happens
* @cool_temp: the temperature (degC) at which the battery is
* considered cool charging current and voltage is reduced.
* Use INT_MIN to indicate not valid.
* @warm_temp: the temperature (degC) at which the battery is
* considered warm charging current and voltage is reduced
* Use INT_MIN to indicate not valid.
* @temp_check_period: The polling interval in seconds to check battery
* temeperature if it has gone to cool or warm temperature
* area
* @max_bat_chg_current: Max charge current of the battery in mA
* Usually 70% of full charge capacity
* @usb_max_current: Maximum USB current in mA
* @cool_bat_chg_current: chg current (mA) when the battery is cool
* @warm_bat_chg_current: chg current (mA) when the battery is warm
* @cool_bat_voltage: chg voltage (mV) when the battery is cool
* @warm_bat_voltage: chg voltage (mV) when the battery is warm
* @get_batt_capacity_percent:
* a board specific function to return battery
* capacity. If null - a default one will be used
* @has_dc_supply: report DC online if this bit is set in board file
* @trkl_voltage: the trkl voltage in (mV) below which hw controlled
* trkl charging happens with linear charger
* @weak_voltage: the weak voltage (mV) below which hw controlled
* trkl charging happens with switching mode charger
* @trkl_current: the trkl current in (mA) to use for trkl charging phase
* @weak_current: the weak current in (mA) to use for weak charging phase
* @vin_min: the input voltage regulation point (mV) - if the
* voltage falls below this, the charger reduces charge
* current or stop charging temporarily
* @thermal_mitigation: the array of charge currents to use as temperature
* increases
* @thermal_levels: the number of thermal mitigation levels supported
* @cold_thr: if high battery will be cold when VBAT_THERM goes above
* 80% of VREF_THERM (typically 1.8volts), if low the
* battery will be considered cold if VBAT_THERM goes above
* 70% of VREF_THERM. Hardware defaults to low.
* @hot_thr: if high the battery will be considered hot when the
* VBAT_THERM goes below 35% of VREF_THERM, if low the
* battery will be considered hot when VBAT_THERM goes
* below 25% of VREF_THERM. Hardware defaults to low.
* @rconn_mohm: resistance in milliOhm from the vbat sense to ground
* with the battery terminals shorted. This indicates
* resistance of the pads, connectors, battery terminals
* and rsense.
* @led_src_config: Power source for anode of charger indicator LED.
* @btc_override: disable the comparators for conifugrations where a
* suitable voltages don't appear on vbatt therm line
* for the charger to detect battery is either cold / hot.
* @btc_override_cold_degc: Temperature in degCelcius when the battery is
* deemed cold and charging never happens. Used
* only if btc_override = 1
* @btc_override_hot_degc: Temperature in degCelcius when the battery is
* deemed hot and charging never happens. Used
* only if btc_override = 1
* @btc_delay_ms: Delay in milliseconds to monitor the battery temperature
* while charging when btc_override = 1
* @btc_panic_if_cant_stop_chg: flag to instruct the driver to panic if the
* driver couldn't stop charging when battery
* temperature is out of bounds. Used only if
* btc_override = 1
* stop_chg_upon_expiry: flag to indicate that the charger driver should
* stop charging the battery when the safety timer
* expires. If not set the charger driver will
* restart charging upon expiry.
*/
struct pm8921_charger_platform_data {
struct pm8xxx_charger_core_data charger_cdata;
unsigned int ttrkl_time;
unsigned int update_time;
unsigned int max_voltage;
unsigned int min_voltage;
unsigned int uvd_thresh_voltage;
unsigned int safe_current_ma;
unsigned int alarm_low_mv;
unsigned int alarm_high_mv;
unsigned int resume_voltage_delta;
int resume_charge_percent;
unsigned int term_current;
int cool_temp;
int warm_temp;
unsigned int temp_check_period;
unsigned int max_bat_chg_current;
unsigned int usb_max_current;
unsigned int cool_bat_chg_current;
unsigned int warm_bat_chg_current;
unsigned int cool_bat_voltage;
unsigned int warm_bat_voltage;
int hysteresis_temp;
unsigned int (*get_batt_capacity_percent) (void);
int64_t batt_id_min;
int64_t batt_id_max;
bool keep_btm_on_suspend;
bool has_dc_supply;
int trkl_voltage;
int weak_voltage;
int trkl_current;
int weak_current;
int vin_min;
int *thermal_mitigation;
int thermal_levels;
enum pm8921_chg_cold_thr cold_thr;
enum pm8921_chg_hot_thr hot_thr;
int rconn_mohm;
enum pm8921_chg_led_src_config led_src_config;
int battery_less_hardware;
int btc_override;
int btc_override_cold_degc;
int btc_override_hot_degc;
int btc_delay_ms;
int btc_panic_if_cant_stop_chg;
int stop_chg_upon_expiry;
bool disable_chg_rmvl_wrkarnd;
};
enum pm8921_charger_source {
PM8921_CHG_SRC_NONE,
PM8921_CHG_SRC_USB,
PM8921_CHG_SRC_DC,
};
#if defined(CONFIG_PM8921_CHARGER) || defined(CONFIG_PM8921_CHARGER_MODULE)
void pm8921_charger_vbus_draw(unsigned int mA);
int pm8921_charger_register_vbus_sn(void (*callback)(int));
void pm8921_charger_unregister_vbus_sn(void (*callback)(int));
/**
* pm8921_is_usb_chg_plugged_in - is usb plugged in
*
* if usb is under voltage or over voltage this will return false
*/
int pm8921_is_usb_chg_plugged_in(void);
/**
* pm8921_is_dc_chg_plugged_in - is dc plugged in
*
* if dc is under voltage or over voltage this will return false
*/
int pm8921_is_dc_chg_plugged_in(void);
/**
* pm8921_is_battery_present -
*
* returns if the pmic sees the battery present
*/
int pm8921_is_battery_present(void);
/**
* pm8921_set_max_battery_charge_current - set max battery chg current
*
* @ma: max charge current in milliAmperes
*/
int pm8921_set_max_battery_charge_current(int ma);
/**
* pm8921_disable_input_current_limt - disable input current limit
*
* @disable: disable input curren_limit limit
*
* Disabling the charge current limit causes current
* current limits to have no monitoring. An adequate charger
* capable of supplying high current while sustaining VIN_MIN
* is required if input current limiting is disabled.
*/
int pm8921_disable_input_current_limit(bool disable);
/**
* pm8921_set_usb_power_supply_type - set USB supply type
*
* @type: power_supply_type enum
*
* This api lets one set a specific usb power_supply_type.
* USB drivers can distinguish between types of USB connections
* and set the appropriate type for the USB supply.
*/
int pm8921_set_usb_power_supply_type(enum power_supply_type type);
/**
* pm8921_disable_source_current - disable drawing current from source
* @disable: true to disable current drawing from source false otherwise
*
* This function will stop all charging activities and disable any current
* drawn from the charger. The battery provides the system current.
*/
int pm8921_disable_source_current(bool disable);
/**
* pm8921_regulate_input_voltage -
* @voltage: voltage in millivolts to regulate
* allowable values are from 4300mV to 6500mV
*/
int pm8921_regulate_input_voltage(int voltage);
/**
* pm8921_is_battery_charging -
* @source: when the battery is charging the source is updated to reflect which
* charger, usb or dc, is charging the battery.
*
* RETURNS: bool, whether the battery is being charged or not
*/
bool pm8921_is_battery_charging(int *source);
/**
* pm8921_batt_temperature - get battery temp in degC
*
*/
int pm8921_batt_temperature(void);
/**
* pm8921_usb_ovp_set_threshold -
* Set the usb threshold as defined in by
* enum usb_ov_threshold
*/
int pm8921_usb_ovp_set_threshold(enum pm8921_usb_ov_threshold ov);
/**
* pm8921_usb_ovp_set_hystersis -
* @ms: the debounce time enum
*
* Sets the debounce time for usb insertion/removal detection
*
*/
int pm8921_usb_ovp_set_hystersis(enum pm8921_usb_debounce_time ms);
/**
* pm8921_usb_ovp_disable -
*
* when disabled there is no over voltage protection. The usb voltage is
* fed to the pmic as is. This should be disabled only when there is
* over voltage protection circuitry present outside the pmic chip.
*
*/
int pm8921_usb_ovp_disable(int disable);
/**
* pm8921_is_batfet_closed - battery fet status
*
* Returns 1 if batfet is closed 0 if open. On configurations without
* batfet this will return 0.
*/
int pm8921_is_batfet_closed(void);
#else
static inline void pm8921_charger_vbus_draw(unsigned int mA)
{
}
static inline int pm8921_charger_register_vbus_sn(void (*callback)(int))
{
return -ENXIO;
}
static inline void pm8921_charger_unregister_vbus_sn(void (*callback)(int))
{
}
static inline int pm8921_is_usb_chg_plugged_in(void)
{
return -ENXIO;
}
static inline int pm8921_is_dc_chg_plugged_in(void)
{
return -ENXIO;
}
static inline int pm8921_is_battery_present(void)
{
return -ENXIO;
}
static inline int pm8917_set_under_voltage_detection_threshold(int mv)
{
return -ENXIO;
}
static inline int pm8921_disable_input_current_limit(bool disable)
{
return -ENXIO;
}
static inline int pm8921_set_usb_power_supply_type(enum power_supply_type type)
{
return -ENXIO;
}
static inline int pm8921_set_max_battery_charge_current(int ma)
{
return -ENXIO;
}
static inline int pm8921_disable_source_current(bool disable)
{
return -ENXIO;
}
static inline int pm8921_regulate_input_voltage(int voltage)
{
return -ENXIO;
}
static inline bool pm8921_is_battery_charging(int *source)
{
*source = PM8921_CHG_SRC_NONE;
return 0;
}
static inline int pm8921_batt_temperature(void)
{
return -ENXIO;
}
static inline int pm8921_usb_ovp_set_threshold(enum pm8921_usb_ov_threshold ov)
{
return -ENXIO;
}
static inline int pm8921_usb_ovp_set_hystersis(enum pm8921_usb_debounce_time ms)
{
return -ENXIO;
}
static inline int pm8921_usb_ovp_disable(int disable)
{
return -ENXIO;
}
static inline int pm8921_is_batfet_closed(void)
{
return 1;
}
#endif
#endif
kernel/include/linux/mfd/pm8xxx/pm8921.h
+147
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/*
* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Qualcomm PMIC 8921 driver header file
*
*/
#ifndef __MFD_PM8921_H
#define __MFD_PM8921_H
#include <linux/mfd/pm8xxx/irq.h>
#include <linux/mfd/pm8xxx/gpio.h>
#include <linux/mfd/pm8xxx/mpp.h>
#include <linux/mfd/pm8xxx/rtc.h>
#include <linux/mfd/pm8xxx/pwm.h>
#include <linux/mfd/pm8xxx/misc.h>
#include <linux/mfd/pm8xxx/tm.h>
#include <linux/mfd/pm8xxx/batt-alarm.h>
#include <linux/input/pmic8xxx-pwrkey.h>
#include <linux/input/pmic8xxx-keypad.h>
#include <linux/regulator/pm8xxx-regulator.h>
#include <linux/mfd/pm8xxx/pm8921-charger.h>
#include <linux/mfd/pm8xxx/pm8xxx-adc.h>
#include <linux/mfd/pm8xxx/pm8921-bms.h>
#include <linux/leds-pm8xxx.h>
#include <linux/mfd/pm8xxx/vibrator.h>
#include <linux/mfd/pm8xxx/ccadc.h>
#define PM8921_NR_IRQS 256
#define PM8921_NR_GPIOS 44
#define PM8917_NR_GPIOS 38
#define PM8921_NR_MPPS 12
#define PM8917_NR_MPPS 10
#define PM8921_GPIO_BLOCK_START 24
#define PM8921_MPP_BLOCK_START 16
#define PM8921_IRQ_BLOCK_BIT(block, bit) ((block) * 8 + (bit))
/* GPIOs and MPPs [1,N] */
#define PM8921_GPIO_IRQ(base, gpio) ((base) + \
PM8921_IRQ_BLOCK_BIT(PM8921_GPIO_BLOCK_START, (gpio)-1))
#define PM8921_MPP_IRQ(base, mpp) ((base) + \
PM8921_IRQ_BLOCK_BIT(PM8921_MPP_BLOCK_START, (mpp)-1))
/* PMIC Interrupts */
#define PM8921_RTC_ALARM_IRQ PM8921_IRQ_BLOCK_BIT(4, 7)
#define PM8921_BATT_ALARM_IRQ PM8921_IRQ_BLOCK_BIT(5, 6)
#define PM8921_PWRKEY_REL_IRQ PM8921_IRQ_BLOCK_BIT(6, 2)
#define PM8921_PWRKEY_PRESS_IRQ PM8921_IRQ_BLOCK_BIT(6, 3)
#define PM8921_KEYPAD_IRQ PM8921_IRQ_BLOCK_BIT(9, 2)
#define PM8921_KEYSTUCK_IRQ PM8921_IRQ_BLOCK_BIT(9, 3)
#define PM8921_ADC_EOC_USR_IRQ PM8921_IRQ_BLOCK_BIT(9, 6)
#define PM8921_ADC_BATT_TEMP_WARM_IRQ PM8921_IRQ_BLOCK_BIT(9, 1)
#define PM8921_ADC_BATT_TEMP_COLD_IRQ PM8921_IRQ_BLOCK_BIT(9, 0)
#define PM8921_USB_ID_IN_IRQ(base) (base + PM8921_IRQ_BLOCK_BIT(6, 1))
#define PM8921_USBIN_VALID_IRQ PM8921_IRQ_BLOCK_BIT(1, 7)
#define PM8921_USBIN_OV_IRQ PM8921_IRQ_BLOCK_BIT(1, 6)
#define PM8921_BATT_INSERTED_IRQ PM8921_IRQ_BLOCK_BIT(1, 5)
#define PM8921_VBATDET_LOW_IRQ PM8921_IRQ_BLOCK_BIT(1, 4)
#define PM8921_USBIN_UV_IRQ PM8921_IRQ_BLOCK_BIT(1, 3)
#define PM8921_VBAT_OV_IRQ PM8921_IRQ_BLOCK_BIT(1, 2)
#define PM8921_CHGWDOG_IRQ PM8921_IRQ_BLOCK_BIT(1, 1)
#define PM8921_VCP_IRQ PM8921_IRQ_BLOCK_BIT(1, 0)
#define PM8921_ATCDONE_IRQ PM8921_IRQ_BLOCK_BIT(2, 7)
#define PM8921_ATCFAIL_IRQ PM8921_IRQ_BLOCK_BIT(2, 6)
#define PM8921_CHGDONE_IRQ PM8921_IRQ_BLOCK_BIT(2, 5)
#define PM8921_CHGFAIL_IRQ PM8921_IRQ_BLOCK_BIT(2, 4)
#define PM8921_CHGSTATE_IRQ PM8921_IRQ_BLOCK_BIT(2, 3)
#define PM8921_LOOP_CHANGE_IRQ PM8921_IRQ_BLOCK_BIT(2, 2)
#define PM8921_FASTCHG_IRQ PM8921_IRQ_BLOCK_BIT(2, 1)
#define PM8921_TRKLCHG_IRQ PM8921_IRQ_BLOCK_BIT(2, 0)
#define PM8921_BATT_REMOVED_IRQ PM8921_IRQ_BLOCK_BIT(3, 7)
#define PM8921_BATTTEMP_HOT_IRQ PM8921_IRQ_BLOCK_BIT(3, 6)
#define PM8921_CHGHOT_IRQ PM8921_IRQ_BLOCK_BIT(3, 5)
#define PM8921_BATTTEMP_COLD_IRQ PM8921_IRQ_BLOCK_BIT(3, 4)
#define PM8921_CHG_GONE_IRQ PM8921_IRQ_BLOCK_BIT(3, 3)
#define PM8921_BAT_TEMP_OK_IRQ PM8921_IRQ_BLOCK_BIT(3, 2)
#define PM8921_COARSE_DET_LOW_IRQ PM8921_IRQ_BLOCK_BIT(3, 1)
#define PM8921_VDD_LOOP_IRQ PM8921_IRQ_BLOCK_BIT(3, 0)
#define PM8921_VREG_OV_IRQ PM8921_IRQ_BLOCK_BIT(5, 7)
#define PM8921_VBATDET_IRQ PM8921_IRQ_BLOCK_BIT(5, 5)
#define PM8921_BATFET_IRQ PM8921_IRQ_BLOCK_BIT(5, 4)
#define PM8921_PSI_IRQ PM8921_IRQ_BLOCK_BIT(5, 3)
#define PM8921_DCIN_VALID_IRQ PM8921_IRQ_BLOCK_BIT(5, 2)
#define PM8921_DCIN_OV_IRQ PM8921_IRQ_BLOCK_BIT(5, 1)
#define PM8921_DCIN_UV_IRQ PM8921_IRQ_BLOCK_BIT(5, 0)
#define PM8921_BMS_SBI_WRITE_OK PM8921_IRQ_BLOCK_BIT(15, 7)
#define PM8921_BMS_CC_THR PM8921_IRQ_BLOCK_BIT(15, 6)
#define PM8921_BMS_VSENSE_THR PM8921_IRQ_BLOCK_BIT(15, 5)
#define PM8921_BMS_VSENSE_FOR_R PM8921_IRQ_BLOCK_BIT(15, 4)
#define PM8921_BMS_OCV_FOR_R PM8921_IRQ_BLOCK_BIT(15, 3)
#define PM8921_BMS_GOOD_OCV PM8921_IRQ_BLOCK_BIT(15, 2)
#define PM8921_BMS_VSENSE_AVG PM8921_IRQ_BLOCK_BIT(15, 1)
#define PM8921_BMS_CCADC_EOC PM8921_IRQ_BLOCK_BIT(15, 0)
#define PM8921_OVERTEMP_IRQ PM8921_IRQ_BLOCK_BIT(4, 2)
#define PM8921_TEMPSTAT_IRQ PM8921_IRQ_BLOCK_BIT(6, 7)
#define PM8921_RESOUT_IRQ PM8921_IRQ_BLOCK_BIT(6, 4)
#define PM8921_USB_OTG_OCP_IRQ PM8921_IRQ_BLOCK_BIT(6, 0)
#define PM8921_LVS7_OCP_IRQ PM8921_IRQ_BLOCK_BIT(13, 7)
#define PM8921_LVS6_OCP_IRQ PM8921_IRQ_BLOCK_BIT(13, 6)
#define PM8921_LVS5_OCP_IRQ PM8921_IRQ_BLOCK_BIT(13, 5)
#define PM8921_LVS4_OCP_IRQ PM8921_IRQ_BLOCK_BIT(13, 4)
#define PM8921_LVS3_OCP_IRQ PM8921_IRQ_BLOCK_BIT(13, 3)
#define PM8921_LVS2_OCP_IRQ PM8921_IRQ_BLOCK_BIT(13, 2)
#define PM8921_LVS1_OCP_IRQ PM8921_IRQ_BLOCK_BIT(13, 1)
#define PM8921_HDMI_MVS_OCP_IRQ PM8921_IRQ_BLOCK_BIT(13, 0)
/* PMIC I/O Resources */
#define PM8921_RTC_BASE 0x11D
struct pm8921_platform_data {
int irq_base;
struct pm8xxx_irq_platform_data *irq_pdata;
struct pm8xxx_gpio_platform_data *gpio_pdata;
struct pm8xxx_mpp_platform_data *mpp_pdata;
struct pm8xxx_rtc_platform_data *rtc_pdata;
struct pm8xxx_pwrkey_platform_data *pwrkey_pdata;
struct pm8xxx_keypad_platform_data *keypad_pdata;
struct pm8921_charger_platform_data *charger_pdata;
struct pm8921_bms_platform_data *bms_pdata;
struct pm8xxx_misc_platform_data *misc_pdata;
struct pm8xxx_regulator_platform_data *regulator_pdatas;
int num_regulators;
struct pm8xxx_adc_platform_data *adc_pdata;
struct pm8xxx_led_platform_data *leds_pdata;
struct pm8xxx_vibrator_platform_data *vibrator_pdata;
struct pm8xxx_ccadc_platform_data *ccadc_pdata;
struct pm8xxx_pwm_platform_data *pwm_pdata;
};
#endif
kernel/include/linux/mfd/pm8xxx/pm8xxx-adc.h
+604
View File
@@ -0,0 +1,604 @@
/*
* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Qualcomm PMIC 8921/8018 ADC driver header file
*
*/
#ifndef __PM8XXX_ADC_H
#define __PM8XXX_ADC_H
#include <linux/kernel.h>
#include <linux/list.h>
/**
* enum pm8xxx_adc_channels - PM8XXX AMUX arbiter channels
* %CHANNEL_VCOIN: Backup voltage for certain register set
* %CHANNEL_VBAT: Battery voltage
* %CHANNEL_DCIN: Charger input voltage without internal OVP
* %CHANNEL_ICHG: Charge-current monitor
* %CHANNEL_VPH_PWR: Main system power
* %CHANNEL_IBAT: Battery charge current
* %CHANNEL_MPP_1: 16:1 pre-mux unity scale MPP input
* %CHANNEL_MPP_2: 16:1 pre-mux 1/3 scale MPP input
* %CHANNEL_BATT_THERM: Battery temperature
* %CHANNEL_BATT_ID: Battery detection
* %CHANNEL_USBIN: Charger input voltage with internal OVP
* %CHANNEL_DIE_TEMP: Pmic_die temperature
* %CHANNEL_625MV: 625mv reference channel
* %CHANNEL_125V: 1.25v reference channel
* %CHANNEL_CHG_TEMP: Charger temperature
* %CHANNEL_MUXOFF: Channel to reduce input load on the mux
* %CHANNEL_NONE: Do not use this channel
*/
enum pm8xxx_adc_channels {
CHANNEL_VCOIN = 0,
CHANNEL_VBAT,
CHANNEL_DCIN,
CHANNEL_ICHG,
CHANNEL_VPH_PWR,
CHANNEL_IBAT,
CHANNEL_MPP_1,
CHANNEL_MPP_2,
CHANNEL_BATT_THERM,
/* PM8018 ADC Arbiter uses a single channel on AMUX8
* to read either Batt_id or Batt_therm.
*/
CHANNEL_BATT_ID_THERM = CHANNEL_BATT_THERM,
CHANNEL_BATT_ID,
CHANNEL_USBIN,
CHANNEL_DIE_TEMP,
CHANNEL_625MV,
CHANNEL_125V,
CHANNEL_CHG_TEMP,
CHANNEL_MUXOFF,
CHANNEL_NONE,
ADC_MPP_1_ATEST_8 = 20,
ADC_MPP_1_USB_SNS_DIV20,
ADC_MPP_1_DCIN_SNS_DIV20,
ADC_MPP_1_AMUX3,
ADC_MPP_1_AMUX4,
ADC_MPP_1_AMUX5,
ADC_MPP_1_AMUX6,
ADC_MPP_1_AMUX7,
ADC_MPP_1_AMUX8,
ADC_MPP_1_ATEST_1,
ADC_MPP_1_ATEST_2,
ADC_MPP_1_ATEST_3,
ADC_MPP_1_ATEST_4,
ADC_MPP_1_ATEST_5,
ADC_MPP_1_ATEST_6,
ADC_MPP_1_ATEST_7,
ADC_MPP_2_ATEST_8 = 40,
ADC_MPP_2_USB_SNS_DIV20,
ADC_MPP_2_DCIN_SNS_DIV20,
ADC_MPP_2_AMUX3,
ADC_MPP_2_AMUX4,
ADC_MPP_2_AMUX5,
ADC_MPP_2_AMUX6,
ADC_MPP_2_AMUX7,
ADC_MPP_2_AMUX8,
ADC_MPP_2_ATEST_1,
ADC_MPP_2_ATEST_2,
ADC_MPP_2_ATEST_3,
ADC_MPP_2_ATEST_4,
ADC_MPP_2_ATEST_5,
ADC_MPP_2_ATEST_6,
ADC_MPP_2_ATEST_7,
ADC_CHANNEL_MAX_NUM,
};
#define PM8XXX_ADC_PMIC_0 0x0
#define PM8XXX_CHANNEL_ADC_625_UV 625000
#define PM8XXX_CHANNEL_MPP_SCALE1_IDX 20
#define PM8XXX_CHANNEL_MPP_SCALE3_IDX 40
#define PM8XXX_AMUX_MPP_3 0x3
#define PM8XXX_AMUX_MPP_4 0x4
#define PM8XXX_AMUX_MPP_5 0x5
#define PM8XXX_AMUX_MPP_6 0x6
#define PM8XXX_AMUX_MPP_7 0x7
#define PM8XXX_AMUX_MPP_8 0x8
#define PM8XXX_ADC_DEV_NAME "pm8xxx-adc"
/**
* enum pm8xxx_adc_decimation_type - Sampling rate supported
* %ADC_DECIMATION_TYPE1: 512
* %ADC_DECIMATION_TYPE2: 1K
* %ADC_DECIMATION_TYPE3: 2K
* %ADC_DECIMATION_TYPE4: 4k
* %ADC_DECIMATION_NONE: Do not use this Sampling type
*
* The Sampling rate is specific to each channel of the PM8XXX ADC arbiter.
*/
enum pm8xxx_adc_decimation_type {
ADC_DECIMATION_TYPE1 = 0,
ADC_DECIMATION_TYPE2,
ADC_DECIMATION_TYPE3,
ADC_DECIMATION_TYPE4,
ADC_DECIMATION_NONE,
};
/**
* enum pm8xxx_adc_calib_type - PM8XXX ADC Calibration type
* %ADC_CALIB_ABSOLUTE: Use 625mV and 1.25V reference channels
* %ADC_CALIB_RATIOMETRIC: Use reference Voltage/GND
* %ADC_CALIB_CONFIG_NONE: Do not use this calibration type
*
* Use the input reference voltage depending on the calibration type
* to calcluate the offset and gain parameters. The calibration is
* specific to each channel of the PM8XXX ADC.
*/
enum pm8xxx_adc_calib_type {
ADC_CALIB_ABSOLUTE = 0,
ADC_CALIB_RATIOMETRIC,
ADC_CALIB_NONE,
};
/**
* enum pm8xxx_adc_channel_scaling_param - pre-scaling AMUX ratio
* %CHAN_PATH_SCALING1: ratio of {1, 1}
* %CHAN_PATH_SCALING2: ratio of {1, 3}
* %CHAN_PATH_SCALING3: ratio of {1, 4}
* %CHAN_PATH_SCALING4: ratio of {1, 6}
* %CHAN_PATH_NONE: Do not use this pre-scaling ratio type
*
* The pre-scaling is applied for signals to be within the voltage range
* of the ADC.
*/
enum pm8xxx_adc_channel_scaling_param {
CHAN_PATH_SCALING1 = 0,
CHAN_PATH_SCALING2,
CHAN_PATH_SCALING3,
CHAN_PATH_SCALING4,
CHAN_PATH_SCALING_NONE,
};
/**
* enum pm8xxx_adc_amux_input_rsv - HK/XOADC reference voltage
* %AMUX_RSV0: XO_IN/XOADC_GND
* %AMUX_RSV1: PMIC_IN/XOADC_GND
* %AMUX_RSV2: PMIC_IN/BMS_CSP
* %AMUX_RSV3: not used
* %AMUX_RSV4: XOADC_GND/XOADC_GND
* %AMUX_RSV5: XOADC_VREF/XOADC_GND
* %AMUX_NONE: Do not use this input reference voltage selection
*/
enum pm8xxx_adc_amux_input_rsv {
AMUX_RSV0 = 0,
AMUX_RSV1,
AMUX_RSV2,
AMUX_RSV3,
AMUX_RSV4,
AMUX_RSV5,
AMUX_NONE,
};
/**
* enum pm8xxx_adc_premux_mpp_scale_type - 16:1 pre-mux scale ratio
* %PREMUX_MPP_SCALE_0: No scaling to the input signal
* %PREMUX_MPP_SCALE_1: Unity scaling selected by the user for MPP input
* %PREMUX_MPP_SCALE_1_DIV3: 1/3 pre-scale to the input MPP signal
* %PREMUX_MPP_NONE: Do not use this pre-scale mpp type
*/
enum pm8xxx_adc_premux_mpp_scale_type {
PREMUX_MPP_SCALE_0 = 0,
PREMUX_MPP_SCALE_1,
PREMUX_MPP_SCALE_1_DIV3,
PREMUX_MPP_NONE,
};
/**
* enum pm8xxx_adc_scale_fn_type - Scaling function for pm8921 pre calibrated
* digital data relative to ADC reference
* %ADC_SCALE_DEFAULT: Default scaling to convert raw adc code to voltage
* %ADC_SCALE_BATT_THERM: Conversion to temperature based on btm parameters
* %ADC_SCALE_PMIC_THERM: Returns result in milli degree's Centigrade
* %ADC_SCALE_XTERN_CHGR_CUR: Returns current across 0.1 ohm resistor
* %ADC_SCALE_XOTHERM: Returns XO thermistor voltage in degree's Centigrade
* %ADC_SCALE_NONE: Do not use this scaling type
*/
enum pm8xxx_adc_scale_fn_type {
ADC_SCALE_DEFAULT = 0,
ADC_SCALE_BATT_THERM,
ADC_SCALE_PA_THERM,
ADC_SCALE_PMIC_THERM,
ADC_SCALE_XOTHERM,
ADC_SCALE_NONE,
};
/**
* struct pm8xxx_adc_linear_graph - Represent ADC characteristics
* @dy: Numerator slope to calculate the gain
* @dx: Denominator slope to calculate the gain
* @adc_vref: A/D word of the voltage reference used for the channel
* @adc_gnd: A/D word of the ground reference used for the channel
*
* Each ADC device has different offset and gain parameters which are computed
* to calibrate the device.
*/
struct pm8xxx_adc_linear_graph {
int64_t dy;
int64_t dx;
int64_t adc_vref;
int64_t adc_gnd;
};
/**
* struct pm8xxx_adc_map_pt - Map the graph representation for ADC channel
* @x: Represent the ADC digitized code
* @y: Represent the physical data which can be temperature, voltage,
* resistance
*/
struct pm8xxx_adc_map_pt {
int32_t x;
int32_t y;
};
/**
* struct pm8xxx_adc_scaling_ratio - Represent scaling ratio for adc input
* @num: Numerator scaling parameter
* @den: Denominator scaling parameter
*/
struct pm8xxx_adc_scaling_ratio {
int32_t num;
int32_t den;
};
/**
* struct pm8xxx_adc_properties - Represent the ADC properties
* @adc_reference: Reference voltage for PM8XXX ADC
* @bitresolution: ADC bit resolution for PM8XXX ADC
* @biploar: Polarity for PM8XXX ADC
*/
struct pm8xxx_adc_properties {
uint32_t adc_vdd_reference;
uint32_t bitresolution;
bool bipolar;
};
/**
* struct pm8xxx_adc_chan_properties - Represent channel properties of the ADC
* @offset_gain_numerator: The inverse numerator of the gain applied to the
* input channel
* @offset_gain_denominator: The inverse denominator of the gain applied to the
* input channel
* @adc_graph: ADC graph for the channel of struct type pm8xxx_adc_linear_graph
*/
struct pm8xxx_adc_chan_properties {
uint32_t offset_gain_numerator;
uint32_t offset_gain_denominator;
struct pm8xxx_adc_linear_graph adc_graph[2];
};
/**
* struct pm8xxx_adc_chan_result - Represent the result of the PM8XXX ADC
* @chan: The channel number of the requested conversion
* @adc_code: The pre-calibrated digital output of a given ADC relative to the
* the ADC reference
* @measurement: In units specific for a given ADC; most ADC uses reference
* voltage but some ADC uses reference current. This measurement
* here is a number relative to a reference of a given ADC
* @physical: The data meaningful for each individual channel whether it is
* voltage, current, temperature, etc.
* All voltage units are represented in micro - volts.
* -Battery temperature units are represented as 0.1 DegC
* -PA Therm temperature units are represented as DegC
* -PMIC Die temperature units are represented as 0.001 DegC
*/
struct pm8xxx_adc_chan_result {
uint32_t chan;
int32_t adc_code;
int64_t measurement;
int64_t physical;
};
#if defined(CONFIG_SENSORS_PM8XXX_ADC) \
|| defined(CONFIG_SENSORS_PM8XXX_ADC_MODULE)
/**
* pm8xxx_adc_scale_default() - Scales the pre-calibrated digital output
* of an ADC to the ADC reference and compensates for the
* gain and offset.
* @adc_code: pre-calibrated digital ouput of the ADC.
* @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
* reference voltage.
* @chan_prop: individual channel properties to compensate the i/p scaling,
* slope and offset.
* @chan_rslt: Physical result to be stored.
*/
int32_t pm8xxx_adc_scale_default(int32_t adc_code,
const struct pm8xxx_adc_properties *adc_prop,
const struct pm8xxx_adc_chan_properties *chan_prop,
struct pm8xxx_adc_chan_result *chan_rslt);
/**
* pm8xxx_adc_scale_tdkntcg_therm() - Scales the pre-calibrated digital output
* of an ADC to the ADC reference and compensates for the
* gain and offset. Returns the temperature of the xo therm in mili
degC.
* @adc_code: pre-calibrated digital ouput of the ADC.
* @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
* reference voltage.
* @chan_prop: individual channel properties to compensate the i/p scaling,
* slope and offset.
* @chan_rslt: physical result to be stored.
*/
int32_t pm8xxx_adc_tdkntcg_therm(int32_t adc_code,
const struct pm8xxx_adc_properties *adc_prop,
const struct pm8xxx_adc_chan_properties *chan_prop,
struct pm8xxx_adc_chan_result *chan_rslt);
/**
* pm8xxx_adc_scale_batt_therm() - Scales the pre-calibrated digital output
* of an ADC to the ADC reference and compensates for the
* gain and offset. Returns the temperature in degC.
* @adc_code: pre-calibrated digital ouput of the ADC.
* @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
* reference voltage.
* @chan_prop: individual channel properties to compensate the i/p scaling,
* slope and offset.
* @chan_rslt: physical result to be stored.
*/
int32_t pm8xxx_adc_scale_batt_therm(int32_t adc_code,
const struct pm8xxx_adc_properties *adc_prop,
const struct pm8xxx_adc_chan_properties *chan_prop,
struct pm8xxx_adc_chan_result *chan_rslt);
/**
* pm8xxx_adc_scale_pa_therm() - Scales the pre-calibrated digital output
* of an ADC to the ADC reference and compensates for the
* gain and offset. Returns the temperature in degC.
* @adc_code: pre-calibrated digital ouput of the ADC.
* @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
* reference voltage.
* @chan_prop: individual channel properties to compensate the i/p scaling,
* slope and offset.
* @chan_rslt: physical result to be stored.
*/
int32_t pm8xxx_adc_scale_pa_therm(int32_t adc_code,
const struct pm8xxx_adc_properties *adc_prop,
const struct pm8xxx_adc_chan_properties *chan_prop,
struct pm8xxx_adc_chan_result *chan_rslt);
/**
* pm8xxx_adc_scale_pmic_therm() - Scales the pre-calibrated digital output
* of an ADC to the ADC reference and compensates for the
* gain and offset. Performs the AMUX out as 2mv/K and returns
* the temperature in mili degC.
* @adc_code: pre-calibrated digital ouput of the ADC.
* @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
* reference voltage.
* @chan_prop: individual channel properties to compensate the i/p scaling,
* slope and offset.
* @chan_rslt: physical result to be stored.
*/
int32_t pm8xxx_adc_scale_pmic_therm(int32_t adc_code,
const struct pm8xxx_adc_properties *adc_prop,
const struct pm8xxx_adc_chan_properties *chan_prop,
struct pm8xxx_adc_chan_result *chan_rslt);
/**
* pm8xxx_adc_scale_batt_id() - Scales the pre-calibrated digital output
* of an ADC to the ADC reference and compensates for the
* gain and offset.
* @adc_code: pre-calibrated digital ouput of the ADC.
* @adc_prop: adc properties of the pm8xxx adc such as bit resolution,
* reference voltage.
* @chan_prop: individual channel properties to compensate the i/p scaling,
* slope and offset.
* @chan_rslt: physical result to be stored.
*/
int32_t pm8xxx_adc_scale_batt_id(int32_t adc_code,
const struct pm8xxx_adc_properties *adc_prop,
const struct pm8xxx_adc_chan_properties *chan_prop,
struct pm8xxx_adc_chan_result *chan_rslt);
#else
static inline int32_t pm8xxx_adc_scale_default(int32_t adc_code,
const struct pm8xxx_adc_properties *adc_prop,
const struct pm8xxx_adc_chan_properties *chan_prop,
struct pm8xxx_adc_chan_result *chan_rslt)
{ return -ENXIO; }
static inline int32_t pm8xxx_adc_tdkntcg_therm(int32_t adc_code,
const struct pm8xxx_adc_properties *adc_prop,
const struct pm8xxx_adc_chan_properties *chan_prop,
struct pm8xxx_adc_chan_result *chan_rslt)
{ return -ENXIO; }
static inline int32_t pm8xxx_adc_scale_batt_therm(int32_t adc_code,
const struct pm8xxx_adc_properties *adc_prop,
const struct pm8xxx_adc_chan_properties *chan_prop,
struct pm8xxx_adc_chan_result *chan_rslt)
{ return -ENXIO; }
static inline int32_t pm8xxx_adc_scale_pa_therm(int32_t adc_code,
const struct pm8xxx_adc_properties *adc_prop,
const struct pm8xxx_adc_chan_properties *chan_prop,
struct pm8xxx_adc_chan_result *chan_rslt)
{ return -ENXIO; }
static inline int32_t pm8xxx_adc_scale_pmic_therm(int32_t adc_code,
const struct pm8xxx_adc_properties *adc_prop,
const struct pm8xxx_adc_chan_properties *chan_prop,
struct pm8xxx_adc_chan_result *chan_rslt)
{ return -ENXIO; }
static inline int32_t pm8xxx_adc_scale_batt_id(int32_t adc_code,
const struct pm8xxx_adc_properties *adc_prop,
const struct pm8xxx_adc_chan_properties *chan_prop,
struct pm8xxx_adc_chan_result *chan_rslt)
{ return -ENXIO; }
#endif
/**
* struct pm8xxx_adc_scale_fn - Scaling function prototype
* @chan: Function pointer to one of the scaling functions
* which takes the adc properties, channel properties,
* and returns the physical result
*/
struct pm8xxx_adc_scale_fn {
int32_t (*chan) (int32_t,
const struct pm8xxx_adc_properties *,
const struct pm8xxx_adc_chan_properties *,
struct pm8xxx_adc_chan_result *);
};
/**
* struct pm8xxx_adc_amux - AMUX properties for individual channel
* @name: Channel name
* @channel_name: Channel in integer used from pm8xxx_adc_channels
* @chan_path_prescaling: Channel scaling performed on the input signal
* @adc_rsv: Input reference Voltage/GND selection to the ADC
* @adc_decimation: Sampling rate desired for the channel
* adc_scale_fn: Scaling function to convert to the data meaningful for
* each individual channel whether it is voltage, current,
* temperature, etc and compensates the channel properties
*/
struct pm8xxx_adc_amux {
char *name;
enum pm8xxx_adc_channels channel_name;
enum pm8xxx_adc_channel_scaling_param chan_path_prescaling;
enum pm8xxx_adc_amux_input_rsv adc_rsv;
enum pm8xxx_adc_decimation_type adc_decimation;
enum pm8xxx_adc_scale_fn_type adc_scale_fn;
};
/**
* struct pm8xxx_adc_arb_btm_param - PM8XXX ADC BTM parameters to set threshold
* temperature for client notification
* @low_thr_temp: low temperature threshold request for notification
* @high_thr_temp: high temperature threshold request for notification
* @low_thr_voltage: low temperature converted to voltage by arbiter driver
* @high_thr_voltage: high temperature converted to voltage by arbiter driver
* @interval: Interval period to check for temperature notification
* @btm_warm_fn: Remote function call for warm threshold.
* @btm_cool_fn: Remote function call for cold threshold.
*
* BTM client passes the parameters to be set for the
* temperature threshold notifications. The client is
* responsible for setting the new threshold
* levels once the thresholds are reached
*/
struct pm8xxx_adc_arb_btm_param {
int32_t low_thr_temp;
int32_t high_thr_temp;
uint64_t low_thr_voltage;
uint64_t high_thr_voltage;
int32_t interval;
void (*btm_warm_fn) (bool);
void (*btm_cool_fn) (bool);
};
int32_t pm8xxx_adc_batt_scaler(struct pm8xxx_adc_arb_btm_param *,
const struct pm8xxx_adc_properties *adc_prop,
const struct pm8xxx_adc_chan_properties *chan_prop);
/**
* struct pm8xxx_adc_platform_data - PM8XXX ADC platform data
* @adc_prop: ADC specific parameters, voltage and channel setup
* @adc_channel: Channel properties of the ADC arbiter
* @adc_num_board_channel: Number of channels added in the board file
* @adc_mpp_base: PM8XXX MPP0 base passed from board file. This is used
* to offset the PM8XXX MPP passed to configure the
* the MPP to AMUX mapping.
*/
struct pm8xxx_adc_platform_data {
struct pm8xxx_adc_properties *adc_prop;
struct pm8xxx_adc_amux *adc_channel;
uint32_t adc_num_board_channel;
uint32_t adc_mpp_base;
};
/* Public API */
#if defined(CONFIG_SENSORS_PM8XXX_ADC) \
|| defined(CONFIG_SENSORS_PM8XXX_ADC_MODULE)
/**
* pm8xxx_adc_read() - Performs ADC read on the channel.
* @channel: Input channel to perform the ADC read.
* @result: Structure pointer of type adc_chan_result
* in which the ADC read results are stored.
*/
uint32_t pm8xxx_adc_read(enum pm8xxx_adc_channels channel,
struct pm8xxx_adc_chan_result *result);
/**
* pm8xxx_adc_mpp_config_read() - Configure's the PM8XXX MPP
* to AMUX6 and performs an ADC read.
*
* On PM8921 ADC the MPP needs to first be configured
* as an analog input to the AMUX pre-mux channel before
* issuing a read request. PM8921 MPP 8 is mapped to AMUX8
* and is common between remote processor's.
*
* On PM8018 ADC the MPP is directly connected to the AMUX
* pre-mux. Therefore clients of the PM8018 MPP do not need
* to configure the MPP as an analog input to the pre-mux.
* Clients can directly issue request on the pre-mux AMUX
* channel to read the ADC on the MPP. Clients can directly
* call the pm8xxx_adc_read().
* @mpp_num PM8XXX MPP number to configure to AMUX6.
* @channel: Input channel to perform the ADC read.
* a) 'ADC_MPP_1_AMUX6' if the input voltage is less than 1.8V
* b) 'ADC_MPP_2_AMUX6' if the input voltage is greater then 1.8V
* the input voltage is pre-divided by 3 and passed to the ADC.
* The appropriate scaling function needs to be selected to let
* the driver know a post scaling is required before returning
* the result.
* @result: Structure pointer of type adc_chan_result
* in which the ADC read results are stored.
*/
uint32_t pm8xxx_adc_mpp_config_read(uint32_t mpp_num,
enum pm8xxx_adc_channels channel,
struct pm8xxx_adc_chan_result *result);
/**
* pm8xxx_adc_btm_start() - Configure the BTM registers and start
monitoring the BATT_THERM channel for
threshold warm/cold temperature set
by the Battery client. The btm_start
api is to be used after calling the
pm8xxx_btm_configure() api which sets
the temperature thresholds, interval
and functions to call when warm/cold
events are triggered.
* @param: none.
*/
uint32_t pm8xxx_adc_btm_start(void);
/**
* pm8xxx_adc_btm_end() - Configures the BTM registers to stop
* monitoring the BATT_THERM channel for
* warm/cold events and disables the
* interval timer.
* @param: none.
*/
uint32_t pm8xxx_adc_btm_end(void);
/**
* pm8xxx_adc_btm_configure() - Configures the BATT_THERM channel
* parameters for warm/cold thresholds.
* Sets the interval timer for perfoming
* reading the temperature done by the HW.
* @btm_param: Structure pointer of type adc_arb_btm_param *
* which client provides for threshold warm/cold,
* interval and functions to call when warm/cold
* events are triggered.
*/
uint32_t pm8xxx_adc_btm_configure(struct pm8xxx_adc_arb_btm_param *);
#else
static inline uint32_t pm8xxx_adc_read(uint32_t channel,
struct pm8xxx_adc_chan_result *result)
{ return -ENXIO; }
static inline uint32_t pm8xxx_adc_mpp_config_read(uint32_t mpp_num,
enum pm8xxx_adc_channels channel,
struct pm8xxx_adc_chan_result *result)
{ return -ENXIO; }
static inline uint32_t pm8xxx_adc_btm_start(void)
{ return -ENXIO; }
static inline uint32_t pm8xxx_adc_btm_end(void)
{ return -ENXIO; }
static inline uint32_t pm8xxx_adc_btm_configure(
struct pm8xxx_adc_arb_btm_param *param)
{ return -ENXIO; }
#endif
#endif /* PM8XXX_ADC_H */
kernel/include/linux/mfd/pm8xxx/pwm.h
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/* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __PM8XXX_PWM_H__
#define __PM8XXX_PWM_H__
#include <linux/pwm.h>
#define PM8XXX_PWM_DEV_NAME "pm8xxx-pwm"
#define PM8XXX_PWM_PERIOD_MIN 7 /* usec: 19.2M, n=6, m=0, pre=2 */
#define PM8XXX_PWM_PERIOD_MAX (384 * USEC_PER_SEC) /* 1K, n=9, m=7, pre=6 */
#define PM_PWM_LUT_SIZE 64
#define PM_PWM_LUT_DUTY_TIME_MAX 512 /* ms */
#define PM_PWM_LUT_PAUSE_MAX (7000 * PM_PWM_LUT_DUTY_TIME_MAX)
/* Flags for Look Up Table */
#define PM_PWM_LUT_LOOP 0x01
#define PM_PWM_LUT_RAMP_UP 0x02
#define PM_PWM_LUT_REVERSE 0x04
#define PM_PWM_LUT_PAUSE_HI_EN 0x10
#define PM_PWM_LUT_PAUSE_LO_EN 0x20
#define PM_PWM_LUT_NO_TABLE 0x100
#define PM_PWM_BANK_LO 0x1000
#define PM_PWM_BANK_HI 0x2000
/**
* PWM frequency/period control
*
* PWM Frequency = ClockFrequency / (N * T)
* or
* PWM Period = Clock Period * (N * T)
* where
* N = 2^9 or 2^6 for 9-bit or 6-bit PWM size
* T = Pre-divide * 2^m, m = 0..7 (exponent)
*
*/
enum pm_pwm_size {
PM_PWM_SIZE_6BIT = 6,
PM_PWM_SIZE_9BIT = 9,
};
enum pm_pwm_clk {
PM_PWM_CLK_1KHZ,
PM_PWM_CLK_32KHZ,
PM_PWM_CLK_19P2MHZ,
};
enum pm_pwm_pre_div {
PM_PWM_PDIV_2,
PM_PWM_PDIV_3,
PM_PWM_PDIV_5,
PM_PWM_PDIV_6,
};
/**
* struct pm8xxx_pwm_period - PWM period structure
* @pwm_size: enum pm_pwm_size
* @clk: enum pm_pwm_clk
* @pre_div: enum pm_pwm_pre_div
* @pre_div_exp: exponent of 2 as part of pre-divider: 0..7
*/
struct pm8xxx_pwm_period {
enum pm_pwm_size pwm_size;
enum pm_pwm_clk clk;
enum pm_pwm_pre_div pre_div;
int pre_div_exp;
};
/**
* struct pm8xxx_pwm_duty_cycles - PWM duty cycle info
* duty_pcts - pointer to an array of duty percentage for a pwm period
* num_duty_pcts - total entries in duty_pcts array
* duty_ms - duty cycle time in ms
* start_idx - index in the LUT
*/
struct pm8xxx_pwm_duty_cycles {
int *duty_pcts;
int num_duty_pcts;
int duty_ms;
int start_idx;
};
/**
* struct pm8xxx_pwm_platform_data - PWM platform data
* dtest_channel - Enable LPG DTEST mode for this LPG channel
*/
struct pm8xxx_pwm_platform_data {
int dtest_channel;
};
/**
* pm8xxx_pwm_config_period - change PWM period
*
* @pwm: the PWM device
* @pwm_p: period in struct pm8xxx_pwm_period
*/
int pm8xxx_pwm_config_period(struct pwm_device *pwm,
struct pm8xxx_pwm_period *pwm_p);
/**
* pm8xxx_pwm_config_pwm_value - change a PWM device configuration
* @pwm: the PWM device
* @pwm_value: the duty cycle in raw PWM value (< 2^pwm_size)
*/
int pm8xxx_pwm_config_pwm_value(struct pwm_device *pwm, int pwm_value);
/**
* pm8xxx_pwm_lut_config - change a PWM device configuration to use LUT
* @pwm: the PWM device
* @period_us: period in micro second
* @duty_pct: arrary of duty cycles in percent, like 20, 50.
* @duty_time_ms: time for each duty cycle in millisecond
* @start_idx: start index in lookup table from 0 to MAX-1
* @idx_len: number of index
* @pause_lo: pause time in millisecond at low index
* @pause_hi: pause time in millisecond at high index
* @flags: control flags
*/
int pm8xxx_pwm_lut_config(struct pwm_device *pwm, int period_us,
int duty_pct[], int duty_time_ms, int start_idx,
int len, int pause_lo, int pause_hi, int flags);
/**
* pm8xxx_pwm_lut_enable - control a PWM device to start/stop LUT ramp
* @pwm: the PWM device
* @start: to start (1), or stop (0)
*/
int pm8xxx_pwm_lut_enable(struct pwm_device *pwm, int start);
/* Standard APIs supported */
/**
* pwm_request - request a PWM device
* @pwm_id: PWM id or channel
* @label: the label to identify the user
*/
/**
* pwm_free - free a PWM device
* @pwm: the PWM device
*/
/**
* pwm_config - change a PWM device configuration
* @pwm: the PWM device
* @period_us: period in microsecond
* @duty_us: duty cycle in microsecond
*/
/**
* pwm_enable - start a PWM output toggling
* @pwm: the PWM device
*/
/**
* pwm_disable - stop a PWM output toggling
* @pwm: the PWM device
*/
#endif /* __PM8XXX_PWM_H__ */
kernel/include/linux/mfd/pm8xxx/regulator.h
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/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MFD_PM8XXX_REGULATOR_H__
#define __MFD_PM8XXX_REGULATOR_H__
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/pm8xxx-regulator.h>
/**
* enum pm8xxx_regulator_type - possible PM8XXX voltage regulator types
* %PM8XXX_REGULATOR_TYPE_PLDO: PMOS low drop-out linear regulator
* %PM8XXX_REGULATOR_TYPE_NLDO: NMOS low drop-out linear regulator
* %PM8XXX_REGULATOR_TYPE_NLDO1200: NMOS low drop-out linear regulator
* capable of supplying up to 1200 mA
* %PM8XXX_REGULATOR_TYPE_SMPS: switched-mode power supply (buck)
* %PM8XXX_REGULATOR_TYPE_FTSMPS: fast transient switched-mode power
* supply (buck)
* %PM8XXX_REGULATOR_TYPE_VS: voltage switch capable of sourcing 100mA
* %PM8XXX_REGULATOR_TYPE_VS300: voltage switch capable of sourcing 300mA
* %PM8XXX_REGULATOR_TYPE_NCP: negative charge pump
* %PM8XXX_REGULATOR_TYPE_BOOST: boost regulator
* %PM8XXX_REGULATOR_TYPE_MAX: used internally for error checking; not
* a valid regulator type.
*
* Each of these has a different register control interface.
*/
enum pm8xxx_regulator_type {
PM8XXX_REGULATOR_TYPE_PLDO,
PM8XXX_REGULATOR_TYPE_NLDO,
PM8XXX_REGULATOR_TYPE_NLDO1200,
PM8XXX_REGULATOR_TYPE_SMPS,
PM8XXX_REGULATOR_TYPE_FTSMPS,
PM8XXX_REGULATOR_TYPE_VS,
PM8XXX_REGULATOR_TYPE_VS300,
PM8XXX_REGULATOR_TYPE_NCP,
PM8XXX_REGULATOR_TYPE_BOOST,
PM8XXX_REGULATOR_TYPE_MAX,
};
/**
* struct pm8xxx_vreg - regulator configuration and state data used by the
* pm8xxx-regulator driver
* @rdesc: regulator description
* @rdesc_pc: pin control regulator description. rdesc_pc.name == NULL
* implies that there is no pin control version of this
* regulator.
* @type: regulator type
* @hpm_min_load: minimum load in uA that will result in the regulator
* being set to high power mode
* @ctrl_addr: control register SSBI address
* @test_addr: test register SSBI address (not needed for all types)
* @clk_ctrl_addr: clock control register SSBI address (only used by SMPS
* type regulators)
* @sleep_ctrl_addr: sleep control register SSBI address (only used by SMPS
* type regulators)
* @pfm_ctrl_addr: pulse-frequency modulation control register SSBI address
* (only used by FTSMPS type regulators)
* @pwr_cnfg_addr: power configuration register SSBI address (only used by
* FTSMPS type regulators)
* @pdata: this platform data struct is filled based using the
* platform data pointed to in a core platform data struct
* @rdev: pointer to regulator device which is created with
* regulator_register
* @rdev_pc: pointer to pin controlled regulator device which is
* created with regulator_register
* @dev: pointer to pm8xxx-regulator device
* @dev_pc: pointer to pin control pm8xxx-regulator device
* @pc_lock: mutex lock to handle sharing between pin controlled and
* non-pin controlled versions of a given regulator. Note,
* this lock must be initialized in the PMIC core driver.)
* @save_uV: current regulator voltage in uV
* @mode: current mode of the regulator
* @write_count: number of SSBI writes that have taken place for this
* regulator. This is used for debug printing to determine
* if a given operation is redundant.
* @prev_write_count: number of SSBI writes that have taken place for this
* regulator at the start of an operation. This is used for
* debug printing to determine if a given operation is
* redundant.
* @is_enabled: true if the regulator is currently enabled, false if not
* @is_enabled_pc: true if the pin controlled version of the regulator is
* currently enabled (i.e. pin control is active), false if
* not
* @test_reg: last value read from or written to each of the banks of
* the test register
* @ctrl_reg: last value read from or written to the control register
* @clk_ctrl_reg: last value read from or written to the clock control
* register
* @sleep_ctrl_reg: last value read from or written to the sleep control
* register
* @pfm_ctrl_reg: last value read from or written to the PFM control
* register
* @pwr_cnfg_reg: last value read from or written to the power
* configuration register
*
* This data structure should only need to be instantiated in a PMIC core driver
* It is used to specify PMIC specific as opposed to board specific
* configuration data. It is also used to hold all state variables needed by
* the pm8xxx-regulator driver as these variables need to be shared between
* pin controlled and non-pin controlled versions of a given regulator, which
* are probed separately.
*/
struct pm8xxx_vreg {
/* Configuration data */
struct regulator_desc rdesc;
struct regulator_desc rdesc_pc;
enum pm8xxx_regulator_type type;
const int hpm_min_load;
const u16 ctrl_addr;
const u16 test_addr;
const u16 clk_ctrl_addr;
const u16 sleep_ctrl_addr;
const u16 pfm_ctrl_addr;
const u16 pwr_cnfg_addr;
/* State data */
struct pm8xxx_regulator_platform_data pdata;
struct regulator_dev *rdev;
struct regulator_dev *rdev_pc;
struct device *dev;
struct device *dev_pc;
struct mutex pc_lock;
int save_uV;
int mode;
u32 write_count;
u32 prev_write_count;
bool is_enabled;
bool is_enabled_pc;
u8 test_reg[REGULATOR_TEST_BANKS_MAX];
u8 ctrl_reg;
u8 clk_ctrl_reg;
u8 sleep_ctrl_reg;
u8 pfm_ctrl_reg;
u8 pwr_cnfg_reg;
};
/**
* struct pm8xxx_regulator_core_platform_data - platform data specified in a
* PMIC core driver and utilized in the pm8xxx-regulator driver
* @vreg: pointer to pm8xxx_vreg data structure that may be shared
* between pin controlled and non-pin controlled versions
* of a given regulator. Note that this data must persist
* as long as the regulator device is in use.
* @pdata: pointer to platform data passed in from a board file
* @is_pin_controlled: true if the regulator driver represents the pin control
* portion of a regulator, false if not.
*
* This data structure should only be needed in a PMIC core driver.
*/
struct pm8xxx_regulator_core_platform_data {
struct pm8xxx_vreg *vreg;
struct pm8xxx_regulator_platform_data *pdata;
bool is_pin_controlled;
};
/* Helper macros */
#define PLDO(_name, _pc_name, _ctrl_addr, _test_addr, _hpm_min_load) \
{ \
.type = PM8XXX_REGULATOR_TYPE_PLDO, \
.ctrl_addr = _ctrl_addr, \
.test_addr = _test_addr, \
.hpm_min_load = PM8XXX_VREG_##_hpm_min_load##_HPM_MIN_LOAD, \
.rdesc.name = _name, \
.rdesc_pc.name = _pc_name, \
.write_count = 0, \
.prev_write_count = -1, \
}
#define NLDO(_name, _pc_name, _ctrl_addr, _test_addr, _hpm_min_load) \
{ \
.type = PM8XXX_REGULATOR_TYPE_NLDO, \
.ctrl_addr = _ctrl_addr, \
.test_addr = _test_addr, \
.hpm_min_load = PM8XXX_VREG_##_hpm_min_load##_HPM_MIN_LOAD, \
.rdesc.name = _name, \
.rdesc_pc.name = _pc_name, \
.write_count = 0, \
.prev_write_count = -1, \
}
#define NLDO1200(_name, _ctrl_addr, _test_addr, _hpm_min_load) \
{ \
.type = PM8XXX_REGULATOR_TYPE_NLDO1200, \
.ctrl_addr = _ctrl_addr, \
.test_addr = _test_addr, \
.hpm_min_load = PM8XXX_VREG_##_hpm_min_load##_HPM_MIN_LOAD, \
.rdesc.name = _name, \
.write_count = 0, \
.prev_write_count = -1, \
}
#define SMPS(_name, _pc_name, _ctrl_addr, _test_addr, _clk_ctrl_addr, \
_sleep_ctrl_addr, _hpm_min_load) \
{ \
.type = PM8XXX_REGULATOR_TYPE_SMPS, \
.ctrl_addr = _ctrl_addr, \
.test_addr = _test_addr, \
.clk_ctrl_addr = _clk_ctrl_addr, \
.sleep_ctrl_addr = _sleep_ctrl_addr, \
.hpm_min_load = PM8XXX_VREG_##_hpm_min_load##_HPM_MIN_LOAD, \
.rdesc.name = _name, \
.rdesc_pc.name = _pc_name, \
.write_count = 0, \
.prev_write_count = -1, \
}
#define FTSMPS(_name, _pwm_ctrl_addr, _fts_cnfg1_addr, _pfm_ctrl_addr, \
_pwr_cnfg_addr, _hpm_min_load) \
{ \
.type = PM8XXX_REGULATOR_TYPE_FTSMPS, \
.ctrl_addr = _pwm_ctrl_addr, \
.test_addr = _fts_cnfg1_addr, \
.pfm_ctrl_addr = _pfm_ctrl_addr, \
.pwr_cnfg_addr = _pwr_cnfg_addr, \
.hpm_min_load = PM8XXX_VREG_##_hpm_min_load##_HPM_MIN_LOAD, \
.rdesc.name = _name, \
.write_count = 0, \
.prev_write_count = -1, \
}
#define VS(_name, _pc_name, _ctrl_addr, _test_addr) \
{ \
.type = PM8XXX_REGULATOR_TYPE_VS, \
.ctrl_addr = _ctrl_addr, \
.test_addr = _test_addr, \
.rdesc.name = _name, \
.rdesc_pc.name = _pc_name, \
.write_count = 0, \
.prev_write_count = -1, \
}
#define VS300(_name, _ctrl_addr, _test_addr) \
{ \
.type = PM8XXX_REGULATOR_TYPE_VS300, \
.ctrl_addr = _ctrl_addr, \
.test_addr = _test_addr, \
.rdesc.name = _name, \
.write_count = 0, \
.prev_write_count = -1, \
}
#define NCP(_name, _ctrl_addr) \
{ \
.type = PM8XXX_REGULATOR_TYPE_NCP, \
.ctrl_addr = _ctrl_addr, \
.rdesc.name = _name, \
.write_count = 0, \
.prev_write_count = -1, \
}
#define BOOST(_name, _ctrl_addr) \
{ \
.type = PM8XXX_REGULATOR_TYPE_BOOST, \
.ctrl_addr = _ctrl_addr, \
.rdesc.name = _name, \
.write_count = 0, \
.prev_write_count = -1, \
}
#endif
kernel/include/linux/mfd/pm8xxx/rtc.h
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/* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __RTC_PM8XXX_H__
#define __RTC_PM8XXX_H__
#define PM8XXX_RTC_DEV_NAME "rtc-pm8xxx"
/**
* struct pm8xxx_rtc_pdata - RTC driver platform data
* @rtc_write_enable: variable stating RTC write capability
*/
struct pm8xxx_rtc_platform_data {
bool rtc_write_enable;
bool rtc_alarm_powerup;
};
#endif /* __RTC_PM8XXX_H__ */
kernel/include/linux/mfd/pm8xxx/spk.h
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/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SPK_PM8XXX_H__
#define __SPK_PM8XXX_H__
#define PM8XXX_SPK_DEV_NAME "pm8xxx-spk"
/**
* struct pm8xxx_spk_pdata - SPK driver platform data
* @spk_add_enable: variable stating SPK secondary input adding capability
*/
struct pm8xxx_spk_platform_data {
bool spk_add_enable;
int cd_ng_threshold;
int cd_nf_preamp_bias;
int cd_ng_hold;
int cd_ng_max_atten;
int noise_mute;
int cd_ng_decay_rate;
int cd_ng_attack_rate;
int cd_delay;
};
/*
* pm8xxx_spk_mute - mute/unmute speaker pamp
*
* @mute: bool value for mute
*/
int pm8xxx_spk_mute(bool mute);
/*
* pm8xxx_spk_gain - Set Speaker gain
*
* @gain: Speaker gain
*/
int pm8xxx_spk_gain(u8 gain);
/*
* pm8xxx_spk_enable - Enable/Disable Speaker
*
* @enable: bool enable/disable Speaker
*/
int pm8xxx_spk_enable(int enable);
#endif /* __SPK_PM8XXX_H__ */
kernel/include/linux/mfd/pm8xxx/tm.h
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/*
* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Qualcomm PMIC PM8xxx Thermal Manager driver
*/
#ifndef __PM8XXX_TM_H
#define __PM8XXX_TM_H
#include <linux/errno.h>
#define PM8XXX_TM_DEV_NAME "pm8xxx-tm"
/**
* enum pm8xxx_tm_adc_type - support ADC API types for PMIC thermal manager
* %PM8XXX_TM_ADC_NONE: Do not call any ADC API and instead estimate
* PMIC temerature based on over temperature stage.
* %PM8XXX_TM_ADC_PM8058_ADC: Use the pmic8058-xoadc ADC API
* %PM8XXX_TM_ADC_PM8XXX_ADC: Use the pm8xxx-adc ADC API
*/
enum pm8xxx_tm_adc_type {
PM8XXX_TM_ADC_NONE,
PM8XXX_TM_ADC_PM8058_ADC,
PM8XXX_TM_ADC_PM8XXX_ADC,
};
/**
* struct pm8xxx_tm_core_data - PM8XXX thermal manager core data
* @tm_name: Thermal zone name for the device
* @irq_name_temp_stat: String name used to identify TEMP_STAT IRQ
* @irq_name_over_temp: String name used to identify OVER_TEMP IRQ
* @reg_addr_temp_alarm_ctrl: PMIC SSBI address for temp alarm control
* register
* @reg_addr_temp_alarm_pwm: PMIC SSBI address for temp alarm pwm register
* @adc_type: Determines which ADC API to use in order to read
* the PMIC die temperature.
* @adc_channel: ADC channel identifier
* If adc_type == PM8XXX_TM_ADC_PM8XXX_ADC, then
* use a value from enum pm8xxx_adc_channels.
* If adc_type == PM8XXX_TM_ADC_PM8058_ADC, then
* use a channel value specified in
* <linux/pmic8058-xoadc.h>
* @default_no_adc_temp: Default temperature in millicelcius to report
* while stage == 0 and stage has never been
* greater than 0 if adc_type == PM8XXX_TM_ADC_NONE
* @allow_software_override: true --> writing "enabled" to thermalfs mode
* file results in software override of PMIC
* automatic over temperature shutdown
* false --> PMIC automatic over temperature
* shutdown always enabled. mode file cannot be
* set to "enabled".
*/
struct pm8xxx_tm_core_data {
char *tm_name;
char *irq_name_temp_stat;
char *irq_name_over_temp;
u16 reg_addr_temp_alarm_ctrl;
u16 reg_addr_temp_alarm_pwm;
enum pm8xxx_tm_adc_type adc_type;
int adc_channel;
unsigned long default_no_adc_temp;
bool allow_software_override;
};
#endif
kernel/include/linux/mfd/pm8xxx/upl.h
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/* Copyright (c) 2010,2011 The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __PM8XXX_UPL_H__
#define __PM8XXX_UPL_H__
struct pm8xxx_upl_device;
#define PM8XXX_UPL_DEV_NAME "pm8xxx-upl"
/* control masks and flags */
#define PM8XXX_UPL_MOD_ENABLE_MASK (0x10)
#define PM8XXX_UPL_MOD_ENABLE (0x10)
#define PM8XXX_UPL_MOD_DISABLE (0x00)
#define PM8XXX_UPL_OUT_DTEST_MASK (0xE0)
#define PM8XXX_UPL_OUT_GPIO_ONLY (0x00)
#define PM8XXX_UPL_OUT_DTEST_1 (0x80)
#define PM8XXX_UPL_OUT_DTEST_2 (0xA0)
#define PM8XXX_UPL_OUT_DTEST_3 (0xC0)
#define PM8XXX_UPL_OUT_DTEST_4 (0xE0)
#define PM8XXX_UPL_IN_A_MASK (0x01)
#define PM8XXX_UPL_IN_A_GPIO (0x00)
#define PM8XXX_UPL_IN_A_DTEST (0x01)
#define PM8XXX_UPL_IN_B_MASK (0x02)
#define PM8XXX_UPL_IN_B_GPIO (0x00)
#define PM8XXX_UPL_IN_B_DTEST (0x02)
#define PM8XXX_UPL_IN_C_MASK (0x04)
#define PM8XXX_UPL_IN_C_GPIO (0x00)
#define PM8XXX_UPL_IN_C_DTEST (0x04)
#define PM8XXX_UPL_IN_D_MASK (0x08)
#define PM8XXX_UPL_IN_D_GPIO (0x00)
#define PM8XXX_UPL_IN_D_DTEST (0x08)
/*
* pm8xxx_upl_request - request a handle to access UPL device
*/
struct pm8xxx_upl_device *pm8xxx_upl_request(void);
int pm8xxx_upl_read_truthtable(struct pm8xxx_upl_device *upldev,
u16 *truthtable);
int pm8xxx_upl_write_truthtable(struct pm8xxx_upl_device *upldev,
u16 truthtable);
/*
* pm8xxx_upl_config - configure UPL I/O settings and UPL enable/disable
*
* @upldev: the UPL device
* @mask: setting mask to configure
* @flags: setting flags
*/
int pm8xxx_upl_config(struct pm8xxx_upl_device *upldev, u32 mask, u32 flags);
#endif /* __PM8XXX_UPL_H__ */
kernel/include/linux/mfd/pm8xxx/vibrator.h
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/* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __PMIC8XXX_VIBRATOR_H__
#define __PMIC8XXX_VIBRATOR_H__
#define PM8XXX_VIBRATOR_DEV_NAME "pm8xxx-vib"
enum pm8xxx_vib_en_mode {
PM8XXX_VIB_MANUAL,
PM8XXX_VIB_DTEST1,
PM8XXX_VIB_DTEST2,
PM8XXX_VIB_DTEST3
};
struct pm8xxx_vib_config {
u16 drive_mV;
u8 active_low;
enum pm8xxx_vib_en_mode enable_mode;
};
struct pm8xxx_vibrator_platform_data {
int initial_vibrate_ms;
int max_timeout_ms;
int level_mV;
};
int pm8xxx_vibrator_config(struct pm8xxx_vib_config *vib_config);
#endif /* __PMIC8XXX_VIBRATOR_H__ */
kernel/include/linux/mfd/pmic8058.h
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/* Copyright (c) 2009-2011, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
/*
* Qualcomm PMIC8058 driver header file
*
*/
#ifndef __MFD_PMIC8058_H__
#define __MFD_PMIC8058_H__
#include <linux/irq.h>
#include <linux/mfd/core.h>
#include <linux/mfd/pm8xxx/irq.h>
#include <linux/mfd/pm8xxx/gpio.h>
#include <linux/mfd/pm8xxx/mpp.h>
#include <linux/mfd/pm8xxx/rtc.h>
#include <linux/input/pmic8xxx-pwrkey.h>
#include <linux/input/pmic8xxx-keypad.h>
#include <linux/mfd/pm8xxx/vibrator.h>
#include <linux/mfd/pm8xxx/nfc.h>
#include <linux/mfd/pm8xxx/upl.h>
#include <linux/mfd/pm8xxx/misc.h>
#include <linux/mfd/pm8xxx/batt-alarm.h>
#include <linux/leds-pmic8058.h>
#include <linux/pmic8058-othc.h>
#include <linux/mfd/pm8xxx/tm.h>
#include <linux/pmic8058-xoadc.h>
#include <linux/regulator/pmic8058-regulator.h>
#include <linux/regulator/pm8058-xo.h>
#include <linux/pwm.h>
#include <linux/pmic8058-pwm.h>
#define PM8058_GPIOS 40
#define PM8058_MPPS 12
#define PM8058_GPIO_BLOCK_START 24
#define PM8058_MPP_BLOCK_START 16
#define PM8058_NR_IRQS 256
#define PM8058_IRQ_BLOCK_BIT(block, bit) ((block) * 8 + (bit))
/* MPPs and GPIOs [0,N) */
#define PM8058_MPP_IRQ(base, mpp) ((base) + \
PM8058_IRQ_BLOCK_BIT(16, (mpp)))
#define PM8058_GPIO_IRQ(base, gpio) ((base) + \
PM8058_IRQ_BLOCK_BIT(24, (gpio)))
/* PM8058 IRQ's */
#define PM8058_VCP_IRQ PM8058_IRQ_BLOCK_BIT(1, 0)
#define PM8058_CHGILIM_IRQ PM8058_IRQ_BLOCK_BIT(1, 3)
#define PM8058_VBATDET_LOW_IRQ PM8058_IRQ_BLOCK_BIT(1, 4)
#define PM8058_BATT_REPLACE_IRQ PM8058_IRQ_BLOCK_BIT(1, 5)
#define PM8058_CHGINVAL_IRQ PM8058_IRQ_BLOCK_BIT(1, 6)
#define PM8058_CHGVAL_IRQ PM8058_IRQ_BLOCK_BIT(1, 7)
#define PM8058_CHG_END_IRQ PM8058_IRQ_BLOCK_BIT(2, 0)
#define PM8058_FASTCHG_IRQ PM8058_IRQ_BLOCK_BIT(2, 1)
#define PM8058_CHGSTATE_IRQ PM8058_IRQ_BLOCK_BIT(2, 3)
#define PM8058_AUTO_CHGFAIL_IRQ PM8058_IRQ_BLOCK_BIT(2, 4)
#define PM8058_AUTO_CHGDONE_IRQ PM8058_IRQ_BLOCK_BIT(2, 5)
#define PM8058_ATCFAIL_IRQ PM8058_IRQ_BLOCK_BIT(2, 6)
#define PM8058_ATC_DONE_IRQ PM8058_IRQ_BLOCK_BIT(2, 7)
#define PM8058_OVP_OK_IRQ PM8058_IRQ_BLOCK_BIT(3, 0)
#define PM8058_COARSE_DET_OVP_IRQ PM8058_IRQ_BLOCK_BIT(3, 1)
#define PM8058_VCPMAJOR_IRQ PM8058_IRQ_BLOCK_BIT(3, 2)
#define PM8058_CHG_GONE_IRQ PM8058_IRQ_BLOCK_BIT(3, 3)
#define PM8058_CHGTLIMIT_IRQ PM8058_IRQ_BLOCK_BIT(3, 4)
#define PM8058_CHGHOT_IRQ PM8058_IRQ_BLOCK_BIT(3, 5)
#define PM8058_BATTTEMP_IRQ PM8058_IRQ_BLOCK_BIT(3, 6)
#define PM8058_BATTCONNECT_IRQ PM8058_IRQ_BLOCK_BIT(3, 7)
#define PM8058_BATFET_IRQ PM8058_IRQ_BLOCK_BIT(5, 4)
#define PM8058_VBATDET_IRQ PM8058_IRQ_BLOCK_BIT(5, 5)
#define PM8058_VBAT_IRQ PM8058_IRQ_BLOCK_BIT(5, 6)
#define PM8058_RTC_IRQ PM8058_IRQ_BLOCK_BIT(6, 5)
#define PM8058_RTC_ALARM_IRQ PM8058_IRQ_BLOCK_BIT(4, 7)
#define PM8058_PWRKEY_REL_IRQ PM8058_IRQ_BLOCK_BIT(6, 2)
#define PM8058_PWRKEY_PRESS_IRQ PM8058_IRQ_BLOCK_BIT(6, 3)
#define PM8058_KEYPAD_IRQ PM8058_IRQ_BLOCK_BIT(9, 2)
#define PM8058_KEYSTUCK_IRQ PM8058_IRQ_BLOCK_BIT(9, 3)
#define PM8058_BATT_ALARM_IRQ PM8058_IRQ_BLOCK_BIT(5, 6)
#define PM8058_SW_0_IRQ PM8058_IRQ_BLOCK_BIT(7, 1)
#define PM8058_IR_0_IRQ PM8058_IRQ_BLOCK_BIT(7, 0)
#define PM8058_SW_1_IRQ PM8058_IRQ_BLOCK_BIT(7, 3)
#define PM8058_IR_1_IRQ PM8058_IRQ_BLOCK_BIT(7, 2)
#define PM8058_SW_2_IRQ PM8058_IRQ_BLOCK_BIT(7, 5)
#define PM8058_IR_2_IRQ PM8058_IRQ_BLOCK_BIT(7, 4)
#define PM8058_TEMPSTAT_IRQ PM8058_IRQ_BLOCK_BIT(6, 7)
#define PM8058_OVERTEMP_IRQ PM8058_IRQ_BLOCK_BIT(4, 2)
#define PM8058_ADC_IRQ PM8058_IRQ_BLOCK_BIT(9, 4)
#define PM8058_OSCHALT_IRQ PM8058_IRQ_BLOCK_BIT(4, 6)
#define PM8058_CBLPWR_IRQ PM8058_IRQ_BLOCK_BIT(4, 3)
#define PM8058_RESOUT_IRQ PM8058_IRQ_BLOCK_BIT(6, 4)
struct pmic8058_charger_data {
unsigned int max_source_current;
int charger_type;
bool charger_data_valid;
};
struct pm8058_platform_data {
struct pm8xxx_mpp_platform_data *mpp_pdata;
struct pm8xxx_keypad_platform_data *keypad_pdata;
struct pm8xxx_gpio_platform_data *gpio_pdata;
struct pm8xxx_irq_platform_data *irq_pdata;
struct pm8xxx_rtc_platform_data *rtc_pdata;
struct pm8xxx_pwrkey_platform_data *pwrkey_pdata;
struct pm8xxx_vibrator_platform_data *vibrator_pdata;
struct pm8xxx_misc_platform_data *misc_pdata;
struct pmic8058_leds_platform_data *leds_pdata;
struct pmic8058_othc_config_pdata *othc0_pdata;
struct pmic8058_othc_config_pdata *othc1_pdata;
struct pmic8058_othc_config_pdata *othc2_pdata;
struct xoadc_platform_data *xoadc_pdata;
struct pm8058_pwm_pdata *pwm_pdata;
struct pm8058_vreg_pdata *regulator_pdatas;
int num_regulators;
struct pm8058_xo_pdata *xo_buffer_pdata;
int num_xo_buffers;
struct pmic8058_charger_data *charger_pdata;
};
#endif /* __MFD_PMIC8058_H__ */
kernel/include/linux/mfd/pmic8901.h
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/* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __PMIC8901_H__
#define __PMIC8901_H__
/*
* Qualcomm PMIC8901 driver header file
*
*/
#include <linux/irq.h>
#include <linux/mfd/core.h>
#include <linux/mfd/pm8xxx/irq.h>
#include <linux/mfd/pm8xxx/mpp.h>
#include <linux/mfd/pm8xxx/tm.h>
#include <linux/regulator/pmic8901-regulator.h>
#include <linux/mfd/pm8xxx/misc.h>
#define PM8901_IRQ_BLOCK_BIT(block, bit) ((block) * 8 + (bit))
#define PM8901_NR_IRQS 72
/* PM8901 MPP */
#define PM8901_MPP_BLOCK_START 6
#define PM8901_MPPS 4
/* PM8901 IRQs */
#define PM8901_MPP_IRQ(mpp) PM8901_IRQ_BLOCK_BIT(6, (mpp))
#define PM8901_TEMPSTAT_IRQ PM8901_IRQ_BLOCK_BIT(6, 4)
#define PM8901_OVERTEMP_IRQ PM8901_IRQ_BLOCK_BIT(6, 5)
struct pm8901_platform_data {
struct pm8xxx_irq_platform_data *irq_pdata;
struct pm8xxx_mpp_platform_data *mpp_pdata;
struct pm8xxx_misc_platform_data *misc_pdata;
struct pm8901_vreg_pdata *regulator_pdatas;
int num_regulators;
};
#endif /* __PMIC8901_H__ */
kernel/include/linux/mfd/rc5t583.h
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/*
* Core driver interface to access RICOH_RC5T583 power management chip.
*
* Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
* Author: Laxman dewangan <ldewangan@nvidia.com>
*
* Based on code
* Copyright (C) 2011 RICOH COMPANY,LTD
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
#ifndef __LINUX_MFD_RC5T583_H
#define __LINUX_MFD_RC5T583_H
#include <linux/mutex.h>
#include <linux/types.h>
#include <linux/regmap.h>
#define RC5T583_MAX_REGS 0xF8
/* Maximum number of main interrupts */
#define MAX_MAIN_INTERRUPT 5
#define RC5T583_MAX_GPEDGE_REG 2
#define RC5T583_MAX_INTERRUPT_MASK_REGS 9
/* Interrupt enable register */
#define RC5T583_INT_EN_SYS1 0x19
#define RC5T583_INT_EN_SYS2 0x1D
#define RC5T583_INT_EN_DCDC 0x41
#define RC5T583_INT_EN_RTC 0xED
#define RC5T583_INT_EN_ADC1 0x90
#define RC5T583_INT_EN_ADC2 0x91
#define RC5T583_INT_EN_ADC3 0x92
/* Interrupt status registers (monitor regs in Ricoh)*/
#define RC5T583_INTC_INTPOL 0xAD
#define RC5T583_INTC_INTEN 0xAE
#define RC5T583_INTC_INTMON 0xAF
#define RC5T583_INT_MON_GRP 0xAF
#define RC5T583_INT_MON_SYS1 0x1B
#define RC5T583_INT_MON_SYS2 0x1F
#define RC5T583_INT_MON_DCDC 0x43
#define RC5T583_INT_MON_RTC 0xEE
/* Interrupt clearing registers */
#define RC5T583_INT_IR_SYS1 0x1A
#define RC5T583_INT_IR_SYS2 0x1E
#define RC5T583_INT_IR_DCDC 0x42
#define RC5T583_INT_IR_RTC 0xEE
#define RC5T583_INT_IR_ADCL 0x94
#define RC5T583_INT_IR_ADCH 0x95
#define RC5T583_INT_IR_ADCEND 0x96
#define RC5T583_INT_IR_GPIOR 0xA9
#define RC5T583_INT_IR_GPIOF 0xAA
/* Sleep sequence registers */
#define RC5T583_SLPSEQ1 0x21
#define RC5T583_SLPSEQ2 0x22
#define RC5T583_SLPSEQ3 0x23
#define RC5T583_SLPSEQ4 0x24
#define RC5T583_SLPSEQ5 0x25
#define RC5T583_SLPSEQ6 0x26
#define RC5T583_SLPSEQ7 0x27
#define RC5T583_SLPSEQ8 0x28
#define RC5T583_SLPSEQ9 0x29
#define RC5T583_SLPSEQ10 0x2A
#define RC5T583_SLPSEQ11 0x2B
/* Regulator registers */
#define RC5T583_REG_DC0CTL 0x30
#define RC5T583_REG_DC0DAC 0x31
#define RC5T583_REG_DC0LATCTL 0x32
#define RC5T583_REG_SR0CTL 0x33
#define RC5T583_REG_DC1CTL 0x34
#define RC5T583_REG_DC1DAC 0x35
#define RC5T583_REG_DC1LATCTL 0x36
#define RC5T583_REG_SR1CTL 0x37
#define RC5T583_REG_DC2CTL 0x38
#define RC5T583_REG_DC2DAC 0x39
#define RC5T583_REG_DC2LATCTL 0x3A
#define RC5T583_REG_SR2CTL 0x3B
#define RC5T583_REG_DC3CTL 0x3C
#define RC5T583_REG_DC3DAC 0x3D
#define RC5T583_REG_DC3LATCTL 0x3E
#define RC5T583_REG_SR3CTL 0x3F
#define RC5T583_REG_LDOEN1 0x50
#define RC5T583_REG_LDOEN2 0x51
#define RC5T583_REG_LDODIS1 0x52
#define RC5T583_REG_LDODIS2 0x53
#define RC5T583_REG_LDO0DAC 0x54
#define RC5T583_REG_LDO1DAC 0x55
#define RC5T583_REG_LDO2DAC 0x56
#define RC5T583_REG_LDO3DAC 0x57
#define RC5T583_REG_LDO4DAC 0x58
#define RC5T583_REG_LDO5DAC 0x59
#define RC5T583_REG_LDO6DAC 0x5A
#define RC5T583_REG_LDO7DAC 0x5B
#define RC5T583_REG_LDO8DAC 0x5C
#define RC5T583_REG_LDO9DAC 0x5D
#define RC5T583_REG_DC0DAC_DS 0x60
#define RC5T583_REG_DC1DAC_DS 0x61
#define RC5T583_REG_DC2DAC_DS 0x62
#define RC5T583_REG_DC3DAC_DS 0x63
#define RC5T583_REG_LDO0DAC_DS 0x64
#define RC5T583_REG_LDO1DAC_DS 0x65
#define RC5T583_REG_LDO2DAC_DS 0x66
#define RC5T583_REG_LDO3DAC_DS 0x67
#define RC5T583_REG_LDO4DAC_DS 0x68
#define RC5T583_REG_LDO5DAC_DS 0x69
#define RC5T583_REG_LDO6DAC_DS 0x6A
#define RC5T583_REG_LDO7DAC_DS 0x6B
#define RC5T583_REG_LDO8DAC_DS 0x6C
#define RC5T583_REG_LDO9DAC_DS 0x6D
/* GPIO register base address */
#define RC5T583_GPIO_IOSEL 0xA0
#define RC5T583_GPIO_PDEN 0xA1
#define RC5T583_GPIO_IOOUT 0xA2
#define RC5T583_GPIO_PGSEL 0xA3
#define RC5T583_GPIO_GPINV 0xA4
#define RC5T583_GPIO_GPDEB 0xA5
#define RC5T583_GPIO_GPEDGE1 0xA6
#define RC5T583_GPIO_GPEDGE2 0xA7
#define RC5T583_GPIO_EN_INT 0xA8
#define RC5T583_GPIO_MON_IOIN 0xAB
#define RC5T583_GPIO_GPOFUNC 0xAC
/* RICOH_RC5T583 IRQ definitions */
enum {
RC5T583_IRQ_ONKEY,
RC5T583_IRQ_ACOK,
RC5T583_IRQ_LIDOPEN,
RC5T583_IRQ_PREOT,
RC5T583_IRQ_CLKSTP,
RC5T583_IRQ_ONKEY_OFF,
RC5T583_IRQ_WD,
RC5T583_IRQ_EN_PWRREQ1,
RC5T583_IRQ_EN_PWRREQ2,
RC5T583_IRQ_PRE_VINDET,
RC5T583_IRQ_DC0LIM,
RC5T583_IRQ_DC1LIM,
RC5T583_IRQ_DC2LIM,
RC5T583_IRQ_DC3LIM,
RC5T583_IRQ_CTC,
RC5T583_IRQ_YALE,
RC5T583_IRQ_DALE,
RC5T583_IRQ_WALE,
RC5T583_IRQ_AIN1L,
RC5T583_IRQ_AIN2L,
RC5T583_IRQ_AIN3L,
RC5T583_IRQ_VBATL,
RC5T583_IRQ_VIN3L,
RC5T583_IRQ_VIN8L,
RC5T583_IRQ_AIN1H,
RC5T583_IRQ_AIN2H,
RC5T583_IRQ_AIN3H,
RC5T583_IRQ_VBATH,
RC5T583_IRQ_VIN3H,
RC5T583_IRQ_VIN8H,
RC5T583_IRQ_ADCEND,
RC5T583_IRQ_GPIO0,
RC5T583_IRQ_GPIO1,
RC5T583_IRQ_GPIO2,
RC5T583_IRQ_GPIO3,
RC5T583_IRQ_GPIO4,
RC5T583_IRQ_GPIO5,
RC5T583_IRQ_GPIO6,
RC5T583_IRQ_GPIO7,
/* Should be last entry */
RC5T583_MAX_IRQS,
};
/* Ricoh583 gpio definitions */
enum {
RC5T583_GPIO0,
RC5T583_GPIO1,
RC5T583_GPIO2,
RC5T583_GPIO3,
RC5T583_GPIO4,
RC5T583_GPIO5,
RC5T583_GPIO6,
RC5T583_GPIO7,
/* Should be last entry */
RC5T583_MAX_GPIO,
};
enum {
RC5T583_DS_NONE,
RC5T583_DS_DC0,
RC5T583_DS_DC1,
RC5T583_DS_DC2,
RC5T583_DS_DC3,
RC5T583_DS_LDO0,
RC5T583_DS_LDO1,
RC5T583_DS_LDO2,
RC5T583_DS_LDO3,
RC5T583_DS_LDO4,
RC5T583_DS_LDO5,
RC5T583_DS_LDO6,
RC5T583_DS_LDO7,
RC5T583_DS_LDO8,
RC5T583_DS_LDO9,
RC5T583_DS_PSO0,
RC5T583_DS_PSO1,
RC5T583_DS_PSO2,
RC5T583_DS_PSO3,
RC5T583_DS_PSO4,
RC5T583_DS_PSO5,
RC5T583_DS_PSO6,
RC5T583_DS_PSO7,
/* Should be last entry */
RC5T583_DS_MAX,
};
/*
* Ricoh pmic RC5T583 supports sleep through two external controls.
* The output of gpios and regulator can be enable/disable through
* this external signals.
*/
enum {
RC5T583_EXT_PWRREQ1_CONTROL = 0x1,
RC5T583_EXT_PWRREQ2_CONTROL = 0x2,
};
struct rc5t583 {
struct device *dev;
struct regmap *regmap;
int chip_irq;
int irq_base;
struct mutex irq_lock;
unsigned long group_irq_en[MAX_MAIN_INTERRUPT];
/* For main interrupt bits in INTC */
uint8_t intc_inten_reg;
/* For group interrupt bits and address */
uint8_t irq_en_reg[RC5T583_MAX_INTERRUPT_MASK_REGS];
/* For gpio edge */
uint8_t gpedge_reg[RC5T583_MAX_GPEDGE_REG];
};
/*
* rc5t583_platform_data: Platform data for ricoh rc5t583 pmu.
* The board specific data is provided through this structure.
* @irq_base: Irq base number on which this device registers their interrupts.
* @enable_shutdown: Enable shutdown through the input pin "shutdown".
*/
struct rc5t583_platform_data {
int irq_base;
bool enable_shutdown;
};
static inline int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val)
{
struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
return regmap_write(rc5t583->regmap, reg, val);
}
static inline int rc5t583_read(struct device *dev, uint8_t reg, uint8_t *val)
{
struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
unsigned int ival;
int ret;
ret = regmap_read(rc5t583->regmap, reg, &ival);
if (!ret)
*val = (uint8_t)ival;
return ret;
}
static inline int rc5t583_set_bits(struct device *dev, unsigned int reg,
unsigned int bit_mask)
{
struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
return regmap_update_bits(rc5t583->regmap, reg, bit_mask, bit_mask);
}
static inline int rc5t583_clear_bits(struct device *dev, unsigned int reg,
unsigned int bit_mask)
{
struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
return regmap_update_bits(rc5t583->regmap, reg, bit_mask, 0);
}
static inline int rc5t583_update(struct device *dev, unsigned int reg,
unsigned int val, unsigned int mask)
{
struct rc5t583 *rc5t583 = dev_get_drvdata(dev);
return regmap_update_bits(rc5t583->regmap, reg, mask, val);
}
int rc5t583_ext_power_req_config(struct device *dev, int deepsleep_id,
int ext_pwr_req, int deepsleep_slot_nr);
int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base);
int rc5t583_irq_exit(struct rc5t583 *rc5t583);
#endif
kernel/include/linux/mfd/rdc321x.h
+26
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#ifndef __RDC321X_MFD_H
#define __RDC321X_MFD_H
#include <linux/types.h>
#include <linux/pci.h>
/* Offsets to be accessed in the southbridge PCI
* device configuration register */
#define RDC321X_WDT_CTRL 0x44
#define RDC321X_GPIO_CTRL_REG1 0x48
#define RDC321X_GPIO_DATA_REG1 0x4c
#define RDC321X_GPIO_CTRL_REG2 0x84
#define RDC321X_GPIO_DATA_REG2 0x88
#define RDC321X_MAX_GPIO 58
struct rdc321x_gpio_pdata {
struct pci_dev *sb_pdev;
unsigned max_gpios;
};
struct rdc321x_wdt_pdata {
struct pci_dev *sb_pdev;
};
#endif /* __RDC321X_MFD_H */
kernel/include/linux/mfd/s5m87xx/s5m-core.h
+373
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/*
* s5m-core.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_S5M_CORE_H
#define __LINUX_MFD_S5M_CORE_H
#define NUM_IRQ_REGS 4
enum s5m_device_type {
S5M8751X,
S5M8763X,
S5M8767X,
};
/* S5M8767 registers */
enum s5m8767_reg {
S5M8767_REG_ID,
S5M8767_REG_INT1,
S5M8767_REG_INT2,
S5M8767_REG_INT3,
S5M8767_REG_INT1M,
S5M8767_REG_INT2M,
S5M8767_REG_INT3M,
S5M8767_REG_STATUS1,
S5M8767_REG_STATUS2,
S5M8767_REG_STATUS3,
S5M8767_REG_CTRL1,
S5M8767_REG_CTRL2,
S5M8767_REG_LOWBAT1,
S5M8767_REG_LOWBAT2,
S5M8767_REG_BUCHG,
S5M8767_REG_DVSRAMP,
S5M8767_REG_DVSTIMER2 = 0x10,
S5M8767_REG_DVSTIMER3,
S5M8767_REG_DVSTIMER4,
S5M8767_REG_LDO1,
S5M8767_REG_LDO2,
S5M8767_REG_LDO3,
S5M8767_REG_LDO4,
S5M8767_REG_LDO5,
S5M8767_REG_LDO6,
S5M8767_REG_LDO7,
S5M8767_REG_LDO8,
S5M8767_REG_LDO9,
S5M8767_REG_LDO10,
S5M8767_REG_LDO11,
S5M8767_REG_LDO12,
S5M8767_REG_LDO13,
S5M8767_REG_LDO14 = 0x20,
S5M8767_REG_LDO15,
S5M8767_REG_LDO16,
S5M8767_REG_LDO17,
S5M8767_REG_LDO18,
S5M8767_REG_LDO19,
S5M8767_REG_LDO20,
S5M8767_REG_LDO21,
S5M8767_REG_LDO22,
S5M8767_REG_LDO23,
S5M8767_REG_LDO24,
S5M8767_REG_LDO25,
S5M8767_REG_LDO26,
S5M8767_REG_LDO27,
S5M8767_REG_LDO28,
S5M8767_REG_UVLO = 0x31,
S5M8767_REG_BUCK1CTRL1,
S5M8767_REG_BUCK1CTRL2,
S5M8767_REG_BUCK2CTRL,
S5M8767_REG_BUCK2DVS1,
S5M8767_REG_BUCK2DVS2,
S5M8767_REG_BUCK2DVS3,
S5M8767_REG_BUCK2DVS4,
S5M8767_REG_BUCK2DVS5,
S5M8767_REG_BUCK2DVS6,
S5M8767_REG_BUCK2DVS7,
S5M8767_REG_BUCK2DVS8,
S5M8767_REG_BUCK3CTRL,
S5M8767_REG_BUCK3DVS1,
S5M8767_REG_BUCK3DVS2,
S5M8767_REG_BUCK3DVS3,
S5M8767_REG_BUCK3DVS4,
S5M8767_REG_BUCK3DVS5,
S5M8767_REG_BUCK3DVS6,
S5M8767_REG_BUCK3DVS7,
S5M8767_REG_BUCK3DVS8,
S5M8767_REG_BUCK4CTRL,
S5M8767_REG_BUCK4DVS1,
S5M8767_REG_BUCK4DVS2,
S5M8767_REG_BUCK4DVS3,
S5M8767_REG_BUCK4DVS4,
S5M8767_REG_BUCK4DVS5,
S5M8767_REG_BUCK4DVS6,
S5M8767_REG_BUCK4DVS7,
S5M8767_REG_BUCK4DVS8,
S5M8767_REG_BUCK5CTRL1,
S5M8767_REG_BUCK5CTRL2,
S5M8767_REG_BUCK5CTRL3,
S5M8767_REG_BUCK5CTRL4,
S5M8767_REG_BUCK5CTRL5,
S5M8767_REG_BUCK6CTRL1,
S5M8767_REG_BUCK6CTRL2,
S5M8767_REG_BUCK7CTRL1,
S5M8767_REG_BUCK7CTRL2,
S5M8767_REG_BUCK8CTRL1,
S5M8767_REG_BUCK8CTRL2,
S5M8767_REG_BUCK9CTRL1,
S5M8767_REG_BUCK9CTRL2,
S5M8767_REG_LDO1CTRL,
S5M8767_REG_LDO2_1CTRL,
S5M8767_REG_LDO2_2CTRL,
S5M8767_REG_LDO2_3CTRL,
S5M8767_REG_LDO2_4CTRL,
S5M8767_REG_LDO3CTRL,
S5M8767_REG_LDO4CTRL,
S5M8767_REG_LDO5CTRL,
S5M8767_REG_LDO6CTRL,
S5M8767_REG_LDO7CTRL,
S5M8767_REG_LDO8CTRL,
S5M8767_REG_LDO9CTRL,
S5M8767_REG_LDO10CTRL,
S5M8767_REG_LDO11CTRL,
S5M8767_REG_LDO12CTRL,
S5M8767_REG_LDO13CTRL,
S5M8767_REG_LDO14CTRL,
S5M8767_REG_LDO15CTRL,
S5M8767_REG_LDO16CTRL,
S5M8767_REG_LDO17CTRL,
S5M8767_REG_LDO18CTRL,
S5M8767_REG_LDO19CTRL,
S5M8767_REG_LDO20CTRL,
S5M8767_REG_LDO21CTRL,
S5M8767_REG_LDO22CTRL,
S5M8767_REG_LDO23CTRL,
S5M8767_REG_LDO24CTRL,
S5M8767_REG_LDO25CTRL,
S5M8767_REG_LDO26CTRL,
S5M8767_REG_LDO27CTRL,
S5M8767_REG_LDO28CTRL,
};
/* S5M8763 registers */
enum s5m8763_reg {
S5M8763_REG_IRQ1,
S5M8763_REG_IRQ2,
S5M8763_REG_IRQ3,
S5M8763_REG_IRQ4,
S5M8763_REG_IRQM1,
S5M8763_REG_IRQM2,
S5M8763_REG_IRQM3,
S5M8763_REG_IRQM4,
S5M8763_REG_STATUS1,
S5M8763_REG_STATUS2,
S5M8763_REG_STATUSM1,
S5M8763_REG_STATUSM2,
S5M8763_REG_CHGR1,
S5M8763_REG_CHGR2,
S5M8763_REG_LDO_ACTIVE_DISCHARGE1,
S5M8763_REG_LDO_ACTIVE_DISCHARGE2,
S5M8763_REG_BUCK_ACTIVE_DISCHARGE3,
S5M8763_REG_ONOFF1,
S5M8763_REG_ONOFF2,
S5M8763_REG_ONOFF3,
S5M8763_REG_ONOFF4,
S5M8763_REG_BUCK1_VOLTAGE1,
S5M8763_REG_BUCK1_VOLTAGE2,
S5M8763_REG_BUCK1_VOLTAGE3,
S5M8763_REG_BUCK1_VOLTAGE4,
S5M8763_REG_BUCK2_VOLTAGE1,
S5M8763_REG_BUCK2_VOLTAGE2,
S5M8763_REG_BUCK3,
S5M8763_REG_BUCK4,
S5M8763_REG_LDO1_LDO2,
S5M8763_REG_LDO3,
S5M8763_REG_LDO4,
S5M8763_REG_LDO5,
S5M8763_REG_LDO6,
S5M8763_REG_LDO7,
S5M8763_REG_LDO7_LDO8,
S5M8763_REG_LDO9_LDO10,
S5M8763_REG_LDO11,
S5M8763_REG_LDO12,
S5M8763_REG_LDO13,
S5M8763_REG_LDO14,
S5M8763_REG_LDO15,
S5M8763_REG_LDO16,
S5M8763_REG_BKCHR,
S5M8763_REG_LBCNFG1,
S5M8763_REG_LBCNFG2,
};
enum s5m8767_irq {
S5M8767_IRQ_PWRR,
S5M8767_IRQ_PWRF,
S5M8767_IRQ_PWR1S,
S5M8767_IRQ_JIGR,
S5M8767_IRQ_JIGF,
S5M8767_IRQ_LOWBAT2,
S5M8767_IRQ_LOWBAT1,
S5M8767_IRQ_MRB,
S5M8767_IRQ_DVSOK2,
S5M8767_IRQ_DVSOK3,
S5M8767_IRQ_DVSOK4,
S5M8767_IRQ_RTC60S,
S5M8767_IRQ_RTCA1,
S5M8767_IRQ_RTCA2,
S5M8767_IRQ_SMPL,
S5M8767_IRQ_RTC1S,
S5M8767_IRQ_WTSR,
S5M8767_IRQ_NR,
};
#define S5M8767_IRQ_PWRR_MASK (1 << 0)
#define S5M8767_IRQ_PWRF_MASK (1 << 1)
#define S5M8767_IRQ_PWR1S_MASK (1 << 3)
#define S5M8767_IRQ_JIGR_MASK (1 << 4)
#define S5M8767_IRQ_JIGF_MASK (1 << 5)
#define S5M8767_IRQ_LOWBAT2_MASK (1 << 6)
#define S5M8767_IRQ_LOWBAT1_MASK (1 << 7)
#define S5M8767_IRQ_MRB_MASK (1 << 2)
#define S5M8767_IRQ_DVSOK2_MASK (1 << 3)
#define S5M8767_IRQ_DVSOK3_MASK (1 << 4)
#define S5M8767_IRQ_DVSOK4_MASK (1 << 5)
#define S5M8767_IRQ_RTC60S_MASK (1 << 0)
#define S5M8767_IRQ_RTCA1_MASK (1 << 1)
#define S5M8767_IRQ_RTCA2_MASK (1 << 2)
#define S5M8767_IRQ_SMPL_MASK (1 << 3)
#define S5M8767_IRQ_RTC1S_MASK (1 << 4)
#define S5M8767_IRQ_WTSR_MASK (1 << 5)
enum s5m8763_irq {
S5M8763_IRQ_DCINF,
S5M8763_IRQ_DCINR,
S5M8763_IRQ_JIGF,
S5M8763_IRQ_JIGR,
S5M8763_IRQ_PWRONF,
S5M8763_IRQ_PWRONR,
S5M8763_IRQ_WTSREVNT,
S5M8763_IRQ_SMPLEVNT,
S5M8763_IRQ_ALARM1,
S5M8763_IRQ_ALARM0,
S5M8763_IRQ_ONKEY1S,
S5M8763_IRQ_TOPOFFR,
S5M8763_IRQ_DCINOVPR,
S5M8763_IRQ_CHGRSTF,
S5M8763_IRQ_DONER,
S5M8763_IRQ_CHGFAULT,
S5M8763_IRQ_LOBAT1,
S5M8763_IRQ_LOBAT2,
S5M8763_IRQ_NR,
};
#define S5M8763_IRQ_DCINF_MASK (1 << 2)
#define S5M8763_IRQ_DCINR_MASK (1 << 3)
#define S5M8763_IRQ_JIGF_MASK (1 << 4)
#define S5M8763_IRQ_JIGR_MASK (1 << 5)
#define S5M8763_IRQ_PWRONF_MASK (1 << 6)
#define S5M8763_IRQ_PWRONR_MASK (1 << 7)
#define S5M8763_IRQ_WTSREVNT_MASK (1 << 0)
#define S5M8763_IRQ_SMPLEVNT_MASK (1 << 1)
#define S5M8763_IRQ_ALARM1_MASK (1 << 2)
#define S5M8763_IRQ_ALARM0_MASK (1 << 3)
#define S5M8763_IRQ_ONKEY1S_MASK (1 << 0)
#define S5M8763_IRQ_TOPOFFR_MASK (1 << 2)
#define S5M8763_IRQ_DCINOVPR_MASK (1 << 3)
#define S5M8763_IRQ_CHGRSTF_MASK (1 << 4)
#define S5M8763_IRQ_DONER_MASK (1 << 5)
#define S5M8763_IRQ_CHGFAULT_MASK (1 << 7)
#define S5M8763_IRQ_LOBAT1_MASK (1 << 0)
#define S5M8763_IRQ_LOBAT2_MASK (1 << 1)
#define S5M8763_ENRAMP (1 << 4)
/**
* struct s5m87xx_dev - s5m87xx master device for sub-drivers
* @dev: master device of the chip (can be used to access platform data)
* @i2c: i2c client private data for regulator
* @rtc: i2c client private data for rtc
* @iolock: mutex for serializing io access
* @irqlock: mutex for buslock
* @irq_base: base IRQ number for s5m87xx, required for IRQs
* @irq: generic IRQ number for s5m87xx
* @ono: power onoff IRQ number for s5m87xx
* @irq_masks_cur: currently active value
* @irq_masks_cache: cached hardware value
* @type: indicate which s5m87xx "variant" is used
*/
struct s5m87xx_dev {
struct device *dev;
struct regmap *regmap;
struct i2c_client *i2c;
struct i2c_client *rtc;
struct mutex iolock;
struct mutex irqlock;
int device_type;
int irq_base;
int irq;
int ono;
u8 irq_masks_cur[NUM_IRQ_REGS];
u8 irq_masks_cache[NUM_IRQ_REGS];
int type;
bool wakeup;
};
int s5m_irq_init(struct s5m87xx_dev *s5m87xx);
void s5m_irq_exit(struct s5m87xx_dev *s5m87xx);
int s5m_irq_resume(struct s5m87xx_dev *s5m87xx);
extern int s5m_reg_read(struct s5m87xx_dev *s5m87xx, u8 reg, void *dest);
extern int s5m_bulk_read(struct s5m87xx_dev *s5m87xx, u8 reg, int count, u8 *buf);
extern int s5m_reg_write(struct s5m87xx_dev *s5m87xx, u8 reg, u8 value);
extern int s5m_bulk_write(struct s5m87xx_dev *s5m87xx, u8 reg, int count, u8 *buf);
extern int s5m_reg_update(struct s5m87xx_dev *s5m87xx, u8 reg, u8 val, u8 mask);
struct s5m_platform_data {
struct s5m_regulator_data *regulators;
int device_type;
int num_regulators;
int irq_base;
int (*cfg_pmic_irq)(void);
int ono;
bool wakeup;
bool buck_voltage_lock;
int buck_gpios[3];
int buck2_voltage[8];
bool buck2_gpiodvs;
int buck3_voltage[8];
bool buck3_gpiodvs;
int buck4_voltage[8];
bool buck4_gpiodvs;
int buck_set1;
int buck_set2;
int buck_set3;
int buck2_enable;
int buck3_enable;
int buck4_enable;
int buck_default_idx;
int buck2_default_idx;
int buck3_default_idx;
int buck4_default_idx;
int buck_ramp_delay;
bool buck2_ramp_enable;
bool buck3_ramp_enable;
bool buck4_ramp_enable;
};
#endif /* __LINUX_MFD_S5M_CORE_H */
kernel/include/linux/mfd/s5m87xx/s5m-pmic.h
+100
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/* s5m87xx.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_MFD_S5M_PMIC_H
#define __LINUX_MFD_S5M_PMIC_H
#include <linux/regulator/machine.h>
/* S5M8767 regulator ids */
enum s5m8767_regulators {
S5M8767_LDO1,
S5M8767_LDO2,
S5M8767_LDO3,
S5M8767_LDO4,
S5M8767_LDO5,
S5M8767_LDO6,
S5M8767_LDO7,
S5M8767_LDO8,
S5M8767_LDO9,
S5M8767_LDO10,
S5M8767_LDO11,
S5M8767_LDO12,
S5M8767_LDO13,
S5M8767_LDO14,
S5M8767_LDO15,
S5M8767_LDO16,
S5M8767_LDO17,
S5M8767_LDO18,
S5M8767_LDO19,
S5M8767_LDO20,
S5M8767_LDO21,
S5M8767_LDO22,
S5M8767_LDO23,
S5M8767_LDO24,
S5M8767_LDO25,
S5M8767_LDO26,
S5M8767_LDO27,
S5M8767_LDO28,
S5M8767_BUCK1,
S5M8767_BUCK2,
S5M8767_BUCK3,
S5M8767_BUCK4,
S5M8767_BUCK5,
S5M8767_BUCK6,
S5M8767_BUCK7,
S5M8767_BUCK8,
S5M8767_BUCK9,
S5M8767_AP_EN32KHZ,
S5M8767_CP_EN32KHZ,
S5M8767_REG_MAX,
};
/* S5M8763 regulator ids */
enum s5m8763_regulators {
S5M8763_LDO1,
S5M8763_LDO2,
S5M8763_LDO3,
S5M8763_LDO4,
S5M8763_LDO5,
S5M8763_LDO6,
S5M8763_LDO7,
S5M8763_LDO8,
S5M8763_LDO9,
S5M8763_LDO10,
S5M8763_LDO11,
S5M8763_LDO12,
S5M8763_LDO13,
S5M8763_LDO14,
S5M8763_LDO15,
S5M8763_LDO16,
S5M8763_BUCK1,
S5M8763_BUCK2,
S5M8763_BUCK3,
S5M8763_BUCK4,
S5M8763_AP_EN32KHZ,
S5M8763_CP_EN32KHZ,
S5M8763_ENCHGVI,
S5M8763_ESAFEUSB1,
S5M8763_ESAFEUSB2,
};
/**
* s5m87xx_regulator_data - regulator data
* @id: regulator id
* @initdata: regulator init data (contraints, supplies, ...)
*/
struct s5m_regulator_data {
int id;
struct regulator_init_data *initdata;
};
#endif /* __LINUX_MFD_S5M_PMIC_H */
kernel/include/linux/mfd/s5m87xx/s5m-rtc.h
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/*
* s5m-rtc.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_S5M_RTC_H
#define __LINUX_MFD_S5M_RTC_H
enum s5m87xx_rtc_reg {
S5M87XX_RTC_SEC,
S5M87XX_RTC_MIN,
S5M87XX_RTC_HOUR,
S5M87XX_RTC_WEEKDAY,
S5M87XX_RTC_DATE,
S5M87XX_RTC_MONTH,
S5M87XX_RTC_YEAR1,
S5M87XX_RTC_YEAR2,
S5M87XX_ALARM0_SEC,
S5M87XX_ALARM0_MIN,
S5M87XX_ALARM0_HOUR,
S5M87XX_ALARM0_WEEKDAY,
S5M87XX_ALARM0_DATE,
S5M87XX_ALARM0_MONTH,
S5M87XX_ALARM0_YEAR1,
S5M87XX_ALARM0_YEAR2,
S5M87XX_ALARM1_SEC,
S5M87XX_ALARM1_MIN,
S5M87XX_ALARM1_HOUR,
S5M87XX_ALARM1_WEEKDAY,
S5M87XX_ALARM1_DATE,
S5M87XX_ALARM1_MONTH,
S5M87XX_ALARM1_YEAR1,
S5M87XX_ALARM1_YEAR2,
S5M87XX_ALARM0_CONF,
S5M87XX_ALARM1_CONF,
S5M87XX_RTC_STATUS,
S5M87XX_WTSR_SMPL_CNTL,
S5M87XX_RTC_UDR_CON,
};
#define RTC_I2C_ADDR (0x0C >> 1)
#define HOUR_12 (1 << 7)
#define HOUR_AMPM (1 << 6)
#define HOUR_PM (1 << 5)
#define ALARM0_STATUS (1 << 1)
#define ALARM1_STATUS (1 << 2)
#define UPDATE_AD (1 << 0)
/* RTC Control Register */
#define BCD_EN_SHIFT 0
#define BCD_EN_MASK (1 << BCD_EN_SHIFT)
#define MODEL24_SHIFT 1
#define MODEL24_MASK (1 << MODEL24_SHIFT)
/* RTC Update Register1 */
#define RTC_UDR_SHIFT 0
#define RTC_UDR_MASK (1 << RTC_UDR_SHIFT)
/* RTC Hour register */
#define HOUR_PM_SHIFT 6
#define HOUR_PM_MASK (1 << HOUR_PM_SHIFT)
/* RTC Alarm Enable */
#define ALARM_ENABLE_SHIFT 7
#define ALARM_ENABLE_MASK (1 << ALARM_ENABLE_SHIFT)
enum {
RTC_SEC = 0,
RTC_MIN,
RTC_HOUR,
RTC_WEEKDAY,
RTC_DATE,
RTC_MONTH,
RTC_YEAR1,
RTC_YEAR2,
};
#endif /* __LINUX_MFD_S5M_RTC_H */
kernel/include/linux/mfd/stmpe.h
+225
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/*
* Copyright (C) ST-Ericsson SA 2010
*
* License Terms: GNU General Public License, version 2
* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
*/
#ifndef __LINUX_MFD_STMPE_H
#define __LINUX_MFD_STMPE_H
#include <linux/mutex.h>
struct device;
enum stmpe_block {
STMPE_BLOCK_GPIO = 1 << 0,
STMPE_BLOCK_KEYPAD = 1 << 1,
STMPE_BLOCK_TOUCHSCREEN = 1 << 2,
STMPE_BLOCK_ADC = 1 << 3,
STMPE_BLOCK_PWM = 1 << 4,
STMPE_BLOCK_ROTATOR = 1 << 5,
};
enum stmpe_partnum {
STMPE610,
STMPE801,
STMPE811,
STMPE1601,
STMPE2401,
STMPE2403,
STMPE_NBR_PARTS
};
/*
* For registers whose locations differ on variants, the correct address is
* obtained by indexing stmpe->regs with one of the following.
*/
enum {
STMPE_IDX_CHIP_ID,
STMPE_IDX_ICR_LSB,
STMPE_IDX_IER_LSB,
STMPE_IDX_ISR_MSB,
STMPE_IDX_GPMR_LSB,
STMPE_IDX_GPSR_LSB,
STMPE_IDX_GPCR_LSB,
STMPE_IDX_GPDR_LSB,
STMPE_IDX_GPEDR_MSB,
STMPE_IDX_GPRER_LSB,
STMPE_IDX_GPFER_LSB,
STMPE_IDX_GPAFR_U_MSB,
STMPE_IDX_IEGPIOR_LSB,
STMPE_IDX_ISGPIOR_MSB,
STMPE_IDX_MAX,
};
struct stmpe_variant_info;
struct stmpe_client_info;
/**
* struct stmpe - STMPE MFD structure
* @lock: lock protecting I/O operations
* @irq_lock: IRQ bus lock
* @dev: device, mostly for dev_dbg()
* @client: client - i2c or spi
* @ci: client specific information
* @partnum: part number
* @variant: the detected STMPE model number
* @regs: list of addresses of registers which are at different addresses on
* different variants. Indexed by one of STMPE_IDX_*.
* @irq: irq number for stmpe
* @irq_base: starting IRQ number for internal IRQs
* @num_gpios: number of gpios, differs for variants
* @ier: cache of IER registers for bus_lock
* @oldier: cache of IER registers for bus_lock
* @pdata: platform data
*/
struct stmpe {
struct mutex lock;
struct mutex irq_lock;
struct device *dev;
void *client;
struct stmpe_client_info *ci;
enum stmpe_partnum partnum;
struct stmpe_variant_info *variant;
const u8 *regs;
int irq;
int irq_base;
int num_gpios;
u8 ier[2];
u8 oldier[2];
struct stmpe_platform_data *pdata;
};
extern int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 data);
extern int stmpe_reg_read(struct stmpe *stmpe, u8 reg);
extern int stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length,
u8 *values);
extern int stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length,
const u8 *values);
extern int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val);
extern int stmpe_set_altfunc(struct stmpe *stmpe, u32 pins,
enum stmpe_block block);
extern int stmpe_enable(struct stmpe *stmpe, unsigned int blocks);
extern int stmpe_disable(struct stmpe *stmpe, unsigned int blocks);
struct matrix_keymap_data;
/**
* struct stmpe_keypad_platform_data - STMPE keypad platform data
* @keymap_data: key map table and size
* @debounce_ms: debounce interval, in ms. Maximum is
* %STMPE_KEYPAD_MAX_DEBOUNCE.
* @scan_count: number of key scanning cycles to confirm key data.
* Maximum is %STMPE_KEYPAD_MAX_SCAN_COUNT.
* @no_autorepeat: disable key autorepeat
*/
struct stmpe_keypad_platform_data {
struct matrix_keymap_data *keymap_data;
unsigned int debounce_ms;
unsigned int scan_count;
bool no_autorepeat;
};
#define STMPE_GPIO_NOREQ_811_TOUCH (0xf0)
/**
* struct stmpe_gpio_platform_data - STMPE GPIO platform data
* @gpio_base: first gpio number assigned. A maximum of
* %STMPE_NR_GPIOS GPIOs will be allocated.
* @norequest_mask: bitmask specifying which GPIOs should _not_ be
* requestable due to different usage (e.g. touch, keypad)
* STMPE_GPIO_NOREQ_* macros can be used here.
* @setup: board specific setup callback.
* @remove: board specific remove callback
*/
struct stmpe_gpio_platform_data {
int gpio_base;
unsigned norequest_mask;
void (*setup)(struct stmpe *stmpe, unsigned gpio_base);
void (*remove)(struct stmpe *stmpe, unsigned gpio_base);
};
/**
* struct stmpe_ts_platform_data - stmpe811 touch screen controller platform
* data
* @sample_time: ADC converstion time in number of clock.
* (0 -> 36 clocks, 1 -> 44 clocks, 2 -> 56 clocks, 3 -> 64 clocks,
* 4 -> 80 clocks, 5 -> 96 clocks, 6 -> 144 clocks),
* recommended is 4.
* @mod_12b: ADC Bit mode (0 -> 10bit ADC, 1 -> 12bit ADC)
* @ref_sel: ADC reference source
* (0 -> internal reference, 1 -> external reference)
* @adc_freq: ADC Clock speed
* (0 -> 1.625 MHz, 1 -> 3.25 MHz, 2 || 3 -> 6.5 MHz)
* @ave_ctrl: Sample average control
* (0 -> 1 sample, 1 -> 2 samples, 2 -> 4 samples, 3 -> 8 samples)
* @touch_det_delay: Touch detect interrupt delay
* (0 -> 10 us, 1 -> 50 us, 2 -> 100 us, 3 -> 500 us,
* 4-> 1 ms, 5 -> 5 ms, 6 -> 10 ms, 7 -> 50 ms)
* recommended is 3
* @settling: Panel driver settling time
* (0 -> 10 us, 1 -> 100 us, 2 -> 500 us, 3 -> 1 ms,
* 4 -> 5 ms, 5 -> 10 ms, 6 for 50 ms, 7 -> 100 ms)
* recommended is 2
* @fraction_z: Length of the fractional part in z
* (fraction_z ([0..7]) = Count of the fractional part)
* recommended is 7
* @i_drive: current limit value of the touchscreen drivers
* (0 -> 20 mA typical 35 mA max, 1 -> 50 mA typical 80 mA max)
*
* */
struct stmpe_ts_platform_data {
u8 sample_time;
u8 mod_12b;
u8 ref_sel;
u8 adc_freq;
u8 ave_ctrl;
u8 touch_det_delay;
u8 settling;
u8 fraction_z;
u8 i_drive;
};
/**
* struct stmpe_platform_data - STMPE platform data
* @id: device id to distinguish between multiple STMPEs on the same board
* @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*)
* @irq_trigger: IRQ trigger to use for the interrupt to the host
* @irq_invert_polarity: IRQ line is connected with reversed polarity
* @autosleep: bool to enable/disable stmpe autosleep
* @autosleep_timeout: inactivity timeout in milliseconds for autosleep
* @irq_base: base IRQ number. %STMPE_NR_IRQS irqs will be used, or
* %STMPE_NR_INTERNAL_IRQS if the GPIO driver is not used.
* @irq_over_gpio: true if gpio is used to get irq
* @irq_gpio: gpio number over which irq will be requested (significant only if
* irq_over_gpio is true)
* @gpio: GPIO-specific platform data
* @keypad: keypad-specific platform data
* @ts: touchscreen-specific platform data
*/
struct stmpe_platform_data {
int id;
unsigned int blocks;
int irq_base;
unsigned int irq_trigger;
bool irq_invert_polarity;
bool autosleep;
bool irq_over_gpio;
int irq_gpio;
int autosleep_timeout;
struct stmpe_gpio_platform_data *gpio;
struct stmpe_keypad_platform_data *keypad;
struct stmpe_ts_platform_data *ts;
};
#define STMPE_NR_INTERNAL_IRQS 9
#define STMPE_INT_GPIO(x) (STMPE_NR_INTERNAL_IRQS + (x))
#define STMPE_NR_GPIOS 24
#define STMPE_NR_IRQS STMPE_INT_GPIO(STMPE_NR_GPIOS)
#endif
kernel/include/linux/mfd/t7l66xb.h
+34
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/*
* This file contains the definitions for the T7L66XB
*
* (C) Copyright 2005 Ian Molton <spyro@f2s.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef MFD_T7L66XB_H
#define MFD_T7L66XB_H
#include <linux/mfd/core.h>
#include <linux/mfd/tmio.h>
struct t7l66xb_platform_data {
int (*enable)(struct platform_device *dev);
int (*disable)(struct platform_device *dev);
int (*suspend)(struct platform_device *dev);
int (*resume)(struct platform_device *dev);
int irq_base; /* The base for subdevice irqs */
struct tmio_nand_data *nand_data;
};
#define IRQ_T7L66XB_MMC (1)
#define IRQ_T7L66XB_NAND (3)
#define T7L66XB_NR_IRQS 8
#endif
kernel/include/linux/mfd/tc3589x.h
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/*
* Copyright (C) ST-Ericsson SA 2010
*
* License Terms: GNU General Public License, version 2
*/
#ifndef __LINUX_MFD_TC3589x_H
#define __LINUX_MFD_TC3589x_H
struct device;
enum tx3589x_block {
TC3589x_BLOCK_GPIO = 1 << 0,
TC3589x_BLOCK_KEYPAD = 1 << 1,
};
#define TC3589x_RSTCTRL_IRQRST (1 << 4)
#define TC3589x_RSTCTRL_TIMRST (1 << 3)
#define TC3589x_RSTCTRL_ROTRST (1 << 2)
#define TC3589x_RSTCTRL_KBDRST (1 << 1)
#define TC3589x_RSTCTRL_GPIRST (1 << 0)
/* Keyboard Configuration Registers */
#define TC3589x_KBDSETTLE_REG 0x01
#define TC3589x_KBDBOUNCE 0x02
#define TC3589x_KBDSIZE 0x03
#define TC3589x_KBCFG_LSB 0x04
#define TC3589x_KBCFG_MSB 0x05
#define TC3589x_KBDIC 0x08
#define TC3589x_KBDMSK 0x09
#define TC3589x_EVTCODE_FIFO 0x10
#define TC3589x_KBDMFS 0x8F
#define TC3589x_IRQST 0x91
#define TC3589x_MANFCODE_MAGIC 0x03
#define TC3589x_MANFCODE 0x80
#define TC3589x_VERSION 0x81
#define TC3589x_IOCFG 0xA7
#define TC3589x_CLKMODE 0x88
#define TC3589x_CLKCFG 0x89
#define TC3589x_CLKEN 0x8A
#define TC3589x_RSTCTRL 0x82
#define TC3589x_EXTRSTN 0x83
#define TC3589x_RSTINTCLR 0x84
/* Pull up/down configuration registers */
#define TC3589x_IOCFG 0xA7
#define TC3589x_IOPULLCFG0_LSB 0xAA
#define TC3589x_IOPULLCFG0_MSB 0xAB
#define TC3589x_IOPULLCFG1_LSB 0xAC
#define TC3589x_IOPULLCFG1_MSB 0xAD
#define TC3589x_IOPULLCFG2_LSB 0xAE
#define TC3589x_GPIOIS0 0xC9
#define TC3589x_GPIOIS1 0xCA
#define TC3589x_GPIOIS2 0xCB
#define TC3589x_GPIOIBE0 0xCC
#define TC3589x_GPIOIBE1 0xCD
#define TC3589x_GPIOIBE2 0xCE
#define TC3589x_GPIOIEV0 0xCF
#define TC3589x_GPIOIEV1 0xD0
#define TC3589x_GPIOIEV2 0xD1
#define TC3589x_GPIOIE0 0xD2
#define TC3589x_GPIOIE1 0xD3
#define TC3589x_GPIOIE2 0xD4
#define TC3589x_GPIORIS0 0xD6
#define TC3589x_GPIORIS1 0xD7
#define TC3589x_GPIORIS2 0xD8
#define TC3589x_GPIOMIS0 0xD9
#define TC3589x_GPIOMIS1 0xDA
#define TC3589x_GPIOMIS2 0xDB
#define TC3589x_GPIOIC0 0xDC
#define TC3589x_GPIOIC1 0xDD
#define TC3589x_GPIOIC2 0xDE
#define TC3589x_GPIODATA0 0xC0
#define TC3589x_GPIOMASK0 0xc1
#define TC3589x_GPIODATA1 0xC2
#define TC3589x_GPIOMASK1 0xc3
#define TC3589x_GPIODATA2 0xC4
#define TC3589x_GPIOMASK2 0xC5
#define TC3589x_GPIODIR0 0xC6
#define TC3589x_GPIODIR1 0xC7
#define TC3589x_GPIODIR2 0xC8
#define TC3589x_GPIOSYNC0 0xE6
#define TC3589x_GPIOSYNC1 0xE7
#define TC3589x_GPIOSYNC2 0xE8
#define TC3589x_GPIOWAKE0 0xE9
#define TC3589x_GPIOWAKE1 0xEA
#define TC3589x_GPIOWAKE2 0xEB
#define TC3589x_GPIOODM0 0xE0
#define TC3589x_GPIOODE0 0xE1
#define TC3589x_GPIOODM1 0xE2
#define TC3589x_GPIOODE1 0xE3
#define TC3589x_GPIOODM2 0xE4
#define TC3589x_GPIOODE2 0xE5
#define TC3589x_INT_GPIIRQ 0
#define TC3589x_INT_TI0IRQ 1
#define TC3589x_INT_TI1IRQ 2
#define TC3589x_INT_TI2IRQ 3
#define TC3589x_INT_ROTIRQ 5
#define TC3589x_INT_KBDIRQ 6
#define TC3589x_INT_PORIRQ 7
#define TC3589x_NR_INTERNAL_IRQS 8
#define TC3589x_INT_GPIO(x) (TC3589x_NR_INTERNAL_IRQS + (x))
struct tc3589x {
struct mutex lock;
struct device *dev;
struct i2c_client *i2c;
int irq_base;
int num_gpio;
struct tc3589x_platform_data *pdata;
};
extern int tc3589x_reg_write(struct tc3589x *tc3589x, u8 reg, u8 data);
extern int tc3589x_reg_read(struct tc3589x *tc3589x, u8 reg);
extern int tc3589x_block_read(struct tc3589x *tc3589x, u8 reg, u8 length,
u8 *values);
extern int tc3589x_block_write(struct tc3589x *tc3589x, u8 reg, u8 length,
const u8 *values);
extern int tc3589x_set_bits(struct tc3589x *tc3589x, u8 reg, u8 mask, u8 val);
/*
* Keypad related platform specific constants
* These values may be modified for fine tuning
*/
#define TC_KPD_ROWS 0x8
#define TC_KPD_COLUMNS 0x8
#define TC_KPD_DEBOUNCE_PERIOD 0xA3
#define TC_KPD_SETTLE_TIME 0xA3
/**
* struct tc35893_platform_data - data structure for platform specific data
* @keymap_data: matrix scan code table for keycodes
* @krow: mask for available rows, value is 0xFF
* @kcol: mask for available columns, value is 0xFF
* @debounce_period: platform specific debounce time
* @settle_time: platform specific settle down time
* @irqtype: type of interrupt, falling or rising edge
* @enable_wakeup: specifies if keypad event can wake up system from sleep
* @no_autorepeat: flag for auto repetition
*/
struct tc3589x_keypad_platform_data {
const struct matrix_keymap_data *keymap_data;
u8 krow;
u8 kcol;
u8 debounce_period;
u8 settle_time;
unsigned long irqtype;
bool enable_wakeup;
bool no_autorepeat;
};
/**
* struct tc3589x_gpio_platform_data - TC3589x GPIO platform data
* @gpio_base: first gpio number assigned to TC3589x. A maximum of
* %TC3589x_NR_GPIOS GPIOs will be allocated.
* @setup: callback for board-specific initialization
* @remove: callback for board-specific teardown
*/
struct tc3589x_gpio_platform_data {
int gpio_base;
void (*setup)(struct tc3589x *tc3589x, unsigned gpio_base);
void (*remove)(struct tc3589x *tc3589x, unsigned gpio_base);
};
/**
* struct tc3589x_platform_data - TC3589x platform data
* @block: bitmask of blocks to enable (use TC3589x_BLOCK_*)
* @irq_base: base IRQ number. %TC3589x_NR_IRQS irqs will be used.
* @gpio: GPIO-specific platform data
* @keypad: keypad-specific platform data
*/
struct tc3589x_platform_data {
unsigned int block;
int irq_base;
struct tc3589x_gpio_platform_data *gpio;
const struct tc3589x_keypad_platform_data *keypad;
};
#define TC3589x_NR_GPIOS 24
#define TC3589x_NR_IRQS TC3589x_INT_GPIO(TC3589x_NR_GPIOS)
#endif
kernel/include/linux/mfd/tc6387xb.h
+20
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/*
* This file contains the definitions for the TC6387XB
*
* (C) Copyright 2005 Ian Molton <spyro@f2s.com>
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
*/
#ifndef MFD_TC6387XB_H
#define MFD_TC6387XB_H
struct tc6387xb_platform_data {
int (*enable)(struct platform_device *dev);
int (*disable)(struct platform_device *dev);
int (*suspend)(struct platform_device *dev);
int (*resume)(struct platform_device *dev);
};
#endif
kernel/include/linux/mfd/tc6393xb.h
+59
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/*
* Toshiba TC6393XB SoC support
*
* Copyright(c) 2005-2006 Chris Humbert
* Copyright(c) 2005 Dirk Opfer
* Copyright(c) 2005 Ian Molton <spyro@f2s.com>
* Copyright(c) 2007 Dmitry Baryshkov
*
* Based on code written by Sharp/Lineo for 2.4 kernels
* Based on locomo.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef MFD_TC6393XB_H
#define MFD_TC6393XB_H
#include <linux/fb.h>
/* Also one should provide the CK3P6MI clock */
struct tc6393xb_platform_data {
u16 scr_pll2cr; /* PLL2 Control */
u16 scr_gper; /* GP Enable */
int (*enable)(struct platform_device *dev);
int (*disable)(struct platform_device *dev);
int (*suspend)(struct platform_device *dev);
int (*resume)(struct platform_device *dev);
int irq_base; /* base for subdevice irqs */
int gpio_base;
int (*setup)(struct platform_device *dev);
void (*teardown)(struct platform_device *dev);
struct tmio_nand_data *nand_data;
struct tmio_fb_data *fb_data;
unsigned resume_restore : 1; /* make special actions
to preserve the state
on suspend/resume */
};
extern int tc6393xb_lcd_mode(struct platform_device *fb,
const struct fb_videomode *mode);
extern int tc6393xb_lcd_set_power(struct platform_device *fb, bool on);
/*
* Relative to irq_base
*/
#define IRQ_TC6393_NAND 0
#define IRQ_TC6393_MMC 1
#define IRQ_TC6393_OHCI 2
#define IRQ_TC6393_FB 4
#define TC6393XB_NR_IRQS 8
#endif
kernel/include/linux/mfd/ti_ssp.h
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/*
* Sequencer Serial Port (SSP) driver for Texas Instruments' SoCs
*
* Copyright (C) 2010 Texas Instruments Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __TI_SSP_H__
#define __TI_SSP_H__
struct ti_ssp_dev_data {
const char *dev_name;
void *pdata;
size_t pdata_size;
};
struct ti_ssp_data {
unsigned long out_clock;
struct ti_ssp_dev_data dev_data[2];
};
struct ti_ssp_spi_data {
unsigned long iosel;
int num_cs;
void (*select)(int cs);
};
/*
* Sequencer port IO pin configuration bits. These do not correlate 1-1 with
* the hardware. The iosel field in the port data combines iosel1 and iosel2,
* and is therefore not a direct map to register space. It is best to use the
* macros below to construct iosel values.
*
* least significant 16 bits --> iosel1
* most significant 16 bits --> iosel2
*/
#define SSP_IN 0x0000
#define SSP_DATA 0x0001
#define SSP_CLOCK 0x0002
#define SSP_CHIPSEL 0x0003
#define SSP_OUT 0x0004
#define SSP_PIN_SEL(pin, v) ((v) << ((pin) * 3))
#define SSP_PIN_MASK(pin) SSP_PIN_SEL(pin, 0x7)
#define SSP_INPUT_SEL(pin) ((pin) << 16)
/* Sequencer port config bits */
#define SSP_EARLY_DIN BIT(8)
#define SSP_DELAY_DOUT BIT(9)
/* Sequence map definitions */
#define SSP_CLK_HIGH BIT(0)
#define SSP_CLK_LOW 0
#define SSP_DATA_HIGH BIT(1)
#define SSP_DATA_LOW 0
#define SSP_CS_HIGH BIT(2)
#define SSP_CS_LOW 0
#define SSP_OUT_MODE BIT(3)
#define SSP_IN_MODE 0
#define SSP_DATA_REG BIT(4)
#define SSP_ADDR_REG 0
#define SSP_OPCODE_DIRECT ((0x0) << 5)
#define SSP_OPCODE_TOGGLE ((0x1) << 5)
#define SSP_OPCODE_SHIFT ((0x2) << 5)
#define SSP_OPCODE_BRANCH0 ((0x4) << 5)
#define SSP_OPCODE_BRANCH1 ((0x5) << 5)
#define SSP_OPCODE_BRANCH ((0x6) << 5)
#define SSP_OPCODE_STOP ((0x7) << 5)
#define SSP_BRANCH(addr) ((addr) << 8)
#define SSP_COUNT(cycles) ((cycles) << 8)
int ti_ssp_raw_read(struct device *dev);
int ti_ssp_raw_write(struct device *dev, u32 val);
int ti_ssp_load(struct device *dev, int offs, u32* prog, int len);
int ti_ssp_run(struct device *dev, u32 pc, u32 input, u32 *output);
int ti_ssp_set_mode(struct device *dev, int mode);
int ti_ssp_set_iosel(struct device *dev, u32 iosel);
#endif /* __TI_SSP_H__ */
kernel/include/linux/mfd/timpani-audio.h
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kernel/include/linux/mfd/tmio.h
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#ifndef MFD_TMIO_H
#define MFD_TMIO_H
#include <linux/device.h>
#include <linux/fb.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#define tmio_ioread8(addr) readb(addr)
#define tmio_ioread16(addr) readw(addr)
#define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
#define tmio_ioread32(addr) \
(((u32) readw((addr))) | (((u32) readw((addr) + 2)) << 16))
#define tmio_iowrite8(val, addr) writeb((val), (addr))
#define tmio_iowrite16(val, addr) writew((val), (addr))
#define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
#define tmio_iowrite32(val, addr) \
do { \
writew((val), (addr)); \
writew((val) >> 16, (addr) + 2); \
} while (0)
#define CNF_CMD 0x04
#define CNF_CTL_BASE 0x10
#define CNF_INT_PIN 0x3d
#define CNF_STOP_CLK_CTL 0x40
#define CNF_GCLK_CTL 0x41
#define CNF_SD_CLK_MODE 0x42
#define CNF_PIN_STATUS 0x44
#define CNF_PWR_CTL_1 0x48
#define CNF_PWR_CTL_2 0x49
#define CNF_PWR_CTL_3 0x4a
#define CNF_CARD_DETECT_MODE 0x4c
#define CNF_SD_SLOT 0x50
#define CNF_EXT_GCLK_CTL_1 0xf0
#define CNF_EXT_GCLK_CTL_2 0xf1
#define CNF_EXT_GCLK_CTL_3 0xf9
#define CNF_SD_LED_EN_1 0xfa
#define CNF_SD_LED_EN_2 0xfe
#define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
#define sd_config_write8(base, shift, reg, val) \
tmio_iowrite8((val), (base) + ((reg) << (shift)))
#define sd_config_write16(base, shift, reg, val) \
tmio_iowrite16((val), (base) + ((reg) << (shift)))
#define sd_config_write32(base, shift, reg, val) \
do { \
tmio_iowrite16((val), (base) + ((reg) << (shift))); \
tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
} while (0)
/* tmio MMC platform flags */
#define TMIO_MMC_WRPROTECT_DISABLE (1 << 0)
/*
* Some controllers can support a 2-byte block size when the bus width
* is configured in 4-bit mode.
*/
#define TMIO_MMC_BLKSZ_2BYTES (1 << 1)
/*
* Some controllers can support SDIO IRQ signalling.
*/
#define TMIO_MMC_SDIO_IRQ (1 << 2)
/*
* Some platforms can detect card insertion events with controller powered
* down, using a GPIO IRQ, in which case they have to fill in cd_irq, cd_gpio,
* and cd_flags fields of struct tmio_mmc_data.
*/
#define TMIO_MMC_HAS_COLD_CD (1 << 3)
/*
* Some controllers require waiting for the SD bus to become
* idle before writing to some registers.
*/
#define TMIO_MMC_HAS_IDLE_WAIT (1 << 4)
/*
* A GPIO is used for card hotplug detection. We need an extra flag for this,
* because 0 is a valid GPIO number too, and requiring users to specify
* cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility.
*/
#define TMIO_MMC_USE_GPIO_CD (1 << 5)
int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
struct tmio_mmc_dma {
void *chan_priv_tx;
void *chan_priv_rx;
int alignment_shift;
};
struct tmio_mmc_host;
/*
* data for the MMC controller
*/
struct tmio_mmc_data {
unsigned int hclk;
unsigned long capabilities;
unsigned long flags;
u32 ocr_mask; /* available voltages */
struct tmio_mmc_dma *dma;
struct device *dev;
unsigned int cd_gpio;
void (*set_pwr)(struct platform_device *host, int state);
void (*set_clk_div)(struct platform_device *host, int state);
int (*get_cd)(struct platform_device *host);
int (*write16_hook)(struct tmio_mmc_host *host, int addr);
};
/*
* This function is deprecated and will be removed soon. Please, convert your
* platform to use drivers/mmc/core/cd-gpio.c
*/
#include <linux/mmc/host.h>
static inline void tmio_mmc_cd_wakeup(struct tmio_mmc_data *pdata)
{
if (pdata)
mmc_detect_change(dev_get_drvdata(pdata->dev),
msecs_to_jiffies(100));
}
/*
* data for the NAND controller
*/
struct tmio_nand_data {
struct nand_bbt_descr *badblock_pattern;
struct mtd_partition *partition;
unsigned int num_partitions;
};
#define FBIO_TMIO_ACC_WRITE 0x7C639300
#define FBIO_TMIO_ACC_SYNC 0x7C639301
struct tmio_fb_data {
int (*lcd_set_power)(struct platform_device *fb_dev,
bool on);
int (*lcd_mode)(struct platform_device *fb_dev,
const struct fb_videomode *mode);
int num_modes;
struct fb_videomode *modes;
/* in mm: size of screen */
int height;
int width;
};
#endif
kernel/include/linux/mfd/tps6105x.h
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/*
* Copyright (C) 2011 ST-Ericsson SA
* Written on behalf of Linaro for ST-Ericsson
*
* Author: Linus Walleij <linus.walleij@linaro.org>
*
* License terms: GNU General Public License (GPL) version 2
*/
#ifndef MFD_TPS6105X_H
#define MFD_TPS6105X_H
#include <linux/i2c.h>
#include <linux/regulator/machine.h>
/*
* Register definitions to all subdrivers
*/
#define TPS6105X_REG_0 0x00
#define TPS6105X_REG0_MODE_SHIFT 6
#define TPS6105X_REG0_MODE_MASK (0x03<<6)
/* These defines for both reg0 and reg1 */
#define TPS6105X_REG0_MODE_SHUTDOWN 0x00
#define TPS6105X_REG0_MODE_TORCH 0x01
#define TPS6105X_REG0_MODE_TORCH_FLASH 0x02
#define TPS6105X_REG0_MODE_VOLTAGE 0x03
#define TPS6105X_REG0_VOLTAGE_SHIFT 4
#define TPS6105X_REG0_VOLTAGE_MASK (3<<4)
#define TPS6105X_REG0_VOLTAGE_450 0
#define TPS6105X_REG0_VOLTAGE_500 1
#define TPS6105X_REG0_VOLTAGE_525 2
#define TPS6105X_REG0_VOLTAGE_500_2 3
#define TPS6105X_REG0_DIMMING_SHIFT 3
#define TPS6105X_REG0_TORCHC_SHIFT 0
#define TPS6105X_REG0_TORCHC_MASK (7<<0)
#define TPS6105X_REG0_TORCHC_0 0x00
#define TPS6105X_REG0_TORCHC_50 0x01
#define TPS6105X_REG0_TORCHC_75 0x02
#define TPS6105X_REG0_TORCHC_100 0x03
#define TPS6105X_REG0_TORCHC_150 0x04
#define TPS6105X_REG0_TORCHC_200 0x05
#define TPS6105X_REG0_TORCHC_250_400 0x06
#define TPS6105X_REG0_TORCHC_250_500 0x07
#define TPS6105X_REG_1 0x01
#define TPS6105X_REG1_MODE_SHIFT 6
#define TPS6105X_REG1_MODE_MASK (0x03<<6)
#define TPS6105X_REG1_MODE_SHUTDOWN 0x00
#define TPS6105X_REG1_MODE_TORCH 0x01
#define TPS6105X_REG1_MODE_TORCH_FLASH 0x02
#define TPS6105X_REG1_MODE_VOLTAGE 0x03
#define TPS6105X_REG_2 0x02
#define TPS6105X_REG_3 0x03
/**
* enum tps6105x_mode - desired mode for the TPS6105x
* @TPS6105X_MODE_SHUTDOWN: this instance is inactive, not used for anything
* @TPS61905X_MODE_TORCH: this instance is used as a LED, usually a while
* LED, for example as backlight or flashlight. If this is set, the
* TPS6105X will register to the LED framework
* @TPS6105X_MODE_TORCH_FLASH: this instance is used as a flashgun, usually
* in a camera
* @TPS6105X_MODE_VOLTAGE: this instance is used as a voltage regulator and
* will register to the regulator framework
*/
enum tps6105x_mode {
TPS6105X_MODE_SHUTDOWN,
TPS6105X_MODE_TORCH,
TPS6105X_MODE_TORCH_FLASH,
TPS6105X_MODE_VOLTAGE,
};
/**
* struct tps6105x_platform_data - TPS61905x platform data
* @mode: what mode this instance shall be operated in,
* this is not selectable at runtime
* @regulator_data: initialization data for the voltage
* regulator if used as a voltage source
*/
struct tps6105x_platform_data {
enum tps6105x_mode mode;
struct regulator_init_data *regulator_data;
};
/**
* struct tps6105x - state holder for the TPS6105x drivers
* @mutex: mutex to serialize I2C accesses
* @i2c_client: corresponding I2C client
* @regulator: regulator device if used in voltage mode
*/
struct tps6105x {
struct tps6105x_platform_data *pdata;
struct mutex lock;
struct i2c_client *client;
struct regulator_dev *regulator;
};
extern int tps6105x_set(struct tps6105x *tps6105x, u8 reg, u8 value);
extern int tps6105x_get(struct tps6105x *tps6105x, u8 reg, u8 *buf);
extern int tps6105x_mask_and_set(struct tps6105x *tps6105x, u8 reg,
u8 bitmask, u8 bitvalues);
#endif
kernel/include/linux/mfd/tps65023.h
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/* Copyright (c) 2009, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __LINUX_I2C_TPS65023_H
#define __LINUX_I2C_TPS65023_H
#ifndef CONFIG_TPS65023
/* Set the output voltage for the DCDC1 convertor */
#define tps65023_set_dcdc1_level(mvolts) (-ENODEV)
/* Read the output voltage from the DCDC1 convertor */
#define tps65023_get_dcdc1_level(mvolts) (-ENODEV)
#else
/* Set the output voltage for the DCDC1 convertor */
extern int tps65023_set_dcdc1_level(int mvolts);
/* Read the output voltage from the DCDC1 convertor */
extern int tps65023_get_dcdc1_level(int *mvolts);
#endif
#endif
kernel/include/linux/mfd/tps6507x.h
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/* linux/mfd/tps6507x.h
*
* Functions to access TPS65070 power management chip.
*
* Copyright (c) 2009 RidgeRun (todd.fischer@ridgerun.com)
*
*
* For licencing details see kernel-base/COPYING
*/
#ifndef __LINUX_MFD_TPS6507X_H
#define __LINUX_MFD_TPS6507X_H
/*
* ----------------------------------------------------------------------------
* Registers, all 8 bits
* ----------------------------------------------------------------------------
*/
/* Register definitions */
#define TPS6507X_REG_PPATH1 0X01
#define TPS6507X_CHG_USB BIT(7)
#define TPS6507X_CHG_AC BIT(6)
#define TPS6507X_CHG_USB_PW_ENABLE BIT(5)
#define TPS6507X_CHG_AC_PW_ENABLE BIT(4)
#define TPS6507X_CHG_AC_CURRENT BIT(2)
#define TPS6507X_CHG_USB_CURRENT BIT(0)
#define TPS6507X_REG_INT 0X02
#define TPS6507X_REG_MASK_AC_USB BIT(7)
#define TPS6507X_REG_MASK_TSC BIT(6)
#define TPS6507X_REG_MASK_PB_IN BIT(5)
#define TPS6507X_REG_TSC_INT BIT(3)
#define TPS6507X_REG_PB_IN_INT BIT(2)
#define TPS6507X_REG_AC_USB_APPLIED BIT(1)
#define TPS6507X_REG_AC_USB_REMOVED BIT(0)
#define TPS6507X_REG_CHGCONFIG0 0X03
#define TPS6507X_REG_CHGCONFIG1 0X04
#define TPS6507X_CON_CTRL1_DCDC1_ENABLE BIT(4)
#define TPS6507X_CON_CTRL1_DCDC2_ENABLE BIT(3)
#define TPS6507X_CON_CTRL1_DCDC3_ENABLE BIT(2)
#define TPS6507X_CON_CTRL1_LDO1_ENABLE BIT(1)
#define TPS6507X_CON_CTRL1_LDO2_ENABLE BIT(0)
#define TPS6507X_REG_CHGCONFIG2 0X05
#define TPS6507X_REG_CHGCONFIG3 0X06
#define TPS6507X_REG_ADCONFIG 0X07
#define TPS6507X_ADCONFIG_AD_ENABLE BIT(7)
#define TPS6507X_ADCONFIG_START_CONVERSION BIT(6)
#define TPS6507X_ADCONFIG_CONVERSION_DONE BIT(5)
#define TPS6507X_ADCONFIG_VREF_ENABLE BIT(4)
#define TPS6507X_ADCONFIG_INPUT_AD_IN1 0
#define TPS6507X_ADCONFIG_INPUT_AD_IN2 1
#define TPS6507X_ADCONFIG_INPUT_AD_IN3 2
#define TPS6507X_ADCONFIG_INPUT_AD_IN4 3
#define TPS6507X_ADCONFIG_INPUT_TS_PIN 4
#define TPS6507X_ADCONFIG_INPUT_BAT_CURRENT 5
#define TPS6507X_ADCONFIG_INPUT_AC_VOLTAGE 6
#define TPS6507X_ADCONFIG_INPUT_SYS_VOLTAGE 7
#define TPS6507X_ADCONFIG_INPUT_CHARGER_VOLTAGE 8
#define TPS6507X_ADCONFIG_INPUT_BAT_VOLTAGE 9
#define TPS6507X_ADCONFIG_INPUT_THRESHOLD_VOLTAGE 10
#define TPS6507X_ADCONFIG_INPUT_ISET1_VOLTAGE 11
#define TPS6507X_ADCONFIG_INPUT_ISET2_VOLTAGE 12
#define TPS6507X_ADCONFIG_INPUT_REAL_TSC 14
#define TPS6507X_ADCONFIG_INPUT_TSC 15
#define TPS6507X_REG_TSCMODE 0X08
#define TPS6507X_TSCMODE_X_POSITION 0
#define TPS6507X_TSCMODE_Y_POSITION 1
#define TPS6507X_TSCMODE_PRESSURE 2
#define TPS6507X_TSCMODE_X_PLATE 3
#define TPS6507X_TSCMODE_Y_PLATE 4
#define TPS6507X_TSCMODE_STANDBY 5
#define TPS6507X_TSCMODE_ADC_INPUT 6
#define TPS6507X_TSCMODE_DISABLE 7
#define TPS6507X_REG_ADRESULT_1 0X09
#define TPS6507X_REG_ADRESULT_2 0X0A
#define TPS6507X_REG_ADRESULT_2_MASK (BIT(1) | BIT(0))
#define TPS6507X_REG_PGOOD 0X0B
#define TPS6507X_REG_PGOODMASK 0X0C
#define TPS6507X_REG_CON_CTRL1 0X0D
#define TPS6507X_CON_CTRL1_DCDC1_ENABLE BIT(4)
#define TPS6507X_CON_CTRL1_DCDC2_ENABLE BIT(3)
#define TPS6507X_CON_CTRL1_DCDC3_ENABLE BIT(2)
#define TPS6507X_CON_CTRL1_LDO1_ENABLE BIT(1)
#define TPS6507X_CON_CTRL1_LDO2_ENABLE BIT(0)
#define TPS6507X_REG_CON_CTRL2 0X0E
#define TPS6507X_REG_CON_CTRL3 0X0F
#define TPS6507X_REG_DEFDCDC1 0X10
#define TPS6507X_DEFDCDC1_DCDC1_EXT_ADJ_EN BIT(7)
#define TPS6507X_DEFDCDC1_DCDC1_MASK 0X3F
#define TPS6507X_REG_DEFDCDC2_LOW 0X11
#define TPS6507X_DEFDCDC2_LOW_DCDC2_MASK 0X3F
#define TPS6507X_REG_DEFDCDC2_HIGH 0X12
#define TPS6507X_DEFDCDC2_HIGH_DCDC2_MASK 0X3F
#define TPS6507X_REG_DEFDCDC3_LOW 0X13
#define TPS6507X_DEFDCDC3_LOW_DCDC3_MASK 0X3F
#define TPS6507X_REG_DEFDCDC3_HIGH 0X14
#define TPS6507X_DEFDCDC3_HIGH_DCDC3_MASK 0X3F
#define TPS6507X_REG_DEFSLEW 0X15
#define TPS6507X_REG_LDO_CTRL1 0X16
#define TPS6507X_REG_LDO_CTRL1_LDO1_MASK 0X0F
#define TPS6507X_REG_DEFLDO2 0X17
#define TPS6507X_REG_DEFLDO2_LDO2_MASK 0X3F
#define TPS6507X_REG_WLED_CTRL1 0X18
#define TPS6507X_REG_WLED_CTRL2 0X19
/* VDCDC MASK */
#define TPS6507X_DEFDCDCX_DCDC_MASK 0X3F
#define TPS6507X_MAX_REGISTER 0X19
/**
* struct tps6507x_board - packages regulator and touchscreen init data
* @tps6507x_regulator_data: regulator initialization values
*
* Board data may be used to initialize regulator and touchscreen.
*/
struct tps6507x_board {
struct regulator_init_data *tps6507x_pmic_init_data;
struct touchscreen_init_data *tps6507x_ts_init_data;
};
/**
* struct tps6507x_dev - tps6507x sub-driver chip access routines
* @read_dev() - I2C register read function
* @write_dev() - I2C register write function
*
* Device data may be used to access the TPS6507x chip
*/
struct tps6507x_dev {
struct device *dev;
struct i2c_client *i2c_client;
int (*read_dev)(struct tps6507x_dev *tps6507x, char reg, int size,
void *dest);
int (*write_dev)(struct tps6507x_dev *tps6507x, char reg, int size,
void *src);
/* Client devices */
struct tps6507x_pmic *pmic;
struct tps6507x_ts *ts;
};
#endif /* __LINUX_MFD_TPS6507X_H */
kernel/include/linux/mfd/tps65090.h
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/*
* Core driver interface for TI TPS65090 PMIC family
*
* Copyright (C) 2012 NVIDIA Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*
*/
#ifndef __LINUX_MFD_TPS65090_H
#define __LINUX_MFD_TPS65090_H
struct tps65090_subdev_info {
int id;
const char *name;
void *platform_data;
};
struct tps65090_platform_data {
int irq_base;
int num_subdevs;
struct tps65090_subdev_info *subdevs;
};
/*
* NOTE: the functions below are not intended for use outside
* of the TPS65090 sub-device drivers
*/
extern int tps65090_write(struct device *dev, int reg, uint8_t val);
extern int tps65090_read(struct device *dev, int reg, uint8_t *val);
extern int tps65090_set_bits(struct device *dev, int reg, uint8_t bit_num);
extern int tps65090_clr_bits(struct device *dev, int reg, uint8_t bit_num);
#endif /*__LINUX_MFD_TPS65090_H */
kernel/include/linux/mfd/tps65217.h
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/*
* linux/mfd/tps65217.h
*
* Functions to access TPS65217 power management chip.
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __LINUX_MFD_TPS65217_H
#define __LINUX_MFD_TPS65217_H
#include <linux/i2c.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
/* I2C ID for TPS65217 part */
#define TPS65217_I2C_ID 0x24
/* All register addresses */
#define TPS65217_REG_CHIPID 0X00
#define TPS65217_REG_PPATH 0X01
#define TPS65217_REG_INT 0X02
#define TPS65217_REG_CHGCONFIG0 0X03
#define TPS65217_REG_CHGCONFIG1 0X04
#define TPS65217_REG_CHGCONFIG2 0X05
#define TPS65217_REG_CHGCONFIG3 0X06
#define TPS65217_REG_WLEDCTRL1 0X07
#define TPS65217_REG_WLEDCTRL2 0X08
#define TPS65217_REG_MUXCTRL 0X09
#define TPS65217_REG_STATUS 0X0A
#define TPS65217_REG_PASSWORD 0X0B
#define TPS65217_REG_PGOOD 0X0C
#define TPS65217_REG_DEFPG 0X0D
#define TPS65217_REG_DEFDCDC1 0X0E
#define TPS65217_REG_DEFDCDC2 0X0F
#define TPS65217_REG_DEFDCDC3 0X10
#define TPS65217_REG_DEFSLEW 0X11
#define TPS65217_REG_DEFLDO1 0X12
#define TPS65217_REG_DEFLDO2 0X13
#define TPS65217_REG_DEFLS1 0X14
#define TPS65217_REG_DEFLS2 0X15
#define TPS65217_REG_ENABLE 0X16
#define TPS65217_REG_DEFUVLO 0X18
#define TPS65217_REG_SEQ1 0X19
#define TPS65217_REG_SEQ2 0X1A
#define TPS65217_REG_SEQ3 0X1B
#define TPS65217_REG_SEQ4 0X1C
#define TPS65217_REG_SEQ5 0X1D
#define TPS65217_REG_SEQ6 0X1E
/* Register field definitions */
#define TPS65217_CHIPID_CHIP_MASK 0xF0
#define TPS65217_CHIPID_REV_MASK 0x0F
#define TPS65217_PPATH_ACSINK_ENABLE BIT(7)
#define TPS65217_PPATH_USBSINK_ENABLE BIT(6)
#define TPS65217_PPATH_AC_PW_ENABLE BIT(5)
#define TPS65217_PPATH_USB_PW_ENABLE BIT(4)
#define TPS65217_PPATH_AC_CURRENT_MASK 0x0C
#define TPS65217_PPATH_USB_CURRENT_MASK 0x03
#define TPS65217_INT_PBM BIT(6)
#define TPS65217_INT_ACM BIT(5)
#define TPS65217_INT_USBM BIT(4)
#define TPS65217_INT_PBI BIT(2)
#define TPS65217_INT_ACI BIT(1)
#define TPS65217_INT_USBI BIT(0)
#define TPS65217_CHGCONFIG0_TREG BIT(7)
#define TPS65217_CHGCONFIG0_DPPM BIT(6)
#define TPS65217_CHGCONFIG0_TSUSP BIT(5)
#define TPS65217_CHGCONFIG0_TERMI BIT(4)
#define TPS65217_CHGCONFIG0_ACTIVE BIT(3)
#define TPS65217_CHGCONFIG0_CHGTOUT BIT(2)
#define TPS65217_CHGCONFIG0_PCHGTOUT BIT(1)
#define TPS65217_CHGCONFIG0_BATTEMP BIT(0)
#define TPS65217_CHGCONFIG1_TMR_MASK 0xC0
#define TPS65217_CHGCONFIG1_TMR_ENABLE BIT(5)
#define TPS65217_CHGCONFIG1_NTC_TYPE BIT(4)
#define TPS65217_CHGCONFIG1_RESET BIT(3)
#define TPS65217_CHGCONFIG1_TERM BIT(2)
#define TPS65217_CHGCONFIG1_SUSP BIT(1)
#define TPS65217_CHGCONFIG1_CHG_EN BIT(0)
#define TPS65217_CHGCONFIG2_DYNTMR BIT(7)
#define TPS65217_CHGCONFIG2_VPREGHG BIT(6)
#define TPS65217_CHGCONFIG2_VOREG_MASK 0x30
#define TPS65217_CHGCONFIG3_ICHRG_MASK 0xC0
#define TPS65217_CHGCONFIG3_DPPMTH_MASK 0x30
#define TPS65217_CHGCONFIG2_PCHRGT BIT(3)
#define TPS65217_CHGCONFIG2_TERMIF 0x06
#define TPS65217_CHGCONFIG2_TRANGE BIT(0)
#define TPS65217_WLEDCTRL1_ISINK_ENABLE BIT(3)
#define TPS65217_WLEDCTRL1_ISEL BIT(2)
#define TPS65217_WLEDCTRL1_FDIM_MASK 0x03
#define TPS65217_WLEDCTRL2_DUTY_MASK 0x7F
#define TPS65217_MUXCTRL_MUX_MASK 0x07
#define TPS65217_STATUS_OFF BIT(7)
#define TPS65217_STATUS_ACPWR BIT(3)
#define TPS65217_STATUS_USBPWR BIT(2)
#define TPS65217_STATUS_PB BIT(0)
#define TPS65217_PASSWORD_REGS_UNLOCK 0x7D
#define TPS65217_PGOOD_LDO3_PG BIT(6)
#define TPS65217_PGOOD_LDO4_PG BIT(5)
#define TPS65217_PGOOD_DC1_PG BIT(4)
#define TPS65217_PGOOD_DC2_PG BIT(3)
#define TPS65217_PGOOD_DC3_PG BIT(2)
#define TPS65217_PGOOD_LDO1_PG BIT(1)
#define TPS65217_PGOOD_LDO2_PG BIT(0)
#define TPS65217_DEFPG_LDO1PGM BIT(3)
#define TPS65217_DEFPG_LDO2PGM BIT(2)
#define TPS65217_DEFPG_PGDLY_MASK 0x03
#define TPS65217_DEFDCDCX_XADJX BIT(7)
#define TPS65217_DEFDCDCX_DCDC_MASK 0x3F
#define TPS65217_DEFSLEW_GO BIT(7)
#define TPS65217_DEFSLEW_GODSBL BIT(6)
#define TPS65217_DEFSLEW_PFM_EN1 BIT(5)
#define TPS65217_DEFSLEW_PFM_EN2 BIT(4)
#define TPS65217_DEFSLEW_PFM_EN3 BIT(3)
#define TPS65217_DEFSLEW_SLEW_MASK 0x07
#define TPS65217_DEFLDO1_LDO1_MASK 0x0F
#define TPS65217_DEFLDO2_TRACK BIT(6)
#define TPS65217_DEFLDO2_LDO2_MASK 0x3F
#define TPS65217_DEFLDO3_LDO3_EN BIT(5)
#define TPS65217_DEFLDO3_LDO3_MASK 0x1F
#define TPS65217_DEFLDO4_LDO4_EN BIT(5)
#define TPS65217_DEFLDO4_LDO4_MASK 0x1F
#define TPS65217_ENABLE_LS1_EN BIT(6)
#define TPS65217_ENABLE_LS2_EN BIT(5)
#define TPS65217_ENABLE_DC1_EN BIT(4)
#define TPS65217_ENABLE_DC2_EN BIT(3)
#define TPS65217_ENABLE_DC3_EN BIT(2)
#define TPS65217_ENABLE_LDO1_EN BIT(1)
#define TPS65217_ENABLE_LDO2_EN BIT(0)
#define TPS65217_DEFUVLO_UVLOHYS BIT(2)
#define TPS65217_DEFUVLO_UVLO_MASK 0x03
#define TPS65217_SEQ1_DC1_SEQ_MASK 0xF0
#define TPS65217_SEQ1_DC2_SEQ_MASK 0x0F
#define TPS65217_SEQ2_DC3_SEQ_MASK 0xF0
#define TPS65217_SEQ2_LDO1_SEQ_MASK 0x0F
#define TPS65217_SEQ3_LDO2_SEQ_MASK 0xF0
#define TPS65217_SEQ3_LDO3_SEQ_MASK 0x0F
#define TPS65217_SEQ4_LDO4_SEQ_MASK 0xF0
#define TPS65217_SEQ5_DLY1_MASK 0xC0
#define TPS65217_SEQ5_DLY2_MASK 0x30
#define TPS65217_SEQ5_DLY3_MASK 0x0C
#define TPS65217_SEQ5_DLY4_MASK 0x03
#define TPS65217_SEQ6_DLY5_MASK 0xC0
#define TPS65217_SEQ6_DLY6_MASK 0x30
#define TPS65217_SEQ6_SEQUP BIT(2)
#define TPS65217_SEQ6_SEQDWN BIT(1)
#define TPS65217_SEQ6_INSTDWN BIT(0)
#define TPS65217_MAX_REGISTER 0x1E
#define TPS65217_PROTECT_NONE 0
#define TPS65217_PROTECT_L1 1
#define TPS65217_PROTECT_L2 2
enum tps65217_regulator_id {
/* DCDC's */
TPS65217_DCDC_1,
TPS65217_DCDC_2,
TPS65217_DCDC_3,
/* LDOs */
TPS65217_LDO_1,
TPS65217_LDO_2,
TPS65217_LDO_3,
TPS65217_LDO_4,
};
#define TPS65217_MAX_REG_ID TPS65217_LDO_4
/* Number of step-down converters available */
#define TPS65217_NUM_DCDC 3
/* Number of LDO voltage regulators available */
#define TPS65217_NUM_LDO 4
/* Number of total regulators available */
#define TPS65217_NUM_REGULATOR (TPS65217_NUM_DCDC + TPS65217_NUM_LDO)
/**
* struct tps65217_board - packages regulator init data
* @tps65217_regulator_data: regulator initialization values
*
* Board data may be used to initialize regulator.
*/
struct tps65217_board {
struct regulator_init_data *tps65217_init_data;
};
/**
* struct tps_info - packages regulator constraints
* @name: Voltage regulator name
* @min_uV: minimum micro volts
* @max_uV: minimum micro volts
* @vsel_to_uv: Function pointer to get voltage from selector
* @uv_to_vsel: Function pointer to get selector from voltage
* @table: Table for non-uniform voltage step-size
* @table_len: Length of the voltage table
* @enable_mask: Regulator enable mask bits
* @set_vout_reg: Regulator output voltage set register
* @set_vout_mask: Regulator output voltage set mask
*
* This data is used to check the regualtor voltage limits while setting.
*/
struct tps_info {
const char *name;
int min_uV;
int max_uV;
int (*vsel_to_uv)(unsigned int vsel);
int (*uv_to_vsel)(int uV, unsigned int *vsel);
const int *table;
unsigned int table_len;
unsigned int enable_mask;
unsigned int set_vout_reg;
unsigned int set_vout_mask;
};
/**
* struct tps65217 - tps65217 sub-driver chip access routines
*
* Device data may be used to access the TPS65217 chip
*/
struct tps65217 {
struct device *dev;
struct tps65217_board *pdata;
struct regulator_desc desc[TPS65217_NUM_REGULATOR];
struct regulator_dev *rdev[TPS65217_NUM_REGULATOR];
struct tps_info *info[TPS65217_NUM_REGULATOR];
struct regmap *regmap;
/* Client devices */
struct platform_device *regulator_pdev[TPS65217_NUM_REGULATOR];
};
static inline struct tps65217 *dev_to_tps65217(struct device *dev)
{
return dev_get_drvdata(dev);
}
int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
unsigned int *val);
int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
unsigned int val, unsigned int level);
int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
unsigned int mask, unsigned int val, unsigned int level);
int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
unsigned int mask, unsigned int level);
#endif /* __LINUX_MFD_TPS65217_H */
kernel/include/linux/mfd/tps6586x.h
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#ifndef __LINUX_MFD_TPS6586X_H
#define __LINUX_MFD_TPS6586X_H
#define TPS6586X_SLEW_RATE_INSTANTLY 0x00
#define TPS6586X_SLEW_RATE_110UV 0x01
#define TPS6586X_SLEW_RATE_220UV 0x02
#define TPS6586X_SLEW_RATE_440UV 0x03
#define TPS6586X_SLEW_RATE_880UV 0x04
#define TPS6586X_SLEW_RATE_1760UV 0x05
#define TPS6586X_SLEW_RATE_3520UV 0x06
#define TPS6586X_SLEW_RATE_7040UV 0x07
#define TPS6586X_SLEW_RATE_SET 0x08
#define TPS6586X_SLEW_RATE_MASK 0x07
enum {
TPS6586X_ID_SM_0,
TPS6586X_ID_SM_1,
TPS6586X_ID_SM_2,
TPS6586X_ID_LDO_0,
TPS6586X_ID_LDO_1,
TPS6586X_ID_LDO_2,
TPS6586X_ID_LDO_3,
TPS6586X_ID_LDO_4,
TPS6586X_ID_LDO_5,
TPS6586X_ID_LDO_6,
TPS6586X_ID_LDO_7,
TPS6586X_ID_LDO_8,
TPS6586X_ID_LDO_9,
TPS6586X_ID_LDO_RTC,
};
enum {
TPS6586X_INT_PLDO_0,
TPS6586X_INT_PLDO_1,
TPS6586X_INT_PLDO_2,
TPS6586X_INT_PLDO_3,
TPS6586X_INT_PLDO_4,
TPS6586X_INT_PLDO_5,
TPS6586X_INT_PLDO_6,
TPS6586X_INT_PLDO_7,
TPS6586X_INT_COMP_DET,
TPS6586X_INT_ADC,
TPS6586X_INT_PLDO_8,
TPS6586X_INT_PLDO_9,
TPS6586X_INT_PSM_0,
TPS6586X_INT_PSM_1,
TPS6586X_INT_PSM_2,
TPS6586X_INT_PSM_3,
TPS6586X_INT_RTC_ALM1,
TPS6586X_INT_ACUSB_OVP,
TPS6586X_INT_USB_DET,
TPS6586X_INT_AC_DET,
TPS6586X_INT_BAT_DET,
TPS6586X_INT_CHG_STAT,
TPS6586X_INT_CHG_TEMP,
TPS6586X_INT_PP,
TPS6586X_INT_RESUME,
TPS6586X_INT_LOW_SYS,
TPS6586X_INT_RTC_ALM2,
};
struct tps6586x_settings {
int slew_rate;
};
struct tps6586x_subdev_info {
int id;
const char *name;
void *platform_data;
};
struct tps6586x_platform_data {
int num_subdevs;
struct tps6586x_subdev_info *subdevs;
int gpio_base;
int irq_base;
};
/*
* NOTE: the functions below are not intended for use outside
* of the TPS6586X sub-device drivers
*/
extern int tps6586x_write(struct device *dev, int reg, uint8_t val);
extern int tps6586x_writes(struct device *dev, int reg, int len, uint8_t *val);
extern int tps6586x_read(struct device *dev, int reg, uint8_t *val);
extern int tps6586x_reads(struct device *dev, int reg, int len, uint8_t *val);
extern int tps6586x_set_bits(struct device *dev, int reg, uint8_t bit_mask);
extern int tps6586x_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
extern int tps6586x_update(struct device *dev, int reg, uint8_t val,
uint8_t mask);
#endif /*__LINUX_MFD_TPS6586X_H */
kernel/include/linux/mfd/tps65910.h
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/*
* tps65910.h -- TI TPS6591x
*
* Copyright 2010-2011 Texas Instruments Inc.
*
* Author: Graeme Gregory <gg@slimlogic.co.uk>
* Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
* Author: Arnaud Deconinck <a-deconinck@ti.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_TPS65910_H
#define __LINUX_MFD_TPS65910_H
#include <linux/gpio.h>
/* TPS chip id list */
#define TPS65910 0
#define TPS65911 1
/* TPS regulator type list */
#define REGULATOR_LDO 0
#define REGULATOR_DCDC 1
/*
* List of registers for component TPS65910
*
*/
#define TPS65910_SECONDS 0x0
#define TPS65910_MINUTES 0x1
#define TPS65910_HOURS 0x2
#define TPS65910_DAYS 0x3
#define TPS65910_MONTHS 0x4
#define TPS65910_YEARS 0x5
#define TPS65910_WEEKS 0x6
#define TPS65910_ALARM_SECONDS 0x8
#define TPS65910_ALARM_MINUTES 0x9
#define TPS65910_ALARM_HOURS 0xA
#define TPS65910_ALARM_DAYS 0xB
#define TPS65910_ALARM_MONTHS 0xC
#define TPS65910_ALARM_YEARS 0xD
#define TPS65910_RTC_CTRL 0x10
#define TPS65910_RTC_STATUS 0x11
#define TPS65910_RTC_INTERRUPTS 0x12
#define TPS65910_RTC_COMP_LSB 0x13
#define TPS65910_RTC_COMP_MSB 0x14
#define TPS65910_RTC_RES_PROG 0x15
#define TPS65910_RTC_RESET_STATUS 0x16
#define TPS65910_BCK1 0x17
#define TPS65910_BCK2 0x18
#define TPS65910_BCK3 0x19
#define TPS65910_BCK4 0x1A
#define TPS65910_BCK5 0x1B
#define TPS65910_PUADEN 0x1C
#define TPS65910_REF 0x1D
#define TPS65910_VRTC 0x1E
#define TPS65910_VIO 0x20
#define TPS65910_VDD1 0x21
#define TPS65910_VDD1_OP 0x22
#define TPS65910_VDD1_SR 0x23
#define TPS65910_VDD2 0x24
#define TPS65910_VDD2_OP 0x25
#define TPS65910_VDD2_SR 0x26
#define TPS65910_VDD3 0x27
#define TPS65910_VDIG1 0x30
#define TPS65910_VDIG2 0x31
#define TPS65910_VAUX1 0x32
#define TPS65910_VAUX2 0x33
#define TPS65910_VAUX33 0x34
#define TPS65910_VMMC 0x35
#define TPS65910_VPLL 0x36
#define TPS65910_VDAC 0x37
#define TPS65910_THERM 0x38
#define TPS65910_BBCH 0x39
#define TPS65910_DCDCCTRL 0x3E
#define TPS65910_DEVCTRL 0x3F
#define TPS65910_DEVCTRL2 0x40
#define TPS65910_SLEEP_KEEP_LDO_ON 0x41
#define TPS65910_SLEEP_KEEP_RES_ON 0x42
#define TPS65910_SLEEP_SET_LDO_OFF 0x43
#define TPS65910_SLEEP_SET_RES_OFF 0x44
#define TPS65910_EN1_LDO_ASS 0x45
#define TPS65910_EN1_SMPS_ASS 0x46
#define TPS65910_EN2_LDO_ASS 0x47
#define TPS65910_EN2_SMPS_ASS 0x48
#define TPS65910_EN3_LDO_ASS 0x49
#define TPS65910_SPARE 0x4A
#define TPS65910_INT_STS 0x50
#define TPS65910_INT_MSK 0x51
#define TPS65910_INT_STS2 0x52
#define TPS65910_INT_MSK2 0x53
#define TPS65910_INT_STS3 0x54
#define TPS65910_INT_MSK3 0x55
#define TPS65910_GPIO0 0x60
#define TPS65910_GPIO1 0x61
#define TPS65910_GPIO2 0x62
#define TPS65910_GPIO3 0x63
#define TPS65910_GPIO4 0x64
#define TPS65910_GPIO5 0x65
#define TPS65910_GPIO6 0x66
#define TPS65910_GPIO7 0x67
#define TPS65910_GPIO8 0x68
#define TPS65910_JTAGVERNUM 0x80
#define TPS65910_MAX_REGISTER 0x80
/*
* List of registers specific to TPS65911
*/
#define TPS65911_VDDCTRL 0x27
#define TPS65911_VDDCTRL_OP 0x28
#define TPS65911_VDDCTRL_SR 0x29
#define TPS65911_LDO1 0x30
#define TPS65911_LDO2 0x31
#define TPS65911_LDO5 0x32
#define TPS65911_LDO8 0x33
#define TPS65911_LDO7 0x34
#define TPS65911_LDO6 0x35
#define TPS65911_LDO4 0x36
#define TPS65911_LDO3 0x37
#define TPS65911_VMBCH 0x6A
#define TPS65911_VMBCH2 0x6B
/*
* List of register bitfields for component TPS65910
*
*/
/*Register BCK1 (0x80) register.RegisterDescription */
#define BCK1_BCKUP_MASK 0xFF
#define BCK1_BCKUP_SHIFT 0
/*Register BCK2 (0x80) register.RegisterDescription */
#define BCK2_BCKUP_MASK 0xFF
#define BCK2_BCKUP_SHIFT 0
/*Register BCK3 (0x80) register.RegisterDescription */
#define BCK3_BCKUP_MASK 0xFF
#define BCK3_BCKUP_SHIFT 0
/*Register BCK4 (0x80) register.RegisterDescription */
#define BCK4_BCKUP_MASK 0xFF
#define BCK4_BCKUP_SHIFT 0
/*Register BCK5 (0x80) register.RegisterDescription */
#define BCK5_BCKUP_MASK 0xFF
#define BCK5_BCKUP_SHIFT 0
/*Register PUADEN (0x80) register.RegisterDescription */
#define PUADEN_EN3P_MASK 0x80
#define PUADEN_EN3P_SHIFT 7
#define PUADEN_I2CCTLP_MASK 0x40
#define PUADEN_I2CCTLP_SHIFT 6
#define PUADEN_I2CSRP_MASK 0x20
#define PUADEN_I2CSRP_SHIFT 5
#define PUADEN_PWRONP_MASK 0x10
#define PUADEN_PWRONP_SHIFT 4
#define PUADEN_SLEEPP_MASK 0x08
#define PUADEN_SLEEPP_SHIFT 3
#define PUADEN_PWRHOLDP_MASK 0x04
#define PUADEN_PWRHOLDP_SHIFT 2
#define PUADEN_BOOT1P_MASK 0x02
#define PUADEN_BOOT1P_SHIFT 1
#define PUADEN_BOOT0P_MASK 0x01
#define PUADEN_BOOT0P_SHIFT 0
/*Register REF (0x80) register.RegisterDescription */
#define REF_VMBCH_SEL_MASK 0x0C
#define REF_VMBCH_SEL_SHIFT 2
#define REF_ST_MASK 0x03
#define REF_ST_SHIFT 0
/*Register VRTC (0x80) register.RegisterDescription */
#define VRTC_VRTC_OFFMASK_MASK 0x08
#define VRTC_VRTC_OFFMASK_SHIFT 3
#define VRTC_ST_MASK 0x03
#define VRTC_ST_SHIFT 0
/*Register VIO (0x80) register.RegisterDescription */
#define VIO_ILMAX_MASK 0xC0
#define VIO_ILMAX_SHIFT 6
#define VIO_SEL_MASK 0x0C
#define VIO_SEL_SHIFT 2
#define VIO_ST_MASK 0x03
#define VIO_ST_SHIFT 0
/*Register VDD1 (0x80) register.RegisterDescription */
#define VDD1_VGAIN_SEL_MASK 0xC0
#define VDD1_VGAIN_SEL_SHIFT 6
#define VDD1_ILMAX_MASK 0x20
#define VDD1_ILMAX_SHIFT 5
#define VDD1_TSTEP_MASK 0x1C
#define VDD1_TSTEP_SHIFT 2
#define VDD1_ST_MASK 0x03
#define VDD1_ST_SHIFT 0
/*Register VDD1_OP (0x80) register.RegisterDescription */
#define VDD1_OP_CMD_MASK 0x80
#define VDD1_OP_CMD_SHIFT 7
#define VDD1_OP_SEL_MASK 0x7F
#define VDD1_OP_SEL_SHIFT 0
/*Register VDD1_SR (0x80) register.RegisterDescription */
#define VDD1_SR_SEL_MASK 0x7F
#define VDD1_SR_SEL_SHIFT 0
/*Register VDD2 (0x80) register.RegisterDescription */
#define VDD2_VGAIN_SEL_MASK 0xC0
#define VDD2_VGAIN_SEL_SHIFT 6
#define VDD2_ILMAX_MASK 0x20
#define VDD2_ILMAX_SHIFT 5
#define VDD2_TSTEP_MASK 0x1C
#define VDD2_TSTEP_SHIFT 2
#define VDD2_ST_MASK 0x03
#define VDD2_ST_SHIFT 0
/*Register VDD2_OP (0x80) register.RegisterDescription */
#define VDD2_OP_CMD_MASK 0x80
#define VDD2_OP_CMD_SHIFT 7
#define VDD2_OP_SEL_MASK 0x7F
#define VDD2_OP_SEL_SHIFT 0
/*Register VDD2_SR (0x80) register.RegisterDescription */
#define VDD2_SR_SEL_MASK 0x7F
#define VDD2_SR_SEL_SHIFT 0
/*Registers VDD1, VDD2 voltage values definitions */
#define VDD1_2_NUM_VOLT_FINE 73
#define VDD1_2_NUM_VOLT_COARSE 3
#define VDD1_2_MIN_VOLT 6000
#define VDD1_2_OFFSET 125
/*Register VDD3 (0x80) register.RegisterDescription */
#define VDD3_CKINEN_MASK 0x04
#define VDD3_CKINEN_SHIFT 2
#define VDD3_ST_MASK 0x03
#define VDD3_ST_SHIFT 0
#define VDDCTRL_MIN_VOLT 6000
#define VDDCTRL_OFFSET 125
/*Registers VDIG (0x80) to VDAC register.RegisterDescription */
#define LDO_SEL_MASK 0x0C
#define LDO_SEL_SHIFT 2
#define LDO_ST_MASK 0x03
#define LDO_ST_SHIFT 0
#define LDO_ST_ON_BIT 0x01
#define LDO_ST_MODE_BIT 0x02
/* Registers LDO1 to LDO8 in tps65910 */
#define LDO1_SEL_MASK 0xFC
#define LDO3_SEL_MASK 0x7C
#define LDO_MIN_VOLT 1000
#define LDO_MAX_VOLT 3300
/*Register VDIG1 (0x80) register.RegisterDescription */
#define VDIG1_SEL_MASK 0x0C
#define VDIG1_SEL_SHIFT 2
#define VDIG1_ST_MASK 0x03
#define VDIG1_ST_SHIFT 0
/*Register VDIG2 (0x80) register.RegisterDescription */
#define VDIG2_SEL_MASK 0x0C
#define VDIG2_SEL_SHIFT 2
#define VDIG2_ST_MASK 0x03
#define VDIG2_ST_SHIFT 0
/*Register VAUX1 (0x80) register.RegisterDescription */
#define VAUX1_SEL_MASK 0x0C
#define VAUX1_SEL_SHIFT 2
#define VAUX1_ST_MASK 0x03
#define VAUX1_ST_SHIFT 0
/*Register VAUX2 (0x80) register.RegisterDescription */
#define VAUX2_SEL_MASK 0x0C
#define VAUX2_SEL_SHIFT 2
#define VAUX2_ST_MASK 0x03
#define VAUX2_ST_SHIFT 0
/*Register VAUX33 (0x80) register.RegisterDescription */
#define VAUX33_SEL_MASK 0x0C
#define VAUX33_SEL_SHIFT 2
#define VAUX33_ST_MASK 0x03
#define VAUX33_ST_SHIFT 0
/*Register VMMC (0x80) register.RegisterDescription */
#define VMMC_SEL_MASK 0x0C
#define VMMC_SEL_SHIFT 2
#define VMMC_ST_MASK 0x03
#define VMMC_ST_SHIFT 0
/*Register VPLL (0x80) register.RegisterDescription */
#define VPLL_SEL_MASK 0x0C
#define VPLL_SEL_SHIFT 2
#define VPLL_ST_MASK 0x03
#define VPLL_ST_SHIFT 0
/*Register VDAC (0x80) register.RegisterDescription */
#define VDAC_SEL_MASK 0x0C
#define VDAC_SEL_SHIFT 2
#define VDAC_ST_MASK 0x03
#define VDAC_ST_SHIFT 0
/*Register THERM (0x80) register.RegisterDescription */
#define THERM_THERM_HD_MASK 0x20
#define THERM_THERM_HD_SHIFT 5
#define THERM_THERM_TS_MASK 0x10
#define THERM_THERM_TS_SHIFT 4
#define THERM_THERM_HDSEL_MASK 0x0C
#define THERM_THERM_HDSEL_SHIFT 2
#define THERM_RSVD1_MASK 0x02
#define THERM_RSVD1_SHIFT 1
#define THERM_THERM_STATE_MASK 0x01
#define THERM_THERM_STATE_SHIFT 0
/*Register BBCH (0x80) register.RegisterDescription */
#define BBCH_BBSEL_MASK 0x06
#define BBCH_BBSEL_SHIFT 1
#define BBCH_BBCHEN_MASK 0x01
#define BBCH_BBCHEN_SHIFT 0
/*Register DCDCCTRL (0x80) register.RegisterDescription */
#define DCDCCTRL_VDD2_PSKIP_MASK 0x20
#define DCDCCTRL_VDD2_PSKIP_SHIFT 5
#define DCDCCTRL_VDD1_PSKIP_MASK 0x10
#define DCDCCTRL_VDD1_PSKIP_SHIFT 4
#define DCDCCTRL_VIO_PSKIP_MASK 0x08
#define DCDCCTRL_VIO_PSKIP_SHIFT 3
#define DCDCCTRL_DCDCCKEXT_MASK 0x04
#define DCDCCTRL_DCDCCKEXT_SHIFT 2
#define DCDCCTRL_DCDCCKSYNC_MASK 0x03
#define DCDCCTRL_DCDCCKSYNC_SHIFT 0
/*Register DEVCTRL (0x80) register.RegisterDescription */
#define DEVCTRL_RTC_PWDN_MASK 0x40
#define DEVCTRL_RTC_PWDN_SHIFT 6
#define DEVCTRL_CK32K_CTRL_MASK 0x20
#define DEVCTRL_CK32K_CTRL_SHIFT 5
#define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10
#define DEVCTRL_SR_CTL_I2C_SEL_SHIFT 4
#define DEVCTRL_DEV_OFF_RST_MASK 0x08
#define DEVCTRL_DEV_OFF_RST_SHIFT 3
#define DEVCTRL_DEV_ON_MASK 0x04
#define DEVCTRL_DEV_ON_SHIFT 2
#define DEVCTRL_DEV_SLP_MASK 0x02
#define DEVCTRL_DEV_SLP_SHIFT 1
#define DEVCTRL_DEV_OFF_MASK 0x01
#define DEVCTRL_DEV_OFF_SHIFT 0
/*Register DEVCTRL2 (0x80) register.RegisterDescription */
#define DEVCTRL2_TSLOT_LENGTH_MASK 0x30
#define DEVCTRL2_TSLOT_LENGTH_SHIFT 4
#define DEVCTRL2_SLEEPSIG_POL_MASK 0x08
#define DEVCTRL2_SLEEPSIG_POL_SHIFT 3
#define DEVCTRL2_PWON_LP_OFF_MASK 0x04
#define DEVCTRL2_PWON_LP_OFF_SHIFT 2
#define DEVCTRL2_PWON_LP_RST_MASK 0x02
#define DEVCTRL2_PWON_LP_RST_SHIFT 1
#define DEVCTRL2_IT_POL_MASK 0x01
#define DEVCTRL2_IT_POL_SHIFT 0
/*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */
#define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80
#define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7
#define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40
#define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT 6
#define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20
#define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT 5
#define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10
#define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT 4
#define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08
#define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT 3
#define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04
#define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT 2
#define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02
#define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT 1
#define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01
#define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0
/*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */
#define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80
#define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7
#define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40
#define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT 6
#define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20
#define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT 5
#define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10
#define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT 4
#define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08
#define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT 3
#define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04
#define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT 2
#define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02
#define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT 1
#define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01
#define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0
/*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */
#define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80
#define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7
#define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40
#define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT 6
#define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20
#define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT 5
#define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10
#define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT 4
#define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08
#define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT 3
#define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04
#define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT 2
#define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02
#define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT 1
#define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01
#define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0
/*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */
#define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80
#define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7
#define SLEEP_SET_RES_OFF_RSVD_MASK 0x60
#define SLEEP_SET_RES_OFF_RSVD_SHIFT 5
#define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10
#define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT 4
#define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08
#define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT 3
#define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04
#define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT 2
#define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02
#define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT 1
#define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01
#define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0
/*Register EN1_LDO_ASS (0x80) register.RegisterDescription */
#define EN1_LDO_ASS_VDAC_EN1_MASK 0x80
#define EN1_LDO_ASS_VDAC_EN1_SHIFT 7
#define EN1_LDO_ASS_VPLL_EN1_MASK 0x40
#define EN1_LDO_ASS_VPLL_EN1_SHIFT 6
#define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20
#define EN1_LDO_ASS_VAUX33_EN1_SHIFT 5
#define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10
#define EN1_LDO_ASS_VAUX2_EN1_SHIFT 4
#define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08
#define EN1_LDO_ASS_VAUX1_EN1_SHIFT 3
#define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04
#define EN1_LDO_ASS_VDIG2_EN1_SHIFT 2
#define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02
#define EN1_LDO_ASS_VDIG1_EN1_SHIFT 1
#define EN1_LDO_ASS_VMMC_EN1_MASK 0x01
#define EN1_LDO_ASS_VMMC_EN1_SHIFT 0
/*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */
#define EN1_SMPS_ASS_RSVD_MASK 0xE0
#define EN1_SMPS_ASS_RSVD_SHIFT 5
#define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10
#define EN1_SMPS_ASS_SPARE_EN1_SHIFT 4
#define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08
#define EN1_SMPS_ASS_VDD3_EN1_SHIFT 3
#define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04
#define EN1_SMPS_ASS_VDD2_EN1_SHIFT 2
#define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02
#define EN1_SMPS_ASS_VDD1_EN1_SHIFT 1
#define EN1_SMPS_ASS_VIO_EN1_MASK 0x01
#define EN1_SMPS_ASS_VIO_EN1_SHIFT 0
/*Register EN2_LDO_ASS (0x80) register.RegisterDescription */
#define EN2_LDO_ASS_VDAC_EN2_MASK 0x80
#define EN2_LDO_ASS_VDAC_EN2_SHIFT 7
#define EN2_LDO_ASS_VPLL_EN2_MASK 0x40
#define EN2_LDO_ASS_VPLL_EN2_SHIFT 6
#define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20
#define EN2_LDO_ASS_VAUX33_EN2_SHIFT 5
#define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10
#define EN2_LDO_ASS_VAUX2_EN2_SHIFT 4
#define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08
#define EN2_LDO_ASS_VAUX1_EN2_SHIFT 3
#define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04
#define EN2_LDO_ASS_VDIG2_EN2_SHIFT 2
#define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02
#define EN2_LDO_ASS_VDIG1_EN2_SHIFT 1
#define EN2_LDO_ASS_VMMC_EN2_MASK 0x01
#define EN2_LDO_ASS_VMMC_EN2_SHIFT 0
/*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */
#define EN2_SMPS_ASS_RSVD_MASK 0xE0
#define EN2_SMPS_ASS_RSVD_SHIFT 5
#define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10
#define EN2_SMPS_ASS_SPARE_EN2_SHIFT 4
#define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08
#define EN2_SMPS_ASS_VDD3_EN2_SHIFT 3
#define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04
#define EN2_SMPS_ASS_VDD2_EN2_SHIFT 2
#define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02
#define EN2_SMPS_ASS_VDD1_EN2_SHIFT 1
#define EN2_SMPS_ASS_VIO_EN2_MASK 0x01
#define EN2_SMPS_ASS_VIO_EN2_SHIFT 0
/*Register EN3_LDO_ASS (0x80) register.RegisterDescription */
#define EN3_LDO_ASS_VDAC_EN3_MASK 0x80
#define EN3_LDO_ASS_VDAC_EN3_SHIFT 7
#define EN3_LDO_ASS_VPLL_EN3_MASK 0x40
#define EN3_LDO_ASS_VPLL_EN3_SHIFT 6
#define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20
#define EN3_LDO_ASS_VAUX33_EN3_SHIFT 5
#define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10
#define EN3_LDO_ASS_VAUX2_EN3_SHIFT 4
#define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08
#define EN3_LDO_ASS_VAUX1_EN3_SHIFT 3
#define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04
#define EN3_LDO_ASS_VDIG2_EN3_SHIFT 2
#define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02
#define EN3_LDO_ASS_VDIG1_EN3_SHIFT 1
#define EN3_LDO_ASS_VMMC_EN3_MASK 0x01
#define EN3_LDO_ASS_VMMC_EN3_SHIFT 0
/*Register SPARE (0x80) register.RegisterDescription */
#define SPARE_SPARE_MASK 0xFF
#define SPARE_SPARE_SHIFT 0
/*Register INT_STS (0x80) register.RegisterDescription */
#define INT_STS_RTC_PERIOD_IT_MASK 0x80
#define INT_STS_RTC_PERIOD_IT_SHIFT 7
#define INT_STS_RTC_ALARM_IT_MASK 0x40
#define INT_STS_RTC_ALARM_IT_SHIFT 6
#define INT_STS_HOTDIE_IT_MASK 0x20
#define INT_STS_HOTDIE_IT_SHIFT 5
#define INT_STS_PWRHOLD_IT_MASK 0x10
#define INT_STS_PWRHOLD_IT_SHIFT 4
#define INT_STS_PWRON_LP_IT_MASK 0x08
#define INT_STS_PWRON_LP_IT_SHIFT 3
#define INT_STS_PWRON_IT_MASK 0x04
#define INT_STS_PWRON_IT_SHIFT 2
#define INT_STS_VMBHI_IT_MASK 0x02
#define INT_STS_VMBHI_IT_SHIFT 1
#define INT_STS_VMBDCH_IT_MASK 0x01
#define INT_STS_VMBDCH_IT_SHIFT 0
/*Register INT_MSK (0x80) register.RegisterDescription */
#define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80
#define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7
#define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40
#define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6
#define INT_MSK_HOTDIE_IT_MSK_MASK 0x20
#define INT_MSK_HOTDIE_IT_MSK_SHIFT 5
#define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10
#define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4
#define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08
#define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3
#define INT_MSK_PWRON_IT_MSK_MASK 0x04
#define INT_MSK_PWRON_IT_MSK_SHIFT 2
#define INT_MSK_VMBHI_IT_MSK_MASK 0x02
#define INT_MSK_VMBHI_IT_MSK_SHIFT 1
#define INT_MSK_VMBDCH_IT_MSK_MASK 0x01
#define INT_MSK_VMBDCH_IT_MSK_SHIFT 0
/*Register INT_STS2 (0x80) register.RegisterDescription */
#define INT_STS2_GPIO3_F_IT_MASK 0x80
#define INT_STS2_GPIO3_F_IT_SHIFT 7
#define INT_STS2_GPIO3_R_IT_MASK 0x40
#define INT_STS2_GPIO3_R_IT_SHIFT 6
#define INT_STS2_GPIO2_F_IT_MASK 0x20
#define INT_STS2_GPIO2_F_IT_SHIFT 5
#define INT_STS2_GPIO2_R_IT_MASK 0x10
#define INT_STS2_GPIO2_R_IT_SHIFT 4
#define INT_STS2_GPIO1_F_IT_MASK 0x08
#define INT_STS2_GPIO1_F_IT_SHIFT 3
#define INT_STS2_GPIO1_R_IT_MASK 0x04
#define INT_STS2_GPIO1_R_IT_SHIFT 2
#define INT_STS2_GPIO0_F_IT_MASK 0x02
#define INT_STS2_GPIO0_F_IT_SHIFT 1
#define INT_STS2_GPIO0_R_IT_MASK 0x01
#define INT_STS2_GPIO0_R_IT_SHIFT 0
/*Register INT_MSK2 (0x80) register.RegisterDescription */
#define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80
#define INT_MSK2_GPIO3_F_IT_MSK_SHIFT 7
#define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40
#define INT_MSK2_GPIO3_R_IT_MSK_SHIFT 6
#define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20
#define INT_MSK2_GPIO2_F_IT_MSK_SHIFT 5
#define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10
#define INT_MSK2_GPIO2_R_IT_MSK_SHIFT 4
#define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08
#define INT_MSK2_GPIO1_F_IT_MSK_SHIFT 3
#define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04
#define INT_MSK2_GPIO1_R_IT_MSK_SHIFT 2
#define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02
#define INT_MSK2_GPIO0_F_IT_MSK_SHIFT 1
#define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01
#define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0
/*Register INT_STS3 (0x80) register.RegisterDescription */
#define INT_STS3_GPIO5_F_IT_MASK 0x08
#define INT_STS3_GPIO5_F_IT_SHIFT 3
#define INT_STS3_GPIO5_R_IT_MASK 0x04
#define INT_STS3_GPIO5_R_IT_SHIFT 2
#define INT_STS3_GPIO4_F_IT_MASK 0x02
#define INT_STS3_GPIO4_F_IT_SHIFT 1
#define INT_STS3_GPIO4_R_IT_MASK 0x01
#define INT_STS3_GPIO4_R_IT_SHIFT 0
/*Register INT_MSK3 (0x80) register.RegisterDescription */
#define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08
#define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3
#define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04
#define INT_MSK3_GPIO5_R_IT_MSK_SHIFT 2
#define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02
#define INT_MSK3_GPIO4_F_IT_MSK_SHIFT 1
#define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01
#define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0
/*Register GPIO (0x80) register.RegisterDescription */
#define GPIO_SLEEP_MASK 0x80
#define GPIO_SLEEP_SHIFT 7
#define GPIO_DEB_MASK 0x10
#define GPIO_DEB_SHIFT 4
#define GPIO_PUEN_MASK 0x08
#define GPIO_PUEN_SHIFT 3
#define GPIO_CFG_MASK 0x04
#define GPIO_CFG_SHIFT 2
#define GPIO_STS_MASK 0x02
#define GPIO_STS_SHIFT 1
#define GPIO_SET_MASK 0x01
#define GPIO_SET_SHIFT 0
/*Register JTAGVERNUM (0x80) register.RegisterDescription */
#define JTAGVERNUM_VERNUM_MASK 0x0F
#define JTAGVERNUM_VERNUM_SHIFT 0
/* Register VDDCTRL (0x27) bit definitions */
#define VDDCTRL_ST_MASK 0x03
#define VDDCTRL_ST_SHIFT 0
/*Register VDDCTRL_OP (0x28) bit definitios */
#define VDDCTRL_OP_CMD_MASK 0x80
#define VDDCTRL_OP_CMD_SHIFT 7
#define VDDCTRL_OP_SEL_MASK 0x7F
#define VDDCTRL_OP_SEL_SHIFT 0
/*Register VDDCTRL_SR (0x29) bit definitions */
#define VDDCTRL_SR_SEL_MASK 0x7F
#define VDDCTRL_SR_SEL_SHIFT 0
/* IRQ Definitions */
#define TPS65910_IRQ_VBAT_VMBDCH 0
#define TPS65910_IRQ_VBAT_VMHI 1
#define TPS65910_IRQ_PWRON 2
#define TPS65910_IRQ_PWRON_LP 3
#define TPS65910_IRQ_PWRHOLD 4
#define TPS65910_IRQ_HOTDIE 5
#define TPS65910_IRQ_RTC_ALARM 6
#define TPS65910_IRQ_RTC_PERIOD 7
#define TPS65910_IRQ_GPIO_R 8
#define TPS65910_IRQ_GPIO_F 9
#define TPS65910_NUM_IRQ 10
#define TPS65911_IRQ_VBAT_VMBDCH 0
#define TPS65911_IRQ_VBAT_VMBDCH2L 1
#define TPS65911_IRQ_VBAT_VMBDCH2H 2
#define TPS65911_IRQ_VBAT_VMHI 3
#define TPS65911_IRQ_PWRON 4
#define TPS65911_IRQ_PWRON_LP 5
#define TPS65911_IRQ_PWRHOLD_F 6
#define TPS65911_IRQ_PWRHOLD_R 7
#define TPS65911_IRQ_HOTDIE 8
#define TPS65911_IRQ_RTC_ALARM 9
#define TPS65911_IRQ_RTC_PERIOD 10
#define TPS65911_IRQ_GPIO0_R 11
#define TPS65911_IRQ_GPIO0_F 12
#define TPS65911_IRQ_GPIO1_R 13
#define TPS65911_IRQ_GPIO1_F 14
#define TPS65911_IRQ_GPIO2_R 15
#define TPS65911_IRQ_GPIO2_F 16
#define TPS65911_IRQ_GPIO3_R 17
#define TPS65911_IRQ_GPIO3_F 18
#define TPS65911_IRQ_GPIO4_R 19
#define TPS65911_IRQ_GPIO4_F 20
#define TPS65911_IRQ_GPIO5_R 21
#define TPS65911_IRQ_GPIO5_F 22
#define TPS65911_IRQ_WTCHDG 23
#define TPS65911_IRQ_PWRDN 24
#define TPS65911_NUM_IRQ 25
/* GPIO Register Definitions */
#define TPS65910_GPIO_DEB BIT(2)
#define TPS65910_GPIO_PUEN BIT(3)
#define TPS65910_GPIO_CFG BIT(2)
#define TPS65910_GPIO_STS BIT(1)
#define TPS65910_GPIO_SET BIT(0)
/* Max number of TPS65910/11 GPIOs */
#define TPS65910_NUM_GPIO 6
#define TPS65911_NUM_GPIO 9
#define TPS6591X_MAX_NUM_GPIO 9
/* Regulator Index Definitions */
#define TPS65910_REG_VRTC 0
#define TPS65910_REG_VIO 1
#define TPS65910_REG_VDD1 2
#define TPS65910_REG_VDD2 3
#define TPS65910_REG_VDD3 4
#define TPS65910_REG_VDIG1 5
#define TPS65910_REG_VDIG2 6
#define TPS65910_REG_VPLL 7
#define TPS65910_REG_VDAC 8
#define TPS65910_REG_VAUX1 9
#define TPS65910_REG_VAUX2 10
#define TPS65910_REG_VAUX33 11
#define TPS65910_REG_VMMC 12
#define TPS65911_REG_VDDCTRL 4
#define TPS65911_REG_LDO1 5
#define TPS65911_REG_LDO2 6
#define TPS65911_REG_LDO3 7
#define TPS65911_REG_LDO4 8
#define TPS65911_REG_LDO5 9
#define TPS65911_REG_LDO6 10
#define TPS65911_REG_LDO7 11
#define TPS65911_REG_LDO8 12
/* Max number of TPS65910/11 regulators */
#define TPS65910_NUM_REGS 13
/* External sleep controls through EN1/EN2/EN3/SLEEP inputs */
#define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 0x1
#define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 0x2
#define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 0x4
#define TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP 0x8
/**
* struct tps65910_board
* Board platform data may be used to initialize regulators.
*/
struct tps65910_board {
int gpio_base;
int irq;
int irq_base;
int vmbch_threshold;
int vmbch2_threshold;
bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO];
unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS];
struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS];
};
/**
* struct tps65910 - tps65910 sub-driver chip access routines
*/
struct tps65910 {
struct device *dev;
struct i2c_client *i2c_client;
struct regmap *regmap;
struct mutex io_mutex;
unsigned int id;
int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest);
int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src);
/* Client devices */
struct tps65910_pmic *pmic;
struct tps65910_rtc *rtc;
struct tps65910_power *power;
/* GPIO Handling */
struct gpio_chip gpio;
/* IRQ Handling */
struct mutex irq_lock;
int chip_irq;
int irq_base;
int irq_num;
u32 irq_mask;
};
struct tps65910_platform_data {
int irq;
int irq_base;
};
int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base);
int tps65910_irq_init(struct tps65910 *tps65910, int irq,
struct tps65910_platform_data *pdata);
int tps65910_irq_exit(struct tps65910 *tps65910);
static inline int tps65910_chip_id(struct tps65910 *tps65910)
{
return tps65910->id;
}
#endif /* __LINUX_MFD_TPS65910_H */
kernel/include/linux/mfd/tps65912.h
+327
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@@ -0,0 +1,327 @@
/*
* tps65912.h -- TI TPS6591x
*
* Copyright 2011 Texas Instruments Inc.
*
* Author: Margarita Olaya <magi@slimlogic.co.uk>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_TPS65912_H
#define __LINUX_MFD_TPS65912_H
/* TPS regulator type list */
#define REGULATOR_LDO 0
#define REGULATOR_DCDC 1
/*
* List of registers for TPS65912
*/
#define TPS65912_DCDC1_CTRL 0x00
#define TPS65912_DCDC2_CTRL 0x01
#define TPS65912_DCDC3_CTRL 0x02
#define TPS65912_DCDC4_CTRL 0x03
#define TPS65912_DCDC1_OP 0x04
#define TPS65912_DCDC1_AVS 0x05
#define TPS65912_DCDC1_LIMIT 0x06
#define TPS65912_DCDC2_OP 0x07
#define TPS65912_DCDC2_AVS 0x08
#define TPS65912_DCDC2_LIMIT 0x09
#define TPS65912_DCDC3_OP 0x0A
#define TPS65912_DCDC3_AVS 0x0B
#define TPS65912_DCDC3_LIMIT 0x0C
#define TPS65912_DCDC4_OP 0x0D
#define TPS65912_DCDC4_AVS 0x0E
#define TPS65912_DCDC4_LIMIT 0x0F
#define TPS65912_LDO1_OP 0x10
#define TPS65912_LDO1_AVS 0x11
#define TPS65912_LDO1_LIMIT 0x12
#define TPS65912_LDO2_OP 0x13
#define TPS65912_LDO2_AVS 0x14
#define TPS65912_LDO2_LIMIT 0x15
#define TPS65912_LDO3_OP 0x16
#define TPS65912_LDO3_AVS 0x17
#define TPS65912_LDO3_LIMIT 0x18
#define TPS65912_LDO4_OP 0x19
#define TPS65912_LDO4_AVS 0x1A
#define TPS65912_LDO4_LIMIT 0x1B
#define TPS65912_LDO5 0x1C
#define TPS65912_LDO6 0x1D
#define TPS65912_LDO7 0x1E
#define TPS65912_LDO8 0x1F
#define TPS65912_LDO9 0x20
#define TPS65912_LDO10 0x21
#define TPS65912_THRM 0x22
#define TPS65912_CLK32OUT 0x23
#define TPS65912_DEVCTRL 0x24
#define TPS65912_DEVCTRL2 0x25
#define TPS65912_I2C_SPI_CFG 0x26
#define TPS65912_KEEP_ON 0x27
#define TPS65912_KEEP_ON2 0x28
#define TPS65912_SET_OFF1 0x29
#define TPS65912_SET_OFF2 0x2A
#define TPS65912_DEF_VOLT 0x2B
#define TPS65912_DEF_VOLT_MAPPING 0x2C
#define TPS65912_DISCHARGE 0x2D
#define TPS65912_DISCHARGE2 0x2E
#define TPS65912_EN1_SET1 0x2F
#define TPS65912_EN1_SET2 0x30
#define TPS65912_EN2_SET1 0x31
#define TPS65912_EN2_SET2 0x32
#define TPS65912_EN3_SET1 0x33
#define TPS65912_EN3_SET2 0x34
#define TPS65912_EN4_SET1 0x35
#define TPS65912_EN4_SET2 0x36
#define TPS65912_PGOOD 0x37
#define TPS65912_PGOOD2 0x38
#define TPS65912_INT_STS 0x39
#define TPS65912_INT_MSK 0x3A
#define TPS65912_INT_STS2 0x3B
#define TPS65912_INT_MSK2 0x3C
#define TPS65912_INT_STS3 0x3D
#define TPS65912_INT_MSK3 0x3E
#define TPS65912_INT_STS4 0x3F
#define TPS65912_INT_MSK4 0x40
#define TPS65912_GPIO1 0x41
#define TPS65912_GPIO2 0x42
#define TPS65912_GPIO3 0x43
#define TPS65912_GPIO4 0x44
#define TPS65912_GPIO5 0x45
#define TPS65912_VMON 0x46
#define TPS65912_LEDA_CTRL1 0x47
#define TPS65912_LEDA_CTRL2 0x48
#define TPS65912_LEDA_CTRL3 0x49
#define TPS65912_LEDA_CTRL4 0x4A
#define TPS65912_LEDA_CTRL5 0x4B
#define TPS65912_LEDA_CTRL6 0x4C
#define TPS65912_LEDA_CTRL7 0x4D
#define TPS65912_LEDA_CTRL8 0x4E
#define TPS65912_LEDB_CTRL1 0x4F
#define TPS65912_LEDB_CTRL2 0x50
#define TPS65912_LEDB_CTRL3 0x51
#define TPS65912_LEDB_CTRL4 0x52
#define TPS65912_LEDB_CTRL5 0x53
#define TPS65912_LEDB_CTRL6 0x54
#define TPS65912_LEDB_CTRL7 0x55
#define TPS65912_LEDB_CTRL8 0x56
#define TPS65912_LEDC_CTRL1 0x57
#define TPS65912_LEDC_CTRL2 0x58
#define TPS65912_LEDC_CTRL3 0x59
#define TPS65912_LEDC_CTRL4 0x5A
#define TPS65912_LEDC_CTRL5 0x5B
#define TPS65912_LEDC_CTRL6 0x5C
#define TPS65912_LEDC_CTRL7 0x5D
#define TPS65912_LEDC_CTRL8 0x5E
#define TPS65912_LED_RAMP_UP_TIME 0x5F
#define TPS65912_LED_RAMP_DOWN_TIME 0x60
#define TPS65912_LED_SEQ_EN 0x61
#define TPS65912_LOADSWITCH 0x62
#define TPS65912_SPARE 0x63
#define TPS65912_VERNUM 0x64
#define TPS6591X_MAX_REGISTER 0x64
/* IRQ Definitions */
#define TPS65912_IRQ_PWRHOLD_F 0
#define TPS65912_IRQ_VMON 1
#define TPS65912_IRQ_PWRON 2
#define TPS65912_IRQ_PWRON_LP 3
#define TPS65912_IRQ_PWRHOLD_R 4
#define TPS65912_IRQ_HOTDIE 5
#define TPS65912_IRQ_GPIO1_R 6
#define TPS65912_IRQ_GPIO1_F 7
#define TPS65912_IRQ_GPIO2_R 8
#define TPS65912_IRQ_GPIO2_F 9
#define TPS65912_IRQ_GPIO3_R 10
#define TPS65912_IRQ_GPIO3_F 11
#define TPS65912_IRQ_GPIO4_R 12
#define TPS65912_IRQ_GPIO4_F 13
#define TPS65912_IRQ_GPIO5_R 14
#define TPS65912_IRQ_GPIO5_F 15
#define TPS65912_IRQ_PGOOD_DCDC1 16
#define TPS65912_IRQ_PGOOD_DCDC2 17
#define TPS65912_IRQ_PGOOD_DCDC3 18
#define TPS65912_IRQ_PGOOD_DCDC4 19
#define TPS65912_IRQ_PGOOD_LDO1 20
#define TPS65912_IRQ_PGOOD_LDO2 21
#define TPS65912_IRQ_PGOOD_LDO3 22
#define TPS65912_IRQ_PGOOD_LDO4 23
#define TPS65912_IRQ_PGOOD_LDO5 24
#define TPS65912_IRQ_PGOOD_LDO6 25
#define TPS65912_IRQ_PGOOD_LDO7 26
#define TPS65912_IRQ_PGOOD_LD08 27
#define TPS65912_IRQ_PGOOD_LDO9 28
#define TPS65912_IRQ_PGOOD_LDO10 29
#define TPS65912_NUM_IRQ 30
/* GPIO 1 and 2 Register Definitions */
#define GPIO_SLEEP_MASK 0x80
#define GPIO_SLEEP_SHIFT 7
#define GPIO_DEB_MASK 0x10
#define GPIO_DEB_SHIFT 4
#define GPIO_CFG_MASK 0x04
#define GPIO_CFG_SHIFT 2
#define GPIO_STS_MASK 0x02
#define GPIO_STS_SHIFT 1
#define GPIO_SET_MASK 0x01
#define GPIO_SET_SHIFT 0
/* GPIO 3 Register Definitions */
#define GPIO3_SLEEP_MASK 0x80
#define GPIO3_SLEEP_SHIFT 7
#define GPIO3_SEL_MASK 0x40
#define GPIO3_SEL_SHIFT 6
#define GPIO3_ODEN_MASK 0x20
#define GPIO3_ODEN_SHIFT 5
#define GPIO3_DEB_MASK 0x10
#define GPIO3_DEB_SHIFT 4
#define GPIO3_PDEN_MASK 0x08
#define GPIO3_PDEN_SHIFT 3
#define GPIO3_CFG_MASK 0x04
#define GPIO3_CFG_SHIFT 2
#define GPIO3_STS_MASK 0x02
#define GPIO3_STS_SHIFT 1
#define GPIO3_SET_MASK 0x01
#define GPIO3_SET_SHIFT 0
/* GPIO 4 Register Definitions */
#define GPIO4_SLEEP_MASK 0x80
#define GPIO4_SLEEP_SHIFT 7
#define GPIO4_SEL_MASK 0x40
#define GPIO4_SEL_SHIFT 6
#define GPIO4_ODEN_MASK 0x20
#define GPIO4_ODEN_SHIFT 5
#define GPIO4_DEB_MASK 0x10
#define GPIO4_DEB_SHIFT 4
#define GPIO4_PDEN_MASK 0x08
#define GPIO4_PDEN_SHIFT 3
#define GPIO4_CFG_MASK 0x04
#define GPIO4_CFG_SHIFT 2
#define GPIO4_STS_MASK 0x02
#define GPIO4_STS_SHIFT 1
#define GPIO4_SET_MASK 0x01
#define GPIO4_SET_SHIFT 0
/* Register THERM (0x80) register.RegisterDescription */
#define THERM_THERM_HD_MASK 0x20
#define THERM_THERM_HD_SHIFT 5
#define THERM_THERM_TS_MASK 0x10
#define THERM_THERM_TS_SHIFT 4
#define THERM_THERM_HDSEL_MASK 0x0C
#define THERM_THERM_HDSEL_SHIFT 2
#define THERM_RSVD1_MASK 0x02
#define THERM_RSVD1_SHIFT 1
#define THERM_THERM_STATE_MASK 0x01
#define THERM_THERM_STATE_SHIFT 0
/* Register DCDCCTRL1 register.RegisterDescription */
#define DCDCCTRL_VCON_ENABLE_MASK 0x80
#define DCDCCTRL_VCON_ENABLE_SHIFT 7
#define DCDCCTRL_VCON_RANGE1_MASK 0x40
#define DCDCCTRL_VCON_RANGE1_SHIFT 6
#define DCDCCTRL_VCON_RANGE0_MASK 0x20
#define DCDCCTRL_VCON_RANGE0_SHIFT 5
#define DCDCCTRL_TSTEP2_MASK 0x10
#define DCDCCTRL_TSTEP2_SHIFT 4
#define DCDCCTRL_TSTEP1_MASK 0x08
#define DCDCCTRL_TSTEP1_SHIFT 3
#define DCDCCTRL_TSTEP0_MASK 0x04
#define DCDCCTRL_TSTEP0_SHIFT 2
#define DCDCCTRL_DCDC1_MODE_MASK 0x02
#define DCDCCTRL_DCDC1_MODE_SHIFT 1
/* Register DCDCCTRL2 and DCDCCTRL3 register.RegisterDescription */
#define DCDCCTRL_TSTEP2_MASK 0x10
#define DCDCCTRL_TSTEP2_SHIFT 4
#define DCDCCTRL_TSTEP1_MASK 0x08
#define DCDCCTRL_TSTEP1_SHIFT 3
#define DCDCCTRL_TSTEP0_MASK 0x04
#define DCDCCTRL_TSTEP0_SHIFT 2
#define DCDCCTRL_DCDC_MODE_MASK 0x02
#define DCDCCTRL_DCDC_MODE_SHIFT 1
#define DCDCCTRL_RSVD0_MASK 0x01
#define DCDCCTRL_RSVD0_SHIFT 0
/* Register DCDCCTRL4 register.RegisterDescription */
#define DCDCCTRL_RAMP_TIME_MASK 0x01
#define DCDCCTRL_RAMP_TIME_SHIFT 0
/* Register DCDCx_AVS */
#define DCDC_AVS_ENABLE_MASK 0x80
#define DCDC_AVS_ENABLE_SHIFT 7
#define DCDC_AVS_ECO_MASK 0x40
#define DCDC_AVS_ECO_SHIFT 6
/* Register DCDCx_LIMIT */
#define DCDC_LIMIT_RANGE_MASK 0xC0
#define DCDC_LIMIT_RANGE_SHIFT 6
#define DCDC_LIMIT_MAX_SEL_MASK 0x3F
#define DCDC_LIMIT_MAX_SEL_SHIFT 0
/**
* struct tps65912_board
* Board platform dat may be used to initialize regulators.
*/
struct tps65912_board {
int is_dcdc1_avs;
int is_dcdc2_avs;
int is_dcdc3_avs;
int is_dcdc4_avs;
int irq;
int irq_base;
int gpio_base;
struct regulator_init_data *tps65912_pmic_init_data;
};
/**
* struct tps65912 - tps65912 sub-driver chip access routines
*/
struct tps65912 {
struct device *dev;
/* for read/write acces */
struct mutex io_mutex;
/* For device IO interfaces: I2C or SPI */
void *control_data;
int (*read)(struct tps65912 *tps65912, u8 reg, int size, void *dest);
int (*write)(struct tps65912 *tps65912, u8 reg, int size, void *src);
/* Client devices */
struct tps65912_pmic *pmic;
/* GPIO Handling */
struct gpio_chip gpio;
/* IRQ Handling */
struct mutex irq_lock;
int chip_irq;
int irq_base;
int irq_num;
u32 irq_mask;
};
struct tps65912_platform_data {
int irq;
int irq_base;
};
unsigned int tps_chip(void);
int tps65912_set_bits(struct tps65912 *tps65912, u8 reg, u8 mask);
int tps65912_clear_bits(struct tps65912 *tps65912, u8 reg, u8 mask);
int tps65912_reg_read(struct tps65912 *tps65912, u8 reg);
int tps65912_reg_write(struct tps65912 *tps65912, u8 reg, u8 val);
int tps65912_device_init(struct tps65912 *tps65912);
void tps65912_device_exit(struct tps65912 *tps65912);
int tps65912_irq_init(struct tps65912 *tps65912, int irq,
struct tps65912_platform_data *pdata);
#endif /* __LINUX_MFD_TPS65912_H */
kernel/include/linux/mfd/twl4030-audio.h
+272
View File
@@ -0,0 +1,272 @@
/*
* MFD driver for twl4030 audio submodule
*
* Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
*
* Copyright: (C) 2009 Nokia Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#ifndef __TWL4030_CODEC_H__
#define __TWL4030_CODEC_H__
/* Codec registers */
#define TWL4030_REG_CODEC_MODE 0x01
#define TWL4030_REG_OPTION 0x02
#define TWL4030_REG_UNKNOWN 0x03
#define TWL4030_REG_MICBIAS_CTL 0x04
#define TWL4030_REG_ANAMICL 0x05
#define TWL4030_REG_ANAMICR 0x06
#define TWL4030_REG_AVADC_CTL 0x07
#define TWL4030_REG_ADCMICSEL 0x08
#define TWL4030_REG_DIGMIXING 0x09
#define TWL4030_REG_ATXL1PGA 0x0A
#define TWL4030_REG_ATXR1PGA 0x0B
#define TWL4030_REG_AVTXL2PGA 0x0C
#define TWL4030_REG_AVTXR2PGA 0x0D
#define TWL4030_REG_AUDIO_IF 0x0E
#define TWL4030_REG_VOICE_IF 0x0F
#define TWL4030_REG_ARXR1PGA 0x10
#define TWL4030_REG_ARXL1PGA 0x11
#define TWL4030_REG_ARXR2PGA 0x12
#define TWL4030_REG_ARXL2PGA 0x13
#define TWL4030_REG_VRXPGA 0x14
#define TWL4030_REG_VSTPGA 0x15
#define TWL4030_REG_VRX2ARXPGA 0x16
#define TWL4030_REG_AVDAC_CTL 0x17
#define TWL4030_REG_ARX2VTXPGA 0x18
#define TWL4030_REG_ARXL1_APGA_CTL 0x19
#define TWL4030_REG_ARXR1_APGA_CTL 0x1A
#define TWL4030_REG_ARXL2_APGA_CTL 0x1B
#define TWL4030_REG_ARXR2_APGA_CTL 0x1C
#define TWL4030_REG_ATX2ARXPGA 0x1D
#define TWL4030_REG_BT_IF 0x1E
#define TWL4030_REG_BTPGA 0x1F
#define TWL4030_REG_BTSTPGA 0x20
#define TWL4030_REG_EAR_CTL 0x21
#define TWL4030_REG_HS_SEL 0x22
#define TWL4030_REG_HS_GAIN_SET 0x23
#define TWL4030_REG_HS_POPN_SET 0x24
#define TWL4030_REG_PREDL_CTL 0x25
#define TWL4030_REG_PREDR_CTL 0x26
#define TWL4030_REG_PRECKL_CTL 0x27
#define TWL4030_REG_PRECKR_CTL 0x28
#define TWL4030_REG_HFL_CTL 0x29
#define TWL4030_REG_HFR_CTL 0x2A
#define TWL4030_REG_ALC_CTL 0x2B
#define TWL4030_REG_ALC_SET1 0x2C
#define TWL4030_REG_ALC_SET2 0x2D
#define TWL4030_REG_BOOST_CTL 0x2E
#define TWL4030_REG_SOFTVOL_CTL 0x2F
#define TWL4030_REG_DTMF_FREQSEL 0x30
#define TWL4030_REG_DTMF_TONEXT1H 0x31
#define TWL4030_REG_DTMF_TONEXT1L 0x32
#define TWL4030_REG_DTMF_TONEXT2H 0x33
#define TWL4030_REG_DTMF_TONEXT2L 0x34
#define TWL4030_REG_DTMF_TONOFF 0x35
#define TWL4030_REG_DTMF_WANONOFF 0x36
#define TWL4030_REG_I2S_RX_SCRAMBLE_H 0x37
#define TWL4030_REG_I2S_RX_SCRAMBLE_M 0x38
#define TWL4030_REG_I2S_RX_SCRAMBLE_L 0x39
#define TWL4030_REG_APLL_CTL 0x3A
#define TWL4030_REG_DTMF_CTL 0x3B
#define TWL4030_REG_DTMF_PGA_CTL2 0x3C
#define TWL4030_REG_DTMF_PGA_CTL1 0x3D
#define TWL4030_REG_MISC_SET_1 0x3E
#define TWL4030_REG_PCMBTMUX 0x3F
#define TWL4030_REG_RX_PATH_SEL 0x43
#define TWL4030_REG_VDL_APGA_CTL 0x44
#define TWL4030_REG_VIBRA_CTL 0x45
#define TWL4030_REG_VIBRA_SET 0x46
#define TWL4030_REG_VIBRA_PWM_SET 0x47
#define TWL4030_REG_ANAMIC_GAIN 0x48
#define TWL4030_REG_MISC_SET_2 0x49
/* Bitfield Definitions */
/* TWL4030_CODEC_MODE (0x01) Fields */
#define TWL4030_APLL_RATE 0xF0
#define TWL4030_APLL_RATE_8000 0x00
#define TWL4030_APLL_RATE_11025 0x10
#define TWL4030_APLL_RATE_12000 0x20
#define TWL4030_APLL_RATE_16000 0x40
#define TWL4030_APLL_RATE_22050 0x50
#define TWL4030_APLL_RATE_24000 0x60
#define TWL4030_APLL_RATE_32000 0x80
#define TWL4030_APLL_RATE_44100 0x90
#define TWL4030_APLL_RATE_48000 0xA0
#define TWL4030_APLL_RATE_96000 0xE0
#define TWL4030_SEL_16K 0x08
#define TWL4030_CODECPDZ 0x02
#define TWL4030_OPT_MODE 0x01
#define TWL4030_OPTION_1 (1 << 0)
#define TWL4030_OPTION_2 (0 << 0)
/* TWL4030_OPTION (0x02) Fields */
#define TWL4030_ATXL1_EN (1 << 0)
#define TWL4030_ATXR1_EN (1 << 1)
#define TWL4030_ATXL2_VTXL_EN (1 << 2)
#define TWL4030_ATXR2_VTXR_EN (1 << 3)
#define TWL4030_ARXL1_VRX_EN (1 << 4)
#define TWL4030_ARXR1_EN (1 << 5)
#define TWL4030_ARXL2_EN (1 << 6)
#define TWL4030_ARXR2_EN (1 << 7)
/* TWL4030_REG_MICBIAS_CTL (0x04) Fields */
#define TWL4030_MICBIAS2_CTL 0x40
#define TWL4030_MICBIAS1_CTL 0x20
#define TWL4030_HSMICBIAS_EN 0x04
#define TWL4030_MICBIAS2_EN 0x02
#define TWL4030_MICBIAS1_EN 0x01
/* ANAMICL (0x05) Fields */
#define TWL4030_CNCL_OFFSET_START 0x80
#define TWL4030_OFFSET_CNCL_SEL 0x60
#define TWL4030_OFFSET_CNCL_SEL_ARX1 0x00
#define TWL4030_OFFSET_CNCL_SEL_ARX2 0x20
#define TWL4030_OFFSET_CNCL_SEL_VRX 0x40
#define TWL4030_OFFSET_CNCL_SEL_ALL 0x60
#define TWL4030_MICAMPL_EN 0x10
#define TWL4030_CKMIC_EN 0x08
#define TWL4030_AUXL_EN 0x04
#define TWL4030_HSMIC_EN 0x02
#define TWL4030_MAINMIC_EN 0x01
/* ANAMICR (0x06) Fields */
#define TWL4030_MICAMPR_EN 0x10
#define TWL4030_AUXR_EN 0x04
#define TWL4030_SUBMIC_EN 0x01
/* AVADC_CTL (0x07) Fields */
#define TWL4030_ADCL_EN 0x08
#define TWL4030_AVADC_CLK_PRIORITY 0x04
#define TWL4030_ADCR_EN 0x02
/* TWL4030_REG_ADCMICSEL (0x08) Fields */
#define TWL4030_DIGMIC1_EN 0x08
#define TWL4030_TX2IN_SEL 0x04
#define TWL4030_DIGMIC0_EN 0x02
#define TWL4030_TX1IN_SEL 0x01
/* AUDIO_IF (0x0E) Fields */
#define TWL4030_AIF_SLAVE_EN 0x80
#define TWL4030_DATA_WIDTH 0x60
#define TWL4030_DATA_WIDTH_16S_16W 0x00
#define TWL4030_DATA_WIDTH_32S_16W 0x40
#define TWL4030_DATA_WIDTH_32S_24W 0x60
#define TWL4030_AIF_FORMAT 0x18
#define TWL4030_AIF_FORMAT_CODEC 0x00
#define TWL4030_AIF_FORMAT_LEFT 0x08
#define TWL4030_AIF_FORMAT_RIGHT 0x10
#define TWL4030_AIF_FORMAT_TDM 0x18
#define TWL4030_AIF_TRI_EN 0x04
#define TWL4030_CLK256FS_EN 0x02
#define TWL4030_AIF_EN 0x01
/* VOICE_IF (0x0F) Fields */
#define TWL4030_VIF_SLAVE_EN 0x80
#define TWL4030_VIF_DIN_EN 0x40
#define TWL4030_VIF_DOUT_EN 0x20
#define TWL4030_VIF_SWAP 0x10
#define TWL4030_VIF_FORMAT 0x08
#define TWL4030_VIF_TRI_EN 0x04
#define TWL4030_VIF_SUB_EN 0x02
#define TWL4030_VIF_EN 0x01
/* EAR_CTL (0x21) */
#define TWL4030_EAR_GAIN 0x30
/* HS_GAIN_SET (0x23) Fields */
#define TWL4030_HSR_GAIN 0x0C
#define TWL4030_HSR_GAIN_PWR_DOWN 0x00
#define TWL4030_HSR_GAIN_PLUS_6DB 0x04
#define TWL4030_HSR_GAIN_0DB 0x08
#define TWL4030_HSR_GAIN_MINUS_6DB 0x0C
#define TWL4030_HSL_GAIN 0x03
#define TWL4030_HSL_GAIN_PWR_DOWN 0x00
#define TWL4030_HSL_GAIN_PLUS_6DB 0x01
#define TWL4030_HSL_GAIN_0DB 0x02
#define TWL4030_HSL_GAIN_MINUS_6DB 0x03
/* HS_POPN_SET (0x24) Fields */
#define TWL4030_VMID_EN 0x40
#define TWL4030_EXTMUTE 0x20
#define TWL4030_RAMP_DELAY 0x1C
#define TWL4030_RAMP_DELAY_20MS 0x00
#define TWL4030_RAMP_DELAY_40MS 0x04
#define TWL4030_RAMP_DELAY_81MS 0x08
#define TWL4030_RAMP_DELAY_161MS 0x0C
#define TWL4030_RAMP_DELAY_323MS 0x10
#define TWL4030_RAMP_DELAY_645MS 0x14
#define TWL4030_RAMP_DELAY_1291MS 0x18
#define TWL4030_RAMP_DELAY_2581MS 0x1C
#define TWL4030_RAMP_EN 0x02
/* PREDL_CTL (0x25) */
#define TWL4030_PREDL_GAIN 0x30
/* PREDR_CTL (0x26) */
#define TWL4030_PREDR_GAIN 0x30
/* PRECKL_CTL (0x27) */
#define TWL4030_PRECKL_GAIN 0x30
/* PRECKR_CTL (0x28) */
#define TWL4030_PRECKR_GAIN 0x30
/* HFL_CTL (0x29, 0x2A) Fields */
#define TWL4030_HF_CTL_HB_EN 0x04
#define TWL4030_HF_CTL_LOOP_EN 0x08
#define TWL4030_HF_CTL_RAMP_EN 0x10
#define TWL4030_HF_CTL_REF_EN 0x20
/* APLL_CTL (0x3A) Fields */
#define TWL4030_APLL_EN 0x10
#define TWL4030_APLL_INFREQ 0x0F
#define TWL4030_APLL_INFREQ_19200KHZ 0x05
#define TWL4030_APLL_INFREQ_26000KHZ 0x06
#define TWL4030_APLL_INFREQ_38400KHZ 0x0F
/* REG_MISC_SET_1 (0x3E) Fields */
#define TWL4030_CLK64_EN 0x80
#define TWL4030_SCRAMBLE_EN 0x40
#define TWL4030_FMLOOP_EN 0x20
#define TWL4030_SMOOTH_ANAVOL_EN 0x02
#define TWL4030_DIGMIC_LR_SWAP_EN 0x01
/* VIBRA_CTL (0x45) */
#define TWL4030_VIBRA_EN 0x01
#define TWL4030_VIBRA_DIR 0x02
#define TWL4030_VIBRA_AUDIO_SEL_L1 (0x00 << 2)
#define TWL4030_VIBRA_AUDIO_SEL_R1 (0x01 << 2)
#define TWL4030_VIBRA_AUDIO_SEL_L2 (0x02 << 2)
#define TWL4030_VIBRA_AUDIO_SEL_R2 (0x03 << 2)
#define TWL4030_VIBRA_SEL 0x10
#define TWL4030_VIBRA_DIR_SEL 0x20
/* TWL4030 codec resource IDs */
enum twl4030_audio_res {
TWL4030_AUDIO_RES_POWER = 0,
TWL4030_AUDIO_RES_APLL,
TWL4030_AUDIO_RES_MAX,
};
int twl4030_audio_disable_resource(enum twl4030_audio_res id);
int twl4030_audio_enable_resource(enum twl4030_audio_res id);
unsigned int twl4030_audio_get_mclk(void);
#endif /* End of __TWL4030_CODEC_H__ */
kernel/include/linux/mfd/twl6040.h
+251
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/*
* MFD driver for twl6040
*
* Authors: Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
* Misael Lopez Cruz <misael.lopez@ti.com>
*
* Copyright: (C) 2011 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#ifndef __TWL6040_CODEC_H__
#define __TWL6040_CODEC_H__
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#define TWL6040_REG_ASICID 0x01
#define TWL6040_REG_ASICREV 0x02
#define TWL6040_REG_INTID 0x03
#define TWL6040_REG_INTMR 0x04
#define TWL6040_REG_NCPCTL 0x05
#define TWL6040_REG_LDOCTL 0x06
#define TWL6040_REG_HPPLLCTL 0x07
#define TWL6040_REG_LPPLLCTL 0x08
#define TWL6040_REG_LPPLLDIV 0x09
#define TWL6040_REG_AMICBCTL 0x0A
#define TWL6040_REG_DMICBCTL 0x0B
#define TWL6040_REG_MICLCTL 0x0C
#define TWL6040_REG_MICRCTL 0x0D
#define TWL6040_REG_MICGAIN 0x0E
#define TWL6040_REG_LINEGAIN 0x0F
#define TWL6040_REG_HSLCTL 0x10
#define TWL6040_REG_HSRCTL 0x11
#define TWL6040_REG_HSGAIN 0x12
#define TWL6040_REG_EARCTL 0x13
#define TWL6040_REG_HFLCTL 0x14
#define TWL6040_REG_HFLGAIN 0x15
#define TWL6040_REG_HFRCTL 0x16
#define TWL6040_REG_HFRGAIN 0x17
#define TWL6040_REG_VIBCTLL 0x18
#define TWL6040_REG_VIBDATL 0x19
#define TWL6040_REG_VIBCTLR 0x1A
#define TWL6040_REG_VIBDATR 0x1B
#define TWL6040_REG_HKCTL1 0x1C
#define TWL6040_REG_HKCTL2 0x1D
#define TWL6040_REG_GPOCTL 0x1E
#define TWL6040_REG_ALB 0x1F
#define TWL6040_REG_DLB 0x20
#define TWL6040_REG_TRIM1 0x28
#define TWL6040_REG_TRIM2 0x29
#define TWL6040_REG_TRIM3 0x2A
#define TWL6040_REG_HSOTRIM 0x2B
#define TWL6040_REG_HFOTRIM 0x2C
#define TWL6040_REG_ACCCTL 0x2D
#define TWL6040_REG_STATUS 0x2E
/* INTID (0x03) fields */
#define TWL6040_THINT 0x01
#define TWL6040_PLUGINT 0x02
#define TWL6040_UNPLUGINT 0x04
#define TWL6040_HOOKINT 0x08
#define TWL6040_HFINT 0x10
#define TWL6040_VIBINT 0x20
#define TWL6040_READYINT 0x40
/* INTMR (0x04) fields */
#define TWL6040_THMSK 0x01
#define TWL6040_PLUGMSK 0x02
#define TWL6040_HOOKMSK 0x08
#define TWL6040_HFMSK 0x10
#define TWL6040_VIBMSK 0x20
#define TWL6040_READYMSK 0x40
#define TWL6040_ALLINT_MSK 0x7B
/* NCPCTL (0x05) fields */
#define TWL6040_NCPENA 0x01
#define TWL6040_NCPOPEN 0x40
/* LDOCTL (0x06) fields */
#define TWL6040_LSLDOENA 0x01
#define TWL6040_HSLDOENA 0x04
#define TWL6040_REFENA 0x40
#define TWL6040_OSCENA 0x80
/* HPPLLCTL (0x07) fields */
#define TWL6040_HPLLENA 0x01
#define TWL6040_HPLLRST 0x02
#define TWL6040_HPLLBP 0x04
#define TWL6040_HPLLSQRENA 0x08
#define TWL6040_MCLK_12000KHZ (0 << 5)
#define TWL6040_MCLK_19200KHZ (1 << 5)
#define TWL6040_MCLK_26000KHZ (2 << 5)
#define TWL6040_MCLK_38400KHZ (3 << 5)
#define TWL6040_MCLK_MSK 0x60
/* LPPLLCTL (0x08) fields */
#define TWL6040_LPLLENA 0x01
#define TWL6040_LPLLRST 0x02
#define TWL6040_LPLLSEL 0x04
#define TWL6040_LPLLFIN 0x08
#define TWL6040_HPLLSEL 0x10
/* HSLCTL/R (0x10/0x11) fields */
#define TWL6040_HSDACENA (1 << 0)
#define TWL6040_HSDACMODE (1 << 1)
#define TWL6040_HSDRVMODE (1 << 3)
/* VIBCTLL/R (0x18/0x1A) fields */
#define TWL6040_VIBENA (1 << 0)
#define TWL6040_VIBSEL (1 << 1)
#define TWL6040_VIBCTRL (1 << 2)
#define TWL6040_VIBCTRL_P (1 << 3)
#define TWL6040_VIBCTRL_N (1 << 4)
/* VIBDATL/R (0x19/0x1B) fields */
#define TWL6040_VIBDAT_MAX 0x64
/* GPOCTL (0x1E) fields */
#define TWL6040_GPO1 0x01
#define TWL6040_GPO2 0x02
#define TWL6040_GPO3 0x03
/* ACCCTL (0x2D) fields */
#define TWL6040_I2CSEL 0x01
#define TWL6040_RESETSPLIT 0x04
#define TWL6040_INTCLRMODE 0x08
/* STATUS (0x2E) fields */
#define TWL6040_PLUGCOMP 0x02
#define TWL6040_VIBLOCDET 0x10
#define TWL6040_VIBROCDET 0x20
#define TWL6040_TSHUTDET 0x40
#define TWL6040_CELLS 2
#define TWL6040_REV_ES1_0 0x00
#define TWL6040_REV_ES1_1 0x01
#define TWL6040_REV_ES1_2 0x02
#define TWL6040_IRQ_TH 0
#define TWL6040_IRQ_PLUG 1
#define TWL6040_IRQ_HOOK 2
#define TWL6040_IRQ_HF 3
#define TWL6040_IRQ_VIB 4
#define TWL6040_IRQ_READY 5
/* PLL selection */
#define TWL6040_SYSCLK_SEL_LPPLL 0
#define TWL6040_SYSCLK_SEL_HPPLL 1
struct twl6040_codec_data {
u16 hs_left_step;
u16 hs_right_step;
u16 hf_left_step;
u16 hf_right_step;
};
struct twl6040_vibra_data {
unsigned int vibldrv_res; /* left driver resistance */
unsigned int vibrdrv_res; /* right driver resistance */
unsigned int viblmotor_res; /* left motor resistance */
unsigned int vibrmotor_res; /* right motor resistance */
int vddvibl_uV; /* VDDVIBL volt, set 0 for fixed reg */
int vddvibr_uV; /* VDDVIBR volt, set 0 for fixed reg */
};
struct twl6040_platform_data {
int audpwron_gpio; /* audio power-on gpio */
unsigned int irq_base;
struct twl6040_codec_data *codec;
struct twl6040_vibra_data *vibra;
};
struct regmap;
struct twl6040 {
struct device *dev;
struct regmap *regmap;
struct mutex mutex;
struct mutex io_mutex;
struct mutex irq_mutex;
struct mfd_cell cells[TWL6040_CELLS];
struct completion ready;
int audpwron;
int power_count;
int rev;
u8 vibra_ctrl_cache[2];
/* PLL configuration */
int pll;
unsigned int sysclk;
unsigned int mclk;
unsigned int irq;
unsigned int irq_base;
u8 irq_masks_cur;
u8 irq_masks_cache;
};
int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg);
int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg,
u8 val);
int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg,
u8 mask);
int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg,
u8 mask);
int twl6040_power(struct twl6040 *twl6040, int on);
int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
unsigned int freq_in, unsigned int freq_out);
int twl6040_get_pll(struct twl6040 *twl6040);
unsigned int twl6040_get_sysclk(struct twl6040 *twl6040);
int twl6040_irq_init(struct twl6040 *twl6040);
void twl6040_irq_exit(struct twl6040 *twl6040);
/* Get the combined status of the vibra control register */
int twl6040_get_vibralr_status(struct twl6040 *twl6040);
static inline int twl6040_get_revid(struct twl6040 *twl6040)
{
return twl6040->rev;
}
#endif /* End of __TWL6040_CODEC_H__ */
kernel/include/linux/mfd/ucb1x00.h
+259
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/*
* linux/include/mfd/ucb1x00.h
*
* Copyright (C) 2001 Russell King, All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License.
*/
#ifndef UCB1200_H
#define UCB1200_H
#include <linux/mfd/mcp.h>
#include <linux/gpio.h>
#include <linux/mutex.h>
#define UCB_IO_DATA 0x00
#define UCB_IO_DIR 0x01
#define UCB_IO_0 (1 << 0)
#define UCB_IO_1 (1 << 1)
#define UCB_IO_2 (1 << 2)
#define UCB_IO_3 (1 << 3)
#define UCB_IO_4 (1 << 4)
#define UCB_IO_5 (1 << 5)
#define UCB_IO_6 (1 << 6)
#define UCB_IO_7 (1 << 7)
#define UCB_IO_8 (1 << 8)
#define UCB_IO_9 (1 << 9)
#define UCB_IE_RIS 0x02
#define UCB_IE_FAL 0x03
#define UCB_IE_STATUS 0x04
#define UCB_IE_CLEAR 0x04
#define UCB_IE_ADC (1 << 11)
#define UCB_IE_TSPX (1 << 12)
#define UCB_IE_TSMX (1 << 13)
#define UCB_IE_TCLIP (1 << 14)
#define UCB_IE_ACLIP (1 << 15)
#define UCB_IRQ_TSPX 12
#define UCB_TC_A 0x05
#define UCB_TC_A_LOOP (1 << 7) /* UCB1200 */
#define UCB_TC_A_AMPL (1 << 7) /* UCB1300 */
#define UCB_TC_B 0x06
#define UCB_TC_B_VOICE_ENA (1 << 3)
#define UCB_TC_B_CLIP (1 << 4)
#define UCB_TC_B_ATT (1 << 6)
#define UCB_TC_B_SIDE_ENA (1 << 11)
#define UCB_TC_B_MUTE (1 << 13)
#define UCB_TC_B_IN_ENA (1 << 14)
#define UCB_TC_B_OUT_ENA (1 << 15)
#define UCB_AC_A 0x07
#define UCB_AC_B 0x08
#define UCB_AC_B_LOOP (1 << 8)
#define UCB_AC_B_MUTE (1 << 13)
#define UCB_AC_B_IN_ENA (1 << 14)
#define UCB_AC_B_OUT_ENA (1 << 15)
#define UCB_TS_CR 0x09
#define UCB_TS_CR_TSMX_POW (1 << 0)
#define UCB_TS_CR_TSPX_POW (1 << 1)
#define UCB_TS_CR_TSMY_POW (1 << 2)
#define UCB_TS_CR_TSPY_POW (1 << 3)
#define UCB_TS_CR_TSMX_GND (1 << 4)
#define UCB_TS_CR_TSPX_GND (1 << 5)
#define UCB_TS_CR_TSMY_GND (1 << 6)
#define UCB_TS_CR_TSPY_GND (1 << 7)
#define UCB_TS_CR_MODE_INT (0 << 8)
#define UCB_TS_CR_MODE_PRES (1 << 8)
#define UCB_TS_CR_MODE_POS (2 << 8)
#define UCB_TS_CR_BIAS_ENA (1 << 11)
#define UCB_TS_CR_TSPX_LOW (1 << 12)
#define UCB_TS_CR_TSMX_LOW (1 << 13)
#define UCB_ADC_CR 0x0a
#define UCB_ADC_SYNC_ENA (1 << 0)
#define UCB_ADC_VREFBYP_CON (1 << 1)
#define UCB_ADC_INP_TSPX (0 << 2)
#define UCB_ADC_INP_TSMX (1 << 2)
#define UCB_ADC_INP_TSPY (2 << 2)
#define UCB_ADC_INP_TSMY (3 << 2)
#define UCB_ADC_INP_AD0 (4 << 2)
#define UCB_ADC_INP_AD1 (5 << 2)
#define UCB_ADC_INP_AD2 (6 << 2)
#define UCB_ADC_INP_AD3 (7 << 2)
#define UCB_ADC_EXT_REF (1 << 5)
#define UCB_ADC_START (1 << 7)
#define UCB_ADC_ENA (1 << 15)
#define UCB_ADC_DATA 0x0b
#define UCB_ADC_DAT_VAL (1 << 15)
#define UCB_ADC_DAT(x) (((x) & 0x7fe0) >> 5)
#define UCB_ID 0x0c
#define UCB_ID_1200 0x1004
#define UCB_ID_1300 0x1005
#define UCB_ID_TC35143 0x9712
#define UCB_MODE 0x0d
#define UCB_MODE_DYN_VFLAG_ENA (1 << 12)
#define UCB_MODE_AUD_OFF_CAN (1 << 13)
enum ucb1x00_reset {
UCB_RST_PROBE,
UCB_RST_RESUME,
UCB_RST_SUSPEND,
UCB_RST_REMOVE,
UCB_RST_PROBE_FAIL,
};
struct ucb1x00_plat_data {
void (*reset)(enum ucb1x00_reset);
unsigned irq_base;
int gpio_base;
unsigned can_wakeup;
};
struct ucb1x00 {
raw_spinlock_t irq_lock;
struct mcp *mcp;
unsigned int irq;
int irq_base;
struct mutex adc_mutex;
spinlock_t io_lock;
u16 id;
u16 io_dir;
u16 io_out;
u16 adc_cr;
u16 irq_fal_enbl;
u16 irq_ris_enbl;
u16 irq_mask;
u16 irq_wake;
struct device dev;
struct list_head node;
struct list_head devs;
struct gpio_chip gpio;
};
struct ucb1x00_driver;
struct ucb1x00_dev {
struct list_head dev_node;
struct list_head drv_node;
struct ucb1x00 *ucb;
struct ucb1x00_driver *drv;
void *priv;
};
struct ucb1x00_driver {
struct list_head node;
struct list_head devs;
int (*add)(struct ucb1x00_dev *dev);
void (*remove)(struct ucb1x00_dev *dev);
int (*suspend)(struct ucb1x00_dev *dev);
int (*resume)(struct ucb1x00_dev *dev);
};
#define classdev_to_ucb1x00(cd) container_of(cd, struct ucb1x00, dev)
int ucb1x00_register_driver(struct ucb1x00_driver *);
void ucb1x00_unregister_driver(struct ucb1x00_driver *);
/**
* ucb1x00_clkrate - return the UCB1x00 SIB clock rate
* @ucb: UCB1x00 structure describing chip
*
* Return the SIB clock rate in Hz.
*/
static inline unsigned int ucb1x00_clkrate(struct ucb1x00 *ucb)
{
return mcp_get_sclk_rate(ucb->mcp);
}
/**
* ucb1x00_enable - enable the UCB1x00 SIB clock
* @ucb: UCB1x00 structure describing chip
*
* Enable the SIB clock. This can be called multiple times.
*/
static inline void ucb1x00_enable(struct ucb1x00 *ucb)
{
mcp_enable(ucb->mcp);
}
/**
* ucb1x00_disable - disable the UCB1x00 SIB clock
* @ucb: UCB1x00 structure describing chip
*
* Disable the SIB clock. The SIB clock will only be disabled
* when the number of ucb1x00_enable calls match the number of
* ucb1x00_disable calls.
*/
static inline void ucb1x00_disable(struct ucb1x00 *ucb)
{
mcp_disable(ucb->mcp);
}
/**
* ucb1x00_reg_write - write a UCB1x00 register
* @ucb: UCB1x00 structure describing chip
* @reg: UCB1x00 4-bit register index to write
* @val: UCB1x00 16-bit value to write
*
* Write the UCB1x00 register @reg with value @val. The SIB
* clock must be running for this function to return.
*/
static inline void ucb1x00_reg_write(struct ucb1x00 *ucb, unsigned int reg, unsigned int val)
{
mcp_reg_write(ucb->mcp, reg, val);
}
/**
* ucb1x00_reg_read - read a UCB1x00 register
* @ucb: UCB1x00 structure describing chip
* @reg: UCB1x00 4-bit register index to write
*
* Read the UCB1x00 register @reg and return its value. The SIB
* clock must be running for this function to return.
*/
static inline unsigned int ucb1x00_reg_read(struct ucb1x00 *ucb, unsigned int reg)
{
return mcp_reg_read(ucb->mcp, reg);
}
/**
* ucb1x00_set_audio_divisor -
* @ucb: UCB1x00 structure describing chip
* @div: SIB clock divisor
*/
static inline void ucb1x00_set_audio_divisor(struct ucb1x00 *ucb, unsigned int div)
{
mcp_set_audio_divisor(ucb->mcp, div);
}
/**
* ucb1x00_set_telecom_divisor -
* @ucb: UCB1x00 structure describing chip
* @div: SIB clock divisor
*/
static inline void ucb1x00_set_telecom_divisor(struct ucb1x00 *ucb, unsigned int div)
{
mcp_set_telecom_divisor(ucb->mcp, div);
}
void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int, unsigned int);
void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int, unsigned int);
unsigned int ucb1x00_io_read(struct ucb1x00 *ucb);
#define UCB_NOSYNC (0)
#define UCB_SYNC (1)
unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync);
void ucb1x00_adc_enable(struct ucb1x00 *ucb);
void ucb1x00_adc_disable(struct ucb1x00 *ucb);
#endif
kernel/include/linux/mfd/wcd9xxx/Kbuild
+3
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@@ -0,0 +1,3 @@
header-y += wcd9xxx_registers.h
header-y += wcd9310_registers.h
header-y += wcd9320_registers.h
kernel/include/linux/mfd/wcd9xxx/core.h
+267
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@@ -0,0 +1,267 @@
/* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MFD_TABLA_CORE_H__
#define __MFD_TABLA_CORE_H__
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/pm_qos.h>
#include <linux/platform_device.h>
#include <linux/of_irq.h>
#define WCD9XXX_NUM_IRQ_REGS 4
#define WCD9XXX_SLIM_NUM_PORT_REG 3
#define TABLA_VERSION_1_0 0
#define TABLA_VERSION_1_1 1
#define TABLA_VERSION_2_0 2
#define TABLA_IS_1_X(ver) \
(((ver == TABLA_VERSION_1_0) || (ver == TABLA_VERSION_1_1)) ? 1 : 0)
#define TABLA_IS_2_0(ver) ((ver == TABLA_VERSION_2_0) ? 1 : 0)
#define WCD9XXX_SUPPLY_BUCK_NAME "cdc-vdd-buck"
#define SITAR_VERSION_1P0 0
#define SITAR_VERSION_1P1 1
#define SITAR_IS_1P0(ver) \
((ver == SITAR_VERSION_1P0) ? 1 : 0)
#define SITAR_IS_1P1(ver) \
((ver == SITAR_VERSION_1P1) ? 1 : 0)
#define TAIKO_VERSION_1_0 1
#define TAIKO_IS_1_0(ver) \
((ver == TAIKO_VERSION_1_0) ? 1 : 0)
#define TAPAN_VERSION_1_0 0
#define TAPAN_IS_1_0(ver) \
((ver == TAPAN_VERSION_1_0) ? 1 : 0)
enum wcd9xxx_slim_slave_addr_type {
WCD9XXX_SLIM_SLAVE_ADDR_TYPE_TABLA,
WCD9XXX_SLIM_SLAVE_ADDR_TYPE_TAIKO,
};
enum {
/* INTR_REG 0 */
WCD9XXX_IRQ_SLIMBUS = 0,
WCD9XXX_IRQ_MBHC_REMOVAL,
WCD9XXX_IRQ_MBHC_SHORT_TERM,
WCD9XXX_IRQ_MBHC_PRESS,
WCD9XXX_IRQ_MBHC_RELEASE,
WCD9XXX_IRQ_MBHC_POTENTIAL,
WCD9XXX_IRQ_MBHC_INSERTION,
WCD9XXX_IRQ_BG_PRECHARGE,
/* INTR_REG 1 */
WCD9XXX_IRQ_PA1_STARTUP,
WCD9XXX_IRQ_PA2_STARTUP,
WCD9XXX_IRQ_PA3_STARTUP,
WCD9XXX_IRQ_PA4_STARTUP,
WCD9XXX_IRQ_PA5_STARTUP,
WCD9XXX_IRQ_MICBIAS1_PRECHARGE,
WCD9XXX_IRQ_MICBIAS2_PRECHARGE,
WCD9XXX_IRQ_MICBIAS3_PRECHARGE,
/* INTR_REG 2 */
WCD9XXX_IRQ_HPH_PA_OCPL_FAULT,
WCD9XXX_IRQ_HPH_PA_OCPR_FAULT,
WCD9XXX_IRQ_EAR_PA_OCPL_FAULT,
WCD9XXX_IRQ_HPH_L_PA_STARTUP,
WCD9XXX_IRQ_HPH_R_PA_STARTUP,
WCD9320_IRQ_EAR_PA_STARTUP,
WCD9306_IRQ_MBHC_JACK_SWITCH = WCD9320_IRQ_EAR_PA_STARTUP,
WCD9310_NUM_IRQS,
WCD9XXX_IRQ_RESERVED_0 = WCD9310_NUM_IRQS,
WCD9XXX_IRQ_RESERVED_1,
/* INTR_REG 3 */
WCD9XXX_IRQ_MAD_AUDIO,
WCD9XXX_IRQ_MAD_BEACON,
WCD9XXX_IRQ_MAD_ULTRASOUND,
WCD9XXX_IRQ_SPEAKER_CLIPPING,
WCD9320_IRQ_MBHC_JACK_SWITCH,
WCD9XXX_IRQ_VBAT_MONITOR_ATTACK,
WCD9XXX_IRQ_VBAT_MONITOR_RELEASE,
WCD9XXX_NUM_IRQS,
};
enum {
TABLA_NUM_IRQS = WCD9310_NUM_IRQS,
SITAR_NUM_IRQS = WCD9310_NUM_IRQS,
TAIKO_NUM_IRQS = WCD9XXX_NUM_IRQS,
TAPAN_NUM_IRQS = WCD9XXX_NUM_IRQS,
};
#define MAX(X, Y) (((int)X) >= ((int)Y) ? (X) : (Y))
#define WCD9XXX_MAX_NUM_IRQS (MAX(MAX(TABLA_NUM_IRQS, SITAR_NUM_IRQS), \
TAIKO_NUM_IRQS))
enum wcd9xxx_pm_state {
WCD9XXX_PM_SLEEPABLE,
WCD9XXX_PM_AWAKE,
WCD9XXX_PM_ASLEEP,
};
/*
* data structure for Slimbus and I2S channel.
* Some of fields are only used in smilbus mode
*/
struct wcd9xxx_ch {
u32 sph; /* share channel handle - slimbus only */
u32 ch_num; /*
* vitrual channel number, such as 128 -144.
* apply for slimbus only
*/
u16 ch_h; /* chanel handle - slimbus only */
u16 port; /*
* tabla port for RX and TX
* such as 0-9 for TX and 10 -16 for RX
* apply for both i2s and slimbus
*/
u16 shift; /*
* shift bit for RX and TX
* apply for both i2s and slimbus
*/
struct list_head list; /*
* channel link list
* apply for both i2s and slimbus
*/
};
struct wcd9xxx_codec_dai_data {
u32 rate; /* sample rate */
u32 bit_width; /* sit width 16,24,32 */
struct list_head wcd9xxx_ch_list; /* channel list */
u16 grph; /* slimbus group handle */
unsigned long ch_mask;
wait_queue_head_t dai_wait;
};
enum wcd9xxx_intf_status {
WCD9XXX_INTERFACE_TYPE_PROBING,
WCD9XXX_INTERFACE_TYPE_SLIMBUS,
WCD9XXX_INTERFACE_TYPE_I2C,
};
#define WCD9XXX_CH(xport, xshift) \
{.port = xport, .shift = xshift}
enum wcd9xxx_chipid_major {
TABLA_MAJOR = cpu_to_le16(0x100),
SITAR_MAJOR = cpu_to_le16(0x101),
TAIKO_MAJOR = cpu_to_le16(0x102),
TAPAN_MAJOR = cpu_to_le16(0x103),
};
struct wcd9xxx_codec_type {
u16 id_major;
u16 id_minor;
struct mfd_cell *dev;
int size;
int num_irqs;
int version; /* -1 to retrive version from chip version register */
enum wcd9xxx_slim_slave_addr_type slim_slave_type;
u16 i2c_chip_status;
};
struct wcd9xxx {
struct device *dev;
struct slim_device *slim;
struct slim_device *slim_slave;
struct mutex io_lock;
struct mutex xfer_lock;
struct mutex irq_lock;
struct mutex nested_irq_lock;
u8 version;
int reset_gpio;
int (*read_dev)(struct wcd9xxx *wcd9xxx, unsigned short reg,
int bytes, void *dest, bool interface_reg);
int (*write_dev)(struct wcd9xxx *wcd9xxx, unsigned short reg,
int bytes, void *src, bool interface_reg);
int (*post_reset)(struct wcd9xxx *wcd9xxx);
void *ssr_priv;
bool slim_device_bootup;
u32 num_of_supplies;
struct regulator_bulk_data *supplies;
enum wcd9xxx_pm_state pm_state;
struct mutex pm_lock;
/* pm_wq notifies change of pm_state */
wait_queue_head_t pm_wq;
struct pm_qos_request pm_qos_req;
int wlock_holders;
u16 id_minor;
u16 id_major;
unsigned int irq_base;
unsigned int irq;
u8 irq_masks_cur[WCD9XXX_NUM_IRQ_REGS];
u8 irq_masks_cache[WCD9XXX_NUM_IRQ_REGS];
bool irq_level_high[WCD9XXX_MAX_NUM_IRQS];
/* Slimbus or I2S port */
u32 num_rx_port;
u32 num_tx_port;
struct wcd9xxx_ch *rx_chs;
struct wcd9xxx_ch *tx_chs;
u32 mclk_rate;
const struct wcd9xxx_codec_type *codec_type;
};
int wcd9xxx_reg_read(struct wcd9xxx *wcd9xxx, unsigned short reg);
int wcd9xxx_reg_write(struct wcd9xxx *wcd9xxx, unsigned short reg,
u8 val);
int wcd9xxx_interface_reg_read(struct wcd9xxx *wcd9xxx, unsigned short reg);
int wcd9xxx_interface_reg_write(struct wcd9xxx *wcd9xxx, unsigned short reg,
u8 val);
int wcd9xxx_bulk_read(struct wcd9xxx *wcd9xxx, unsigned short reg,
int count, u8 *buf);
int wcd9xxx_bulk_write(struct wcd9xxx *wcd9xxx, unsigned short reg,
int count, u8 *buf);
int wcd9xxx_irq_init(struct wcd9xxx *wcd9xxx);
void wcd9xxx_irq_exit(struct wcd9xxx *wcd9xxx);
int wcd9xxx_get_logical_addresses(u8 *pgd_la, u8 *inf_la);
enum wcd9xxx_intf_status wcd9xxx_get_intf_type(void);
bool wcd9xxx_lock_sleep(struct wcd9xxx *wcd9xxx);
void wcd9xxx_unlock_sleep(struct wcd9xxx *wcd9xxx);
void wcd9xxx_nested_irq_lock(struct wcd9xxx *wcd9xxx);
void wcd9xxx_nested_irq_unlock(struct wcd9xxx *wcd9xxx);
enum wcd9xxx_pm_state wcd9xxx_pm_cmpxchg(struct wcd9xxx *wcd9xxx,
enum wcd9xxx_pm_state o,
enum wcd9xxx_pm_state n);
int wcd9xxx_request_irq(struct wcd9xxx *wcd9xxx, int irq,
irq_handler_t handler, const char *name, void *data);
void wcd9xxx_free_irq(struct wcd9xxx *wcd9xxx, int irq, void *data);
void wcd9xxx_enable_irq(struct wcd9xxx *wcd9xxx, int irq);
void wcd9xxx_disable_irq(struct wcd9xxx *wcd9xxx, int irq);
void wcd9xxx_disable_irq_sync(struct wcd9xxx *wcd9xxx, int irq);
#if defined(CONFIG_WCD9310_CODEC) || \
defined(CONFIG_WCD9304_CODEC) || \
defined(CONFIG_WCD9320_CODEC) || \
defined(CONFIG_WCD9306_CODEC)
int __init wcd9xxx_irq_of_init(struct device_node *node,
struct device_node *parent);
#else
static inline int __init wcd9xxx_irq_of_init(struct device_node *node,
struct device_node *parent)
{
return 0;
}
#endif /* CONFIG_OF */
#endif

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