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44
kernel/drivers/net/ethernet/xilinx/Kconfig Normal file
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#
# Xilink device configuration
#
config NET_VENDOR_XILINX
bool "Xilinx devices"
default y
depends on PPC || PPC32 || MICROBLAZE
---help---
If you have a network (Ethernet) card belonging to this class, say Y
and read the Ethernet-HOWTO, available from
<http://www.tldp.org/docs.html#howto>.
Note that the answer to this question doesn't directly affect the
kernel: saying N will just cause the configurator to skip all
the questions about Xilinx devices. If you say Y, you will be asked
for your specific card in the following questions.
if NET_VENDOR_XILINX
config XILINX_EMACLITE
tristate "Xilinx 10/100 Ethernet Lite support"
depends on (PPC32 || MICROBLAZE)
select PHYLIB
---help---
This driver supports the 10/100 Ethernet Lite from Xilinx.
config XILINX_AXI_EMAC
tristate "Xilinx 10/100/1000 AXI Ethernet support"
depends on (PPC32 || MICROBLAZE)
select PHYLIB
---help---
This driver supports the 10/100/1000 Ethernet from Xilinx for the
AXI bus interface used in Xilinx Virtex FPGAs.
config XILINX_LL_TEMAC
tristate "Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver"
depends on (PPC || MICROBLAZE)
select PHYLIB
---help---
This driver supports the Xilinx 10/100/1000 LocalLink TEMAC
core used in Xilinx Spartan and Virtex FPGAs
endif # NET_VENDOR_XILINX

9
kernel/drivers/net/ethernet/xilinx/Makefile Normal file
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#
# Makefile for the Xilink network device drivers.
#
ll_temac-objs := ll_temac_main.o ll_temac_mdio.o
obj-$(CONFIG_XILINX_LL_TEMAC) += ll_temac.o
obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
xilinx_emac-objs := xilinx_axienet_main.o xilinx_axienet_mdio.o
obj-$(CONFIG_XILINX_AXI_EMAC) += xilinx_emac.o

385
kernel/drivers/net/ethernet/xilinx/ll_temac.h Normal file
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#ifndef XILINX_LL_TEMAC_H
#define XILINX_LL_TEMAC_H
#include <linux/netdevice.h>
#include <linux/of.h>
#include <linux/spinlock.h>
#ifdef CONFIG_PPC_DCR
#include <asm/dcr.h>
#include <asm/dcr-regs.h>
#endif
/* packet size info */
#define XTE_HDR_SIZE 14 /* size of Ethernet header */
#define XTE_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */
#define XTE_JUMBO_MTU 9000
#define XTE_MAX_JUMBO_FRAME_SIZE (XTE_JUMBO_MTU + XTE_HDR_SIZE + XTE_TRL_SIZE)
/* Configuration options */
/* Accept all incoming packets.
* This option defaults to disabled (cleared) */
#define XTE_OPTION_PROMISC (1 << 0)
/* Jumbo frame support for Tx & Rx.
* This option defaults to disabled (cleared) */
#define XTE_OPTION_JUMBO (1 << 1)
/* VLAN Rx & Tx frame support.
* This option defaults to disabled (cleared) */
#define XTE_OPTION_VLAN (1 << 2)
/* Enable recognition of flow control frames on Rx
* This option defaults to enabled (set) */
#define XTE_OPTION_FLOW_CONTROL (1 << 4)
/* Strip FCS and PAD from incoming frames.
* Note: PAD from VLAN frames is not stripped.
* This option defaults to disabled (set) */
#define XTE_OPTION_FCS_STRIP (1 << 5)
/* Generate FCS field and add PAD automatically for outgoing frames.
* This option defaults to enabled (set) */
#define XTE_OPTION_FCS_INSERT (1 << 6)
/* Enable Length/Type error checking for incoming frames. When this option is
set, the MAC will filter frames that have a mismatched type/length field
and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these
types of frames are encountered. When this option is cleared, the MAC will
allow these types of frames to be received.
This option defaults to enabled (set) */
#define XTE_OPTION_LENTYPE_ERR (1 << 7)
/* Enable the transmitter.
* This option defaults to enabled (set) */
#define XTE_OPTION_TXEN (1 << 11)
/* Enable the receiver
* This option defaults to enabled (set) */
#define XTE_OPTION_RXEN (1 << 12)
/* Default options set when device is initialized or reset */
#define XTE_OPTION_DEFAULTS \
(XTE_OPTION_TXEN | \
XTE_OPTION_FLOW_CONTROL | \
XTE_OPTION_RXEN)
/* XPS_LL_TEMAC SDMA registers definition */
#define TX_NXTDESC_PTR 0x00 /* r */
#define TX_CURBUF_ADDR 0x01 /* r */
#define TX_CURBUF_LENGTH 0x02 /* r */
#define TX_CURDESC_PTR 0x03 /* rw */
#define TX_TAILDESC_PTR 0x04 /* rw */
#define TX_CHNL_CTRL 0x05 /* rw */
/*
0:7 24:31 IRQTimeout
8:15 16:23 IRQCount
16:20 11:15 Reserved
21 10 0
22 9 UseIntOnEnd
23 8 LdIRQCnt
24 7 IRQEn
25:28 3:6 Reserved
29 2 IrqErrEn
30 1 IrqDlyEn
31 0 IrqCoalEn
*/
#define CHNL_CTRL_IRQ_IOE (1 << 9)
#define CHNL_CTRL_IRQ_EN (1 << 7)
#define CHNL_CTRL_IRQ_ERR_EN (1 << 2)
#define CHNL_CTRL_IRQ_DLY_EN (1 << 1)
#define CHNL_CTRL_IRQ_COAL_EN (1 << 0)
#define TX_IRQ_REG 0x06 /* rw */
/*
0:7 24:31 DltTmrValue
8:15 16:23 ClscCntrValue
16:17 14:15 Reserved
18:21 10:13 ClscCnt
22:23 8:9 DlyCnt
24:28 3::7 Reserved
29 2 ErrIrq
30 1 DlyIrq
31 0 CoalIrq
*/
#define TX_CHNL_STS 0x07 /* r */
/*
0:9 22:31 Reserved
10 21 TailPErr
11 20 CmpErr
12 19 AddrErr
13 18 NxtPErr
14 17 CurPErr
15 16 BsyWr
16:23 8:15 Reserved
24 7 Error
25 6 IOE
26 5 SOE
27 4 Cmplt
28 3 SOP
29 2 EOP
30 1 EngBusy
31 0 Reserved
*/
#define RX_NXTDESC_PTR 0x08 /* r */
#define RX_CURBUF_ADDR 0x09 /* r */
#define RX_CURBUF_LENGTH 0x0a /* r */
#define RX_CURDESC_PTR 0x0b /* rw */
#define RX_TAILDESC_PTR 0x0c /* rw */
#define RX_CHNL_CTRL 0x0d /* rw */
/*
0:7 24:31 IRQTimeout
8:15 16:23 IRQCount
16:20 11:15 Reserved
21 10 0
22 9 UseIntOnEnd
23 8 LdIRQCnt
24 7 IRQEn
25:28 3:6 Reserved
29 2 IrqErrEn
30 1 IrqDlyEn
31 0 IrqCoalEn
*/
#define RX_IRQ_REG 0x0e /* rw */
#define IRQ_COAL (1 << 0)
#define IRQ_DLY (1 << 1)
#define IRQ_ERR (1 << 2)
#define IRQ_DMAERR (1 << 7) /* this is not documented ??? */
/*
0:7 24:31 DltTmrValue
8:15 16:23 ClscCntrValue
16:17 14:15 Reserved
18:21 10:13 ClscCnt
22:23 8:9 DlyCnt
24:28 3::7 Reserved
*/
#define RX_CHNL_STS 0x0f /* r */
#define CHNL_STS_ENGBUSY (1 << 1)
#define CHNL_STS_EOP (1 << 2)
#define CHNL_STS_SOP (1 << 3)
#define CHNL_STS_CMPLT (1 << 4)
#define CHNL_STS_SOE (1 << 5)
#define CHNL_STS_IOE (1 << 6)
#define CHNL_STS_ERR (1 << 7)
#define CHNL_STS_BSYWR (1 << 16)
#define CHNL_STS_CURPERR (1 << 17)
#define CHNL_STS_NXTPERR (1 << 18)
#define CHNL_STS_ADDRERR (1 << 19)
#define CHNL_STS_CMPERR (1 << 20)
#define CHNL_STS_TAILERR (1 << 21)
/*
0:9 22:31 Reserved
10 21 TailPErr
11 20 CmpErr
12 19 AddrErr
13 18 NxtPErr
14 17 CurPErr
15 16 BsyWr
16:23 8:15 Reserved
24 7 Error
25 6 IOE
26 5 SOE
27 4 Cmplt
28 3 SOP
29 2 EOP
30 1 EngBusy
31 0 Reserved
*/
#define DMA_CONTROL_REG 0x10 /* rw */
#define DMA_CONTROL_RST (1 << 0)
#define DMA_TAIL_ENABLE (1 << 2)
/* XPS_LL_TEMAC direct registers definition */
#define XTE_RAF0_OFFSET 0x00
#define RAF0_RST (1 << 0)
#define RAF0_MCSTREJ (1 << 1)
#define RAF0_BCSTREJ (1 << 2)
#define XTE_TPF0_OFFSET 0x04
#define XTE_IFGP0_OFFSET 0x08
#define XTE_ISR0_OFFSET 0x0c
#define ISR0_HARDACSCMPLT (1 << 0)
#define ISR0_AUTONEG (1 << 1)
#define ISR0_RXCMPLT (1 << 2)
#define ISR0_RXREJ (1 << 3)
#define ISR0_RXFIFOOVR (1 << 4)
#define ISR0_TXCMPLT (1 << 5)
#define ISR0_RXDCMLCK (1 << 6)
#define XTE_IPR0_OFFSET 0x10
#define XTE_IER0_OFFSET 0x14
#define XTE_MSW0_OFFSET 0x20
#define XTE_LSW0_OFFSET 0x24
#define XTE_CTL0_OFFSET 0x28
#define XTE_RDY0_OFFSET 0x2c
#define XTE_RSE_MIIM_RR_MASK 0x0002
#define XTE_RSE_MIIM_WR_MASK 0x0004
#define XTE_RSE_CFG_RR_MASK 0x0020
#define XTE_RSE_CFG_WR_MASK 0x0040
#define XTE_RDY0_HARD_ACS_RDY_MASK (0x10000)
/* XPS_LL_TEMAC indirect registers offset definition */
#define XTE_RXC0_OFFSET 0x00000200 /* Rx configuration word 0 */
#define XTE_RXC1_OFFSET 0x00000240 /* Rx configuration word 1 */
#define XTE_RXC1_RXRST_MASK (1 << 31) /* Receiver reset */
#define XTE_RXC1_RXJMBO_MASK (1 << 30) /* Jumbo frame enable */
#define XTE_RXC1_RXFCS_MASK (1 << 29) /* FCS not stripped */
#define XTE_RXC1_RXEN_MASK (1 << 28) /* Receiver enable */
#define XTE_RXC1_RXVLAN_MASK (1 << 27) /* VLAN enable */
#define XTE_RXC1_RXHD_MASK (1 << 26) /* Half duplex */
#define XTE_RXC1_RXLT_MASK (1 << 25) /* Length/type check disable */
#define XTE_TXC_OFFSET 0x00000280 /* Tx configuration */
#define XTE_TXC_TXRST_MASK (1 << 31) /* Transmitter reset */
#define XTE_TXC_TXJMBO_MASK (1 << 30) /* Jumbo frame enable */
#define XTE_TXC_TXFCS_MASK (1 << 29) /* Generate FCS */
#define XTE_TXC_TXEN_MASK (1 << 28) /* Transmitter enable */
#define XTE_TXC_TXVLAN_MASK (1 << 27) /* VLAN enable */
#define XTE_TXC_TXHD_MASK (1 << 26) /* Half duplex */
#define XTE_FCC_OFFSET 0x000002C0 /* Flow control config */
#define XTE_FCC_RXFLO_MASK (1 << 29) /* Rx flow control enable */
#define XTE_FCC_TXFLO_MASK (1 << 30) /* Tx flow control enable */
#define XTE_EMCFG_OFFSET 0x00000300 /* EMAC configuration */
#define XTE_EMCFG_LINKSPD_MASK 0xC0000000 /* Link speed */
#define XTE_EMCFG_HOSTEN_MASK (1 << 26) /* Host interface enable */
#define XTE_EMCFG_LINKSPD_10 0x00000000 /* 10 Mbit LINKSPD_MASK */
#define XTE_EMCFG_LINKSPD_100 (1 << 30) /* 100 Mbit LINKSPD_MASK */
#define XTE_EMCFG_LINKSPD_1000 (1 << 31) /* 1000 Mbit LINKSPD_MASK */
#define XTE_GMIC_OFFSET 0x00000320 /* RGMII/SGMII config */
#define XTE_MC_OFFSET 0x00000340 /* MDIO configuration */
#define XTE_UAW0_OFFSET 0x00000380 /* Unicast address word 0 */
#define XTE_UAW1_OFFSET 0x00000384 /* Unicast address word 1 */
#define XTE_MAW0_OFFSET 0x00000388 /* Multicast addr word 0 */
#define XTE_MAW1_OFFSET 0x0000038C /* Multicast addr word 1 */
#define XTE_AFM_OFFSET 0x00000390 /* Promiscuous mode */
#define XTE_AFM_EPPRM_MASK (1 << 31) /* Promiscuous mode enable */
/* Interrupt Request status */
#define XTE_TIS_OFFSET 0x000003A0
#define TIS_FRIS (1 << 0)
#define TIS_MRIS (1 << 1)
#define TIS_MWIS (1 << 2)
#define TIS_ARIS (1 << 3)
#define TIS_AWIS (1 << 4)
#define TIS_CRIS (1 << 5)
#define TIS_CWIS (1 << 6)
#define XTE_TIE_OFFSET 0x000003A4 /* Interrupt enable */
/** MII Mamagement Control register (MGTCR) */
#define XTE_MGTDR_OFFSET 0x000003B0 /* MII data */
#define XTE_MIIMAI_OFFSET 0x000003B4 /* MII control */
#define CNTLREG_WRITE_ENABLE_MASK 0x8000
#define CNTLREG_EMAC1SEL_MASK 0x0400
#define CNTLREG_ADDRESSCODE_MASK 0x03ff
/* CDMAC descriptor status bit definitions */
#define STS_CTRL_APP0_ERR (1 << 31)
#define STS_CTRL_APP0_IRQONEND (1 << 30)
/* undoccumented */
#define STS_CTRL_APP0_STOPONEND (1 << 29)
#define STS_CTRL_APP0_CMPLT (1 << 28)
#define STS_CTRL_APP0_SOP (1 << 27)
#define STS_CTRL_APP0_EOP (1 << 26)
#define STS_CTRL_APP0_ENGBUSY (1 << 25)
/* undocumented */
#define STS_CTRL_APP0_ENGRST (1 << 24)
#define TX_CONTROL_CALC_CSUM_MASK 1
#define MULTICAST_CAM_TABLE_NUM 4
/* TEMAC Synthesis features */
#define TEMAC_FEATURE_RX_CSUM (1 << 0)
#define TEMAC_FEATURE_TX_CSUM (1 << 1)
/* TX/RX CURDESC_PTR points to first descriptor */
/* TX/RX TAILDESC_PTR points to last descriptor in linked list */
/**
* struct cdmac_bd - LocalLink buffer descriptor format
*
* app0 bits:
* 0 Error
* 1 IrqOnEnd generate an interrupt at completion of DMA op
* 2 reserved
* 3 completed Current descriptor completed
* 4 SOP TX - marks first desc/ RX marks first desct
* 5 EOP TX marks last desc/RX marks last desc
* 6 EngBusy DMA is processing
* 7 reserved
* 8:31 application specific
*/
struct cdmac_bd {
u32 next; /* Physical address of next buffer descriptor */
u32 phys;
u32 len;
u32 app0;
u32 app1; /* TX start << 16 | insert */
u32 app2; /* TX csum */
u32 app3;
u32 app4; /* skb for TX length for RX */
};
struct temac_local {
struct net_device *ndev;
struct device *dev;
/* Connection to PHY device */
struct phy_device *phy_dev; /* Pointer to PHY device */
struct device_node *phy_node;
/* MDIO bus data */
struct mii_bus *mii_bus; /* MII bus reference */
int mdio_irqs[PHY_MAX_ADDR]; /* IRQs table for MDIO bus */
/* IO registers, dma functions and IRQs */
void __iomem *regs;
void __iomem *sdma_regs;
#ifdef CONFIG_PPC_DCR
dcr_host_t sdma_dcrs;
#endif
u32 (*dma_in)(struct temac_local *, int);
void (*dma_out)(struct temac_local *, int, u32);
int tx_irq;
int rx_irq;
int emac_num;
struct sk_buff **rx_skb;
spinlock_t rx_lock;
struct mutex indirect_mutex;
u32 options; /* Current options word */
int last_link;
unsigned int temac_features;
/* Buffer descriptors */
struct cdmac_bd *tx_bd_v;
dma_addr_t tx_bd_p;
struct cdmac_bd *rx_bd_v;
dma_addr_t rx_bd_p;
int tx_bd_ci;
int tx_bd_next;
int tx_bd_tail;
int rx_bd_ci;
};
/* xilinx_temac.c */
u32 temac_ior(struct temac_local *lp, int offset);
void temac_iow(struct temac_local *lp, int offset, u32 value);
int temac_indirect_busywait(struct temac_local *lp);
u32 temac_indirect_in32(struct temac_local *lp, int reg);
void temac_indirect_out32(struct temac_local *lp, int reg, u32 value);
/* xilinx_temac_mdio.c */
int temac_mdio_setup(struct temac_local *lp, struct device_node *np);
void temac_mdio_teardown(struct temac_local *lp);
#endif /* XILINX_LL_TEMAC_H */

1189
kernel/drivers/net/ethernet/xilinx/ll_temac_main.c Normal file
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kernel/drivers/net/ethernet/xilinx/ll_temac_mdio.c Normal file
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/*
* MDIO bus driver for the Xilinx TEMAC device
*
* Copyright (c) 2009 Secret Lab Technologies, Ltd.
*/
#include <linux/io.h>
#include <linux/netdevice.h>
#include <linux/mutex.h>
#include <linux/phy.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/of_mdio.h>
#include "ll_temac.h"
/* ---------------------------------------------------------------------
* MDIO Bus functions
*/
static int temac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
{
struct temac_local *lp = bus->priv;
u32 rc;
/* Write the PHY address to the MIIM Access Initiator register.
* When the transfer completes, the PHY register value will appear
* in the LSW0 register */
mutex_lock(&lp->indirect_mutex);
temac_iow(lp, XTE_LSW0_OFFSET, (phy_id << 5) | reg);
rc = temac_indirect_in32(lp, XTE_MIIMAI_OFFSET);
mutex_unlock(&lp->indirect_mutex);
dev_dbg(lp->dev, "temac_mdio_read(phy_id=%i, reg=%x) == %x\n",
phy_id, reg, rc);
return rc;
}
static int temac_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val)
{
struct temac_local *lp = bus->priv;
dev_dbg(lp->dev, "temac_mdio_write(phy_id=%i, reg=%x, val=%x)\n",
phy_id, reg, val);
/* First write the desired value into the write data register
* and then write the address into the access initiator register
*/
mutex_lock(&lp->indirect_mutex);
temac_indirect_out32(lp, XTE_MGTDR_OFFSET, val);
temac_indirect_out32(lp, XTE_MIIMAI_OFFSET, (phy_id << 5) | reg);
mutex_unlock(&lp->indirect_mutex);
return 0;
}
int temac_mdio_setup(struct temac_local *lp, struct device_node *np)
{
struct mii_bus *bus;
const u32 *bus_hz;
int clk_div;
int rc, size;
struct resource res;
/* Calculate a reasonable divisor for the clock rate */
clk_div = 0x3f; /* worst-case default setting */
bus_hz = of_get_property(np, "clock-frequency", &size);
if (bus_hz && size >= sizeof(*bus_hz)) {
clk_div = (*bus_hz) / (2500 * 1000 * 2) - 1;
if (clk_div < 1)
clk_div = 1;
if (clk_div > 0x3f)
clk_div = 0x3f;
}
/* Enable the MDIO bus by asserting the enable bit and writing
* in the clock config */
mutex_lock(&lp->indirect_mutex);
temac_indirect_out32(lp, XTE_MC_OFFSET, 1 << 6 | clk_div);
mutex_unlock(&lp->indirect_mutex);
bus = mdiobus_alloc();
if (!bus)
return -ENOMEM;
of_address_to_resource(np, 0, &res);
snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
(unsigned long long)res.start);
bus->priv = lp;
bus->name = "Xilinx TEMAC MDIO";
bus->read = temac_mdio_read;
bus->write = temac_mdio_write;
bus->parent = lp->dev;
bus->irq = lp->mdio_irqs; /* preallocated IRQ table */
lp->mii_bus = bus;
rc = of_mdiobus_register(bus, np);
if (rc)
goto err_register;
mutex_lock(&lp->indirect_mutex);
dev_dbg(lp->dev, "MDIO bus registered; MC:%x\n",
temac_indirect_in32(lp, XTE_MC_OFFSET));
mutex_unlock(&lp->indirect_mutex);
return 0;
err_register:
mdiobus_free(bus);
return rc;
}
void temac_mdio_teardown(struct temac_local *lp)
{
mdiobus_unregister(lp->mii_bus);
kfree(lp->mii_bus->irq);
mdiobus_free(lp->mii_bus);
lp->mii_bus = NULL;
}

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kernel/drivers/net/ethernet/xilinx/xilinx_axienet.h Normal file
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/*
* Definitions for Xilinx Axi Ethernet device driver.
*
* Copyright (c) 2009 Secret Lab Technologies, Ltd.
* Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
*/
#ifndef XILINX_AXIENET_H
#define XILINX_AXIENET_H
#include <linux/netdevice.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
/* Packet size info */
#define XAE_HDR_SIZE 14 /* Size of Ethernet header */
#define XAE_HDR_VLAN_SIZE 18 /* Size of an Ethernet hdr + VLAN */
#define XAE_TRL_SIZE 4 /* Size of Ethernet trailer (FCS) */
#define XAE_MTU 1500 /* Max MTU of an Ethernet frame */
#define XAE_JUMBO_MTU 9000 /* Max MTU of a jumbo Eth. frame */
#define XAE_MAX_FRAME_SIZE (XAE_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE)
#define XAE_MAX_VLAN_FRAME_SIZE (XAE_MTU + XAE_HDR_VLAN_SIZE + XAE_TRL_SIZE)
#define XAE_MAX_JUMBO_FRAME_SIZE (XAE_JUMBO_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE)
/* Configuration options */
/* Accept all incoming packets. Default: disabled (cleared) */
#define XAE_OPTION_PROMISC (1 << 0)
/* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */
#define XAE_OPTION_JUMBO (1 << 1)
/* VLAN Rx & Tx frame support. Default: disabled (cleared) */
#define XAE_OPTION_VLAN (1 << 2)
/* Enable recognition of flow control frames on Rx. Default: enabled (set) */
#define XAE_OPTION_FLOW_CONTROL (1 << 4)
/* Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
* stripped. Default: disabled (set) */
#define XAE_OPTION_FCS_STRIP (1 << 5)
/* Generate FCS field and add PAD automatically for outgoing frames.
* Default: enabled (set) */
#define XAE_OPTION_FCS_INSERT (1 << 6)
/* Enable Length/Type error checking for incoming frames. When this option is
* set, the MAC will filter frames that have a mismatched type/length field
* and if XAE_OPTION_REPORT_RXERR is set, the user is notified when these
* types of frames are encountered. When this option is cleared, the MAC will
* allow these types of frames to be received. Default: enabled (set) */
#define XAE_OPTION_LENTYPE_ERR (1 << 7)
/* Enable the transmitter. Default: enabled (set) */
#define XAE_OPTION_TXEN (1 << 11)
/* Enable the receiver. Default: enabled (set) */
#define XAE_OPTION_RXEN (1 << 12)
/* Default options set when device is initialized or reset */
#define XAE_OPTION_DEFAULTS \
(XAE_OPTION_TXEN | \
XAE_OPTION_FLOW_CONTROL | \
XAE_OPTION_RXEN)
/* Axi DMA Register definitions */
#define XAXIDMA_TX_CR_OFFSET 0x00000000 /* Channel control */
#define XAXIDMA_TX_SR_OFFSET 0x00000004 /* Status */
#define XAXIDMA_TX_CDESC_OFFSET 0x00000008 /* Current descriptor pointer */
#define XAXIDMA_TX_TDESC_OFFSET 0x00000010 /* Tail descriptor pointer */
#define XAXIDMA_RX_CR_OFFSET 0x00000030 /* Channel control */
#define XAXIDMA_RX_SR_OFFSET 0x00000034 /* Status */
#define XAXIDMA_RX_CDESC_OFFSET 0x00000038 /* Current descriptor pointer */
#define XAXIDMA_RX_TDESC_OFFSET 0x00000040 /* Tail descriptor pointer */
#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
#define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
#define XAXIDMA_BD_NDESC_OFFSET 0x00 /* Next descriptor pointer */
#define XAXIDMA_BD_BUFA_OFFSET 0x08 /* Buffer address */
#define XAXIDMA_BD_CTRL_LEN_OFFSET 0x18 /* Control/buffer length */
#define XAXIDMA_BD_STS_OFFSET 0x1C /* Status */
#define XAXIDMA_BD_USR0_OFFSET 0x20 /* User IP specific word0 */
#define XAXIDMA_BD_USR1_OFFSET 0x24 /* User IP specific word1 */
#define XAXIDMA_BD_USR2_OFFSET 0x28 /* User IP specific word2 */
#define XAXIDMA_BD_USR3_OFFSET 0x2C /* User IP specific word3 */
#define XAXIDMA_BD_USR4_OFFSET 0x30 /* User IP specific word4 */
#define XAXIDMA_BD_ID_OFFSET 0x34 /* Sw ID */
#define XAXIDMA_BD_HAS_STSCNTRL_OFFSET 0x38 /* Whether has stscntrl strm */
#define XAXIDMA_BD_HAS_DRE_OFFSET 0x3C /* Whether has DRE */
#define XAXIDMA_BD_HAS_DRE_SHIFT 8 /* Whether has DRE shift */
#define XAXIDMA_BD_HAS_DRE_MASK 0xF00 /* Whether has DRE mask */
#define XAXIDMA_BD_WORDLEN_MASK 0xFF /* Whether has DRE mask */
#define XAXIDMA_BD_CTRL_LENGTH_MASK 0x007FFFFF /* Requested len */
#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
#define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */
#define XAXIDMA_DELAY_MASK 0xFF000000 /* Delay timeout counter */
#define XAXIDMA_COALESCE_MASK 0x00FF0000 /* Coalesce counter */
#define XAXIDMA_DELAY_SHIFT 24
#define XAXIDMA_COALESCE_SHIFT 16
#define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
#define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
#define XAXIDMA_IRQ_ERROR_MASK 0x00004000 /* Error interrupt */
#define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
/* Default TX/RX Threshold and waitbound values for SGDMA mode */
#define XAXIDMA_DFT_TX_THRESHOLD 24
#define XAXIDMA_DFT_TX_WAITBOUND 254
#define XAXIDMA_DFT_RX_THRESHOLD 24
#define XAXIDMA_DFT_RX_WAITBOUND 254
#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
#define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */
#define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
#define XAXIDMA_BD_STS_COMPLETE_MASK 0x80000000 /* Completed */
#define XAXIDMA_BD_STS_DEC_ERR_MASK 0x40000000 /* Decode error */
#define XAXIDMA_BD_STS_SLV_ERR_MASK 0x20000000 /* Slave error */
#define XAXIDMA_BD_STS_INT_ERR_MASK 0x10000000 /* Internal err */
#define XAXIDMA_BD_STS_ALL_ERR_MASK 0x70000000 /* All errors */
#define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /* First rx pkt */
#define XAXIDMA_BD_STS_RXEOF_MASK 0x04000000 /* Last rx pkt */
#define XAXIDMA_BD_STS_ALL_MASK 0xFC000000 /* All status bits */
#define XAXIDMA_BD_MINIMUM_ALIGNMENT 0x40
/* Axi Ethernet registers definition */
#define XAE_RAF_OFFSET 0x00000000 /* Reset and Address filter */
#define XAE_TPF_OFFSET 0x00000004 /* Tx Pause Frame */
#define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
#define XAE_IS_OFFSET 0x0000000C /* Interrupt status */
#define XAE_IP_OFFSET 0x00000010 /* Interrupt pending */
#define XAE_IE_OFFSET 0x00000014 /* Interrupt enable */
#define XAE_TTAG_OFFSET 0x00000018 /* Tx VLAN TAG */
#define XAE_RTAG_OFFSET 0x0000001C /* Rx VLAN TAG */
#define XAE_UAWL_OFFSET 0x00000020 /* Unicast address word lower */
#define XAE_UAWU_OFFSET 0x00000024 /* Unicast address word upper */
#define XAE_TPID0_OFFSET 0x00000028 /* VLAN TPID0 register */
#define XAE_TPID1_OFFSET 0x0000002C /* VLAN TPID1 register */
#define XAE_PPST_OFFSET 0x00000030 /* PCS PMA Soft Temac Status Reg */
#define XAE_RCW0_OFFSET 0x00000400 /* Rx Configuration Word 0 */
#define XAE_RCW1_OFFSET 0x00000404 /* Rx Configuration Word 1 */
#define XAE_TC_OFFSET 0x00000408 /* Tx Configuration */
#define XAE_FCC_OFFSET 0x0000040C /* Flow Control Configuration */
#define XAE_EMMC_OFFSET 0x00000410 /* EMAC mode configuration */
#define XAE_PHYC_OFFSET 0x00000414 /* RGMII/SGMII configuration */
#define XAE_MDIO_MC_OFFSET 0x00000500 /* MII Management Config */
#define XAE_MDIO_MCR_OFFSET 0x00000504 /* MII Management Control */
#define XAE_MDIO_MWD_OFFSET 0x00000508 /* MII Management Write Data */
#define XAE_MDIO_MRD_OFFSET 0x0000050C /* MII Management Read Data */
#define XAE_MDIO_MIS_OFFSET 0x00000600 /* MII Management Interrupt Status */
#define XAE_MDIO_MIP_OFFSET 0x00000620 /* MII Mgmt Interrupt Pending
* register offset */
#define XAE_MDIO_MIE_OFFSET 0x00000640 /* MII Management Interrupt Enable
* register offset */
#define XAE_MDIO_MIC_OFFSET 0x00000660 /* MII Management Interrupt Clear
* register offset. */
#define XAE_UAW0_OFFSET 0x00000700 /* Unicast address word 0 */
#define XAE_UAW1_OFFSET 0x00000704 /* Unicast address word 1 */
#define XAE_FMI_OFFSET 0x00000708 /* Filter Mask Index */
#define XAE_AF0_OFFSET 0x00000710 /* Address Filter 0 */
#define XAE_AF1_OFFSET 0x00000714 /* Address Filter 1 */
#define XAE_TX_VLAN_DATA_OFFSET 0x00004000 /* TX VLAN data table address */
#define XAE_RX_VLAN_DATA_OFFSET 0x00008000 /* RX VLAN data table address */
#define XAE_MCAST_TABLE_OFFSET 0x00020000 /* Multicast table address */
/* Bit Masks for Axi Ethernet RAF register */
#define XAE_RAF_MCSTREJ_MASK 0x00000002 /* Reject receive multicast
* destination address */
#define XAE_RAF_BCSTREJ_MASK 0x00000004 /* Reject receive broadcast
* destination address */
#define XAE_RAF_TXVTAGMODE_MASK 0x00000018 /* Tx VLAN TAG mode */
#define XAE_RAF_RXVTAGMODE_MASK 0x00000060 /* Rx VLAN TAG mode */
#define XAE_RAF_TXVSTRPMODE_MASK 0x00000180 /* Tx VLAN STRIP mode */
#define XAE_RAF_RXVSTRPMODE_MASK 0x00000600 /* Rx VLAN STRIP mode */
#define XAE_RAF_NEWFNCENBL_MASK 0x00000800 /* New function mode */
#define XAE_RAF_EMULTIFLTRENBL_MASK 0x00001000 /* Exteneded Multicast
* Filtering mode
*/
#define XAE_RAF_STATSRST_MASK 0x00002000 /* Stats. Counter Reset */
#define XAE_RAF_RXBADFRMEN_MASK 0x00004000 /* Recv Bad Frame Enable */
#define XAE_RAF_TXVTAGMODE_SHIFT 3 /* Tx Tag mode shift bits */
#define XAE_RAF_RXVTAGMODE_SHIFT 5 /* Rx Tag mode shift bits */
#define XAE_RAF_TXVSTRPMODE_SHIFT 7 /* Tx strip mode shift bits*/
#define XAE_RAF_RXVSTRPMODE_SHIFT 9 /* Rx Strip mode shift bits*/
/* Bit Masks for Axi Ethernet TPF and IFGP registers */
#define XAE_TPF_TPFV_MASK 0x0000FFFF /* Tx pause frame value */
#define XAE_IFGP0_IFGP_MASK 0x0000007F /* Transmit inter-frame
* gap adjustment value */
/* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
* for all 3 registers. */
#define XAE_INT_HARDACSCMPLT_MASK 0x00000001 /* Hard register access
* complete */
#define XAE_INT_AUTONEG_MASK 0x00000002 /* Auto negotiation
* complete */
#define XAE_INT_RXCMPIT_MASK 0x00000004 /* Rx complete */
#define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
#define XAE_INT_RXFIFOOVR_MASK 0x00000010 /* Rx fifo overrun */
#define XAE_INT_TXCMPIT_MASK 0x00000020 /* Tx complete */
#define XAE_INT_RXDCMLOCK_MASK 0x00000040 /* Rx Dcm Lock */
#define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
#define XAE_INT_PHYRSTCMPLT_MASK 0x00000100 /* Phy Reset complete */
#define XAE_INT_ALL_MASK 0x0000003F /* All the ints */
#define XAE_INT_RECV_ERROR_MASK \
(XAE_INT_RXRJECT_MASK | XAE_INT_RXFIFOOVR_MASK) /* INT bits that
* indicate receive
* errors */
/* Bit masks for Axi Ethernet VLAN TPID Word 0 register */
#define XAE_TPID_0_MASK 0x0000FFFF /* TPID 0 */
#define XAE_TPID_1_MASK 0xFFFF0000 /* TPID 1 */
/* Bit masks for Axi Ethernet VLAN TPID Word 1 register */
#define XAE_TPID_2_MASK 0x0000FFFF /* TPID 0 */
#define XAE_TPID_3_MASK 0xFFFF0000 /* TPID 1 */
/* Bit masks for Axi Ethernet RCW1 register */
#define XAE_RCW1_RST_MASK 0x80000000 /* Reset */
#define XAE_RCW1_JUM_MASK 0x40000000 /* Jumbo frame enable */
#define XAE_RCW1_FCS_MASK 0x20000000 /* In-Band FCS enable
* (FCS not stripped) */
#define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
#define XAE_RCW1_VLAN_MASK 0x08000000 /* VLAN frame enable */
#define XAE_RCW1_LT_DIS_MASK 0x02000000 /* Length/type field valid check
* disable */
#define XAE_RCW1_CL_DIS_MASK 0x01000000 /* Control frame Length check
* disable */
#define XAE_RCW1_PAUSEADDR_MASK 0x0000FFFF /* Pause frame source address
* bits [47:32]. Bits [31:0] are
* stored in register RCW0 */
/* Bit masks for Axi Ethernet TC register */
#define XAE_TC_RST_MASK 0x80000000 /* Reset */
#define XAE_TC_JUM_MASK 0x40000000 /* Jumbo frame enable */
#define XAE_TC_FCS_MASK 0x20000000 /* In-Band FCS enable
* (FCS not generated) */
#define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
#define XAE_TC_VLAN_MASK 0x08000000 /* VLAN frame enable */
#define XAE_TC_IFG_MASK 0x02000000 /* Inter-frame gap adjustment
* enable */
/* Bit masks for Axi Ethernet FCC register */
#define XAE_FCC_FCRX_MASK 0x20000000 /* Rx flow control enable */
#define XAE_FCC_FCTX_MASK 0x40000000 /* Tx flow control enable */
/* Bit masks for Axi Ethernet EMMC register */
#define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
#define XAE_EMMC_RGMII_MASK 0x20000000 /* RGMII mode enable */
#define XAE_EMMC_SGMII_MASK 0x10000000 /* SGMII mode enable */
#define XAE_EMMC_GPCS_MASK 0x08000000 /* 1000BaseX mode enable */
#define XAE_EMMC_HOST_MASK 0x04000000 /* Host interface enable */
#define XAE_EMMC_TX16BIT 0x02000000 /* 16 bit Tx client enable */
#define XAE_EMMC_RX16BIT 0x01000000 /* 16 bit Rx client enable */
#define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
#define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
#define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
/* Bit masks for Axi Ethernet PHYC register */
#define XAE_PHYC_SGMIILINKSPEED_MASK 0xC0000000 /* SGMII link speed mask*/
#define XAE_PHYC_RGMIILINKSPEED_MASK 0x0000000C /* RGMII link speed */
#define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */
#define XAE_PHYC_RGMIILINK_MASK 0x00000001 /* RGMII link status */
#define XAE_PHYC_RGLINKSPD_10 0x00000000 /* RGMII link 10 Mbit */
#define XAE_PHYC_RGLINKSPD_100 0x00000004 /* RGMII link 100 Mbit */
#define XAE_PHYC_RGLINKSPD_1000 0x00000008 /* RGMII link 1000 Mbit */
#define XAE_PHYC_SGLINKSPD_10 0x00000000 /* SGMII link 10 Mbit */
#define XAE_PHYC_SGLINKSPD_100 0x40000000 /* SGMII link 100 Mbit */
#define XAE_PHYC_SGLINKSPD_1000 0x80000000 /* SGMII link 1000 Mbit */
/* Bit masks for Axi Ethernet MDIO interface MC register */
#define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable */
#define XAE_MDIO_MC_CLOCK_DIVIDE_MAX 0x3F /* Maximum MDIO divisor */
/* Bit masks for Axi Ethernet MDIO interface MCR register */
#define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
#define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
#define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
#define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
#define XAE_MDIO_MCR_OP_MASK 0x0000C000 /* Operation Code Mask */
#define XAE_MDIO_MCR_OP_SHIFT 13 /* Operation Code Shift */
#define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
#define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
#define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
#define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
/* Bit masks for Axi Ethernet MDIO interface MIS, MIP, MIE, MIC registers */
#define XAE_MDIO_INT_MIIM_RDY_MASK 0x00000001 /* MIIM Interrupt */
/* Bit masks for Axi Ethernet UAW1 register */
#define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF /* Station address bits
* [47:32]; Station address
* bits [31:0] are stored in
* register UAW0 */
/* Bit masks for Axi Ethernet FMI register */
#define XAE_FMI_PM_MASK 0x80000000 /* Promis. mode enable */
#define XAE_FMI_IND_MASK 0x00000003 /* Index Mask */
#define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
/* Defines for different options for C_PHY_TYPE parameter in Axi Ethernet IP */
#define XAE_PHY_TYPE_MII 0
#define XAE_PHY_TYPE_GMII 1
#define XAE_PHY_TYPE_RGMII_1_3 2
#define XAE_PHY_TYPE_RGMII_2_0 3
#define XAE_PHY_TYPE_SGMII 4
#define XAE_PHY_TYPE_1000BASE_X 5
#define XAE_MULTICAST_CAM_TABLE_NUM 4 /* Total number of entries in the
* hardware multicast table. */
/* Axi Ethernet Synthesis features */
#define XAE_FEATURE_PARTIAL_RX_CSUM (1 << 0)
#define XAE_FEATURE_PARTIAL_TX_CSUM (1 << 1)
#define XAE_FEATURE_FULL_RX_CSUM (1 << 2)
#define XAE_FEATURE_FULL_TX_CSUM (1 << 3)
#define XAE_NO_CSUM_OFFLOAD 0
#define XAE_FULL_CSUM_STATUS_MASK 0x00000038
#define XAE_IP_UDP_CSUM_VALIDATED 0x00000003
#define XAE_IP_TCP_CSUM_VALIDATED 0x00000002
#define DELAY_OF_ONE_MILLISEC 1000
/**
* struct axidma_bd - Axi Dma buffer descriptor layout
* @next: MM2S/S2MM Next Descriptor Pointer
* @reserved1: Reserved and not used
* @phys: MM2S/S2MM Buffer Address
* @reserved2: Reserved and not used
* @reserved3: Reserved and not used
* @reserved4: Reserved and not used
* @cntrl: MM2S/S2MM Control value
* @status: MM2S/S2MM Status value
* @app0: MM2S/S2MM User Application Field 0.
* @app1: MM2S/S2MM User Application Field 1.
* @app2: MM2S/S2MM User Application Field 2.
* @app3: MM2S/S2MM User Application Field 3.
* @app4: MM2S/S2MM User Application Field 4.
* @sw_id_offset: MM2S/S2MM Sw ID
* @reserved5: Reserved and not used
* @reserved6: Reserved and not used
*/
struct axidma_bd {
u32 next; /* Physical address of next buffer descriptor */
u32 reserved1;
u32 phys;
u32 reserved2;
u32 reserved3;
u32 reserved4;
u32 cntrl;
u32 status;
u32 app0;
u32 app1; /* TX start << 16 | insert */
u32 app2; /* TX csum seed */
u32 app3;
u32 app4;
u32 sw_id_offset;
u32 reserved5;
u32 reserved6;
};
/**
* struct axienet_local - axienet private per device data
* @ndev: Pointer for net_device to which it will be attached.
* @dev: Pointer to device structure
* @phy_dev: Pointer to PHY device structure attached to the axienet_local
* @phy_node: Pointer to device node structure
* @mii_bus: Pointer to MII bus structure
* @mdio_irqs: IRQs table for MDIO bus required in mii_bus structure
* @regs: Base address for the axienet_local device address space
* @dma_regs: Base address for the axidma device address space
* @dma_err_tasklet: Tasklet structure to process Axi DMA errors
* @tx_irq: Axidma TX IRQ number
* @rx_irq: Axidma RX IRQ number
* @temac_type: axienet type to identify between soft and hard temac
* @phy_type: Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
* @options: AxiEthernet option word
* @last_link: Phy link state in which the PHY was negotiated earlier
* @features: Stores the extended features supported by the axienet hw
* @tx_bd_v: Virtual address of the TX buffer descriptor ring
* @tx_bd_p: Physical address(start address) of the TX buffer descr. ring
* @rx_bd_v: Virtual address of the RX buffer descriptor ring
* @rx_bd_p: Physical address(start address) of the RX buffer descr. ring
* @tx_bd_ci: Stores the index of the Tx buffer descriptor in the ring being
* accessed currently. Used while alloc. BDs before a TX starts
* @tx_bd_tail: Stores the index of the Tx buffer descriptor in the ring being
* accessed currently. Used while processing BDs after the TX
* completed.
* @rx_bd_ci: Stores the index of the Rx buffer descriptor in the ring being
* accessed currently.
* @max_frm_size: Stores the maximum size of the frame that can be that
* Txed/Rxed in the existing hardware. If jumbo option is
* supported, the maximum frame size would be 9k. Else it is
* 1522 bytes (assuming support for basic VLAN)
* @jumbo_support: Stores hardware configuration for jumbo support. If hardware
* can handle jumbo packets, this entry will be 1, else 0.
*/
struct axienet_local {
struct net_device *ndev;
struct device *dev;
/* Connection to PHY device */
struct phy_device *phy_dev; /* Pointer to PHY device */
struct device_node *phy_node;
/* MDIO bus data */
struct mii_bus *mii_bus; /* MII bus reference */
int mdio_irqs[PHY_MAX_ADDR]; /* IRQs table for MDIO bus */
/* IO registers, dma functions and IRQs */
void __iomem *regs;
void __iomem *dma_regs;
struct tasklet_struct dma_err_tasklet;
int tx_irq;
int rx_irq;
u32 temac_type;
u32 phy_type;
u32 options; /* Current options word */
u32 last_link;
u32 features;
/* Buffer descriptors */
struct axidma_bd *tx_bd_v;
dma_addr_t tx_bd_p;
struct axidma_bd *rx_bd_v;
dma_addr_t rx_bd_p;
u32 tx_bd_ci;
u32 tx_bd_tail;
u32 rx_bd_ci;
u32 max_frm_size;
u32 jumbo_support;
int csum_offload_on_tx_path;
int csum_offload_on_rx_path;
u32 coalesce_count_rx;
u32 coalesce_count_tx;
};
/**
* struct axiethernet_option - Used to set axi ethernet hardware options
* @opt: Option to be set.
* @reg: Register offset to be written for setting the option
* @m_or: Mask to be ORed for setting the option in the register
*/
struct axienet_option {
u32 opt;
u32 reg;
u32 m_or;
};
/**
* axienet_ior - Memory mapped Axi Ethernet register read
* @lp: Pointer to axienet local structure
* @offset: Address offset from the base address of Axi Ethernet core
*
* returns: The contents of the Axi Ethernet register
*
* This function returns the contents of the corresponding register.
*/
static inline u32 axienet_ior(struct axienet_local *lp, off_t offset)
{
return in_be32(lp->regs + offset);
}
/**
* axienet_iow - Memory mapped Axi Ethernet register write
* @lp: Pointer to axienet local structure
* @offset: Address offset from the base address of Axi Ethernet core
* @value: Value to be written into the Axi Ethernet register
*
* This function writes the desired value into the corresponding Axi Ethernet
* register.
*/
static inline void axienet_iow(struct axienet_local *lp, off_t offset,
u32 value)
{
out_be32((lp->regs + offset), value);
}
/* Function prototypes visible in xilinx_axienet_mdio.c for other files */
int axienet_mdio_setup(struct axienet_local *lp, struct device_node *np);
int axienet_mdio_wait_until_ready(struct axienet_local *lp);
void axienet_mdio_teardown(struct axienet_local *lp);
#endif /* XILINX_AXI_ENET_H */

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/*
* MDIO bus driver for the Xilinx Axi Ethernet device
*
* Copyright (c) 2009 Secret Lab Technologies, Ltd.
* Copyright (c) 2010 - 2011 Michal Simek <monstr@monstr.eu>
* Copyright (c) 2010 - 2011 PetaLogix
* Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
*/
#include <linux/of_address.h>
#include <linux/of_mdio.h>
#include <linux/jiffies.h>
#include "xilinx_axienet.h"
#define MAX_MDIO_FREQ 2500000 /* 2.5 MHz */
#define DEFAULT_CLOCK_DIVISOR XAE_MDIO_DIV_DFT
/* Wait till MDIO interface is ready to accept a new transaction.*/
int axienet_mdio_wait_until_ready(struct axienet_local *lp)
{
long end = jiffies + 2;
while (!(axienet_ior(lp, XAE_MDIO_MCR_OFFSET) &
XAE_MDIO_MCR_READY_MASK)) {
if (end - jiffies <= 0) {
WARN_ON(1);
return -ETIMEDOUT;
}
udelay(1);
}
return 0;
}
/**
* axienet_mdio_read - MDIO interface read function
* @bus: Pointer to mii bus structure
* @phy_id: Address of the PHY device
* @reg: PHY register to read
*
* returns: The register contents on success, -ETIMEDOUT on a timeout
*
* Reads the contents of the requested register from the requested PHY
* address by first writing the details into MCR register. After a while
* the register MRD is read to obtain the PHY register content.
*/
static int axienet_mdio_read(struct mii_bus *bus, int phy_id, int reg)
{
u32 rc;
int ret;
struct axienet_local *lp = bus->priv;
ret = axienet_mdio_wait_until_ready(lp);
if (ret < 0)
return ret;
axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
(((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) &
XAE_MDIO_MCR_PHYAD_MASK) |
((reg << XAE_MDIO_MCR_REGAD_SHIFT) &
XAE_MDIO_MCR_REGAD_MASK) |
XAE_MDIO_MCR_INITIATE_MASK |
XAE_MDIO_MCR_OP_READ_MASK));
ret = axienet_mdio_wait_until_ready(lp);
if (ret < 0)
return ret;
rc = axienet_ior(lp, XAE_MDIO_MRD_OFFSET) & 0x0000FFFF;
dev_dbg(lp->dev, "axienet_mdio_read(phy_id=%i, reg=%x) == %x\n",
phy_id, reg, rc);
return rc;
}
/**
* axienet_mdio_write - MDIO interface write function
* @bus: Pointer to mii bus structure
* @phy_id: Address of the PHY device
* @reg: PHY register to write to
* @val: Value to be written into the register
*
* returns: 0 on success, -ETIMEDOUT on a timeout
*
* Writes the value to the requested register by first writing the value
* into MWD register. The the MCR register is then appropriately setup
* to finish the write operation.
*/
static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg,
u16 val)
{
int ret;
struct axienet_local *lp = bus->priv;
dev_dbg(lp->dev, "axienet_mdio_write(phy_id=%i, reg=%x, val=%x)\n",
phy_id, reg, val);
ret = axienet_mdio_wait_until_ready(lp);
if (ret < 0)
return ret;
axienet_iow(lp, XAE_MDIO_MWD_OFFSET, (u32) val);
axienet_iow(lp, XAE_MDIO_MCR_OFFSET,
(((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) &
XAE_MDIO_MCR_PHYAD_MASK) |
((reg << XAE_MDIO_MCR_REGAD_SHIFT) &
XAE_MDIO_MCR_REGAD_MASK) |
XAE_MDIO_MCR_INITIATE_MASK |
XAE_MDIO_MCR_OP_WRITE_MASK));
ret = axienet_mdio_wait_until_ready(lp);
if (ret < 0)
return ret;
return 0;
}
/**
* axienet_mdio_setup - MDIO setup function
* @lp: Pointer to axienet local data structure.
* @np: Pointer to device node
*
* returns: 0 on success, -ETIMEDOUT on a timeout, -ENOMEM when
* mdiobus_alloc (to allocate memory for mii bus structure) fails.
*
* Sets up the MDIO interface by initializing the MDIO clock and enabling the
* MDIO interface in hardware. Register the MDIO interface.
**/
int axienet_mdio_setup(struct axienet_local *lp, struct device_node *np)
{
int ret;
u32 clk_div, host_clock;
u32 *property_p;
struct mii_bus *bus;
struct resource res;
struct device_node *np1;
/* clk_div can be calculated by deriving it from the equation:
* fMDIO = fHOST / ((1 + clk_div) * 2)
*
* Where fMDIO <= 2500000, so we get:
* fHOST / ((1 + clk_div) * 2) <= 2500000
*
* Then we get:
* 1 / ((1 + clk_div) * 2) <= (2500000 / fHOST)
*
* Then we get:
* 1 / (1 + clk_div) <= ((2500000 * 2) / fHOST)
*
* Then we get:
* 1 / (1 + clk_div) <= (5000000 / fHOST)
*
* So:
* (1 + clk_div) >= (fHOST / 5000000)
*
* And finally:
* clk_div >= (fHOST / 5000000) - 1
*
* fHOST can be read from the flattened device tree as property
* "clock-frequency" from the CPU
*/
np1 = of_find_node_by_name(NULL, "cpu");
if (!np1) {
printk(KERN_WARNING "%s(): Could not find CPU device node.",
__func__);
printk(KERN_WARNING "Setting MDIO clock divisor to "
"default %d\n", DEFAULT_CLOCK_DIVISOR);
clk_div = DEFAULT_CLOCK_DIVISOR;
goto issue;
}
property_p = (u32 *) of_get_property(np1, "clock-frequency", NULL);
if (!property_p) {
printk(KERN_WARNING "%s(): Could not find CPU property: "
"clock-frequency.", __func__);
printk(KERN_WARNING "Setting MDIO clock divisor to "
"default %d\n", DEFAULT_CLOCK_DIVISOR);
clk_div = DEFAULT_CLOCK_DIVISOR;
goto issue;
}
host_clock = be32_to_cpup(property_p);
clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1;
/* If there is any remainder from the division of
* fHOST / (MAX_MDIO_FREQ * 2), then we need to add
* 1 to the clock divisor or we will surely be above 2.5 MHz */
if (host_clock % (MAX_MDIO_FREQ * 2))
clk_div++;
printk(KERN_DEBUG "%s(): Setting MDIO clock divisor to %u based "
"on %u Hz host clock.\n", __func__, clk_div, host_clock);
of_node_put(np1);
issue:
axienet_iow(lp, XAE_MDIO_MC_OFFSET,
(((u32) clk_div) | XAE_MDIO_MC_MDIOEN_MASK));
ret = axienet_mdio_wait_until_ready(lp);
if (ret < 0)
return ret;
bus = mdiobus_alloc();
if (!bus)
return -ENOMEM;
np1 = of_get_parent(lp->phy_node);
of_address_to_resource(np1, 0, &res);
snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
(unsigned long long) res.start);
bus->priv = lp;
bus->name = "Xilinx Axi Ethernet MDIO";
bus->read = axienet_mdio_read;
bus->write = axienet_mdio_write;
bus->parent = lp->dev;
bus->irq = lp->mdio_irqs; /* preallocated IRQ table */
lp->mii_bus = bus;
ret = of_mdiobus_register(bus, np1);
if (ret) {
mdiobus_free(bus);
return ret;
}
return 0;
}
/**
* axienet_mdio_teardown - MDIO remove function
* @lp: Pointer to axienet local data structure.
*
* Unregisters the MDIO and frees any associate memory for mii bus.
*/
void axienet_mdio_teardown(struct axienet_local *lp)
{
mdiobus_unregister(lp->mii_bus);
kfree(lp->mii_bus->irq);
mdiobus_free(lp->mii_bus);
lp->mii_bus = NULL;
}

1308
kernel/drivers/net/ethernet/xilinx/xilinx_emaclite.c Normal file
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