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2024-09-09 08:52:07 +00:00
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kernel/arch/mips/include/asm/sibyte/bcm1480_int.h Normal file
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/* *********************************************************************
* BCM1280/BCM1480 Board Support Package
*
* Interrupt Mapper definitions File: bcm1480_int.h
*
* This module contains constants for manipulating the
* BCM1255/BCM1280/BCM1455/BCM1480's interrupt mapper and
* definitions for the interrupt sources.
*
* BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03)
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _BCM1480_INT_H
#define _BCM1480_INT_H
#include "sb1250_defs.h"
/* *********************************************************************
* Interrupt Mapper Constants
********************************************************************* */
/*
* The interrupt mapper deals with 128-bit logical registers that are
* implemented as pairs of 64-bit registers, with the "low" 64 bits in
* a register that has an address 0x1000 higher(!) than the
* corresponding "high" register.
*
* For appropriate registers, bit 0 of the "high" register is a
* cascade bit that summarizes (as a bit-OR) the 64 bits of the "low"
* register.
*/
/*
* This entire file uses _BCM1480_ in all the symbols because it is
* entirely BCM1480 specific.
*/
/*
* Interrupt sources (Table 22)
*/
#define K_BCM1480_INT_SOURCES 128
#define _BCM1480_INT_HIGH(k) (k)
#define _BCM1480_INT_LOW(k) ((k)+64)
#define K_BCM1480_INT_ADDR_TRAP _BCM1480_INT_HIGH(1)
#define K_BCM1480_INT_GPIO_0 _BCM1480_INT_HIGH(4)
#define K_BCM1480_INT_GPIO_1 _BCM1480_INT_HIGH(5)
#define K_BCM1480_INT_GPIO_2 _BCM1480_INT_HIGH(6)
#define K_BCM1480_INT_GPIO_3 _BCM1480_INT_HIGH(7)
#define K_BCM1480_INT_PCI_INTA _BCM1480_INT_HIGH(8)
#define K_BCM1480_INT_PCI_INTB _BCM1480_INT_HIGH(9)
#define K_BCM1480_INT_PCI_INTC _BCM1480_INT_HIGH(10)
#define K_BCM1480_INT_PCI_INTD _BCM1480_INT_HIGH(11)
#define K_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_HIGH(12)
#define K_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_HIGH(13)
#define K_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_HIGH(14)
#define K_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_HIGH(15)
#define K_BCM1480_INT_TIMER_0 _BCM1480_INT_HIGH(20)
#define K_BCM1480_INT_TIMER_1 _BCM1480_INT_HIGH(21)
#define K_BCM1480_INT_TIMER_2 _BCM1480_INT_HIGH(22)
#define K_BCM1480_INT_TIMER_3 _BCM1480_INT_HIGH(23)
#define K_BCM1480_INT_DM_CH_0 _BCM1480_INT_HIGH(28)
#define K_BCM1480_INT_DM_CH_1 _BCM1480_INT_HIGH(29)
#define K_BCM1480_INT_DM_CH_2 _BCM1480_INT_HIGH(30)
#define K_BCM1480_INT_DM_CH_3 _BCM1480_INT_HIGH(31)
#define K_BCM1480_INT_MAC_0 _BCM1480_INT_HIGH(36)
#define K_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_HIGH(37)
#define K_BCM1480_INT_MAC_1 _BCM1480_INT_HIGH(38)
#define K_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_HIGH(39)
#define K_BCM1480_INT_MAC_2 _BCM1480_INT_HIGH(40)
#define K_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_HIGH(41)
#define K_BCM1480_INT_MAC_3 _BCM1480_INT_HIGH(42)
#define K_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_HIGH(43)
#define K_BCM1480_INT_PMI_LOW _BCM1480_INT_HIGH(52)
#define K_BCM1480_INT_PMI_HIGH _BCM1480_INT_HIGH(53)
#define K_BCM1480_INT_PMO_LOW _BCM1480_INT_HIGH(54)
#define K_BCM1480_INT_PMO_HIGH _BCM1480_INT_HIGH(55)
#define K_BCM1480_INT_MBOX_0_0 _BCM1480_INT_HIGH(56)
#define K_BCM1480_INT_MBOX_0_1 _BCM1480_INT_HIGH(57)
#define K_BCM1480_INT_MBOX_0_2 _BCM1480_INT_HIGH(58)
#define K_BCM1480_INT_MBOX_0_3 _BCM1480_INT_HIGH(59)
#define K_BCM1480_INT_MBOX_1_0 _BCM1480_INT_HIGH(60)
#define K_BCM1480_INT_MBOX_1_1 _BCM1480_INT_HIGH(61)
#define K_BCM1480_INT_MBOX_1_2 _BCM1480_INT_HIGH(62)
#define K_BCM1480_INT_MBOX_1_3 _BCM1480_INT_HIGH(63)
#define K_BCM1480_INT_BAD_ECC _BCM1480_INT_LOW(1)
#define K_BCM1480_INT_COR_ECC _BCM1480_INT_LOW(2)
#define K_BCM1480_INT_IO_BUS _BCM1480_INT_LOW(3)
#define K_BCM1480_INT_PERF_CNT _BCM1480_INT_LOW(4)
#define K_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_LOW(5)
#define K_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_LOW(6)
#define K_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_LOW(7)
#define K_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_LOW(8)
#define K_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_LOW(9)
#define K_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_LOW(10)
#define K_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_LOW(11)
#define K_BCM1480_INT_PCI_ERROR _BCM1480_INT_LOW(16)
#define K_BCM1480_INT_PCI_RESET _BCM1480_INT_LOW(17)
#define K_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_LOW(18)
#define K_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_LOW(19)
#define K_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_LOW(20)
#define K_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_LOW(21)
#define K_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_LOW(22)
#define K_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_LOW(23)
#define K_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_LOW(24)
#define K_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_LOW(25)
#define K_BCM1480_INT_LDT_SMI _BCM1480_INT_LOW(32)
#define K_BCM1480_INT_LDT_NMI _BCM1480_INT_LOW(33)
#define K_BCM1480_INT_LDT_INIT _BCM1480_INT_LOW(34)
#define K_BCM1480_INT_LDT_STARTUP _BCM1480_INT_LOW(35)
#define K_BCM1480_INT_LDT_EXT _BCM1480_INT_LOW(36)
#define K_BCM1480_INT_SMB_0 _BCM1480_INT_LOW(40)
#define K_BCM1480_INT_SMB_1 _BCM1480_INT_LOW(41)
#define K_BCM1480_INT_PCMCIA _BCM1480_INT_LOW(42)
#define K_BCM1480_INT_UART_0 _BCM1480_INT_LOW(44)
#define K_BCM1480_INT_UART_1 _BCM1480_INT_LOW(45)
#define K_BCM1480_INT_UART_2 _BCM1480_INT_LOW(46)
#define K_BCM1480_INT_UART_3 _BCM1480_INT_LOW(47)
#define K_BCM1480_INT_GPIO_4 _BCM1480_INT_LOW(52)
#define K_BCM1480_INT_GPIO_5 _BCM1480_INT_LOW(53)
#define K_BCM1480_INT_GPIO_6 _BCM1480_INT_LOW(54)
#define K_BCM1480_INT_GPIO_7 _BCM1480_INT_LOW(55)
#define K_BCM1480_INT_GPIO_8 _BCM1480_INT_LOW(56)
#define K_BCM1480_INT_GPIO_9 _BCM1480_INT_LOW(57)
#define K_BCM1480_INT_GPIO_10 _BCM1480_INT_LOW(58)
#define K_BCM1480_INT_GPIO_11 _BCM1480_INT_LOW(59)
#define K_BCM1480_INT_GPIO_12 _BCM1480_INT_LOW(60)
#define K_BCM1480_INT_GPIO_13 _BCM1480_INT_LOW(61)
#define K_BCM1480_INT_GPIO_14 _BCM1480_INT_LOW(62)
#define K_BCM1480_INT_GPIO_15 _BCM1480_INT_LOW(63)
/*
* Mask values for each interrupt
*/
#define _BCM1480_INT_MASK(w, n) _SB_MAKEMASK(w, ((n) & 0x3F))
#define _BCM1480_INT_MASK1(n) _SB_MAKEMASK1(((n) & 0x3F))
#define _BCM1480_INT_OFFSET(n) (((n) & 0x40) << 6)
#define M_BCM1480_INT_CASCADE _BCM1480_INT_MASK1(_BCM1480_INT_HIGH(0))
#define M_BCM1480_INT_ADDR_TRAP _BCM1480_INT_MASK1(K_BCM1480_INT_ADDR_TRAP)
#define M_BCM1480_INT_GPIO_0 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_0)
#define M_BCM1480_INT_GPIO_1 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_1)
#define M_BCM1480_INT_GPIO_2 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_2)
#define M_BCM1480_INT_GPIO_3 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_3)
#define M_BCM1480_INT_PCI_INTA _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTA)
#define M_BCM1480_INT_PCI_INTB _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTB)
#define M_BCM1480_INT_PCI_INTC _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTC)
#define M_BCM1480_INT_PCI_INTD _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTD)
#define M_BCM1480_INT_CYCLE_CP0 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP0)
#define M_BCM1480_INT_CYCLE_CP1 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP1)
#define M_BCM1480_INT_CYCLE_CP2 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP2)
#define M_BCM1480_INT_CYCLE_CP3 _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP3)
#define M_BCM1480_INT_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_0)
#define M_BCM1480_INT_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_1)
#define M_BCM1480_INT_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_2)
#define M_BCM1480_INT_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_3)
#define M_BCM1480_INT_DM_CH_0 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_0)
#define M_BCM1480_INT_DM_CH_1 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_1)
#define M_BCM1480_INT_DM_CH_2 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_2)
#define M_BCM1480_INT_DM_CH_3 _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_3)
#define M_BCM1480_INT_MAC_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0)
#define M_BCM1480_INT_MAC_0_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0_CH1)
#define M_BCM1480_INT_MAC_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1)
#define M_BCM1480_INT_MAC_1_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1_CH1)
#define M_BCM1480_INT_MAC_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2)
#define M_BCM1480_INT_MAC_2_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2_CH1)
#define M_BCM1480_INT_MAC_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3)
#define M_BCM1480_INT_MAC_3_CH1 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3_CH1)
#define M_BCM1480_INT_PMI_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_LOW)
#define M_BCM1480_INT_PMI_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH)
#define M_BCM1480_INT_PMO_LOW _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW)
#define M_BCM1480_INT_PMO_HIGH _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH)
#define M_BCM1480_INT_MBOX_ALL _BCM1480_INT_MASK(8, K_BCM1480_INT_MBOX_0_0)
#define M_BCM1480_INT_MBOX_0_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0)
#define M_BCM1480_INT_MBOX_0_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1)
#define M_BCM1480_INT_MBOX_0_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2)
#define M_BCM1480_INT_MBOX_0_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_3)
#define M_BCM1480_INT_MBOX_1_0 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_0)
#define M_BCM1480_INT_MBOX_1_1 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_1)
#define M_BCM1480_INT_MBOX_1_2 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_2)
#define M_BCM1480_INT_MBOX_1_3 _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_3)
#define M_BCM1480_INT_BAD_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_BAD_ECC)
#define M_BCM1480_INT_COR_ECC _BCM1480_INT_MASK1(K_BCM1480_INT_COR_ECC)
#define M_BCM1480_INT_IO_BUS _BCM1480_INT_MASK1(K_BCM1480_INT_IO_BUS)
#define M_BCM1480_INT_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_PERF_CNT)
#define M_BCM1480_INT_SW_PERF_CNT _BCM1480_INT_MASK1(K_BCM1480_INT_SW_PERF_CNT)
#define M_BCM1480_INT_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_TRACE_FREEZE)
#define M_BCM1480_INT_SW_TRACE_FREEZE _BCM1480_INT_MASK1(K_BCM1480_INT_SW_TRACE_FREEZE)
#define M_BCM1480_INT_WATCHDOG_TIMER_0 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_0)
#define M_BCM1480_INT_WATCHDOG_TIMER_1 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_1)
#define M_BCM1480_INT_WATCHDOG_TIMER_2 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_2)
#define M_BCM1480_INT_WATCHDOG_TIMER_3 _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_3)
#define M_BCM1480_INT_PCI_ERROR _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_ERROR)
#define M_BCM1480_INT_PCI_RESET _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_RESET)
#define M_BCM1480_INT_NODE_CONTROLLER _BCM1480_INT_MASK1(K_BCM1480_INT_NODE_CONTROLLER)
#define M_BCM1480_INT_HOST_BRIDGE _BCM1480_INT_MASK1(K_BCM1480_INT_HOST_BRIDGE)
#define M_BCM1480_INT_PORT_0_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_FATAL)
#define M_BCM1480_INT_PORT_0_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_NONFATAL)
#define M_BCM1480_INT_PORT_1_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_FATAL)
#define M_BCM1480_INT_PORT_1_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_NONFATAL)
#define M_BCM1480_INT_PORT_2_FATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_FATAL)
#define M_BCM1480_INT_PORT_2_NONFATAL _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_NONFATAL)
#define M_BCM1480_INT_LDT_SMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_SMI)
#define M_BCM1480_INT_LDT_NMI _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_NMI)
#define M_BCM1480_INT_LDT_INIT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_INIT)
#define M_BCM1480_INT_LDT_STARTUP _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_STARTUP)
#define M_BCM1480_INT_LDT_EXT _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_EXT)
#define M_BCM1480_INT_SMB_0 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_0)
#define M_BCM1480_INT_SMB_1 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_1)
#define M_BCM1480_INT_PCMCIA _BCM1480_INT_MASK1(K_BCM1480_INT_PCMCIA)
#define M_BCM1480_INT_UART_0 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_0)
#define M_BCM1480_INT_UART_1 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_1)
#define M_BCM1480_INT_UART_2 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_2)
#define M_BCM1480_INT_UART_3 _BCM1480_INT_MASK1(K_BCM1480_INT_UART_3)
#define M_BCM1480_INT_GPIO_4 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_4)
#define M_BCM1480_INT_GPIO_5 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_5)
#define M_BCM1480_INT_GPIO_6 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_6)
#define M_BCM1480_INT_GPIO_7 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_7)
#define M_BCM1480_INT_GPIO_8 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_8)
#define M_BCM1480_INT_GPIO_9 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_9)
#define M_BCM1480_INT_GPIO_10 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_10)
#define M_BCM1480_INT_GPIO_11 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_11)
#define M_BCM1480_INT_GPIO_12 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_12)
#define M_BCM1480_INT_GPIO_13 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13)
#define M_BCM1480_INT_GPIO_14 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14)
#define M_BCM1480_INT_GPIO_15 _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15)
/*
* Interrupt mappings (Table 18)
*/
#define K_BCM1480_INT_MAP_I0 0 /* interrupt pins on processor */
#define K_BCM1480_INT_MAP_I1 1
#define K_BCM1480_INT_MAP_I2 2
#define K_BCM1480_INT_MAP_I3 3
#define K_BCM1480_INT_MAP_I4 4
#define K_BCM1480_INT_MAP_I5 5
#define K_BCM1480_INT_MAP_NMI 6 /* nonmaskable */
#define K_BCM1480_INT_MAP_DINT 7 /* debug interrupt */
/*
* Interrupt LDT Set Register (Table 19)
*/
#define S_BCM1480_INT_HT_INTMSG 0
#define M_BCM1480_INT_HT_INTMSG _SB_MAKEMASK(3, S_BCM1480_INT_HT_INTMSG)
#define V_BCM1480_INT_HT_INTMSG(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTMSG)
#define G_BCM1480_INT_HT_INTMSG(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTMSG, M_BCM1480_INT_HT_INTMSG)
#define K_BCM1480_INT_HT_INTMSG_FIXED 0
#define K_BCM1480_INT_HT_INTMSG_ARBITRATED 1
#define K_BCM1480_INT_HT_INTMSG_SMI 2
#define K_BCM1480_INT_HT_INTMSG_NMI 3
#define K_BCM1480_INT_HT_INTMSG_INIT 4
#define K_BCM1480_INT_HT_INTMSG_STARTUP 5
#define K_BCM1480_INT_HT_INTMSG_EXTINT 6
#define K_BCM1480_INT_HT_INTMSG_RESERVED 7
#define M_BCM1480_INT_HT_TRIGGERMODE _SB_MAKEMASK1(3)
#define V_BCM1480_INT_HT_EDGETRIGGER 0
#define V_BCM1480_INT_HT_LEVELTRIGGER M_BCM1480_INT_HT_TRIGGERMODE
#define M_BCM1480_INT_HT_DESTMODE _SB_MAKEMASK1(4)
#define V_BCM1480_INT_HT_PHYSICALDEST 0
#define V_BCM1480_INT_HT_LOGICALDEST M_BCM1480_INT_HT_DESTMODE
#define S_BCM1480_INT_HT_INTDEST 5
#define M_BCM1480_INT_HT_INTDEST _SB_MAKEMASK(8, S_BCM1480_INT_HT_INTDEST)
#define V_BCM1480_INT_HT_INTDEST(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTDEST)
#define G_BCM1480_INT_HT_INTDEST(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_INTDEST, M_BCM1480_INT_HT_INTDEST)
#define S_BCM1480_INT_HT_VECTOR 13
#define M_BCM1480_INT_HT_VECTOR _SB_MAKEMASK(8, S_BCM1480_INT_HT_VECTOR)
#define V_BCM1480_INT_HT_VECTOR(x) _SB_MAKEVALUE(x, S_BCM1480_INT_HT_VECTOR)
#define G_BCM1480_INT_HT_VECTOR(x) _SB_GETVALUE(x, S_BCM1480_INT_HT_VECTOR, M_BCM1480_INT_HT_VECTOR)
/*
* Vector prefix (Table 4-7)
*/
#define M_BCM1480_HTVECT_RAISE_INTLDT_HIGH 0x00
#define M_BCM1480_HTVECT_RAISE_MBOX_0 0x40
#define M_BCM1480_HTVECT_RAISE_INTLDT_LO 0x80
#define M_BCM1480_HTVECT_RAISE_MBOX_1 0xC0
#endif /* _BCM1480_INT_H */

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/* *********************************************************************
* BCM1280/BCM1480 Board Support Package
*
* L2 Cache constants and macros File: bcm1480_l2c.h
*
* This module contains constants useful for manipulating the
* level 2 cache.
*
* BCM1400 specification level: 1280-UM100-D2 (11/14/03)
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _BCM1480_L2C_H
#define _BCM1480_L2C_H
#include "sb1250_defs.h"
/*
* Format of level 2 cache management address (Table 55)
*/
#define S_BCM1480_L2C_MGMT_INDEX 5
#define M_BCM1480_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_MGMT_INDEX)
#define V_BCM1480_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_INDEX)
#define G_BCM1480_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_INDEX, M_BCM1480_L2C_MGMT_INDEX)
#define S_BCM1480_L2C_MGMT_WAY 17
#define M_BCM1480_L2C_MGMT_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_MGMT_WAY)
#define V_BCM1480_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_WAY)
#define G_BCM1480_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_WAY, M_BCM1480_L2C_MGMT_WAY)
#define M_BCM1480_L2C_MGMT_DIRTY _SB_MAKEMASK1(20)
#define M_BCM1480_L2C_MGMT_VALID _SB_MAKEMASK1(21)
#define S_BCM1480_L2C_MGMT_ECC_DIAG 22
#define M_BCM1480_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_BCM1480_L2C_MGMT_ECC_DIAG)
#define V_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG)
#define G_BCM1480_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG, M_BCM1480_L2C_MGMT_ECC_DIAG)
#define A_BCM1480_L2C_MGMT_TAG_BASE 0x00D0000000
#define BCM1480_L2C_ENTRIES_PER_WAY 4096
#define BCM1480_L2C_NUM_WAYS 8
/*
* Level 2 Cache Tag register (Table 59)
*/
#define S_BCM1480_L2C_TAG_MBZ 0
#define M_BCM1480_L2C_TAG_MBZ _SB_MAKEMASK(5, S_BCM1480_L2C_TAG_MBZ)
#define S_BCM1480_L2C_TAG_INDEX 5
#define M_BCM1480_L2C_TAG_INDEX _SB_MAKEMASK(12, S_BCM1480_L2C_TAG_INDEX)
#define V_BCM1480_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_INDEX)
#define G_BCM1480_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_INDEX, M_BCM1480_L2C_TAG_INDEX)
/* Note that index bit 16 is also tag bit 40 */
#define S_BCM1480_L2C_TAG_TAG 17
#define M_BCM1480_L2C_TAG_TAG _SB_MAKEMASK(23, S_BCM1480_L2C_TAG_TAG)
#define V_BCM1480_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_TAG)
#define G_BCM1480_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_TAG, M_BCM1480_L2C_TAG_TAG)
#define S_BCM1480_L2C_TAG_ECC 40
#define M_BCM1480_L2C_TAG_ECC _SB_MAKEMASK(6, S_BCM1480_L2C_TAG_ECC)
#define V_BCM1480_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_ECC)
#define G_BCM1480_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_ECC, M_BCM1480_L2C_TAG_ECC)
#define S_BCM1480_L2C_TAG_WAY 46
#define M_BCM1480_L2C_TAG_WAY _SB_MAKEMASK(3, S_BCM1480_L2C_TAG_WAY)
#define V_BCM1480_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_WAY)
#define G_BCM1480_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_BCM1480_L2C_TAG_WAY, M_BCM1480_L2C_TAG_WAY)
#define M_BCM1480_L2C_TAG_DIRTY _SB_MAKEMASK1(49)
#define M_BCM1480_L2C_TAG_VALID _SB_MAKEMASK1(50)
#define S_BCM1480_L2C_DATA_ECC 51
#define M_BCM1480_L2C_DATA_ECC _SB_MAKEMASK(10, S_BCM1480_L2C_DATA_ECC)
#define V_BCM1480_L2C_DATA_ECC(x) _SB_MAKEVALUE(x, S_BCM1480_L2C_DATA_ECC)
#define G_BCM1480_L2C_DATA_ECC(x) _SB_GETVALUE(x, S_BCM1480_L2C_DATA_ECC, M_BCM1480_L2C_DATA_ECC)
/*
* L2 Misc0 Value Register (Table 60)
*/
#define S_BCM1480_L2C_MISC0_WAY_REMOTE 0
#define M_BCM1480_L2C_MISC0_WAY_REMOTE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_REMOTE)
#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_REMOTE, M_BCM1480_L2C_MISC0_WAY_REMOTE)
#define S_BCM1480_L2C_MISC0_WAY_LOCAL 8
#define M_BCM1480_L2C_MISC0_WAY_LOCAL _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_LOCAL)
#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_LOCAL, M_BCM1480_L2C_MISC0_WAY_LOCAL)
#define S_BCM1480_L2C_MISC0_WAY_ENABLE 16
#define M_BCM1480_L2C_MISC0_WAY_ENABLE _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_ENABLE)
#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_ENABLE, M_BCM1480_L2C_MISC0_WAY_ENABLE)
#define S_BCM1480_L2C_MISC0_CACHE_DISABLE 24
#define M_BCM1480_L2C_MISC0_CACHE_DISABLE _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_DISABLE)
#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_DISABLE, M_BCM1480_L2C_MISC0_CACHE_DISABLE)
#define S_BCM1480_L2C_MISC0_CACHE_QUAD 26
#define M_BCM1480_L2C_MISC0_CACHE_QUAD _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_QUAD)
#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_QUAD, M_BCM1480_L2C_MISC0_CACHE_QUAD)
#define S_BCM1480_L2C_MISC0_MC_PRIORITY 30
#define M_BCM1480_L2C_MISC0_MC_PRIORITY _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY)
#define S_BCM1480_L2C_MISC0_ECC_CLEANUP 31
#define M_BCM1480_L2C_MISC0_ECC_CLEANUP _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_ECC_CLEANUP)
/*
* L2 Misc1 Value Register (Table 60)
*/
#define S_BCM1480_L2C_MISC1_WAY_AGENT_0 0
#define M_BCM1480_L2C_MISC1_WAY_AGENT_0 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_0)
#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_0, M_BCM1480_L2C_MISC1_WAY_AGENT_0)
#define S_BCM1480_L2C_MISC1_WAY_AGENT_1 8
#define M_BCM1480_L2C_MISC1_WAY_AGENT_1 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_1)
#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_1, M_BCM1480_L2C_MISC1_WAY_AGENT_1)
#define S_BCM1480_L2C_MISC1_WAY_AGENT_2 16
#define M_BCM1480_L2C_MISC1_WAY_AGENT_2 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_2)
#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_2, M_BCM1480_L2C_MISC1_WAY_AGENT_2)
#define S_BCM1480_L2C_MISC1_WAY_AGENT_3 24
#define M_BCM1480_L2C_MISC1_WAY_AGENT_3 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_3)
#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_3, M_BCM1480_L2C_MISC1_WAY_AGENT_3)
#define S_BCM1480_L2C_MISC1_WAY_AGENT_4 32
#define M_BCM1480_L2C_MISC1_WAY_AGENT_4 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_4)
#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_4, M_BCM1480_L2C_MISC1_WAY_AGENT_4)
/*
* L2 Misc2 Value Register (Table 60)
*/
#define S_BCM1480_L2C_MISC2_WAY_AGENT_8 0
#define M_BCM1480_L2C_MISC2_WAY_AGENT_8 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_8)
#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_8, M_BCM1480_L2C_MISC2_WAY_AGENT_8)
#define S_BCM1480_L2C_MISC2_WAY_AGENT_9 8
#define M_BCM1480_L2C_MISC2_WAY_AGENT_9 _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_9)
#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_9, M_BCM1480_L2C_MISC2_WAY_AGENT_9)
#define S_BCM1480_L2C_MISC2_WAY_AGENT_A 16
#define M_BCM1480_L2C_MISC2_WAY_AGENT_A _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_A)
#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_A, M_BCM1480_L2C_MISC2_WAY_AGENT_A)
#endif /* _BCM1480_L2C_H */

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kernel/arch/mips/include/asm/sibyte/bcm1480_mc.h Normal file
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/* *********************************************************************
* BCM1280/BCM1480 Board Support Package
*
* Memory Controller constants File: bcm1480_mc.h
*
* This module contains constants and macros useful for
* programming the memory controller.
*
* BCM1400 specification level: 1280-UM100-D1 (11/14/03 Review Copy)
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _BCM1480_MC_H
#define _BCM1480_MC_H
#include "sb1250_defs.h"
/*
* Memory Channel Configuration Register (Table 81)
*/
#define S_BCM1480_MC_INTLV0 0
#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0)
#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0)
#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0)
#define V_BCM1480_MC_INTLV0_DEFAULT V_BCM1480_MC_INTLV0(0)
#define S_BCM1480_MC_INTLV1 8
#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1)
#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1)
#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1)
#define V_BCM1480_MC_INTLV1_DEFAULT V_BCM1480_MC_INTLV1(0)
#define S_BCM1480_MC_INTLV2 16
#define M_BCM1480_MC_INTLV2 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV2)
#define V_BCM1480_MC_INTLV2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2)
#define G_BCM1480_MC_INTLV2(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV2, M_BCM1480_MC_INTLV2)
#define V_BCM1480_MC_INTLV2_DEFAULT V_BCM1480_MC_INTLV2(0)
#define S_BCM1480_MC_CS_MODE 32
#define M_BCM1480_MC_CS_MODE _SB_MAKEMASK(8, S_BCM1480_MC_CS_MODE)
#define V_BCM1480_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS_MODE)
#define G_BCM1480_MC_CS_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_CS_MODE, M_BCM1480_MC_CS_MODE)
#define V_BCM1480_MC_CS_MODE_DEFAULT V_BCM1480_MC_CS_MODE(0)
#define V_BCM1480_MC_CONFIG_DEFAULT (V_BCM1480_MC_INTLV0_DEFAULT | \
V_BCM1480_MC_INTLV1_DEFAULT | \
V_BCM1480_MC_INTLV2_DEFAULT | \
V_BCM1480_MC_CS_MODE_DEFAULT)
#define K_BCM1480_MC_CS01_MODE 0x03
#define K_BCM1480_MC_CS02_MODE 0x05
#define K_BCM1480_MC_CS0123_MODE 0x0F
#define K_BCM1480_MC_CS0246_MODE 0x55
#define K_BCM1480_MC_CS0145_MODE 0x33
#define K_BCM1480_MC_CS0167_MODE 0xC3
#define K_BCM1480_MC_CSFULL_MODE 0xFF
/*
* Chip Select Start Address Register (Table 82)
*/
#define S_BCM1480_MC_CS0_START 0
#define M_BCM1480_MC_CS0_START _SB_MAKEMASK(12, S_BCM1480_MC_CS0_START)
#define V_BCM1480_MC_CS0_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_START)
#define G_BCM1480_MC_CS0_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_START, M_BCM1480_MC_CS0_START)
#define S_BCM1480_MC_CS1_START 16
#define M_BCM1480_MC_CS1_START _SB_MAKEMASK(12, S_BCM1480_MC_CS1_START)
#define V_BCM1480_MC_CS1_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_START)
#define G_BCM1480_MC_CS1_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_START, M_BCM1480_MC_CS1_START)
#define S_BCM1480_MC_CS2_START 32
#define M_BCM1480_MC_CS2_START _SB_MAKEMASK(12, S_BCM1480_MC_CS2_START)
#define V_BCM1480_MC_CS2_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_START)
#define G_BCM1480_MC_CS2_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_START, M_BCM1480_MC_CS2_START)
#define S_BCM1480_MC_CS3_START 48
#define M_BCM1480_MC_CS3_START _SB_MAKEMASK(12, S_BCM1480_MC_CS3_START)
#define V_BCM1480_MC_CS3_START(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_START)
#define G_BCM1480_MC_CS3_START(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_START, M_BCM1480_MC_CS3_START)
/*
* Chip Select End Address Register (Table 83)
*/
#define S_BCM1480_MC_CS0_END 0
#define M_BCM1480_MC_CS0_END _SB_MAKEMASK(12, S_BCM1480_MC_CS0_END)
#define V_BCM1480_MC_CS0_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_END)
#define G_BCM1480_MC_CS0_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0_END, M_BCM1480_MC_CS0_END)
#define S_BCM1480_MC_CS1_END 16
#define M_BCM1480_MC_CS1_END _SB_MAKEMASK(12, S_BCM1480_MC_CS1_END)
#define V_BCM1480_MC_CS1_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_END)
#define G_BCM1480_MC_CS1_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS1_END, M_BCM1480_MC_CS1_END)
#define S_BCM1480_MC_CS2_END 32
#define M_BCM1480_MC_CS2_END _SB_MAKEMASK(12, S_BCM1480_MC_CS2_END)
#define V_BCM1480_MC_CS2_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_END)
#define G_BCM1480_MC_CS2_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS2_END, M_BCM1480_MC_CS2_END)
#define S_BCM1480_MC_CS3_END 48
#define M_BCM1480_MC_CS3_END _SB_MAKEMASK(12, S_BCM1480_MC_CS3_END)
#define V_BCM1480_MC_CS3_END(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_END)
#define G_BCM1480_MC_CS3_END(x) _SB_GETVALUE(x, S_BCM1480_MC_CS3_END, M_BCM1480_MC_CS3_END)
/*
* Row Address Bit Select Register 0 (Table 84)
*/
#define S_BCM1480_MC_ROW00 0
#define M_BCM1480_MC_ROW00 _SB_MAKEMASK(6, S_BCM1480_MC_ROW00)
#define V_BCM1480_MC_ROW00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW00)
#define G_BCM1480_MC_ROW00(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW00, M_BCM1480_MC_ROW00)
#define S_BCM1480_MC_ROW01 8
#define M_BCM1480_MC_ROW01 _SB_MAKEMASK(6, S_BCM1480_MC_ROW01)
#define V_BCM1480_MC_ROW01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW01)
#define G_BCM1480_MC_ROW01(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW01, M_BCM1480_MC_ROW01)
#define S_BCM1480_MC_ROW02 16
#define M_BCM1480_MC_ROW02 _SB_MAKEMASK(6, S_BCM1480_MC_ROW02)
#define V_BCM1480_MC_ROW02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW02)
#define G_BCM1480_MC_ROW02(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW02, M_BCM1480_MC_ROW02)
#define S_BCM1480_MC_ROW03 24
#define M_BCM1480_MC_ROW03 _SB_MAKEMASK(6, S_BCM1480_MC_ROW03)
#define V_BCM1480_MC_ROW03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW03)
#define G_BCM1480_MC_ROW03(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW03, M_BCM1480_MC_ROW03)
#define S_BCM1480_MC_ROW04 32
#define M_BCM1480_MC_ROW04 _SB_MAKEMASK(6, S_BCM1480_MC_ROW04)
#define V_BCM1480_MC_ROW04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW04)
#define G_BCM1480_MC_ROW04(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW04, M_BCM1480_MC_ROW04)
#define S_BCM1480_MC_ROW05 40
#define M_BCM1480_MC_ROW05 _SB_MAKEMASK(6, S_BCM1480_MC_ROW05)
#define V_BCM1480_MC_ROW05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW05)
#define G_BCM1480_MC_ROW05(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW05, M_BCM1480_MC_ROW05)
#define S_BCM1480_MC_ROW06 48
#define M_BCM1480_MC_ROW06 _SB_MAKEMASK(6, S_BCM1480_MC_ROW06)
#define V_BCM1480_MC_ROW06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW06)
#define G_BCM1480_MC_ROW06(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW06, M_BCM1480_MC_ROW06)
#define S_BCM1480_MC_ROW07 56
#define M_BCM1480_MC_ROW07 _SB_MAKEMASK(6, S_BCM1480_MC_ROW07)
#define V_BCM1480_MC_ROW07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW07)
#define G_BCM1480_MC_ROW07(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW07, M_BCM1480_MC_ROW07)
/*
* Row Address Bit Select Register 1 (Table 85)
*/
#define S_BCM1480_MC_ROW08 0
#define M_BCM1480_MC_ROW08 _SB_MAKEMASK(6, S_BCM1480_MC_ROW08)
#define V_BCM1480_MC_ROW08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW08)
#define G_BCM1480_MC_ROW08(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW08, M_BCM1480_MC_ROW08)
#define S_BCM1480_MC_ROW09 8
#define M_BCM1480_MC_ROW09 _SB_MAKEMASK(6, S_BCM1480_MC_ROW09)
#define V_BCM1480_MC_ROW09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW09)
#define G_BCM1480_MC_ROW09(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW09, M_BCM1480_MC_ROW09)
#define S_BCM1480_MC_ROW10 16
#define M_BCM1480_MC_ROW10 _SB_MAKEMASK(6, S_BCM1480_MC_ROW10)
#define V_BCM1480_MC_ROW10(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW10)
#define G_BCM1480_MC_ROW10(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW10, M_BCM1480_MC_ROW10)
#define S_BCM1480_MC_ROW11 24
#define M_BCM1480_MC_ROW11 _SB_MAKEMASK(6, S_BCM1480_MC_ROW11)
#define V_BCM1480_MC_ROW11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW11)
#define G_BCM1480_MC_ROW11(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW11, M_BCM1480_MC_ROW11)
#define S_BCM1480_MC_ROW12 32
#define M_BCM1480_MC_ROW12 _SB_MAKEMASK(6, S_BCM1480_MC_ROW12)
#define V_BCM1480_MC_ROW12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW12)
#define G_BCM1480_MC_ROW12(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW12, M_BCM1480_MC_ROW12)
#define S_BCM1480_MC_ROW13 40
#define M_BCM1480_MC_ROW13 _SB_MAKEMASK(6, S_BCM1480_MC_ROW13)
#define V_BCM1480_MC_ROW13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW13)
#define G_BCM1480_MC_ROW13(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW13, M_BCM1480_MC_ROW13)
#define S_BCM1480_MC_ROW14 48
#define M_BCM1480_MC_ROW14 _SB_MAKEMASK(6, S_BCM1480_MC_ROW14)
#define V_BCM1480_MC_ROW14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ROW14)
#define G_BCM1480_MC_ROW14(x) _SB_GETVALUE(x, S_BCM1480_MC_ROW14, M_BCM1480_MC_ROW14)
#define K_BCM1480_MC_ROWX_BIT_SPACING 8
/*
* Column Address Bit Select Register 0 (Table 86)
*/
#define S_BCM1480_MC_COL00 0
#define M_BCM1480_MC_COL00 _SB_MAKEMASK(6, S_BCM1480_MC_COL00)
#define V_BCM1480_MC_COL00(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL00)
#define G_BCM1480_MC_COL00(x) _SB_GETVALUE(x, S_BCM1480_MC_COL00, M_BCM1480_MC_COL00)
#define S_BCM1480_MC_COL01 8
#define M_BCM1480_MC_COL01 _SB_MAKEMASK(6, S_BCM1480_MC_COL01)
#define V_BCM1480_MC_COL01(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL01)
#define G_BCM1480_MC_COL01(x) _SB_GETVALUE(x, S_BCM1480_MC_COL01, M_BCM1480_MC_COL01)
#define S_BCM1480_MC_COL02 16
#define M_BCM1480_MC_COL02 _SB_MAKEMASK(6, S_BCM1480_MC_COL02)
#define V_BCM1480_MC_COL02(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL02)
#define G_BCM1480_MC_COL02(x) _SB_GETVALUE(x, S_BCM1480_MC_COL02, M_BCM1480_MC_COL02)
#define S_BCM1480_MC_COL03 24
#define M_BCM1480_MC_COL03 _SB_MAKEMASK(6, S_BCM1480_MC_COL03)
#define V_BCM1480_MC_COL03(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL03)
#define G_BCM1480_MC_COL03(x) _SB_GETVALUE(x, S_BCM1480_MC_COL03, M_BCM1480_MC_COL03)
#define S_BCM1480_MC_COL04 32
#define M_BCM1480_MC_COL04 _SB_MAKEMASK(6, S_BCM1480_MC_COL04)
#define V_BCM1480_MC_COL04(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL04)
#define G_BCM1480_MC_COL04(x) _SB_GETVALUE(x, S_BCM1480_MC_COL04, M_BCM1480_MC_COL04)
#define S_BCM1480_MC_COL05 40
#define M_BCM1480_MC_COL05 _SB_MAKEMASK(6, S_BCM1480_MC_COL05)
#define V_BCM1480_MC_COL05(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL05)
#define G_BCM1480_MC_COL05(x) _SB_GETVALUE(x, S_BCM1480_MC_COL05, M_BCM1480_MC_COL05)
#define S_BCM1480_MC_COL06 48
#define M_BCM1480_MC_COL06 _SB_MAKEMASK(6, S_BCM1480_MC_COL06)
#define V_BCM1480_MC_COL06(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL06)
#define G_BCM1480_MC_COL06(x) _SB_GETVALUE(x, S_BCM1480_MC_COL06, M_BCM1480_MC_COL06)
#define S_BCM1480_MC_COL07 56
#define M_BCM1480_MC_COL07 _SB_MAKEMASK(6, S_BCM1480_MC_COL07)
#define V_BCM1480_MC_COL07(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL07)
#define G_BCM1480_MC_COL07(x) _SB_GETVALUE(x, S_BCM1480_MC_COL07, M_BCM1480_MC_COL07)
/*
* Column Address Bit Select Register 1 (Table 87)
*/
#define S_BCM1480_MC_COL08 0
#define M_BCM1480_MC_COL08 _SB_MAKEMASK(6, S_BCM1480_MC_COL08)
#define V_BCM1480_MC_COL08(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL08)
#define G_BCM1480_MC_COL08(x) _SB_GETVALUE(x, S_BCM1480_MC_COL08, M_BCM1480_MC_COL08)
#define S_BCM1480_MC_COL09 8
#define M_BCM1480_MC_COL09 _SB_MAKEMASK(6, S_BCM1480_MC_COL09)
#define V_BCM1480_MC_COL09(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL09)
#define G_BCM1480_MC_COL09(x) _SB_GETVALUE(x, S_BCM1480_MC_COL09, M_BCM1480_MC_COL09)
#define S_BCM1480_MC_COL10 16 /* not a valid position, must be prog as 0 */
#define S_BCM1480_MC_COL11 24
#define M_BCM1480_MC_COL11 _SB_MAKEMASK(6, S_BCM1480_MC_COL11)
#define V_BCM1480_MC_COL11(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL11)
#define G_BCM1480_MC_COL11(x) _SB_GETVALUE(x, S_BCM1480_MC_COL11, M_BCM1480_MC_COL11)
#define S_BCM1480_MC_COL12 32
#define M_BCM1480_MC_COL12 _SB_MAKEMASK(6, S_BCM1480_MC_COL12)
#define V_BCM1480_MC_COL12(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL12)
#define G_BCM1480_MC_COL12(x) _SB_GETVALUE(x, S_BCM1480_MC_COL12, M_BCM1480_MC_COL12)
#define S_BCM1480_MC_COL13 40
#define M_BCM1480_MC_COL13 _SB_MAKEMASK(6, S_BCM1480_MC_COL13)
#define V_BCM1480_MC_COL13(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL13)
#define G_BCM1480_MC_COL13(x) _SB_GETVALUE(x, S_BCM1480_MC_COL13, M_BCM1480_MC_COL13)
#define S_BCM1480_MC_COL14 48
#define M_BCM1480_MC_COL14 _SB_MAKEMASK(6, S_BCM1480_MC_COL14)
#define V_BCM1480_MC_COL14(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COL14)
#define G_BCM1480_MC_COL14(x) _SB_GETVALUE(x, S_BCM1480_MC_COL14, M_BCM1480_MC_COL14)
#define K_BCM1480_MC_COLX_BIT_SPACING 8
/*
* CS0 and CS1 Bank Address Bit Select Register (Table 88)
*/
#define S_BCM1480_MC_CS01_BANK0 0
#define M_BCM1480_MC_CS01_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK0)
#define V_BCM1480_MC_CS01_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK0)
#define G_BCM1480_MC_CS01_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK0, M_BCM1480_MC_CS01_BANK0)
#define S_BCM1480_MC_CS01_BANK1 8
#define M_BCM1480_MC_CS01_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK1)
#define V_BCM1480_MC_CS01_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK1)
#define G_BCM1480_MC_CS01_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK1, M_BCM1480_MC_CS01_BANK1)
#define S_BCM1480_MC_CS01_BANK2 16
#define M_BCM1480_MC_CS01_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK2)
#define V_BCM1480_MC_CS01_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK2)
#define G_BCM1480_MC_CS01_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK2, M_BCM1480_MC_CS01_BANK2)
/*
* CS2 and CS3 Bank Address Bit Select Register (Table 89)
*/
#define S_BCM1480_MC_CS23_BANK0 0
#define M_BCM1480_MC_CS23_BANK0 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK0)
#define V_BCM1480_MC_CS23_BANK0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK0)
#define G_BCM1480_MC_CS23_BANK0(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK0, M_BCM1480_MC_CS23_BANK0)
#define S_BCM1480_MC_CS23_BANK1 8
#define M_BCM1480_MC_CS23_BANK1 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK1)
#define V_BCM1480_MC_CS23_BANK1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK1)
#define G_BCM1480_MC_CS23_BANK1(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK1, M_BCM1480_MC_CS23_BANK1)
#define S_BCM1480_MC_CS23_BANK2 16
#define M_BCM1480_MC_CS23_BANK2 _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK2)
#define V_BCM1480_MC_CS23_BANK2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK2)
#define G_BCM1480_MC_CS23_BANK2(x) _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK2, M_BCM1480_MC_CS23_BANK2)
#define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING 8
/*
* DRAM Command Register (Table 90)
*/
#define S_BCM1480_MC_COMMAND 0
#define M_BCM1480_MC_COMMAND _SB_MAKEMASK(4, S_BCM1480_MC_COMMAND)
#define V_BCM1480_MC_COMMAND(x) _SB_MAKEVALUE(x, S_BCM1480_MC_COMMAND)
#define G_BCM1480_MC_COMMAND(x) _SB_GETVALUE(x, S_BCM1480_MC_COMMAND, M_BCM1480_MC_COMMAND)
#define K_BCM1480_MC_COMMAND_EMRS 0
#define K_BCM1480_MC_COMMAND_MRS 1
#define K_BCM1480_MC_COMMAND_PRE 2
#define K_BCM1480_MC_COMMAND_AR 3
#define K_BCM1480_MC_COMMAND_SETRFSH 4
#define K_BCM1480_MC_COMMAND_CLRRFSH 5
#define K_BCM1480_MC_COMMAND_SETPWRDN 6
#define K_BCM1480_MC_COMMAND_CLRPWRDN 7
#if SIBYTE_HDR_FEATURE(1480, PASS2)
#define K_BCM1480_MC_COMMAND_EMRS2 8
#define K_BCM1480_MC_COMMAND_EMRS3 9
#define K_BCM1480_MC_COMMAND_ENABLE_MCLK 10
#define K_BCM1480_MC_COMMAND_DISABLE_MCLK 11
#endif
#define V_BCM1480_MC_COMMAND_EMRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS)
#define V_BCM1480_MC_COMMAND_MRS V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS)
#define V_BCM1480_MC_COMMAND_PRE V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE)
#define V_BCM1480_MC_COMMAND_AR V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR)
#define V_BCM1480_MC_COMMAND_SETRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH)
#define V_BCM1480_MC_COMMAND_CLRRFSH V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH)
#define V_BCM1480_MC_COMMAND_SETPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN)
#define V_BCM1480_MC_COMMAND_CLRPWRDN V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN)
#if SIBYTE_HDR_FEATURE(1480, PASS2)
#define V_BCM1480_MC_COMMAND_EMRS2 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2)
#define V_BCM1480_MC_COMMAND_EMRS3 V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3)
#define V_BCM1480_MC_COMMAND_ENABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_ENABLE_MCLK)
#define V_BCM1480_MC_COMMAND_DISABLE_MCLK V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_DISABLE_MCLK)
#endif
#define S_BCM1480_MC_CS0 4
#define M_BCM1480_MC_CS0 _SB_MAKEMASK1(4)
#define M_BCM1480_MC_CS1 _SB_MAKEMASK1(5)
#define M_BCM1480_MC_CS2 _SB_MAKEMASK1(6)
#define M_BCM1480_MC_CS3 _SB_MAKEMASK1(7)
#define M_BCM1480_MC_CS4 _SB_MAKEMASK1(8)
#define M_BCM1480_MC_CS5 _SB_MAKEMASK1(9)
#define M_BCM1480_MC_CS6 _SB_MAKEMASK1(10)
#define M_BCM1480_MC_CS7 _SB_MAKEMASK1(11)
#define M_BCM1480_MC_CS _SB_MAKEMASK(8, S_BCM1480_MC_CS0)
#define V_BCM1480_MC_CS(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CS0)
#define G_BCM1480_MC_CS(x) _SB_GETVALUE(x, S_BCM1480_MC_CS0, M_BCM1480_MC_CS0)
#define M_BCM1480_MC_CMD_ACTIVE _SB_MAKEMASK1(16)
/*
* DRAM Mode Register (Table 91)
*/
#define S_BCM1480_MC_EMODE 0
#define M_BCM1480_MC_EMODE _SB_MAKEMASK(15, S_BCM1480_MC_EMODE)
#define V_BCM1480_MC_EMODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_EMODE)
#define G_BCM1480_MC_EMODE(x) _SB_GETVALUE(x, S_BCM1480_MC_EMODE, M_BCM1480_MC_EMODE)
#define V_BCM1480_MC_EMODE_DEFAULT V_BCM1480_MC_EMODE(0)
#define S_BCM1480_MC_MODE 16
#define M_BCM1480_MC_MODE _SB_MAKEMASK(15, S_BCM1480_MC_MODE)
#define V_BCM1480_MC_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MODE)
#define G_BCM1480_MC_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_MODE, M_BCM1480_MC_MODE)
#define V_BCM1480_MC_MODE_DEFAULT V_BCM1480_MC_MODE(0)
#define S_BCM1480_MC_DRAM_TYPE 32
#define M_BCM1480_MC_DRAM_TYPE _SB_MAKEMASK(4, S_BCM1480_MC_DRAM_TYPE)
#define V_BCM1480_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DRAM_TYPE)
#define G_BCM1480_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_BCM1480_MC_DRAM_TYPE, M_BCM1480_MC_DRAM_TYPE)
#define K_BCM1480_MC_DRAM_TYPE_JEDEC 0
#define K_BCM1480_MC_DRAM_TYPE_FCRAM 1
#if SIBYTE_HDR_FEATURE(1480, PASS2)
#define K_BCM1480_MC_DRAM_TYPE_DDR2 2
#endif
#define K_BCM1480_MC_DRAM_TYPE_DDR2_PASS1 0
#define V_BCM1480_MC_DRAM_TYPE_JEDEC V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC)
#define V_BCM1480_MC_DRAM_TYPE_FCRAM V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM)
#if SIBYTE_HDR_FEATURE(1480, PASS2)
#define V_BCM1480_MC_DRAM_TYPE_DDR2 V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_DDR2)
#endif
#define M_BCM1480_MC_GANGED _SB_MAKEMASK1(36)
#define M_BCM1480_MC_BY9_INTF _SB_MAKEMASK1(37)
#define M_BCM1480_MC_FORCE_ECC64 _SB_MAKEMASK1(38)
#define M_BCM1480_MC_ECC_DISABLE _SB_MAKEMASK1(39)
#define S_BCM1480_MC_PG_POLICY 40
#define M_BCM1480_MC_PG_POLICY _SB_MAKEMASK(2, S_BCM1480_MC_PG_POLICY)
#define V_BCM1480_MC_PG_POLICY(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PG_POLICY)
#define G_BCM1480_MC_PG_POLICY(x) _SB_GETVALUE(x, S_BCM1480_MC_PG_POLICY, M_BCM1480_MC_PG_POLICY)
#define K_BCM1480_MC_PG_POLICY_CLOSED 0
#define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1
#define V_BCM1480_MC_PG_POLICY_CLOSED V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED)
#define V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK)
#if SIBYTE_HDR_FEATURE(1480, PASS2)
#define M_BCM1480_MC_2T_CMD _SB_MAKEMASK1(42)
#define M_BCM1480_MC_ECC_COR_DIS _SB_MAKEMASK1(43)
#endif
#define V_BCM1480_MC_DRAMMODE_DEFAULT V_BCM1480_MC_EMODE_DEFAULT | V_BCM1480_MC_MODE_DEFAULT | V_BCM1480_MC_DRAM_TYPE_JEDEC | \
V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK)
/*
* Memory Clock Configuration Register (Table 92)
*/
#define S_BCM1480_MC_CLK_RATIO 0
#define M_BCM1480_MC_CLK_RATIO _SB_MAKEMASK(6, S_BCM1480_MC_CLK_RATIO)
#define V_BCM1480_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CLK_RATIO)
#define G_BCM1480_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_BCM1480_MC_CLK_RATIO, M_BCM1480_MC_CLK_RATIO)
#define V_BCM1480_MC_CLK_RATIO_DEFAULT V_BCM1480_MC_CLK_RATIO(10)
#define S_BCM1480_MC_REF_RATE 8
#define M_BCM1480_MC_REF_RATE _SB_MAKEMASK(8, S_BCM1480_MC_REF_RATE)
#define V_BCM1480_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_REF_RATE)
#define G_BCM1480_MC_REF_RATE(x) _SB_GETVALUE(x, S_BCM1480_MC_REF_RATE, M_BCM1480_MC_REF_RATE)
#define K_BCM1480_MC_REF_RATE_100MHz 0x31
#define K_BCM1480_MC_REF_RATE_200MHz 0x62
#define K_BCM1480_MC_REF_RATE_400MHz 0xC4
#define V_BCM1480_MC_REF_RATE_100MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_100MHz)
#define V_BCM1480_MC_REF_RATE_200MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_200MHz)
#define V_BCM1480_MC_REF_RATE_400MHz V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_400MHz)
#define V_BCM1480_MC_REF_RATE_DEFAULT V_BCM1480_MC_REF_RATE_400MHz
#if SIBYTE_HDR_FEATURE(1480, PASS2)
#define M_BCM1480_MC_AUTO_REF_DIS _SB_MAKEMASK1(16)
#endif
/*
* ODT Register (Table 99)
*/
#if SIBYTE_HDR_FEATURE(1480, PASS2)
#define M_BCM1480_MC_RD_ODT0_CS0 _SB_MAKEMASK1(0)
#define M_BCM1480_MC_RD_ODT0_CS2 _SB_MAKEMASK1(1)
#define M_BCM1480_MC_RD_ODT0_CS4 _SB_MAKEMASK1(2)
#define M_BCM1480_MC_RD_ODT0_CS6 _SB_MAKEMASK1(3)
#define M_BCM1480_MC_WR_ODT0_CS0 _SB_MAKEMASK1(4)
#define M_BCM1480_MC_WR_ODT0_CS2 _SB_MAKEMASK1(5)
#define M_BCM1480_MC_WR_ODT0_CS4 _SB_MAKEMASK1(6)
#define M_BCM1480_MC_WR_ODT0_CS6 _SB_MAKEMASK1(7)
#define M_BCM1480_MC_RD_ODT2_CS0 _SB_MAKEMASK1(8)
#define M_BCM1480_MC_RD_ODT2_CS2 _SB_MAKEMASK1(9)
#define M_BCM1480_MC_RD_ODT2_CS4 _SB_MAKEMASK1(10)
#define M_BCM1480_MC_RD_ODT2_CS6 _SB_MAKEMASK1(11)
#define M_BCM1480_MC_WR_ODT2_CS0 _SB_MAKEMASK1(12)
#define M_BCM1480_MC_WR_ODT2_CS2 _SB_MAKEMASK1(13)
#define M_BCM1480_MC_WR_ODT2_CS4 _SB_MAKEMASK1(14)
#define M_BCM1480_MC_WR_ODT2_CS6 _SB_MAKEMASK1(15)
#define M_BCM1480_MC_RD_ODT4_CS0 _SB_MAKEMASK1(16)
#define M_BCM1480_MC_RD_ODT4_CS2 _SB_MAKEMASK1(17)
#define M_BCM1480_MC_RD_ODT4_CS4 _SB_MAKEMASK1(18)
#define M_BCM1480_MC_RD_ODT4_CS6 _SB_MAKEMASK1(19)
#define M_BCM1480_MC_WR_ODT4_CS0 _SB_MAKEMASK1(20)
#define M_BCM1480_MC_WR_ODT4_CS2 _SB_MAKEMASK1(21)
#define M_BCM1480_MC_WR_ODT4_CS4 _SB_MAKEMASK1(22)
#define M_BCM1480_MC_WR_ODT4_CS6 _SB_MAKEMASK1(23)
#define M_BCM1480_MC_RD_ODT6_CS0 _SB_MAKEMASK1(24)
#define M_BCM1480_MC_RD_ODT6_CS2 _SB_MAKEMASK1(25)
#define M_BCM1480_MC_RD_ODT6_CS4 _SB_MAKEMASK1(26)
#define M_BCM1480_MC_RD_ODT6_CS6 _SB_MAKEMASK1(27)
#define M_BCM1480_MC_WR_ODT6_CS0 _SB_MAKEMASK1(28)
#define M_BCM1480_MC_WR_ODT6_CS2 _SB_MAKEMASK1(29)
#define M_BCM1480_MC_WR_ODT6_CS4 _SB_MAKEMASK1(30)
#define M_BCM1480_MC_WR_ODT6_CS6 _SB_MAKEMASK1(31)
#define M_BCM1480_MC_CS_ODD_ODT_EN _SB_MAKEMASK1(32)
#define S_BCM1480_MC_ODT0 0
#define M_BCM1480_MC_ODT0 _SB_MAKEMASK(8, S_BCM1480_MC_ODT0)
#define V_BCM1480_MC_ODT0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT0)
#define S_BCM1480_MC_ODT2 8
#define M_BCM1480_MC_ODT2 _SB_MAKEMASK(8, S_BCM1480_MC_ODT2)
#define V_BCM1480_MC_ODT2(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT2)
#define S_BCM1480_MC_ODT4 16
#define M_BCM1480_MC_ODT4 _SB_MAKEMASK(8, S_BCM1480_MC_ODT4)
#define V_BCM1480_MC_ODT4(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT4)
#define S_BCM1480_MC_ODT6 24
#define M_BCM1480_MC_ODT6 _SB_MAKEMASK(8, S_BCM1480_MC_ODT6)
#define V_BCM1480_MC_ODT6(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ODT6)
#endif
/*
* Memory DLL Configuration Register (Table 93)
*/
#define S_BCM1480_MC_ADDR_COARSE_ADJ 0
#define M_BCM1480_MC_ADDR_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_ADDR_COARSE_ADJ)
#define V_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ)
#define G_BCM1480_MC_ADDR_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ, M_BCM1480_MC_ADDR_COARSE_ADJ)
#define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0)
#if SIBYTE_HDR_FEATURE(1480, PASS2)
#define S_BCM1480_MC_ADDR_FREQ_RANGE 8
#define M_BCM1480_MC_ADDR_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FREQ_RANGE)
#define V_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE)
#define G_BCM1480_MC_ADDR_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE, M_BCM1480_MC_ADDR_FREQ_RANGE)
#define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT V_BCM1480_MC_ADDR_FREQ_RANGE(0x4)
#endif
#define S_BCM1480_MC_ADDR_FINE_ADJ 8
#define M_BCM1480_MC_ADDR_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FINE_ADJ)
#define V_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ)
#define G_BCM1480_MC_ADDR_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ, M_BCM1480_MC_ADDR_FINE_ADJ)
#define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT V_BCM1480_MC_ADDR_FINE_ADJ(0x8)
#define S_BCM1480_MC_DQI_COARSE_ADJ 16
#define M_BCM1480_MC_DQI_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQI_COARSE_ADJ)
#define V_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ)
#define G_BCM1480_MC_DQI_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ, M_BCM1480_MC_DQI_COARSE_ADJ)
#define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0)
#if SIBYTE_HDR_FEATURE(1480, PASS2)
#define S_BCM1480_MC_DQI_FREQ_RANGE 24
#define M_BCM1480_MC_DQI_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FREQ_RANGE)
#define V_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE)
#define G_BCM1480_MC_DQI_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE, M_BCM1480_MC_DQI_FREQ_RANGE)
#define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQI_FREQ_RANGE(0x4)
#endif
#define S_BCM1480_MC_DQI_FINE_ADJ 24
#define M_BCM1480_MC_DQI_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FINE_ADJ)
#define V_BCM1480_MC_DQI_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ)
#define G_BCM1480_MC_DQI_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ, M_BCM1480_MC_DQI_FINE_ADJ)
#define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT V_BCM1480_MC_DQI_FINE_ADJ(0x8)
#define S_BCM1480_MC_DQO_COARSE_ADJ 32
#define M_BCM1480_MC_DQO_COARSE_ADJ _SB_MAKEMASK(6, S_BCM1480_MC_DQO_COARSE_ADJ)
#define V_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ)
#define G_BCM1480_MC_DQO_COARSE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ, M_BCM1480_MC_DQO_COARSE_ADJ)
#define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0)
#if SIBYTE_HDR_FEATURE(1480, PASS2)
#define S_BCM1480_MC_DQO_FREQ_RANGE 40
#define M_BCM1480_MC_DQO_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FREQ_RANGE)
#define V_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE)
#define G_BCM1480_MC_DQO_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE, M_BCM1480_MC_DQO_FREQ_RANGE)
#define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT V_BCM1480_MC_DQO_FREQ_RANGE(0x4)
#endif
#define S_BCM1480_MC_DQO_FINE_ADJ 40
#define M_BCM1480_MC_DQO_FINE_ADJ _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FINE_ADJ)
#define V_BCM1480_MC_DQO_FINE_ADJ(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ)
#define G_BCM1480_MC_DQO_FINE_ADJ(x) _SB_GETVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ, M_BCM1480_MC_DQO_FINE_ADJ)
#define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT V_BCM1480_MC_DQO_FINE_ADJ(0x8)
#if SIBYTE_HDR_FEATURE(1480, PASS2)
#define S_BCM1480_MC_DLL_PDSEL 44
#define M_BCM1480_MC_DLL_PDSEL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_PDSEL)
#define V_BCM1480_MC_DLL_PDSEL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_PDSEL)
#define G_BCM1480_MC_DLL_PDSEL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_PDSEL, M_BCM1480_MC_DLL_PDSEL)
#define V_BCM1480_MC_DLL_DEFAULT_PDSEL V_BCM1480_MC_DLL_PDSEL(0x0)
#define M_BCM1480_MC_DLL_REGBYPASS _SB_MAKEMASK1(46)
#define M_BCM1480_MC_DQO_SHIFT _SB_MAKEMASK1(47)
#endif
#define S_BCM1480_MC_DLL_DEFAULT 48
#define M_BCM1480_MC_DLL_DEFAULT _SB_MAKEMASK(6, S_BCM1480_MC_DLL_DEFAULT)
#define V_BCM1480_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_DEFAULT)
#define G_BCM1480_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_DEFAULT, M_BCM1480_MC_DLL_DEFAULT)
#define V_BCM1480_MC_DLL_DEFAULT_DEFAULT V_BCM1480_MC_DLL_DEFAULT(0x10)
#if SIBYTE_HDR_FEATURE(1480, PASS2)
#define S_BCM1480_MC_DLL_REGCTRL 54
#define M_BCM1480_MC_DLL_REGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_REGCTRL)
#define V_BCM1480_MC_DLL_REGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_REGCTRL)
#define G_BCM1480_MC_DLL_REGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_REGCTRL, M_BCM1480_MC_DLL_REGCTRL)
#define V_BCM1480_MC_DLL_DEFAULT_REGCTRL V_BCM1480_MC_DLL_REGCTRL(0x0)
#endif
#if SIBYTE_HDR_FEATURE(1480, PASS2)
#define S_BCM1480_MC_DLL_FREQ_RANGE 56
#define M_BCM1480_MC_DLL_FREQ_RANGE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_FREQ_RANGE)
#define V_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE)
#define G_BCM1480_MC_DLL_FREQ_RANGE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE, M_BCM1480_MC_DLL_FREQ_RANGE)
#define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT V_BCM1480_MC_DLL_FREQ_RANGE(0x4)
#endif
#define S_BCM1480_MC_DLL_STEP_SIZE 56
#define M_BCM1480_MC_DLL_STEP_SIZE _SB_MAKEMASK(4, S_BCM1480_MC_DLL_STEP_SIZE)
#define V_BCM1480_MC_DLL_STEP_SIZE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE)
#define G_BCM1480_MC_DLL_STEP_SIZE(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE, M_BCM1480_MC_DLL_STEP_SIZE)
#define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT V_BCM1480_MC_DLL_STEP_SIZE(0x8)
#if SIBYTE_HDR_FEATURE(1480, PASS2)
#define S_BCM1480_MC_DLL_BGCTRL 60
#define M_BCM1480_MC_DLL_BGCTRL _SB_MAKEMASK(2, S_BCM1480_MC_DLL_BGCTRL)
#define V_BCM1480_MC_DLL_BGCTRL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_BGCTRL)
#define G_BCM1480_MC_DLL_BGCTRL(x) _SB_GETVALUE(x, S_BCM1480_MC_DLL_BGCTRL, M_BCM1480_MC_DLL_BGCTRL)
#define V_BCM1480_MC_DLL_DEFAULT_BGCTRL V_BCM1480_MC_DLL_BGCTRL(0x0)
#endif
#define M_BCM1480_MC_DLL_BYPASS _SB_MAKEMASK1(63)
/*
* Memory Drive Configuration Register (Table 94)
*/
#define S_BCM1480_MC_RTT_BYP_PULLDOWN 0
#define M_BCM1480_MC_RTT_BYP_PULLDOWN _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLDOWN)
#define V_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN)
#define G_BCM1480_MC_RTT_BYP_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN, M_BCM1480_MC_RTT_BYP_PULLDOWN)
#define S_BCM1480_MC_RTT_BYP_PULLUP 6
#define M_BCM1480_MC_RTT_BYP_PULLUP _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLUP)
#define V_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP)
#define G_BCM1480_MC_RTT_BYP_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP, M_BCM1480_MC_RTT_BYP_PULLUP)
#define M_BCM1480_MC_RTT_BYPASS _SB_MAKEMASK1(8)
#define M_BCM1480_MC_RTT_COMP_MOV_AVG _SB_MAKEMASK1(9)
#define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN 10
#define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
#define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
#define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN, M_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
#define S_BCM1480_MC_PVT_BYP_C1_PULLUP 15
#define M_BCM1480_MC_PVT_BYP_C1_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLUP)
#define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP)
#define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP, M_BCM1480_MC_PVT_BYP_C1_PULLUP)
#define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN 20
#define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
#define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
#define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN, M_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
#define S_BCM1480_MC_PVT_BYP_C2_PULLUP 25
#define M_BCM1480_MC_PVT_BYP_C2_PULLUP _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLUP)
#define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP)
#define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP, M_BCM1480_MC_PVT_BYP_C2_PULLUP)
#define M_BCM1480_MC_PVT_BYPASS _SB_MAKEMASK1(30)
#define M_BCM1480_MC_PVT_COMP_MOV_AVG _SB_MAKEMASK1(31)
#define M_BCM1480_MC_CLK_CLASS _SB_MAKEMASK1(34)
#define M_BCM1480_MC_DATA_CLASS _SB_MAKEMASK1(35)
#define M_BCM1480_MC_ADDR_CLASS _SB_MAKEMASK1(36)
#define M_BCM1480_MC_DQ_ODT_75 _SB_MAKEMASK1(37)
#define M_BCM1480_MC_DQ_ODT_150 _SB_MAKEMASK1(38)
#define M_BCM1480_MC_DQS_ODT_75 _SB_MAKEMASK1(39)
#define M_BCM1480_MC_DQS_ODT_150 _SB_MAKEMASK1(40)
#define M_BCM1480_MC_DQS_DIFF _SB_MAKEMASK1(41)
/*
* ECC Test Data Register (Table 95)
*/
#define S_BCM1480_MC_DATA_INVERT 0
#define M_DATA_ECC_INVERT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_INVERT)
/*
* ECC Test ECC Register (Table 96)
*/
#define S_BCM1480_MC_ECC_INVERT 0
#define M_BCM1480_MC_ECC_INVERT _SB_MAKEMASK(8, S_BCM1480_MC_ECC_INVERT)
/*
* SDRAM Timing Register (Table 97)
*/
#define S_BCM1480_MC_tRCD 0
#define M_BCM1480_MC_tRCD _SB_MAKEMASK(4, S_BCM1480_MC_tRCD)
#define V_BCM1480_MC_tRCD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCD)
#define G_BCM1480_MC_tRCD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCD, M_BCM1480_MC_tRCD)
#define K_BCM1480_MC_tRCD_DEFAULT 3
#define V_BCM1480_MC_tRCD_DEFAULT V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT)
#define S_BCM1480_MC_tCL 4
#define M_BCM1480_MC_tCL _SB_MAKEMASK(4, S_BCM1480_MC_tCL)
#define V_BCM1480_MC_tCL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCL)
#define G_BCM1480_MC_tCL(x) _SB_GETVALUE(x, S_BCM1480_MC_tCL, M_BCM1480_MC_tCL)
#define K_BCM1480_MC_tCL_DEFAULT 2
#define V_BCM1480_MC_tCL_DEFAULT V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT)
#define M_BCM1480_MC_tCrDh _SB_MAKEMASK1(8)
#define S_BCM1480_MC_tWR 9
#define M_BCM1480_MC_tWR _SB_MAKEMASK(3, S_BCM1480_MC_tWR)
#define V_BCM1480_MC_tWR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tWR)
#define G_BCM1480_MC_tWR(x) _SB_GETVALUE(x, S_BCM1480_MC_tWR, M_BCM1480_MC_tWR)
#define K_BCM1480_MC_tWR_DEFAULT 2
#define V_BCM1480_MC_tWR_DEFAULT V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT)
#define S_BCM1480_MC_tCwD 12
#define M_BCM1480_MC_tCwD _SB_MAKEMASK(4, S_BCM1480_MC_tCwD)
#define V_BCM1480_MC_tCwD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tCwD)
#define G_BCM1480_MC_tCwD(x) _SB_GETVALUE(x, S_BCM1480_MC_tCwD, M_BCM1480_MC_tCwD)
#define K_BCM1480_MC_tCwD_DEFAULT 1
#define V_BCM1480_MC_tCwD_DEFAULT V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT)
#define S_BCM1480_MC_tRP 16
#define M_BCM1480_MC_tRP _SB_MAKEMASK(4, S_BCM1480_MC_tRP)
#define V_BCM1480_MC_tRP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRP)
#define G_BCM1480_MC_tRP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRP, M_BCM1480_MC_tRP)
#define K_BCM1480_MC_tRP_DEFAULT 4
#define V_BCM1480_MC_tRP_DEFAULT V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT)
#define S_BCM1480_MC_tRRD 20
#define M_BCM1480_MC_tRRD _SB_MAKEMASK(4, S_BCM1480_MC_tRRD)
#define V_BCM1480_MC_tRRD(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRRD)
#define G_BCM1480_MC_tRRD(x) _SB_GETVALUE(x, S_BCM1480_MC_tRRD, M_BCM1480_MC_tRRD)
#define K_BCM1480_MC_tRRD_DEFAULT 2
#define V_BCM1480_MC_tRRD_DEFAULT V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT)
#define S_BCM1480_MC_tRCw 24
#define M_BCM1480_MC_tRCw _SB_MAKEMASK(5, S_BCM1480_MC_tRCw)
#define V_BCM1480_MC_tRCw(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCw)
#define G_BCM1480_MC_tRCw(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCw, M_BCM1480_MC_tRCw)
#define K_BCM1480_MC_tRCw_DEFAULT 10
#define V_BCM1480_MC_tRCw_DEFAULT V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT)
#define S_BCM1480_MC_tRCr 32
#define M_BCM1480_MC_tRCr _SB_MAKEMASK(5, S_BCM1480_MC_tRCr)
#define V_BCM1480_MC_tRCr(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRCr)
#define G_BCM1480_MC_tRCr(x) _SB_GETVALUE(x, S_BCM1480_MC_tRCr, M_BCM1480_MC_tRCr)
#define K_BCM1480_MC_tRCr_DEFAULT 9
#define V_BCM1480_MC_tRCr_DEFAULT V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT)
#if SIBYTE_HDR_FEATURE(1480, PASS2)
#define S_BCM1480_MC_tFAW 40
#define M_BCM1480_MC_tFAW _SB_MAKEMASK(6, S_BCM1480_MC_tFAW)
#define V_BCM1480_MC_tFAW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFAW)
#define G_BCM1480_MC_tFAW(x) _SB_GETVALUE(x, S_BCM1480_MC_tFAW, M_BCM1480_MC_tFAW)
#define K_BCM1480_MC_tFAW_DEFAULT 0
#define V_BCM1480_MC_tFAW_DEFAULT V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT)
#endif
#define S_BCM1480_MC_tRFC 48
#define M_BCM1480_MC_tRFC _SB_MAKEMASK(7, S_BCM1480_MC_tRFC)
#define V_BCM1480_MC_tRFC(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRFC)
#define G_BCM1480_MC_tRFC(x) _SB_GETVALUE(x, S_BCM1480_MC_tRFC, M_BCM1480_MC_tRFC)
#define K_BCM1480_MC_tRFC_DEFAULT 12
#define V_BCM1480_MC_tRFC_DEFAULT V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT)
#define S_BCM1480_MC_tFIFO 56
#define M_BCM1480_MC_tFIFO _SB_MAKEMASK(2, S_BCM1480_MC_tFIFO)
#define V_BCM1480_MC_tFIFO(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tFIFO)
#define G_BCM1480_MC_tFIFO(x) _SB_GETVALUE(x, S_BCM1480_MC_tFIFO, M_BCM1480_MC_tFIFO)
#define K_BCM1480_MC_tFIFO_DEFAULT 0
#define V_BCM1480_MC_tFIFO_DEFAULT V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT)
#define S_BCM1480_MC_tW2R 58
#define M_BCM1480_MC_tW2R _SB_MAKEMASK(2, S_BCM1480_MC_tW2R)
#define V_BCM1480_MC_tW2R(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2R)
#define G_BCM1480_MC_tW2R(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2R, M_BCM1480_MC_tW2R)
#define K_BCM1480_MC_tW2R_DEFAULT 1
#define V_BCM1480_MC_tW2R_DEFAULT V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT)
#define S_BCM1480_MC_tR2W 60
#define M_BCM1480_MC_tR2W _SB_MAKEMASK(2, S_BCM1480_MC_tR2W)
#define V_BCM1480_MC_tR2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tR2W)
#define G_BCM1480_MC_tR2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tR2W, M_BCM1480_MC_tR2W)
#define K_BCM1480_MC_tR2W_DEFAULT 0
#define V_BCM1480_MC_tR2W_DEFAULT V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT)
#define M_BCM1480_MC_tR2R _SB_MAKEMASK1(62)
#define V_BCM1480_MC_TIMING_DEFAULT (M_BCM1480_MC_tR2R | \
V_BCM1480_MC_tFIFO_DEFAULT | \
V_BCM1480_MC_tR2W_DEFAULT | \
V_BCM1480_MC_tW2R_DEFAULT | \
V_BCM1480_MC_tRFC_DEFAULT | \
V_BCM1480_MC_tRCr_DEFAULT | \
V_BCM1480_MC_tRCw_DEFAULT | \
V_BCM1480_MC_tRRD_DEFAULT | \
V_BCM1480_MC_tRP_DEFAULT | \
V_BCM1480_MC_tCwD_DEFAULT | \
V_BCM1480_MC_tWR_DEFAULT | \
M_BCM1480_MC_tCrDh | \
V_BCM1480_MC_tCL_DEFAULT | \
V_BCM1480_MC_tRCD_DEFAULT)
/*
* SDRAM Timing Register 2
*/
#if SIBYTE_HDR_FEATURE(1480, PASS2)
#define S_BCM1480_MC_tAL 0
#define M_BCM1480_MC_tAL _SB_MAKEMASK(4, S_BCM1480_MC_tAL)
#define V_BCM1480_MC_tAL(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tAL)
#define G_BCM1480_MC_tAL(x) _SB_GETVALUE(x, S_BCM1480_MC_tAL, M_BCM1480_MC_tAL)
#define K_BCM1480_MC_tAL_DEFAULT 0
#define V_BCM1480_MC_tAL_DEFAULT V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT)
#define S_BCM1480_MC_tRTP 4
#define M_BCM1480_MC_tRTP _SB_MAKEMASK(3, S_BCM1480_MC_tRTP)
#define V_BCM1480_MC_tRTP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRTP)
#define G_BCM1480_MC_tRTP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRTP, M_BCM1480_MC_tRTP)
#define K_BCM1480_MC_tRTP_DEFAULT 2
#define V_BCM1480_MC_tRTP_DEFAULT V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT)
#define S_BCM1480_MC_tW2W 8
#define M_BCM1480_MC_tW2W _SB_MAKEMASK(2, S_BCM1480_MC_tW2W)
#define V_BCM1480_MC_tW2W(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tW2W)
#define G_BCM1480_MC_tW2W(x) _SB_GETVALUE(x, S_BCM1480_MC_tW2W, M_BCM1480_MC_tW2W)
#define K_BCM1480_MC_tW2W_DEFAULT 0
#define V_BCM1480_MC_tW2W_DEFAULT V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT)
#define S_BCM1480_MC_tRAP 12
#define M_BCM1480_MC_tRAP _SB_MAKEMASK(4, S_BCM1480_MC_tRAP)
#define V_BCM1480_MC_tRAP(x) _SB_MAKEVALUE(x, S_BCM1480_MC_tRAP)
#define G_BCM1480_MC_tRAP(x) _SB_GETVALUE(x, S_BCM1480_MC_tRAP, M_BCM1480_MC_tRAP)
#define K_BCM1480_MC_tRAP_DEFAULT 0
#define V_BCM1480_MC_tRAP_DEFAULT V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT)
#endif
/*
* Global Registers: single instances per BCM1480
*/
/*
* Global Configuration Register (Table 99)
*/
#define S_BCM1480_MC_BLK_SET_MARK 8
#define M_BCM1480_MC_BLK_SET_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_SET_MARK)
#define V_BCM1480_MC_BLK_SET_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_SET_MARK)
#define G_BCM1480_MC_BLK_SET_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_SET_MARK, M_BCM1480_MC_BLK_SET_MARK)
#define S_BCM1480_MC_BLK_CLR_MARK 12
#define M_BCM1480_MC_BLK_CLR_MARK _SB_MAKEMASK(4, S_BCM1480_MC_BLK_CLR_MARK)
#define V_BCM1480_MC_BLK_CLR_MARK(x) _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_CLR_MARK)
#define G_BCM1480_MC_BLK_CLR_MARK(x) _SB_GETVALUE(x, S_BCM1480_MC_BLK_CLR_MARK, M_BCM1480_MC_BLK_CLR_MARK)
#define M_BCM1480_MC_PKT_PRIORITY _SB_MAKEMASK1(16)
#define S_BCM1480_MC_MAX_AGE 20
#define M_BCM1480_MC_MAX_AGE _SB_MAKEMASK(4, S_BCM1480_MC_MAX_AGE)
#define V_BCM1480_MC_MAX_AGE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_MAX_AGE)
#define G_BCM1480_MC_MAX_AGE(x) _SB_GETVALUE(x, S_BCM1480_MC_MAX_AGE, M_BCM1480_MC_MAX_AGE)
#define M_BCM1480_MC_BERR_DISABLE _SB_MAKEMASK1(29)
#define M_BCM1480_MC_FORCE_SEQ _SB_MAKEMASK1(30)
#define M_BCM1480_MC_VGEN _SB_MAKEMASK1(32)
#define S_BCM1480_MC_SLEW 33
#define M_BCM1480_MC_SLEW _SB_MAKEMASK(2, S_BCM1480_MC_SLEW)
#define V_BCM1480_MC_SLEW(x) _SB_MAKEVALUE(x, S_BCM1480_MC_SLEW)
#define G_BCM1480_MC_SLEW(x) _SB_GETVALUE(x, S_BCM1480_MC_SLEW, M_BCM1480_MC_SLEW)
#define M_BCM1480_MC_SSTL_VOLTAGE _SB_MAKEMASK1(35)
/*
* Global Channel Interleave Register (Table 100)
*/
#define S_BCM1480_MC_INTLV0 0
#define M_BCM1480_MC_INTLV0 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0)
#define V_BCM1480_MC_INTLV0(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0)
#define G_BCM1480_MC_INTLV0(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0)
#define S_BCM1480_MC_INTLV1 8
#define M_BCM1480_MC_INTLV1 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1)
#define V_BCM1480_MC_INTLV1(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1)
#define G_BCM1480_MC_INTLV1(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1)
#define S_BCM1480_MC_INTLV_MODE 16
#define M_BCM1480_MC_INTLV_MODE _SB_MAKEMASK(3, S_BCM1480_MC_INTLV_MODE)
#define V_BCM1480_MC_INTLV_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV_MODE)
#define G_BCM1480_MC_INTLV_MODE(x) _SB_GETVALUE(x, S_BCM1480_MC_INTLV_MODE, M_BCM1480_MC_INTLV_MODE)
#define K_BCM1480_MC_INTLV_MODE_NONE 0x0
#define K_BCM1480_MC_INTLV_MODE_01 0x1
#define K_BCM1480_MC_INTLV_MODE_23 0x2
#define K_BCM1480_MC_INTLV_MODE_01_23 0x3
#define K_BCM1480_MC_INTLV_MODE_0123 0x4
#define V_BCM1480_MC_INTLV_MODE_NONE V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_NONE)
#define V_BCM1480_MC_INTLV_MODE_01 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01)
#define V_BCM1480_MC_INTLV_MODE_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_23)
#define V_BCM1480_MC_INTLV_MODE_01_23 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01_23)
#define V_BCM1480_MC_INTLV_MODE_0123 V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_0123)
/*
* ECC Status Register
*/
#define S_BCM1480_MC_ECC_ERR_ADDR 0
#define M_BCM1480_MC_ECC_ERR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_ERR_ADDR)
#define V_BCM1480_MC_ECC_ERR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR)
#define G_BCM1480_MC_ECC_ERR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR, M_BCM1480_MC_ECC_ERR_ADDR)
#if SIBYTE_HDR_FEATURE(1480, PASS2)
#define M_BCM1480_MC_ECC_ERR_RMW _SB_MAKEMASK1(60)
#endif
#define M_BCM1480_MC_ECC_MULT_ERR_DET _SB_MAKEMASK1(61)
#define M_BCM1480_MC_ECC_UERR_DET _SB_MAKEMASK1(62)
#define M_BCM1480_MC_ECC_CERR_DET _SB_MAKEMASK1(63)
/*
* Global ECC Address Register (Table 102)
*/
#define S_BCM1480_MC_ECC_CORR_ADDR 0
#define M_BCM1480_MC_ECC_CORR_ADDR _SB_MAKEMASK(37, S_BCM1480_MC_ECC_CORR_ADDR)
#define V_BCM1480_MC_ECC_CORR_ADDR(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR)
#define G_BCM1480_MC_ECC_CORR_ADDR(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR, M_BCM1480_MC_ECC_CORR_ADDR)
/*
* Global ECC Correction Register (Table 103)
*/
#define S_BCM1480_MC_ECC_CORRECT 0
#define M_BCM1480_MC_ECC_CORRECT _SB_MAKEMASK(64, S_BCM1480_MC_ECC_CORRECT)
#define V_BCM1480_MC_ECC_CORRECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORRECT)
#define G_BCM1480_MC_ECC_CORRECT(x) _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORRECT, M_BCM1480_MC_ECC_CORRECT)
/*
* Global ECC Performance Counters Control Register (Table 104)
*/
#define S_BCM1480_MC_CHANNEL_SELECT 0
#define M_BCM1480_MC_CHANNEL_SELECT _SB_MAKEMASK(4, S_BCM1480_MC_CHANNEL_SELECT)
#define V_BCM1480_MC_CHANNEL_SELECT(x) _SB_MAKEVALUE(x, S_BCM1480_MC_CHANNEL_SELECT)
#define G_BCM1480_MC_CHANNEL_SELECT(x) _SB_GETVALUE(x, S_BCM1480_MC_CHANNEL_SELECT, M_BCM1480_MC_CHANNEL_SELECT)
#define K_BCM1480_MC_CHANNEL_SELECT_0 0x1
#define K_BCM1480_MC_CHANNEL_SELECT_1 0x2
#define K_BCM1480_MC_CHANNEL_SELECT_2 0x4
#define K_BCM1480_MC_CHANNEL_SELECT_3 0x8
#endif /* _BCM1480_MC_H */

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kernel/arch/mips/include/asm/sibyte/bcm1480_regs.h Normal file
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/* *********************************************************************
* BCM1255/BCM1280/BCM1455/BCM1480 Board Support Package
*
* Register Definitions File: bcm1480_regs.h
*
* This module contains the addresses of the on-chip peripherals
* on the BCM1280 and BCM1480.
*
* BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03)
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _BCM1480_REGS_H
#define _BCM1480_REGS_H
#include "sb1250_defs.h"
/* *********************************************************************
* Pull in the BCM1250's registers since a great deal of the 1480's
* functions are the same as the BCM1250.
********************************************************************* */
#include "sb1250_regs.h"
/* *********************************************************************
* Some general notes:
*
* Register addresses are grouped by function and follow the order
* of the User Manual.
*
* For the most part, when there is more than one peripheral
* of the same type on the SOC, the constants below will be
* offsets from the base of each peripheral. For example,
* the MAC registers are described as offsets from the first
* MAC register, and there will be a MAC_REGISTER() macro
* to calculate the base address of a given MAC.
*
* The information in this file is based on the BCM1X55/BCM1X80
* User Manual, Document 1X55_1X80-UM100-R, 22/12/03.
*
* This file is basically a "what's new" header file. Since the
* BCM1250 and the new BCM1480 (and derivatives) share many common
* features, this file contains only what's new or changed from
* the 1250. (above, you can see that we include the 1250 symbols
* to get the base functionality).
*
* In software, be sure to use the correct symbols, particularly
* for blocks that are different between the two chip families.
* All BCM1480-specific symbols have _BCM1480_ in their names,
* and all BCM1250-specific and "base" functions that are common in
* both chips have no special names (this is for compatibility with
* older include files). Therefore, if you're working with the
* SCD, which is very different on each chip, A_SCD_xxx implies
* the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480
* version.
********************************************************************* */
/* *********************************************************************
* Memory Controller Registers (Section 6)
********************************************************************* */
#define A_BCM1480_MC_BASE_0 0x0010050000
#define A_BCM1480_MC_BASE_1 0x0010051000
#define A_BCM1480_MC_BASE_2 0x0010052000
#define A_BCM1480_MC_BASE_3 0x0010053000
#define BCM1480_MC_REGISTER_SPACING 0x1000
#define A_BCM1480_MC_BASE(ctlid) (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING)
#define A_BCM1480_MC_REGISTER(ctlid, reg) (A_BCM1480_MC_BASE(ctlid)+(reg))
#define R_BCM1480_MC_CONFIG 0x0000000100
#define R_BCM1480_MC_CS_START 0x0000000120
#define R_BCM1480_MC_CS_END 0x0000000140
#define S_BCM1480_MC_CS_STARTEND 24
#define R_BCM1480_MC_CS01_ROW0 0x0000000180
#define R_BCM1480_MC_CS01_ROW1 0x00000001A0
#define R_BCM1480_MC_CS23_ROW0 0x0000000200
#define R_BCM1480_MC_CS23_ROW1 0x0000000220
#define R_BCM1480_MC_CS01_COL0 0x0000000280
#define R_BCM1480_MC_CS01_COL1 0x00000002A0
#define R_BCM1480_MC_CS23_COL0 0x0000000300
#define R_BCM1480_MC_CS23_COL1 0x0000000320
#define R_BCM1480_MC_CSX_BASE 0x0000000180
#define R_BCM1480_MC_CSX_ROW0 0x0000000000 /* relative to CSX_BASE */
#define R_BCM1480_MC_CSX_ROW1 0x0000000020 /* relative to CSX_BASE */
#define R_BCM1480_MC_CSX_COL0 0x0000000100 /* relative to CSX_BASE */
#define R_BCM1480_MC_CSX_COL1 0x0000000120 /* relative to CSX_BASE */
#define BCM1480_MC_CSX_SPACING 0x0000000080 /* CS23 relative to CS01 */
#define R_BCM1480_MC_CS01_BA 0x0000000380
#define R_BCM1480_MC_CS23_BA 0x00000003A0
#define R_BCM1480_MC_DRAMCMD 0x0000000400
#define R_BCM1480_MC_DRAMMODE 0x0000000420
#define R_BCM1480_MC_CLOCK_CFG 0x0000000440
#define R_BCM1480_MC_MCLK_CFG R_BCM1480_MC_CLOCK_CFG
#define R_BCM1480_MC_TEST_DATA 0x0000000480
#define R_BCM1480_MC_TEST_ECC 0x00000004A0
#define R_BCM1480_MC_TIMING1 0x00000004C0
#define R_BCM1480_MC_TIMING2 0x00000004E0
#define R_BCM1480_MC_DLL_CFG 0x0000000500
#define R_BCM1480_MC_DRIVE_CFG 0x0000000520
#if SIBYTE_HDR_FEATURE(1480, PASS2)
#define R_BCM1480_MC_ODT 0x0000000460
#define R_BCM1480_MC_ECC_STATUS 0x0000000540
#endif
/* Global registers (single instance) */
#define A_BCM1480_MC_GLB_CONFIG 0x0010054100
#define A_BCM1480_MC_GLB_INTLV 0x0010054120
#define A_BCM1480_MC_GLB_ECC_STATUS 0x0010054140
#define A_BCM1480_MC_GLB_ECC_ADDR 0x0010054160
#define A_BCM1480_MC_GLB_ECC_CORRECT 0x0010054180
#define A_BCM1480_MC_GLB_PERF_CNT_CONTROL 0x00100541A0
/* *********************************************************************
* L2 Cache Control Registers (Section 5)
********************************************************************* */
#define A_BCM1480_L2_BASE 0x0010040000
#define A_BCM1480_L2_READ_TAG 0x0010040018
#define A_BCM1480_L2_ECC_TAG 0x0010040038
#define A_BCM1480_L2_MISC0_VALUE 0x0010040058
#define A_BCM1480_L2_MISC1_VALUE 0x0010040078
#define A_BCM1480_L2_MISC2_VALUE 0x0010040098
#define A_BCM1480_L2_MISC_CONFIG 0x0010040040 /* x040 */
#define A_BCM1480_L2_CACHE_DISABLE 0x0010040060 /* x060 */
#define A_BCM1480_L2_MAKECACHEDISABLE(x) (A_BCM1480_L2_CACHE_DISABLE | (((x)&0xF) << 12))
#define A_BCM1480_L2_WAY_ENABLE_3_0 0x0010040080 /* x080 */
#define A_BCM1480_L2_WAY_ENABLE_7_4 0x00100400A0 /* x0A0 */
#define A_BCM1480_L2_MAKE_WAY_ENABLE_LO(x) (A_BCM1480_L2_WAY_ENABLE_3_0 | (((x)&0xF) << 12))
#define A_BCM1480_L2_MAKE_WAY_ENABLE_HI(x) (A_BCM1480_L2_WAY_ENABLE_7_4 | (((x)&0xF) << 12))
#define A_BCM1480_L2_MAKE_WAY_DISABLE_LO(x) (A_BCM1480_L2_WAY_ENABLE_3_0 | (((~x)&0xF) << 12))
#define A_BCM1480_L2_MAKE_WAY_DISABLE_HI(x) (A_BCM1480_L2_WAY_ENABLE_7_4 | (((~x)&0xF) << 12))
#define A_BCM1480_L2_WAY_LOCAL_3_0 0x0010040100 /* x100 */
#define A_BCM1480_L2_WAY_LOCAL_7_4 0x0010040120 /* x120 */
#define A_BCM1480_L2_WAY_REMOTE_3_0 0x0010040140 /* x140 */
#define A_BCM1480_L2_WAY_REMOTE_7_4 0x0010040160 /* x160 */
#define A_BCM1480_L2_WAY_AGENT_3_0 0x00100400C0 /* xxC0 */
#define A_BCM1480_L2_WAY_AGENT_7_4 0x00100400E0 /* xxE0 */
#define A_BCM1480_L2_WAY_ENABLE(A, banks) (A | (((~(banks))&0x0F) << 8))
#define A_BCM1480_L2_BANK_BASE 0x00D0300000
#define A_BCM1480_L2_BANK_ADDRESS(b) (A_BCM1480_L2_BANK_BASE | (((b)&0x7)<<17))
#define A_BCM1480_L2_MGMT_TAG_BASE 0x00D0000000
/* *********************************************************************
* PCI-X Interface Registers (Section 7)
********************************************************************* */
#define A_BCM1480_PCI_BASE 0x0010061400
#define A_BCM1480_PCI_RESET 0x0010061400
#define A_BCM1480_PCI_DLL 0x0010061500
#define A_BCM1480_PCI_TYPE00_HEADER 0x002E000000
/* *********************************************************************
* Ethernet MAC Registers (Section 11) and DMA Registers (Section 10.6)
********************************************************************* */
/* No register changes with Rev.C BCM1250, but one additional MAC */
#define A_BCM1480_MAC_BASE_2 0x0010066000
#ifndef A_MAC_BASE_2
#define A_MAC_BASE_2 A_BCM1480_MAC_BASE_2
#endif
#define A_BCM1480_MAC_BASE_3 0x0010067000
#define A_MAC_BASE_3 A_BCM1480_MAC_BASE_3
#define R_BCM1480_MAC_DMA_OODPKTLOST 0x00000038
#ifndef R_MAC_DMA_OODPKTLOST
#define R_MAC_DMA_OODPKTLOST R_BCM1480_MAC_DMA_OODPKTLOST
#endif
/* *********************************************************************
* DUART Registers (Section 14)
********************************************************************* */
/* No significant differences from BCM1250, two DUARTs */
/* Conventions, per user manual:
* DUART generic, channels A,B,C,D
* DUART0 implementing channels A,B
* DUART1 inplementing channels C,D
*/
#define BCM1480_DUART_NUM_PORTS 4
#define A_BCM1480_DUART0 0x0010060000
#define A_BCM1480_DUART1 0x0010060400
#define A_BCM1480_DUART(chan) ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1)
#define BCM1480_DUART_CHANREG_SPACING 0x100
#define A_BCM1480_DUART_CHANREG(chan, reg) \
(A_BCM1480_DUART(chan) + \
BCM1480_DUART_CHANREG_SPACING * (((chan) & 1) + 1) + (reg))
#define A_BCM1480_DUART_CTRLREG(chan, reg) \
(A_BCM1480_DUART(chan) + \
BCM1480_DUART_CHANREG_SPACING * 3 + (reg))
#define DUART_IMRISR_SPACING 0x20
#define DUART_INCHNG_SPACING 0x10
#define R_BCM1480_DUART_IMRREG(chan) \
(R_DUART_IMR_A + ((chan) & 1) * DUART_IMRISR_SPACING)
#define R_BCM1480_DUART_ISRREG(chan) \
(R_DUART_ISR_A + ((chan) & 1) * DUART_IMRISR_SPACING)
#define R_BCM1480_DUART_INCHREG(chan) \
(R_DUART_IN_CHNG_A + ((chan) & 1) * DUART_INCHNG_SPACING)
#define A_BCM1480_DUART_IMRREG(chan) \
(A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_IMRREG(chan)))
#define A_BCM1480_DUART_ISRREG(chan) \
(A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_ISRREG(chan)))
#define A_BCM1480_DUART_IN_PORT(chan) \
(A_BCM1480_DUART_CTRLREG((chan), R_DUART_IN_PORT))
/*
* These constants are the absolute addresses.
*/
#define A_BCM1480_DUART_MODE_REG_1_C 0x0010060400
#define A_BCM1480_DUART_MODE_REG_2_C 0x0010060410
#define A_BCM1480_DUART_STATUS_C 0x0010060420
#define A_BCM1480_DUART_CLK_SEL_C 0x0010060430
#define A_BCM1480_DUART_FULL_CTL_C 0x0010060440
#define A_BCM1480_DUART_CMD_C 0x0010060450
#define A_BCM1480_DUART_RX_HOLD_C 0x0010060460
#define A_BCM1480_DUART_TX_HOLD_C 0x0010060470
#define A_BCM1480_DUART_OPCR_C 0x0010060480
#define A_BCM1480_DUART_AUX_CTRL_C 0x0010060490
#define A_BCM1480_DUART_MODE_REG_1_D 0x0010060500
#define A_BCM1480_DUART_MODE_REG_2_D 0x0010060510
#define A_BCM1480_DUART_STATUS_D 0x0010060520
#define A_BCM1480_DUART_CLK_SEL_D 0x0010060530
#define A_BCM1480_DUART_FULL_CTL_D 0x0010060540
#define A_BCM1480_DUART_CMD_D 0x0010060550
#define A_BCM1480_DUART_RX_HOLD_D 0x0010060560
#define A_BCM1480_DUART_TX_HOLD_D 0x0010060570
#define A_BCM1480_DUART_OPCR_D 0x0010060580
#define A_BCM1480_DUART_AUX_CTRL_D 0x0010060590
#define A_BCM1480_DUART_INPORT_CHNG_CD 0x0010060600
#define A_BCM1480_DUART_AUX_CTRL_CD 0x0010060610
#define A_BCM1480_DUART_ISR_C 0x0010060620
#define A_BCM1480_DUART_IMR_C 0x0010060630
#define A_BCM1480_DUART_ISR_D 0x0010060640
#define A_BCM1480_DUART_IMR_D 0x0010060650
#define A_BCM1480_DUART_OUT_PORT_CD 0x0010060660
#define A_BCM1480_DUART_OPCR_CD 0x0010060670
#define A_BCM1480_DUART_IN_PORT_CD 0x0010060680
#define A_BCM1480_DUART_ISR_CD 0x0010060690
#define A_BCM1480_DUART_IMR_CD 0x00100606A0
#define A_BCM1480_DUART_SET_OPR_CD 0x00100606B0
#define A_BCM1480_DUART_CLEAR_OPR_CD 0x00100606C0
#define A_BCM1480_DUART_INPORT_CHNG_C 0x00100606D0
#define A_BCM1480_DUART_INPORT_CHNG_D 0x00100606E0
/* *********************************************************************
* Generic Bus Registers (Section 15) and PCMCIA Registers (Section 16)
********************************************************************* */
#define A_BCM1480_IO_PCMCIA_CFG_B 0x0010061A58
#define A_BCM1480_IO_PCMCIA_STATUS_B 0x0010061A68
/* *********************************************************************
* GPIO Registers (Section 17)
********************************************************************* */
/* One additional GPIO register, placed _before_ the BCM1250's GPIO block base */
#define A_BCM1480_GPIO_INT_ADD_TYPE 0x0010061A78
#define R_BCM1480_GPIO_INT_ADD_TYPE (-8)
#define A_GPIO_INT_ADD_TYPE A_BCM1480_GPIO_INT_ADD_TYPE
#define R_GPIO_INT_ADD_TYPE R_BCM1480_GPIO_INT_ADD_TYPE
/* *********************************************************************
* SMBus Registers (Section 18)
********************************************************************* */
/* No changes from BCM1250 */
/* *********************************************************************
* Timer Registers (Sections 4.6)
********************************************************************* */
/* BCM1480 has two additional watchdogs */
/* Watchdog timers */
#define A_BCM1480_SCD_WDOG_2 0x0010022050
#define A_BCM1480_SCD_WDOG_3 0x0010022150
#define BCM1480_SCD_NUM_WDOGS 4
#define A_BCM1480_SCD_WDOG_BASE(w) (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100)
#define A_BCM1480_SCD_WDOG_REGISTER(w, r) (A_BCM1480_SCD_WDOG_BASE(w) + (r))
#define A_BCM1480_SCD_WDOG_INIT_2 0x0010022050
#define A_BCM1480_SCD_WDOG_CNT_2 0x0010022058
#define A_BCM1480_SCD_WDOG_CFG_2 0x0010022060
#define A_BCM1480_SCD_WDOG_INIT_3 0x0010022150
#define A_BCM1480_SCD_WDOG_CNT_3 0x0010022158
#define A_BCM1480_SCD_WDOG_CFG_3 0x0010022160
/* BCM1480 has two additional compare registers */
#define A_BCM1480_SCD_ZBBUS_CYCLE_COUNT A_SCD_ZBBUS_CYCLE_COUNT
#define A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE 0x0010020C00
#define A_BCM1480_SCD_ZBBUS_CYCLE_CP0 A_SCD_ZBBUS_CYCLE_CP0
#define A_BCM1480_SCD_ZBBUS_CYCLE_CP1 A_SCD_ZBBUS_CYCLE_CP1
#define A_BCM1480_SCD_ZBBUS_CYCLE_CP2 0x0010020C10
#define A_BCM1480_SCD_ZBBUS_CYCLE_CP3 0x0010020C18
/* *********************************************************************
* System Control Registers (Section 4.2)
********************************************************************* */
/* Scratch register in different place */
#define A_BCM1480_SCD_SCRATCH 0x100200A0
/* *********************************************************************
* System Address Trap Registers (Section 4.9)
********************************************************************* */
/* No changes from BCM1250 */
/* *********************************************************************
* System Interrupt Mapper Registers (Sections 4.3-4.5)
********************************************************************* */
#define A_BCM1480_IMR_CPU0_BASE 0x0010020000
#define A_BCM1480_IMR_CPU1_BASE 0x0010022000
#define A_BCM1480_IMR_CPU2_BASE 0x0010024000
#define A_BCM1480_IMR_CPU3_BASE 0x0010026000
#define BCM1480_IMR_REGISTER_SPACING 0x2000
#define BCM1480_IMR_REGISTER_SPACING_SHIFT 13
#define A_BCM1480_IMR_MAPPER(cpu) (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING)
#define A_BCM1480_IMR_REGISTER(cpu, reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg))
/* Most IMR registers are 128 bits, implemented as non-contiguous
64-bit registers high (_H) and low (_L) */
#define BCM1480_IMR_HL_SPACING 0x1000
#define R_BCM1480_IMR_INTERRUPT_DIAG_H 0x0010
#define R_BCM1480_IMR_LDT_INTERRUPT_H 0x0018
#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_H 0x0020
#define R_BCM1480_IMR_INTERRUPT_MASK_H 0x0028
#define R_BCM1480_IMR_INTERRUPT_TRACE_H 0x0038
#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_H 0x0040
#define R_BCM1480_IMR_LDT_INTERRUPT_SET 0x0048
#define R_BCM1480_IMR_MAILBOX_0_CPU 0x00C0
#define R_BCM1480_IMR_MAILBOX_0_SET_CPU 0x00C8
#define R_BCM1480_IMR_MAILBOX_0_CLR_CPU 0x00D0
#define R_BCM1480_IMR_MAILBOX_1_CPU 0x00E0
#define R_BCM1480_IMR_MAILBOX_1_SET_CPU 0x00E8
#define R_BCM1480_IMR_MAILBOX_1_CLR_CPU 0x00F0
#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H 0x0100
#define BCM1480_IMR_INTERRUPT_STATUS_COUNT 8
#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_H 0x0200
#define BCM1480_IMR_INTERRUPT_MAP_COUNT 64
#define R_BCM1480_IMR_INTERRUPT_DIAG_L 0x1010
#define R_BCM1480_IMR_LDT_INTERRUPT_L 0x1018
#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_L 0x1020
#define R_BCM1480_IMR_INTERRUPT_MASK_L 0x1028
#define R_BCM1480_IMR_INTERRUPT_TRACE_L 0x1038
#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_L 0x1040
#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L 0x1100
#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_L 0x1200
#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE 0x0010028000
#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE 0x0010028100
#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU2_BASE 0x0010028200
#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU3_BASE 0x0010028300
#define BCM1480_IMR_ALIAS_MAILBOX_SPACING 0100
#define A_BCM1480_IMR_ALIAS_MAILBOX(cpu) (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \
(cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING)
#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu, reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg))
#define R_BCM1480_IMR_ALIAS_MAILBOX_0 0x0000 /* 0x0x0 */
#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET 0x0008 /* 0x0x8 */
/*
* these macros work together to build the address of a mailbox
* register, e.g., A_BCM1480_MAILBOX_REGISTER(0,R_BCM1480_IMR_MAILBOX_SET,2)
* for mbox_0_set_cpu2 returns 0x00100240C8
*/
#define R_BCM1480_IMR_MAILBOX_CPU 0x00
#define R_BCM1480_IMR_MAILBOX_SET 0x08
#define R_BCM1480_IMR_MAILBOX_CLR 0x10
#define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20
#define A_BCM1480_MAILBOX_REGISTER(num, reg, cpu) \
(A_BCM1480_IMR_CPU0_BASE + \
(num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \
(cpu * BCM1480_IMR_REGISTER_SPACING) + \
(R_BCM1480_IMR_MAILBOX_0_CPU + reg))
/* *********************************************************************
* System Performance Counter Registers (Section 4.7)
********************************************************************* */
/* BCM1480 has four more performance counter registers, and two control
registers. */
#define A_BCM1480_SCD_PERF_CNT_BASE 0x00100204C0
#define A_BCM1480_SCD_PERF_CNT_CFG0 0x00100204C0
#define A_BCM1480_SCD_PERF_CNT_CFG_0 A_BCM1480_SCD_PERF_CNT_CFG0
#define A_BCM1480_SCD_PERF_CNT_CFG1 0x00100204C8
#define A_BCM1480_SCD_PERF_CNT_CFG_1 A_BCM1480_SCD_PERF_CNT_CFG1
#define A_BCM1480_SCD_PERF_CNT_0 A_SCD_PERF_CNT_0
#define A_BCM1480_SCD_PERF_CNT_1 A_SCD_PERF_CNT_1
#define A_BCM1480_SCD_PERF_CNT_2 A_SCD_PERF_CNT_2
#define A_BCM1480_SCD_PERF_CNT_3 A_SCD_PERF_CNT_3
#define A_BCM1480_SCD_PERF_CNT_4 0x00100204F0
#define A_BCM1480_SCD_PERF_CNT_5 0x00100204F8
#define A_BCM1480_SCD_PERF_CNT_6 0x0010020500
#define A_BCM1480_SCD_PERF_CNT_7 0x0010020508
#define BCM1480_SCD_NUM_PERF_CNT 8
#define BCM1480_SCD_PERF_CNT_SPACING 8
#define A_BCM1480_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*BCM1480_SCD_PERF_CNT_SPACING))
/* *********************************************************************
* System Bus Watcher Registers (Section 4.8)
********************************************************************* */
/* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */
#define A_BCM1480_BUS_ERR_STATUS_DEBUG 0x00100208D8
/* *********************************************************************
* System Debug Controller Registers (Section 19)
********************************************************************* */
/* Same as 1250 */
/* *********************************************************************
* System Trace Unit Registers (Sections 4.10)
********************************************************************* */
/* Same as 1250 */
/* *********************************************************************
* Data Mover DMA Registers (Section 10.7)
********************************************************************* */
/* Same as 1250 */
/* *********************************************************************
* HyperTransport Interface Registers (Section 8)
********************************************************************* */
#define BCM1480_HT_NUM_PORTS 3
#define BCM1480_HT_PORT_SPACING 0x800
#define A_BCM1480_HT_PORT_HEADER(x) (A_BCM1480_HT_PORT0_HEADER + ((x)*BCM1480_HT_PORT_SPACING))
#define A_BCM1480_HT_PORT0_HEADER 0x00FE000000
#define A_BCM1480_HT_PORT1_HEADER 0x00FE000800
#define A_BCM1480_HT_PORT2_HEADER 0x00FE001000
#define A_BCM1480_HT_TYPE00_HEADER 0x00FE002000
/* *********************************************************************
* Node Controller Registers (Section 9)
********************************************************************* */
#define A_BCM1480_NC_BASE 0x00DFBD0000
#define A_BCM1480_NC_RLD_FIELD 0x00DFBD0000
#define A_BCM1480_NC_RLD_TRIGGER 0x00DFBD0020
#define A_BCM1480_NC_RLD_BAD_ERROR 0x00DFBD0040
#define A_BCM1480_NC_RLD_COR_ERROR 0x00DFBD0060
#define A_BCM1480_NC_RLD_ECC_STATUS 0x00DFBD0080
#define A_BCM1480_NC_RLD_WAY_ENABLE 0x00DFBD00A0
#define A_BCM1480_NC_RLD_RANDOM_LFSR 0x00DFBD00C0
#define A_BCM1480_NC_INTERRUPT_STATUS 0x00DFBD00E0
#define A_BCM1480_NC_INTERRUPT_ENABLE 0x00DFBD0100
#define A_BCM1480_NC_TIMEOUT_COUNTER 0x00DFBD0120
#define A_BCM1480_NC_TIMEOUT_COUNTER_SEL 0x00DFBD0140
#define A_BCM1480_NC_CREDIT_STATUS_REG0 0x00DFBD0200
#define A_BCM1480_NC_CREDIT_STATUS_REG1 0x00DFBD0220
#define A_BCM1480_NC_CREDIT_STATUS_REG2 0x00DFBD0240
#define A_BCM1480_NC_CREDIT_STATUS_REG3 0x00DFBD0260
#define A_BCM1480_NC_CREDIT_STATUS_REG4 0x00DFBD0280
#define A_BCM1480_NC_CREDIT_STATUS_REG5 0x00DFBD02A0
#define A_BCM1480_NC_CREDIT_STATUS_REG6 0x00DFBD02C0
#define A_BCM1480_NC_CREDIT_STATUS_REG7 0x00DFBD02E0
#define A_BCM1480_NC_CREDIT_STATUS_REG8 0x00DFBD0300
#define A_BCM1480_NC_CREDIT_STATUS_REG9 0x00DFBD0320
#define A_BCM1480_NC_CREDIT_STATUS_REG10 0x00DFBE0000
#define A_BCM1480_NC_CREDIT_STATUS_REG11 0x00DFBE0020
#define A_BCM1480_NC_CREDIT_STATUS_REG12 0x00DFBE0040
#define A_BCM1480_NC_SR_TIMEOUT_COUNTER 0x00DFBE0060
#define A_BCM1480_NC_SR_TIMEOUT_COUNTER_SEL 0x00DFBE0080
/* *********************************************************************
* H&R Block Configuration Registers (Section 12.4)
********************************************************************* */
#define A_BCM1480_HR_BASE_0 0x00DF820000
#define A_BCM1480_HR_BASE_1 0x00DF8A0000
#define A_BCM1480_HR_BASE_2 0x00DF920000
#define BCM1480_HR_REGISTER_SPACING 0x80000
#define A_BCM1480_HR_BASE(idx) (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING))
#define A_BCM1480_HR_REGISTER(idx, reg) (A_BCM1480_HR_BASE(idx) + (reg))
#define R_BCM1480_HR_CFG 0x0000000000
#define R_BCM1480_HR_MAPPING 0x0000010010
#define BCM1480_HR_RULE_SPACING 0x0000000010
#define BCM1480_HR_NUM_RULES 16
#define BCM1480_HR_OP_OFFSET 0x0000000100
#define BCM1480_HR_TYPE_OFFSET 0x0000000108
#define R_BCM1480_HR_RULE_OP(idx) (BCM1480_HR_OP_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))
#define R_BCM1480_HR_RULE_TYPE(idx) (BCM1480_HR_TYPE_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))
#define BCM1480_HR_LEAF_SPACING 0x0000000010
#define BCM1480_HR_NUM_LEAVES 10
#define BCM1480_HR_LEAF_OFFSET 0x0000000300
#define R_BCM1480_HR_HA_LEAF0(idx) (BCM1480_HR_LEAF_OFFSET + ((idx)*BCM1480_HR_LEAF_SPACING))
#define R_BCM1480_HR_EX_LEAF0 0x00000003A0
#define BCM1480_HR_PATH_SPACING 0x0000000010
#define BCM1480_HR_NUM_PATHS 16
#define BCM1480_HR_PATH_OFFSET 0x0000000600
#define R_BCM1480_HR_PATH(idx) (BCM1480_HR_PATH_OFFSET + ((idx)*BCM1480_HR_PATH_SPACING))
#define R_BCM1480_HR_PATH_DEFAULT 0x0000000700
#define BCM1480_HR_ROUTE_SPACING 8
#define BCM1480_HR_NUM_ROUTES 512
#define BCM1480_HR_ROUTE_OFFSET 0x0000001000
#define R_BCM1480_HR_RT_WORD(idx) (BCM1480_HR_ROUTE_OFFSET + ((idx)*BCM1480_HR_ROUTE_SPACING))
/* checked to here - ehs */
/* *********************************************************************
* Packet Manager DMA Registers (Section 12.5)
********************************************************************* */
#define A_BCM1480_PM_BASE 0x0010056000
#define A_BCM1480_PMI_LCL_0 0x0010058000
#define A_BCM1480_PMO_LCL_0 0x001005C000
#define A_BCM1480_PMI_OFFSET_0 (A_BCM1480_PMI_LCL_0 - A_BCM1480_PM_BASE)
#define A_BCM1480_PMO_OFFSET_0 (A_BCM1480_PMO_LCL_0 - A_BCM1480_PM_BASE)
#define BCM1480_PM_LCL_REGISTER_SPACING 0x100
#define BCM1480_PM_NUM_CHANNELS 32
#define A_BCM1480_PMI_LCL_BASE(idx) (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
#define A_BCM1480_PMI_LCL_REGISTER(idx, reg) (A_BCM1480_PMI_LCL_BASE(idx) + (reg))
#define A_BCM1480_PMO_LCL_BASE(idx) (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
#define A_BCM1480_PMO_LCL_REGISTER(idx, reg) (A_BCM1480_PMO_LCL_BASE(idx) + (reg))
#define BCM1480_PM_INT_PACKING 8
#define BCM1480_PM_INT_FUNCTION_SPACING 0x40
#define BCM1480_PM_INT_NUM_FUNCTIONS 3
/*
* DMA channel registers relative to A_BCM1480_PMI_LCL_BASE(n) and A_BCM1480_PMO_LCL_BASE(n)
*/
#define R_BCM1480_PM_BASE_SIZE 0x0000000000
#define R_BCM1480_PM_CNT 0x0000000008
#define R_BCM1480_PM_PFCNT 0x0000000010
#define R_BCM1480_PM_LAST 0x0000000018
#define R_BCM1480_PM_PFINDX 0x0000000020
#define R_BCM1480_PM_INT_WMK 0x0000000028
#define R_BCM1480_PM_CONFIG0 0x0000000030
#define R_BCM1480_PM_LOCALDEBUG 0x0000000078
#define R_BCM1480_PM_CACHEABILITY 0x0000000080 /* PMI only */
#define R_BCM1480_PM_INT_CNFG 0x0000000088
#define R_BCM1480_PM_DESC_MERGE_TIMER 0x0000000090
#define R_BCM1480_PM_LOCALDEBUG_PIB 0x00000000F8 /* PMI only */
#define R_BCM1480_PM_LOCALDEBUG_POB 0x00000000F8 /* PMO only */
/*
* Global Registers (Not Channelized)
*/
#define A_BCM1480_PMI_GLB_0 0x0010056000
#define A_BCM1480_PMO_GLB_0 0x0010057000
/*
* PM to TX Mapping Register relative to A_BCM1480_PMI_GLB_0 and A_BCM1480_PMO_GLB_0
*/
#define R_BCM1480_PM_PMO_MAPPING 0x00000008C8 /* PMO only */
#define A_BCM1480_PM_PMO_MAPPING (A_BCM1480_PMO_GLB_0 + R_BCM1480_PM_PMO_MAPPING)
/*
* Interrupt mapping registers
*/
#define A_BCM1480_PMI_INT_0 0x0010056800
#define A_BCM1480_PMI_INT(q) (A_BCM1480_PMI_INT_0 + ((q>>8)<<8))
#define A_BCM1480_PMI_INT_OFFSET_0 (A_BCM1480_PMI_INT_0 - A_BCM1480_PM_BASE)
#define A_BCM1480_PMO_INT_0 0x0010057800
#define A_BCM1480_PMO_INT(q) (A_BCM1480_PMO_INT_0 + ((q>>8)<<8))
#define A_BCM1480_PMO_INT_OFFSET_0 (A_BCM1480_PMO_INT_0 - A_BCM1480_PM_BASE)
/*
* Interrupt registers relative to A_BCM1480_PMI_INT_0 and A_BCM1480_PMO_INT_0
*/
#define R_BCM1480_PM_INT_ST 0x0000000000
#define R_BCM1480_PM_INT_MSK 0x0000000040
#define R_BCM1480_PM_INT_CLR 0x0000000080
#define R_BCM1480_PM_MRGD_INT 0x00000000C0
/*
* Debug registers (global)
*/
#define A_BCM1480_PM_GLOBALDEBUGMODE_PMI 0x0010056000
#define A_BCM1480_PM_GLOBALDEBUG_PID 0x00100567F8
#define A_BCM1480_PM_GLOBALDEBUG_PIB 0x0010056FF8
#define A_BCM1480_PM_GLOBALDEBUGMODE_PMO 0x0010057000
#define A_BCM1480_PM_GLOBALDEBUG_POD 0x00100577F8
#define A_BCM1480_PM_GLOBALDEBUG_POB 0x0010057FF8
/* *********************************************************************
* Switch performance counters
********************************************************************* */
#define A_BCM1480_SWPERF_CFG 0xdfb91800
#define A_BCM1480_SWPERF_CNT0 0xdfb91880
#define A_BCM1480_SWPERF_CNT1 0xdfb91888
#define A_BCM1480_SWPERF_CNT2 0xdfb91890
#define A_BCM1480_SWPERF_CNT3 0xdfb91898
/* *********************************************************************
* Switch Trace Unit
********************************************************************* */
#define A_BCM1480_SWTRC_MATCH_CONTROL_0 0xDFB91000
#define A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 0xDFB91100
#define A_BCM1480_SWTRC_MATCH_DATA_MASK_0 0xDFB91108
#define A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 0xDFB91200
#define A_BCM1480_SWTRC_MATCH_TAG_MAKS_0 0xDFB91208
#define A_BCM1480_SWTRC_EVENT_0 0xDFB91300
#define A_BCM1480_SWTRC_SEQUENCE_0 0xDFB91400
#define A_BCM1480_SWTRC_CFG 0xDFB91500
#define A_BCM1480_SWTRC_READ 0xDFB91508
#define A_BCM1480_SWDEBUG_SCHEDSTOP 0xDFB92000
#define A_BCM1480_SWTRC_MATCH_CONTROL(x) (A_BCM1480_SWTRC_MATCH_CONTROL_0 + ((x)*8))
#define A_BCM1480_SWTRC_EVENT(x) (A_BCM1480_SWTRC_EVENT_0 + ((x)*8))
#define A_BCM1480_SWTRC_SEQUENCE(x) (A_BCM1480_SWTRC_SEQUENCE_0 + ((x)*8))
#define A_BCM1480_SWTRC_MATCH_DATA_VALUE(x) (A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 + ((x)*16))
#define A_BCM1480_SWTRC_MATCH_DATA_MASK(x) (A_BCM1480_SWTRC_MATCH_DATA_MASK_0 + ((x)*16))
#define A_BCM1480_SWTRC_MATCH_TAG_VALUE(x) (A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 + ((x)*16))
#define A_BCM1480_SWTRC_MATCH_TAG_MASK(x) (A_BCM1480_SWTRC_MATCH_TAG_MASK_0 + ((x)*16))
/* *********************************************************************
* High-Speed Port Registers (Section 13)
********************************************************************* */
#define A_BCM1480_HSP_BASE_0 0x00DF810000
#define A_BCM1480_HSP_BASE_1 0x00DF890000
#define A_BCM1480_HSP_BASE_2 0x00DF910000
#define BCM1480_HSP_REGISTER_SPACING 0x80000
#define A_BCM1480_HSP_BASE(idx) (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING))
#define A_BCM1480_HSP_REGISTER(idx, reg) (A_BCM1480_HSP_BASE(idx) + (reg))
#define R_BCM1480_HSP_RX_SPI4_CFG_0 0x0000000000
#define R_BCM1480_HSP_RX_SPI4_CFG_1 0x0000000008
#define R_BCM1480_HSP_RX_SPI4_DESKEW_OVERRIDE 0x0000000010
#define R_BCM1480_HSP_RX_SPI4_DESKEW_DATAPATH 0x0000000018
#define R_BCM1480_HSP_RX_SPI4_PORT_INT_EN 0x0000000020
#define R_BCM1480_HSP_RX_SPI4_PORT_INT_STATUS 0x0000000028
#define R_BCM1480_HSP_RX_SPI4_CALENDAR_0 0x0000000200
#define R_BCM1480_HSP_RX_SPI4_CALENDAR_1 0x0000000208
#define R_BCM1480_HSP_RX_PLL_CNFG 0x0000000800
#define R_BCM1480_HSP_RX_CALIBRATION 0x0000000808
#define R_BCM1480_HSP_RX_TEST 0x0000000810
#define R_BCM1480_HSP_RX_DIAG_DETAILS 0x0000000818
#define R_BCM1480_HSP_RX_DIAG_CRC_0 0x0000000820
#define R_BCM1480_HSP_RX_DIAG_CRC_1 0x0000000828
#define R_BCM1480_HSP_RX_DIAG_HTCMD 0x0000000830
#define R_BCM1480_HSP_RX_DIAG_PKTCTL 0x0000000838
#define R_BCM1480_HSP_RX_VIS_FLCTRL_COUNTER 0x0000000870
#define R_BCM1480_HSP_RX_PKT_RAMALLOC_0 0x0000020020
#define R_BCM1480_HSP_RX_PKT_RAMALLOC_1 0x0000020028
#define R_BCM1480_HSP_RX_PKT_RAMALLOC_2 0x0000020030
#define R_BCM1480_HSP_RX_PKT_RAMALLOC_3 0x0000020038
#define R_BCM1480_HSP_RX_PKT_RAMALLOC_4 0x0000020040
#define R_BCM1480_HSP_RX_PKT_RAMALLOC_5 0x0000020048
#define R_BCM1480_HSP_RX_PKT_RAMALLOC_6 0x0000020050
#define R_BCM1480_HSP_RX_PKT_RAMALLOC_7 0x0000020058
#define R_BCM1480_HSP_RX_PKT_RAMALLOC(idx) (R_BCM1480_HSP_RX_PKT_RAMALLOC_0 + 8*(idx))
/* XXX Following registers were shuffled. Renamed/renumbered per errata. */
#define R_BCM1480_HSP_RX_HT_RAMALLOC_0 0x0000020078
#define R_BCM1480_HSP_RX_HT_RAMALLOC_1 0x0000020080
#define R_BCM1480_HSP_RX_HT_RAMALLOC_2 0x0000020088
#define R_BCM1480_HSP_RX_HT_RAMALLOC_3 0x0000020090
#define R_BCM1480_HSP_RX_HT_RAMALLOC_4 0x0000020098
#define R_BCM1480_HSP_RX_HT_RAMALLOC_5 0x00000200A0
#define R_BCM1480_HSP_RX_SPI_WATERMARK_0 0x00000200B0
#define R_BCM1480_HSP_RX_SPI_WATERMARK_1 0x00000200B8
#define R_BCM1480_HSP_RX_SPI_WATERMARK_2 0x00000200C0
#define R_BCM1480_HSP_RX_SPI_WATERMARK_3 0x00000200C8
#define R_BCM1480_HSP_RX_SPI_WATERMARK_4 0x00000200D0
#define R_BCM1480_HSP_RX_SPI_WATERMARK_5 0x00000200D8
#define R_BCM1480_HSP_RX_SPI_WATERMARK_6 0x00000200E0
#define R_BCM1480_HSP_RX_SPI_WATERMARK_7 0x00000200E8
#define R_BCM1480_HSP_RX_SPI_WATERMARK(idx) (R_BCM1480_HSP_RX_SPI_WATERMARK_0 + 8*(idx))
#define R_BCM1480_HSP_RX_VIS_CMDQ_0 0x00000200F0
#define R_BCM1480_HSP_RX_VIS_CMDQ_1 0x00000200F8
#define R_BCM1480_HSP_RX_VIS_CMDQ_2 0x0000020100
#define R_BCM1480_HSP_RX_RAM_READCTL 0x0000020108
#define R_BCM1480_HSP_RX_RAM_READWINDOW 0x0000020110
#define R_BCM1480_HSP_RX_RF_READCTL 0x0000020118
#define R_BCM1480_HSP_RX_RF_READWINDOW 0x0000020120
#define R_BCM1480_HSP_TX_SPI4_CFG_0 0x0000040000
#define R_BCM1480_HSP_TX_SPI4_CFG_1 0x0000040008
#define R_BCM1480_HSP_TX_SPI4_TRAINING_FMT 0x0000040010
#define R_BCM1480_HSP_TX_PKT_RAMALLOC_0 0x0000040020
#define R_BCM1480_HSP_TX_PKT_RAMALLOC_1 0x0000040028
#define R_BCM1480_HSP_TX_PKT_RAMALLOC_2 0x0000040030
#define R_BCM1480_HSP_TX_PKT_RAMALLOC_3 0x0000040038
#define R_BCM1480_HSP_TX_PKT_RAMALLOC_4 0x0000040040
#define R_BCM1480_HSP_TX_PKT_RAMALLOC_5 0x0000040048
#define R_BCM1480_HSP_TX_PKT_RAMALLOC_6 0x0000040050
#define R_BCM1480_HSP_TX_PKT_RAMALLOC_7 0x0000040058
#define R_BCM1480_HSP_TX_PKT_RAMALLOC(idx) (R_BCM1480_HSP_TX_PKT_RAMALLOC_0 + 8*(idx))
#define R_BCM1480_HSP_TX_NPC_RAMALLOC 0x0000040078
#define R_BCM1480_HSP_TX_RSP_RAMALLOC 0x0000040080
#define R_BCM1480_HSP_TX_PC_RAMALLOC 0x0000040088
#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_0 0x0000040090
#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_1 0x0000040098
#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_2 0x00000400A0
#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 0x00000400B0
#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_1 0x00000400B8
#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_2 0x00000400C0
#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_3 0x00000400C8
#define R_BCM1480_HSP_TX_PKT_RXPHITCNT(idx) (R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 + 8*(idx))
#define R_BCM1480_HSP_TX_HTIO_RXPHITCNT 0x00000400D0
#define R_BCM1480_HSP_TX_HTCC_RXPHITCNT 0x00000400D8
#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 0x00000400E0
#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_1 0x00000400E8
#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_2 0x00000400F0
#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_3 0x00000400F8
#define R_BCM1480_HSP_TX_PKT_TXPHITCNT(idx) (R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 + 8*(idx))
#define R_BCM1480_HSP_TX_HTIO_TXPHITCNT 0x0000040100
#define R_BCM1480_HSP_TX_HTCC_TXPHITCNT 0x0000040108
#define R_BCM1480_HSP_TX_SPI4_CALENDAR_0 0x0000040200
#define R_BCM1480_HSP_TX_SPI4_CALENDAR_1 0x0000040208
#define R_BCM1480_HSP_TX_PLL_CNFG 0x0000040800
#define R_BCM1480_HSP_TX_CALIBRATION 0x0000040808
#define R_BCM1480_HSP_TX_TEST 0x0000040810
#define R_BCM1480_HSP_TX_VIS_CMDQ_0 0x0000040840
#define R_BCM1480_HSP_TX_VIS_CMDQ_1 0x0000040848
#define R_BCM1480_HSP_TX_VIS_CMDQ_2 0x0000040850
#define R_BCM1480_HSP_TX_RAM_READCTL 0x0000040860
#define R_BCM1480_HSP_TX_RAM_READWINDOW 0x0000040868
#define R_BCM1480_HSP_TX_RF_READCTL 0x0000040870
#define R_BCM1480_HSP_TX_RF_READWINDOW 0x0000040878
#define R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS 0x0000040880
#define R_BCM1480_HSP_TX_SPI4_PORT_INT_EN 0x0000040888
#define R_BCM1480_HSP_TX_NEXT_ADDR_BASE 0x000040400
#define R_BCM1480_HSP_TX_NEXT_ADDR_REGISTER(x) (R_BCM1480_HSP_TX_NEXT_ADDR_BASE+ 8*(x))
/* *********************************************************************
* Physical Address Map (Table 10 and Figure 7)
********************************************************************* */
#define A_BCM1480_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000)
#define A_BCM1480_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024))
#define A_BCM1480_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000)
#define A_BCM1480_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000)
#define A_BCM1480_PHYS_GENBUS _SB_MAKE64(0x0010090000)
#define A_BCM1480_PHYS_GENBUS_END _SB_MAKE64(0x0028000000)
#define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES _SB_MAKE64(0x0028000000)
#define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES _SB_MAKE64(0x0029000000)
#define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES _SB_MAKE64(0x002C000000)
#define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES _SB_MAKE64(0x002E000000)
#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES _SB_MAKE64(0x002F000000)
#define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES _SB_MAKE64(0x0030000000)
#define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES _SB_MAKE64(0x0040000000)
#define A_BCM1480_PHYS_HT_MEM_MATCH_BITS _SB_MAKE64(0x0060000000)
#define A_BCM1480_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000)
#define A_BCM1480_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000)
#define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS _SB_MAKE64(0x00A8000000)
#define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS _SB_MAKE64(0x00A9000000)
#define A_BCM1480_PHYS_PCI_IO_MATCH_BITS _SB_MAKE64(0x00AC000000)
#define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS _SB_MAKE64(0x00AE000000)
#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS _SB_MAKE64(0x00AF000000)
#define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS _SB_MAKE64(0x00B0000000)
#define A_BCM1480_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000)
#define A_BCM1480_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000)
#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000)
#define A_BCM1480_PHYS_HT_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000)
#define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000)
#define A_BCM1480_PHYS_HS_SUBSYS _SB_MAKE64(0x00DF000000)
#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000)
#define A_BCM1480_PHYS_HT_IO_MATCH_BITS _SB_MAKE64(0x00FC000000)
#define A_BCM1480_PHYS_HT_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000)
#define A_BCM1480_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000)
#define A_BCM1480_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024))
#define A_BCM1480_PHYS_PCI_UPPER _SB_MAKE64(0x1000000000)
#define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES _SB_MAKE64(0x2000000000)
#define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS _SB_MAKE64(0x3000000000)
#define A_BCM1480_PHYS_HT_NODE_ALIAS _SB_MAKE64(0x4000000000)
#define A_BCM1480_PHYS_HT_FULLACCESS _SB_MAKE64(0xF000000000)
/* *********************************************************************
* L2 Cache as RAM (Table 54)
********************************************************************* */
#define A_BCM1480_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000)
#define BCM1480_PHYS_L2CACHE_NUM_WAYS 8
#define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000100000)
#define A_BCM1480_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0300000)
#define A_BCM1480_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D0320000)
#define A_BCM1480_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D0340000)
#define A_BCM1480_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D0360000)
#define A_BCM1480_PHYS_L2CACHE_WAY4 _SB_MAKE64(0x00D0380000)
#define A_BCM1480_PHYS_L2CACHE_WAY5 _SB_MAKE64(0x00D03A0000)
#define A_BCM1480_PHYS_L2CACHE_WAY6 _SB_MAKE64(0x00D03C0000)
#define A_BCM1480_PHYS_L2CACHE_WAY7 _SB_MAKE64(0x00D03E0000)
#endif /* _BCM1480_REGS_H */

406
kernel/arch/mips/include/asm/sibyte/bcm1480_scd.h Normal file
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/* *********************************************************************
* BCM1280/BCM1400 Board Support Package
*
* SCD Constants and Macros File: bcm1480_scd.h
*
* This module contains constants and macros useful for
* manipulating the System Control and Debug module.
*
* BCM1400 specification level: 1X55_1X80-UM100-R (12/18/03)
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003,2004,2005
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _BCM1480_SCD_H
#define _BCM1480_SCD_H
#include "sb1250_defs.h"
/* *********************************************************************
* Pull in the BCM1250's SCD since lots of stuff is the same.
********************************************************************* */
#include "sb1250_scd.h"
/* *********************************************************************
* Some general notes:
*
* This file is basically a "what's new" header file. Since the
* BCM1250 and the new BCM1480 (and derivatives) share many common
* features, this file contains only what's new or changed from
* the 1250. (above, you can see that we include the 1250 symbols
* to get the base functionality).
*
* In software, be sure to use the correct symbols, particularly
* for blocks that are different between the two chip families.
* All BCM1480-specific symbols have _BCM1480_ in their names,
* and all BCM1250-specific and "base" functions that are common in
* both chips have no special names (this is for compatibility with
* older include files). Therefore, if you're working with the
* SCD, which is very different on each chip, A_SCD_xxx implies
* the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480
* version.
********************************************************************* */
/* *********************************************************************
* System control/debug registers
********************************************************************* */
/*
* System Identification and Revision Register (Table 12)
* Register: SCD_SYSTEM_REVISION
* This register is field compatible with the 1250.
*/
/*
* New part definitions
*/
#define K_SYS_PART_BCM1480 0x1406
#define K_SYS_PART_BCM1280 0x1206
#define K_SYS_PART_BCM1455 0x1407
#define K_SYS_PART_BCM1255 0x1257
#define K_SYS_PART_BCM1158 0x1156
/*
* Manufacturing Information Register (Table 14)
* Register: SCD_SYSTEM_MANUF
*/
/*
* System Configuration Register (Table 15)
* Register: SCD_SYSTEM_CFG
* Entire register is different from 1250, all new constants below
*/
#define M_BCM1480_SYS_RESERVED0 _SB_MAKEMASK1(0)
#define M_BCM1480_SYS_HT_MINRSTCNT _SB_MAKEMASK1(1)
#define M_BCM1480_SYS_RESERVED2 _SB_MAKEMASK1(2)
#define M_BCM1480_SYS_RESERVED3 _SB_MAKEMASK1(3)
#define M_BCM1480_SYS_RESERVED4 _SB_MAKEMASK1(4)
#define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5)
#define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6)
#define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV)
#define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV)
#define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV)
#define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11)
#define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV)
#define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV)
#define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV)
#define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16)
#define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17)
#define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18)
#define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE)
#define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE)
#define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE)
#define K_BCM1480_SYS_BOOT_MODE_ROM32 0
#define K_BCM1480_SYS_BOOT_MODE_ROM8 1
#define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2
#define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG 3
#define M_BCM1480_SYS_BOOT_MODE_SMBUS _SB_MAKEMASK1(19)
#define M_BCM1480_SYS_PCI_HOST _SB_MAKEMASK1(20)
#define M_BCM1480_SYS_PCI_ARBITER _SB_MAKEMASK1(21)
#define M_BCM1480_SYS_BIG_ENDIAN _SB_MAKEMASK1(22)
#define M_BCM1480_SYS_GENCLK_EN _SB_MAKEMASK1(23)
#define M_BCM1480_SYS_GEN_PARITY_EN _SB_MAKEMASK1(24)
#define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25)
#define S_BCM1480_SYS_CONFIG 26
#define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG)
#define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG)
#define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG)
#define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32, 15)
#define S_BCM1480_SYS_NODEID 47
#define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID)
#define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID)
#define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID)
#define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51)
#define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52)
#define M_BCM1480_SYS_CPU_RESET_1 _SB_MAKEMASK1(53)
#define M_BCM1480_SYS_CPU_RESET_2 _SB_MAKEMASK1(54)
#define M_BCM1480_SYS_CPU_RESET_3 _SB_MAKEMASK1(55)
#define S_BCM1480_SYS_DISABLECPU0 56
#define M_BCM1480_SYS_DISABLECPU0 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0)
#define S_BCM1480_SYS_DISABLECPU1 57
#define M_BCM1480_SYS_DISABLECPU1 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1)
#define S_BCM1480_SYS_DISABLECPU2 58
#define M_BCM1480_SYS_DISABLECPU2 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2)
#define S_BCM1480_SYS_DISABLECPU3 59
#define M_BCM1480_SYS_DISABLECPU3 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3)
#define M_BCM1480_SYS_SB_SOFTRES _SB_MAKEMASK1(60)
#define M_BCM1480_SYS_EXT_RESET _SB_MAKEMASK1(61)
#define M_BCM1480_SYS_SYSTEM_RESET _SB_MAKEMASK1(62)
#define M_BCM1480_SYS_SW_FLAG _SB_MAKEMASK1(63)
/*
* Scratch Register (Table 16)
* Register: SCD_SYSTEM_SCRATCH
* Same as BCM1250
*/
/*
* Mailbox Registers (Table 17)
* Registers: SCD_MBOX_{0,1}_CPU_x
* Same as BCM1250
*/
/*
* See bcm1480_int.h for interrupt mapper registers.
*/
/*
* Watchdog Timer Initial Count Registers (Table 23)
* Registers: SCD_WDOG_INIT_CNT_x
*
* The watchdogs are almost the same as the 1250, except
* the configuration register has more bits to control the
* other CPUs.
*/
/*
* Watchdog Timer Configuration Registers (Table 25)
* Registers: SCD_WDOG_CFG_x
*/
#define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0)
#define S_BCM1480_SCD_WDOG_RESET_TYPE 2
#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE)
#define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE)
#define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE)
#define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */
#define K_BCM1480_SCD_WDOG_RESET_SOFT 1
#define K_BCM1480_SCD_WDOG_RESET_CPU0 3
#define K_BCM1480_SCD_WDOG_RESET_CPU1 5
#define K_BCM1480_SCD_WDOG_RESET_CPU2 9
#define K_BCM1480_SCD_WDOG_RESET_CPU3 17
#define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS 31
#define M_BCM1480_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(8)
/*
* General Timer Initial Count Registers (Table 26)
* Registers: SCD_TIMER_INIT_x
*
* The timer registers are the same as the BCM1250
*/
/*
* ZBbus Count Register (Table 29)
* Register: ZBBUS_CYCLE_COUNT
*
* Same as BCM1250
*/
/*
* ZBbus Compare Registers (Table 30)
* Registers: ZBBUS_CYCLE_CPx
*
* Same as BCM1250
*/
/*
* System Performance Counter Configuration Register (Table 31)
* Register: PERF_CNT_CFG_0
*
* SPC_CFG_SRC[0-3] is the same as the 1250.
* SPC_CFG_SRC[4-7] only exist on the 1480
* The clear/enable bits are in different locations on the 1250 and 1480.
*/
#define S_SPC_CFG_SRC4 32
#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8, S_SPC_CFG_SRC4)
#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC4)
#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4)
#define S_SPC_CFG_SRC5 40
#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8, S_SPC_CFG_SRC5)
#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC5)
#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5)
#define S_SPC_CFG_SRC6 48
#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8, S_SPC_CFG_SRC6)
#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC6)
#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6)
#define S_SPC_CFG_SRC7 56
#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8, S_SPC_CFG_SRC7)
#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC7)
#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7)
/*
* System Performance Counter Control Register (Table 32)
* Register: PERF_CNT_CFG_1
* BCM1480 specific
*/
#define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0)
#define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1)
#if SIBYTE_HDR_FEATURE_CHIP(1480)
#define M_SPC_CFG_CLEAR M_BCM1480_SPC_CFG_CLEAR
#define M_SPC_CFG_ENABLE M_BCM1480_SPC_CFG_ENABLE
#endif
/*
* System Performance Counters (Table 33)
* Registers: PERF_CNT_x
*/
#define S_BCM1480_SPC_CNT_COUNT 0
#define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT)
#define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT)
#define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT)
#define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40)
/*
* Bus Watcher Error Status Register (Tables 36, 37)
* Registers: BUS_ERR_STATUS, BUS_ERR_STATUS_DEBUG
* Same as BCM1250.
*/
/*
* Bus Watcher Error Data Registers (Table 38)
* Registers: BUS_ERR_DATA_x
* Same as BCM1250.
*/
/*
* Bus Watcher L2 ECC Counter Register (Table 39)
* Register: BUS_L2_ERRORS
* Same as BCM1250.
*/
/*
* Bus Watcher Memory and I/O Error Counter Register (Table 40)
* Register: BUS_MEM_IO_ERRORS
* Same as BCM1250.
*/
/*
* Address Trap Registers
*
* Register layout same as BCM1250, almost. The bus agents
* are different, and the address trap configuration bits are
* slightly different.
*/
#define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4, 0)
#define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40, 0)
#define S_BCM1480_ATRAP_CFG_CNT 0
#define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT)
#define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT)
#define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT)
#define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3)
#define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4)
#define M_BCM1480_ATRAP_CFG_INV _SB_MAKEMASK1(5)
#define M_BCM1480_ATRAP_CFG_USESRC _SB_MAKEMASK1(6)
#define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7)
#define S_BCM1480_ATRAP_CFG_AGENTID 8
#define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID)
#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID)
#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID)
#define K_BCM1480_BUS_AGENT_CPU0 0
#define K_BCM1480_BUS_AGENT_CPU1 1
#define K_BCM1480_BUS_AGENT_NC 2
#define K_BCM1480_BUS_AGENT_IOB 3
#define K_BCM1480_BUS_AGENT_SCD 4
#define K_BCM1480_BUS_AGENT_L2C 6
#define K_BCM1480_BUS_AGENT_MC 7
#define K_BCM1480_BUS_AGENT_CPU2 8
#define K_BCM1480_BUS_AGENT_CPU3 9
#define K_BCM1480_BUS_AGENT_PM 10
#define S_BCM1480_ATRAP_CFG_CATTR 12
#define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR)
#define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR)
#define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR)
#define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0
#define K_BCM1480_ATRAP_CFG_CATTR_UNC 1
#define K_BCM1480_ATRAP_CFG_CATTR_NONCOH 2
#define K_BCM1480_ATRAP_CFG_CATTR_COHERENT 3
#define M_BCM1480_ATRAP_CFG_CATTRINV _SB_MAKEMASK1(14)
/*
* Trace Event Registers (Table 47)
* Same as BCM1250.
*/
/*
* Trace Sequence Control Registers (Table 48)
* Registers: TRACE_SEQUENCE_x
*
* Same as BCM1250 except for two new fields.
*/
#define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25)
#define S_BCM1480_SCD_TRSEQ_SWFUNC 26
#define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC)
#define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC)
#define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC)
/*
* Trace Control Register (Table 49)
* Register: TRACE_CFG
*
* BCM1480 changes to this register (other than location of the CUR_ADDR field)
* are defined below.
*/
#define S_BCM1480_SCD_TRACE_CFG_MODE 16
#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE)
#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE)
#define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE)
#define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0
#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1
#define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2
#endif /* _BCM1480_SCD_H */

48
kernel/arch/mips/include/asm/sibyte/bigsur.h Normal file
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/*
* Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef __ASM_SIBYTE_BIGSUR_H
#define __ASM_SIBYTE_BIGSUR_H
#include <asm/sibyte/sb1250.h>
#include <asm/sibyte/bcm1480_int.h>
#ifdef CONFIG_SIBYTE_BIGSUR
#define SIBYTE_BOARD_NAME "BCM91x80A/B (BigSur)"
#define SIBYTE_HAVE_PCMCIA 1
#define SIBYTE_HAVE_IDE 1
#endif
/* Generic bus chip selects */
#define LEDS_CS 3
#define LEDS_PHYS 0x100a0000
#ifdef SIBYTE_HAVE_IDE
#define IDE_CS 4
#define IDE_PHYS 0x100b0000
#define K_GPIO_GB_IDE 4
#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE)
#endif
#ifdef SIBYTE_HAVE_PCMCIA
#define PCMCIA_CS 6
#define PCMCIA_PHYS 0x11000000
#define K_GPIO_PC_READY 9
#define K_INT_PC_READY (K_INT_GPIO_0 + K_GPIO_PC_READY)
#endif
#endif /* __ASM_SIBYTE_BIGSUR_H */

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kernel/arch/mips/include/asm/sibyte/board.h Normal file
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/*
* Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _SIBYTE_BOARD_H
#define _SIBYTE_BOARD_H
#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_CRHONE) || \
defined(CONFIG_SIBYTE_CRHINE) || defined(CONFIG_SIBYTE_LITTLESUR)
#include <asm/sibyte/swarm.h>
#endif
#if defined(CONFIG_SIBYTE_SENTOSA) || defined(CONFIG_SIBYTE_RHONE)
#include <asm/sibyte/sentosa.h>
#endif
#ifdef CONFIG_SIBYTE_CARMEL
#include <asm/sibyte/carmel.h>
#endif
#ifdef CONFIG_SIBYTE_BIGSUR
#include <asm/sibyte/bigsur.h>
#endif
#ifdef __ASSEMBLY__
#ifdef LEDS_PHYS
#define setleds(t0, t1, c0, c1, c2, c3) \
li t0, (LEDS_PHYS|0xa0000000); \
li t1, c0; \
sb t1, 0x18(t0); \
li t1, c1; \
sb t1, 0x10(t0); \
li t1, c2; \
sb t1, 0x08(t0); \
li t1, c3; \
sb t1, 0x00(t0)
#else
#define setleds(t0, t1, c0, c1, c2, c3)
#endif /* LEDS_PHYS */
#else
void swarm_setup(void);
#ifdef LEDS_PHYS
extern void setleds(char *str);
#else
#define setleds(s) do { } while (0)
#endif /* LEDS_PHYS */
#endif /* __ASSEMBLY__ */
#endif /* _SIBYTE_BOARD_H */

58
kernel/arch/mips/include/asm/sibyte/carmel.h Normal file
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/*
* Copyright (C) 2002 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef __ASM_SIBYTE_CARMEL_H
#define __ASM_SIBYTE_CARMEL_H
#include <asm/sibyte/sb1250.h>
#include <asm/sibyte/sb1250_int.h>
#define SIBYTE_BOARD_NAME "Carmel"
#define GPIO_PHY_INTERRUPT 2
#define GPIO_NONMASKABLE_INT 3
#define GPIO_CF_INSERTED 6
#define GPIO_MONTEREY_RESET 7
#define GPIO_QUADUART_INT 8
#define GPIO_CF_INT 9
#define GPIO_FPGA_CCLK 10
#define GPIO_FPGA_DOUT 11
#define GPIO_FPGA_DIN 12
#define GPIO_FPGA_PGM 13
#define GPIO_FPGA_DONE 14
#define GPIO_FPGA_INIT 15
#define LEDS_CS 2
#define LEDS_PHYS 0x100C0000
#define MLEDS_CS 3
#define MLEDS_PHYS 0x100A0000
#define UART_CS 4
#define UART_PHYS 0x100D0000
#define ARAVALI_CS 5
#define ARAVALI_PHYS 0x11000000
#define IDE_CS 6
#define IDE_PHYS 0x100B0000
#define ARAVALI2_CS 7
#define ARAVALI2_PHYS 0x100E0000
#if defined(CONFIG_SIBYTE_CARMEL)
#define K_GPIO_GB_IDE 9
#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE)
#endif
#endif /* __ASM_SIBYTE_CARMEL_H */

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/*
* Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef _ASM_SIBYTE_SB1250_H
#define _ASM_SIBYTE_SB1250_H
/*
* yymmddpp: year, month, day, patch.
* should sync with Makefile EXTRAVERSION
*/
#define SIBYTE_RELEASE 0x02111403
#define SB1250_NR_IRQS 64
#define BCM1480_NR_IRQS 128
#define BCM1480_NR_IRQS_HALF 64
#define SB1250_DUART_MINOR_BASE 64
#ifndef __ASSEMBLY__
#include <asm/addrspace.h>
/* For revision/pass information */
#include <asm/sibyte/sb1250_scd.h>
#include <asm/sibyte/bcm1480_scd.h>
extern unsigned int sb1_pass;
extern unsigned int soc_pass;
extern unsigned int soc_type;
extern unsigned int periph_rev;
extern unsigned int zbbus_mhz;
extern void sb1250_time_init(void);
extern void sb1250_mask_irq(int cpu, int irq);
extern void sb1250_unmask_irq(int cpu, int irq);
extern void bcm1480_time_init(void);
extern void bcm1480_mask_irq(int cpu, int irq);
extern void bcm1480_unmask_irq(int cpu, int irq);
#define AT_spin \
__asm__ __volatile__ ( \
".set noat\n" \
"li $at, 0\n" \
"1: beqz $at, 1b\n" \
".set at\n" \
)
#endif
#define IOADDR(a) ((void __iomem *)(IO_BASE + (a)))
#endif

259
kernel/arch/mips/include/asm/sibyte/sb1250_defs.h Normal file
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/* *********************************************************************
* SB1250 Board Support Package
*
* Global constants and macros File: sb1250_defs.h
*
* This file contains macros and definitions used by the other
* include files.
*
* SB1250 specification level: User's manual 1/02/02
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_DEFS_H
#define _SB1250_DEFS_H
/*
* These headers require ANSI C89 string concatenation, and GCC or other
* 'long long' (64-bit integer) support.
*/
#if !defined(__STDC__) && !defined(_MSC_VER)
#error SiByte headers require ANSI C89 support
#endif
/* *********************************************************************
* Macros for feature tests, used to enable include file features
* for chip features only present in certain chip revisions.
*
* SIBYTE_HDR_FEATURES may be defined to be the mask value chip/revision
* which is to be exposed by the headers. If undefined, it defaults to
* "all features."
*
* Use like:
*
* #define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_112x_PASS1
*
* Generate defines only for that revision of chip.
*
* #if SIBYTE_HDR_FEATURE(chip,pass)
*
* True if header features for that revision or later of
* that particular chip type are enabled in SIBYTE_HDR_FEATURES.
* (Use this to bracket #defines for features present in a given
* revision and later.)
*
* Note that there is no implied ordering between chip types.
*
* Note also that 'chip' and 'pass' must textually exactly
* match the defines below. So, for example,
* SIBYTE_HDR_FEATURE(112x, PASS1) is OK, but
* SIBYTE_HDR_FEATURE(1120, pass1) is not (for two reasons).
*
* #if SIBYTE_HDR_FEATURE_UP_TO(chip,pass)
*
* Same as SIBYTE_HDR_FEATURE, but true for the named revision
* and earlier revisions of the named chip type.
*
* #if SIBYTE_HDR_FEATURE_EXACT(chip,pass)
*
* Same as SIBYTE_HDR_FEATURE, but only true for the named
* revision of the named chip type. (Note that this CANNOT
* be used to verify that you're compiling only for that
* particular chip/revision. It will be true any time this
* chip/revision is included in SIBYTE_HDR_FEATURES.)
*
* #if SIBYTE_HDR_FEATURE_CHIP(chip)
*
* True if header features for (any revision of) that chip type
* are enabled in SIBYTE_HDR_FEATURES. (Use this to bracket
* #defines for features specific to a given chip type.)
*
* Mask values currently include room for additional revisions of each
* chip type, but can be renumbered at will. Note that they MUST fit
* into 31 bits and may not include C type constructs, for safe use in
* CPP conditionals. Bit positions within chip types DO indicate
* ordering, so be careful when adding support for new minor revs.
********************************************************************* */
#define SIBYTE_HDR_FMASK_1250_ALL 0x000000ff
#define SIBYTE_HDR_FMASK_1250_PASS1 0x00000001
#define SIBYTE_HDR_FMASK_1250_PASS2 0x00000002
#define SIBYTE_HDR_FMASK_1250_PASS3 0x00000004
#define SIBYTE_HDR_FMASK_112x_ALL 0x00000f00
#define SIBYTE_HDR_FMASK_112x_PASS1 0x00000100
#define SIBYTE_HDR_FMASK_1480_ALL 0x0000f000
#define SIBYTE_HDR_FMASK_1480_PASS1 0x00001000
#define SIBYTE_HDR_FMASK_1480_PASS2 0x00002000
/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */
#define SIBYTE_HDR_FMASK(chip, pass) \
(SIBYTE_HDR_FMASK_ ## chip ## _ ## pass)
#define SIBYTE_HDR_FMASK_ALLREVS(chip) \
(SIBYTE_HDR_FMASK_ ## chip ## _ALL)
/* Default constant value for all chips, all revisions */
#define SIBYTE_HDR_FMASK_ALL \
(SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL \
| SIBYTE_HDR_FMASK_1480_ALL)
/* This one is used for the "original" BCM1250/BCM112x chips. We use this
to weed out constants and macros that do not exist on later chips like
the BCM1480 */
#define SIBYTE_HDR_FMASK_1250_112x_ALL \
(SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL)
#define SIBYTE_HDR_FMASK_1250_112x SIBYTE_HDR_FMASK_1250_112x_ALL
#ifndef SIBYTE_HDR_FEATURES
#define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_ALL
#endif
/* Bit mask for revisions of chip exclusively before the named revision. */
#define SIBYTE_HDR_FMASK_BEFORE(chip, pass) \
((SIBYTE_HDR_FMASK(chip, pass) - 1) & SIBYTE_HDR_FMASK_ALLREVS(chip))
/* Bit mask for revisions of chip exclusively after the named revision. */
#define SIBYTE_HDR_FMASK_AFTER(chip, pass) \
(~(SIBYTE_HDR_FMASK(chip, pass) \
| (SIBYTE_HDR_FMASK(chip, pass) - 1)) & SIBYTE_HDR_FMASK_ALLREVS(chip))
/* True if header features enabled for (any revision of) that chip type. */
#define SIBYTE_HDR_FEATURE_CHIP(chip) \
(!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES))
/* True for all versions of the BCM1250 and BCM1125, but not true for
anything else */
#define SIBYTE_HDR_FEATURE_1250_112x \
(SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x))
/* (!! (SIBYTE_HDR_FEATURES & SIBYHTE_HDR_FMASK_1250_112x)) */
/* True if header features enabled for that rev or later, inclusive. */
#define SIBYTE_HDR_FEATURE(chip, pass) \
(!! ((SIBYTE_HDR_FMASK(chip, pass) \
| SIBYTE_HDR_FMASK_AFTER(chip, pass)) & SIBYTE_HDR_FEATURES))
/* True if header features enabled for exactly that rev. */
#define SIBYTE_HDR_FEATURE_EXACT(chip, pass) \
(!! (SIBYTE_HDR_FMASK(chip, pass) & SIBYTE_HDR_FEATURES))
/* True if header features enabled for that rev or before, inclusive. */
#define SIBYTE_HDR_FEATURE_UP_TO(chip, pass) \
(!! ((SIBYTE_HDR_FMASK(chip, pass) \
| SIBYTE_HDR_FMASK_BEFORE(chip, pass)) & SIBYTE_HDR_FEATURES))
/* *********************************************************************
* Naming schemes for constants in these files:
*
* M_xxx MASK constant (identifies bits in a register).
* For multi-bit fields, all bits in the field will
* be set.
*
* K_xxx "Code" constant (value for data in a multi-bit
* field). The value is right justified.
*
* V_xxx "Value" constant. This is the same as the
* corresponding "K_xxx" constant, except it is
* shifted to the correct position in the register.
*
* S_xxx SHIFT constant. This is the number of bits that
* a field value (code) needs to be shifted
* (towards the left) to put the value in the right
* position for the register.
*
* A_xxx ADDRESS constant. This will be a physical
* address. Use the PHYS_TO_K1 macro to generate
* a K1SEG address.
*
* R_xxx RELATIVE offset constant. This is an offset from
* an A_xxx constant (usually the first register in
* a group).
*
* G_xxx(X) GET value. This macro obtains a multi-bit field
* from a register, masks it, and shifts it to
* the bottom of the register (retrieving a K_xxx
* value, for example).
*
* V_xxx(X) VALUE. This macro computes the value of a
* K_xxx constant shifted to the correct position
* in the register.
********************************************************************* */
/*
* Cast to 64-bit number. Presumably the syntax is different in
* assembly language.
*
* Note: you'll need to define uint32_t and uint64_t in your headers.
*/
#if !defined(__ASSEMBLY__)
#define _SB_MAKE64(x) ((uint64_t)(x))
#define _SB_MAKE32(x) ((uint32_t)(x))
#else
#define _SB_MAKE64(x) (x)
#define _SB_MAKE32(x) (x)
#endif
/*
* Make a mask for 1 bit at position 'n'
*/
#define _SB_MAKEMASK1(n) (_SB_MAKE64(1) << _SB_MAKE64(n))
#define _SB_MAKEMASK1_32(n) (_SB_MAKE32(1) << _SB_MAKE32(n))
/*
* Make a mask for 'v' bits at position 'n'
*/
#define _SB_MAKEMASK(v, n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n))
#define _SB_MAKEMASK_32(v, n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n))
/*
* Make a value at 'v' at bit position 'n'
*/
#define _SB_MAKEVALUE(v, n) (_SB_MAKE64(v) << _SB_MAKE64(n))
#define _SB_MAKEVALUE_32(v, n) (_SB_MAKE32(v) << _SB_MAKE32(n))
#define _SB_GETVALUE(v, n, m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n))
#define _SB_GETVALUE_32(v, n, m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n))
/*
* Macros to read/write on-chip registers
* XXX should we do the PHYS_TO_K1 here?
*/
#if defined(__mips64) && !defined(__ASSEMBLY__)
#define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
#endif /* __ASSEMBLY__ */
#endif

594
kernel/arch/mips/include/asm/sibyte/sb1250_dma.h Normal file
View File

@@ -0,0 +1,594 @@
/* *********************************************************************
* SB1250 Board Support Package
*
* DMA definitions File: sb1250_dma.h
*
* This module contains constants and macros useful for
* programming the SB1250's DMA controllers, both the data mover
* and the Ethernet DMA.
*
* SB1250 specification level: User's manual 10/21/02
* BCM1280 specification level: User's manual 11/24/03
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_DMA_H
#define _SB1250_DMA_H
#include "sb1250_defs.h"
/* *********************************************************************
* DMA Registers
********************************************************************* */
/*
* Ethernet and Serial DMA Configuration Register 0 (Table 7-4)
* Registers: DMA_CONFIG0_MAC_x_RX_CH_0
* Registers: DMA_CONFIG0_MAC_x_TX_CH_0
* Registers: DMA_CONFIG0_SER_x_RX
* Registers: DMA_CONFIG0_SER_x_TX
*/
#define M_DMA_DROP _SB_MAKEMASK1(0)
#define M_DMA_CHAIN_SEL _SB_MAKEMASK1(1)
#define M_DMA_RESERVED1 _SB_MAKEMASK1(2)
#define S_DMA_DESC_TYPE _SB_MAKE64(1)
#define M_DMA_DESC_TYPE _SB_MAKEMASK(2, S_DMA_DESC_TYPE)
#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x, S_DMA_DESC_TYPE)
#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x, S_DMA_DESC_TYPE, M_DMA_DESC_TYPE)
#define K_DMA_DESC_TYPE_RING_AL 0
#define K_DMA_DESC_TYPE_CHAIN_AL 1
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define K_DMA_DESC_TYPE_RING_UAL_WI 2
#define K_DMA_DESC_TYPE_RING_UAL_RMW 3
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
#define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3)
#define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4)
#define M_DMA_LWM_INT_EN _SB_MAKEMASK1(5)
#define M_DMA_TBX_EN _SB_MAKEMASK1(6)
#define M_DMA_TDX_EN _SB_MAKEMASK1(7)
#define S_DMA_INT_PKTCNT _SB_MAKE64(8)
#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8, S_DMA_INT_PKTCNT)
#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x, S_DMA_INT_PKTCNT)
#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x, S_DMA_INT_PKTCNT, M_DMA_INT_PKTCNT)
#define S_DMA_RINGSZ _SB_MAKE64(16)
#define M_DMA_RINGSZ _SB_MAKEMASK(16, S_DMA_RINGSZ)
#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x, S_DMA_RINGSZ)
#define G_DMA_RINGSZ(x) _SB_GETVALUE(x, S_DMA_RINGSZ, M_DMA_RINGSZ)
#define S_DMA_HIGH_WATERMARK _SB_MAKE64(32)
#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16, S_DMA_HIGH_WATERMARK)
#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x, S_DMA_HIGH_WATERMARK)
#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x, S_DMA_HIGH_WATERMARK, M_DMA_HIGH_WATERMARK)
#define S_DMA_LOW_WATERMARK _SB_MAKE64(48)
#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16, S_DMA_LOW_WATERMARK)
#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x, S_DMA_LOW_WATERMARK)
#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x, S_DMA_LOW_WATERMARK, M_DMA_LOW_WATERMARK)
/*
* Ethernet and Serial DMA Configuration Register 1 (Table 7-5)
* Registers: DMA_CONFIG1_MAC_x_RX_CH_0
* Registers: DMA_CONFIG1_DMA_x_TX_CH_0
* Registers: DMA_CONFIG1_SER_x_RX
* Registers: DMA_CONFIG1_SER_x_TX
*/
#define M_DMA_HDR_CF_EN _SB_MAKEMASK1(0)
#define M_DMA_ASIC_XFR_EN _SB_MAKEMASK1(1)
#define M_DMA_PRE_ADDR_EN _SB_MAKEMASK1(2)
#define M_DMA_FLOW_CTL_EN _SB_MAKEMASK1(3)
#define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4)
#define M_DMA_L2CA _SB_MAKEMASK1(5)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6)
#define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6)
#define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7)
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
#define M_DMA_MBZ1 _SB_MAKEMASK(6, 15)
#define S_DMA_HDR_SIZE _SB_MAKE64(21)
#define M_DMA_HDR_SIZE _SB_MAKEMASK(9, S_DMA_HDR_SIZE)
#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x, S_DMA_HDR_SIZE)
#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x, S_DMA_HDR_SIZE, M_DMA_HDR_SIZE)
#define M_DMA_MBZ2 _SB_MAKEMASK(5, 32)
#define S_DMA_ASICXFR_SIZE _SB_MAKE64(37)
#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9, S_DMA_ASICXFR_SIZE)
#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x, S_DMA_ASICXFR_SIZE)
#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x, S_DMA_ASICXFR_SIZE, M_DMA_ASICXFR_SIZE)
#define S_DMA_INT_TIMEOUT _SB_MAKE64(48)
#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16, S_DMA_INT_TIMEOUT)
#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x, S_DMA_INT_TIMEOUT)
#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x, S_DMA_INT_TIMEOUT, M_DMA_INT_TIMEOUT)
/*
* Ethernet and Serial DMA Descriptor base address (Table 7-6)
*/
#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4, 0)
/*
* ASIC Mode Base Address (Table 7-7)
*/
#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20, 0)
/*
* DMA Descriptor Count Registers (Table 7-8)
*/
/* No bitfields */
/*
* Current Descriptor Address Register (Table 7-11)
*/
#define S_DMA_CURDSCR_ADDR _SB_MAKE64(0)
#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40, S_DMA_CURDSCR_ADDR)
#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40)
#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16, S_DMA_CURDSCR_COUNT)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56)
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
/*
* Receive Packet Drop Registers
*/
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define S_DMA_OODLOST_RX _SB_MAKE64(0)
#define M_DMA_OODLOST_RX _SB_MAKEMASK(16, S_DMA_OODLOST_RX)
#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x, S_DMA_OODLOST_RX, M_DMA_OODLOST_RX)
#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16)
#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8, S_DMA_EOP_COUNT_RX)
#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x, S_DMA_EOP_COUNT_RX, M_DMA_EOP_COUNT_RX)
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
/* *********************************************************************
* DMA Descriptors
********************************************************************* */
/*
* Descriptor doubleword "A" (Table 7-12)
*/
#define S_DMA_DSCRA_OFFSET _SB_MAKE64(0)
#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5, S_DMA_DSCRA_OFFSET)
#define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_OFFSET)
#define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x, S_DMA_DSCRA_OFFSET, M_DMA_DSCRA_OFFSET)
/* Note: Don't shift the address over, just mask it with the mask below */
#define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5)
#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35, S_DMA_DSCRA_A_ADDR)
#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0)
#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40, S_DMA_DSCRA_A_ADDR_UA)
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40)
#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9, S_DMA_DSCRA_A_SIZE)
#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_A_SIZE)
#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRA_A_SIZE, M_DMA_DSCRA_A_SIZE)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40)
#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8, S_DMA_DSCRA_DSCR_CNT)
#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x, S_DMA_DSCRA_DSCR_CNT, M_DMA_DSCRA_DSCR_CNT)
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49)
#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50)
#define S_DMA_DSCRA_STATUS _SB_MAKE64(51)
#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13, S_DMA_DSCRA_STATUS)
#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x, S_DMA_DSCRA_STATUS)
#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x, S_DMA_DSCRA_STATUS, M_DMA_DSCRA_STATUS)
/*
* Descriptor doubleword "B" (Table 7-13)
*/
#define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0)
#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4, S_DMA_DSCRB_OPTIONS)
#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_OPTIONS)
#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x, S_DMA_DSCRB_OPTIONS, M_DMA_DSCRB_OPTIONS)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8)
#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14, S_DMA_DSCRB_A_SIZE)
#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_A_SIZE)
#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_A_SIZE, M_DMA_DSCRB_A_SIZE)
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10)
/* Note: Don't shift the address over, just mask it with the mask below */
#define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5)
#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35, S_DMA_DSCRB_B_ADDR)
#define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40)
#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9, S_DMA_DSCRB_B_SIZE)
#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_B_SIZE)
#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_B_SIZE, M_DMA_DSCRB_B_SIZE)
#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48)
#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2, S_DMA_DSCRB_PKT_SIZE_MSB)
#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB)
#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB, M_DMA_DSCRB_PKT_SIZE_MSB)
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50)
#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14, S_DMA_DSCRB_PKT_SIZE)
#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE)
#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE, M_DMA_DSCRB_PKT_SIZE)
/*
* from pass2 some bits in dscr_b are also used for rx status
*/
#define S_DMA_DSCRB_STATUS _SB_MAKE64(0)
#define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1, S_DMA_DSCRB_STATUS)
#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_STATUS)
#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x, S_DMA_DSCRB_STATUS, M_DMA_DSCRB_STATUS)
/*
* Ethernet Descriptor Status Bits (Table 7-15)
*/
#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51)
#define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
/* Note: This bit is in the DSCR_B options field */
#define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0)
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
/* Note: These bits are in the DSCR_B options field */
#define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1)
#define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2)
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
#define S_DMA_ETHRX_RXCH 53
#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2, S_DMA_ETHRX_RXCH)
#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x, S_DMA_ETHRX_RXCH)
#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x, S_DMA_ETHRX_RXCH, M_DMA_ETHRX_RXCH)
#define S_DMA_ETHRX_PKTTYPE 55
#define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3, S_DMA_ETHRX_PKTTYPE)
#define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x, S_DMA_ETHRX_PKTTYPE)
#define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x, S_DMA_ETHRX_PKTTYPE, M_DMA_ETHRX_PKTTYPE)
#define K_DMA_ETHRX_PKTTYPE_IPV4 0
#define K_DMA_ETHRX_PKTTYPE_ARPV4 1
#define K_DMA_ETHRX_PKTTYPE_802 2
#define K_DMA_ETHRX_PKTTYPE_OTHER 3
#define K_DMA_ETHRX_PKTTYPE_USER0 4
#define K_DMA_ETHRX_PKTTYPE_USER1 5
#define K_DMA_ETHRX_PKTTYPE_USER2 6
#define K_DMA_ETHRX_PKTTYPE_USER3 7
#define M_DMA_ETHRX_MATCH_HASH _SB_MAKEMASK1(58)
#define M_DMA_ETHRX_MATCH_EXACT _SB_MAKEMASK1(59)
#define M_DMA_ETHRX_BCAST _SB_MAKEMASK1(60)
#define M_DMA_ETHRX_MCAST _SB_MAKEMASK1(61)
#define M_DMA_ETHRX_BAD _SB_MAKEMASK1(62)
#define M_DMA_ETHRX_SOP _SB_MAKEMASK1(63)
/*
* Ethernet Transmit Status Bits (Table 7-16)
*/
#define M_DMA_ETHTX_SOP _SB_MAKEMASK1(63)
/*
* Ethernet Transmit Options (Table 7-17)
*/
#define K_DMA_ETHTX_NOTSOP _SB_MAKE64(0x00)
#define K_DMA_ETHTX_APPENDCRC _SB_MAKE64(0x01)
#define K_DMA_ETHTX_REPLACECRC _SB_MAKE64(0x02)
#define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03)
#define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04)
#define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05)
#define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6)
#define K_DMA_ETHTX_NOMODS _SB_MAKE64(0x07)
#define K_DMA_ETHTX_RESERVED1 _SB_MAKE64(0x08)
#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09)
#define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A)
#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B)
#define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C)
#define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D)
#define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E)
#define K_DMA_ETHTX_RESERVED2 _SB_MAKE64(0x0F)
/*
* Serial Receive Options (Table 7-18)
*/
#define M_DMA_SERRX_CRC_ERROR _SB_MAKEMASK1(56)
#define M_DMA_SERRX_ABORT _SB_MAKEMASK1(57)
#define M_DMA_SERRX_OCTET_ERROR _SB_MAKEMASK1(58)
#define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59)
#define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60)
#define M_DMA_SERRX_OVERRUN_ERROR _SB_MAKEMASK1(61)
#define M_DMA_SERRX_GOOD _SB_MAKEMASK1(62)
#define M_DMA_SERRX_SOP _SB_MAKEMASK1(63)
/*
* Serial Transmit Status Bits (Table 7-20)
*/
#define M_DMA_SERTX_FLAG _SB_MAKEMASK1(63)
/*
* Serial Transmit Options (Table 7-21)
*/
#define K_DMA_SERTX_RESERVED _SB_MAKEMASK1(0)
#define K_DMA_SERTX_APPENDCRC _SB_MAKEMASK1(1)
#define K_DMA_SERTX_APPENDPAD _SB_MAKEMASK1(2)
#define K_DMA_SERTX_ABORT _SB_MAKEMASK1(3)
/* *********************************************************************
* Data Mover Registers
********************************************************************* */
/*
* Data Mover Descriptor Base Address Register (Table 7-22)
* Register: DM_DSCR_BASE_0
* Register: DM_DSCR_BASE_1
* Register: DM_DSCR_BASE_2
* Register: DM_DSCR_BASE_3
*/
#define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(4, 0)
/* Note: Just mask the base address and then OR it in. */
#define S_DM_DSCR_BASE_ADDR _SB_MAKE64(4)
#define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36, S_DM_DSCR_BASE_ADDR)
#define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40)
#define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16, S_DM_DSCR_BASE_RINGSZ)
#define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x, S_DM_DSCR_BASE_RINGSZ)
#define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x, S_DM_DSCR_BASE_RINGSZ, M_DM_DSCR_BASE_RINGSZ)
#define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56)
#define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3, S_DM_DSCR_BASE_PRIORITY)
#define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x, S_DM_DSCR_BASE_PRIORITY)
#define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x, S_DM_DSCR_BASE_PRIORITY, M_DM_DSCR_BASE_PRIORITY)
#define K_DM_DSCR_BASE_PRIORITY_1 0
#define K_DM_DSCR_BASE_PRIORITY_2 1
#define K_DM_DSCR_BASE_PRIORITY_4 2
#define K_DM_DSCR_BASE_PRIORITY_8 3
#define K_DM_DSCR_BASE_PRIORITY_16 4
#define M_DM_DSCR_BASE_ACTIVE _SB_MAKEMASK1(59)
#define M_DM_DSCR_BASE_INTERRUPT _SB_MAKEMASK1(60)
#define M_DM_DSCR_BASE_RESET _SB_MAKEMASK1(61) /* write register */
#define M_DM_DSCR_BASE_ERROR _SB_MAKEMASK1(61) /* read register */
#define M_DM_DSCR_BASE_ABORT _SB_MAKEMASK1(62)
#define M_DM_DSCR_BASE_ENABL _SB_MAKEMASK1(63)
/*
* Data Mover Descriptor Count Register (Table 7-25)
*/
/* no bitfields */
/*
* Data Mover Current Descriptor Address (Table 7-24)
* Register: DM_CUR_DSCR_ADDR_0
* Register: DM_CUR_DSCR_ADDR_1
* Register: DM_CUR_DSCR_ADDR_2
* Register: DM_CUR_DSCR_ADDR_3
*/
#define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0)
#define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40, S_DM_CUR_DSCR_DSCR_ADDR)
#define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48)
#define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16, S_DM_CUR_DSCR_DSCR_COUNT)
#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT)
#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT,\
M_DM_CUR_DSCR_DSCR_COUNT)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
/*
* Data Mover Channel Partial Result Registers
* Register: DM_PARTIAL_0
* Register: DM_PARTIAL_1
* Register: DM_PARTIAL_2
* Register: DM_PARTIAL_3
*/
#define S_DM_PARTIAL_CRC_PARTIAL _SB_MAKE64(0)
#define M_DM_PARTIAL_CRC_PARTIAL _SB_MAKEMASK(32, S_DM_PARTIAL_CRC_PARTIAL)
#define V_DM_PARTIAL_CRC_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_CRC_PARTIAL)
#define G_DM_PARTIAL_CRC_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_CRC_PARTIAL,\
M_DM_PARTIAL_CRC_PARTIAL)
#define S_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKE64(32)
#define M_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKEMASK(16, S_DM_PARTIAL_TCPCS_PARTIAL)
#define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL)
#define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL,\
M_DM_PARTIAL_TCPCS_PARTIAL)
#define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48)
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
/*
* Data Mover CRC Definition Registers
* Register: CRC_DEF_0
* Register: CRC_DEF_1
*/
#define S_CRC_DEF_CRC_INIT _SB_MAKE64(0)
#define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32, S_CRC_DEF_CRC_INIT)
#define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r, S_CRC_DEF_CRC_INIT)
#define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r, S_CRC_DEF_CRC_INIT,\
M_CRC_DEF_CRC_INIT)
#define S_CRC_DEF_CRC_POLY _SB_MAKE64(32)
#define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32, S_CRC_DEF_CRC_POLY)
#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r, S_CRC_DEF_CRC_POLY)
#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r, S_CRC_DEF_CRC_POLY,\
M_CRC_DEF_CRC_POLY)
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
/*
* Data Mover CRC/Checksum Definition Registers
* Register: CTCP_DEF_0
* Register: CTCP_DEF_1
*/
#define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0)
#define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32, S_CTCP_DEF_CRC_TXOR)
#define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_TXOR)
#define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r, S_CTCP_DEF_CRC_TXOR,\
M_CTCP_DEF_CRC_TXOR)
#define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32)
#define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16, S_CTCP_DEF_TCPCS_INIT)
#define V_CTCP_DEF_TCPCS_INIT(r) _SB_MAKEVALUE(r, S_CTCP_DEF_TCPCS_INIT)
#define G_CTCP_DEF_TCPCS_INIT(r) _SB_GETVALUE(r, S_CTCP_DEF_TCPCS_INIT,\
M_CTCP_DEF_TCPCS_INIT)
#define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48)
#define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2, S_CTCP_DEF_CRC_WIDTH)
#define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_WIDTH)
#define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r, S_CTCP_DEF_CRC_WIDTH,\
M_CTCP_DEF_CRC_WIDTH)
#define K_CTCP_DEF_CRC_WIDTH_4 0
#define K_CTCP_DEF_CRC_WIDTH_2 1
#define K_CTCP_DEF_CRC_WIDTH_1 2
#define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50)
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
/*
* Data Mover Descriptor Doubleword "A" (Table 7-26)
*/
#define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0)
#define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40, S_DM_DSCRA_DST_ADDR)
#define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40)
#define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41)
#define M_DM_DSCRA_INTERRUPT _SB_MAKEMASK1(42)
#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
#define M_DM_DSCRA_THROTTLE _SB_MAKEMASK1(43)
#endif /* up to 1250 PASS1 */
#define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44)
#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2, S_DM_DSCRA_DIR_DEST)
#define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_DEST)
#define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x, S_DM_DSCRA_DIR_DEST, M_DM_DSCRA_DIR_DEST)
#define K_DM_DSCRA_DIR_DEST_INCR 0
#define K_DM_DSCRA_DIR_DEST_DECR 1
#define K_DM_DSCRA_DIR_DEST_CONST 2
#define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR, S_DM_DSCRA_DIR_DEST)
#define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR, S_DM_DSCRA_DIR_DEST)
#define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST, S_DM_DSCRA_DIR_DEST)
#define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46)
#define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2, S_DM_DSCRA_DIR_SRC)
#define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_SRC)
#define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x, S_DM_DSCRA_DIR_SRC, M_DM_DSCRA_DIR_SRC)
#define K_DM_DSCRA_DIR_SRC_INCR 0
#define K_DM_DSCRA_DIR_SRC_DECR 1
#define K_DM_DSCRA_DIR_SRC_CONST 2
#define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR, S_DM_DSCRA_DIR_SRC)
#define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR, S_DM_DSCRA_DIR_SRC)
#define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST, S_DM_DSCRA_DIR_SRC)
#define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48)
#define M_DM_DSCRA_PREFETCH _SB_MAKEMASK1(49)
#define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50)
#define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52)
#define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53)
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54)
#define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55)
#define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56)
#define M_DM_DSCRA_CRC_EN _SB_MAKEMASK1(57)
#define M_DM_DSCRA_CRC_RES _SB_MAKEMASK1(58)
#define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59)
#define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60)
#define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61)
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3, 61)
/*
* Data Mover Descriptor Doubleword "B" (Table 7-25)
*/
#define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0)
#define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40, S_DM_DSCRB_SRC_ADDR)
#define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40)
#define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20, S_DM_DSCRB_SRC_LENGTH)
#define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x, S_DM_DSCRB_SRC_LENGTH)
#define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x, S_DM_DSCRB_SRC_LENGTH, M_DM_DSCRB_SRC_LENGTH)
#endif

474
kernel/arch/mips/include/asm/sibyte/sb1250_genbus.h Normal file
View File

@@ -0,0 +1,474 @@
/* *********************************************************************
* SB1250 Board Support Package
*
* Generic Bus Constants File: sb1250_genbus.h
*
* This module contains constants and macros useful for
* manipulating the SB1250's Generic Bus interface
*
* SB1250 specification level: User's manual 10/21/02
* BCM1280 specification level: User's Manual 11/14/03
*
*********************************************************************
*
* Copyright 2000, 2001, 2002, 2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_GENBUS_H
#define _SB1250_GENBUS_H
#include "sb1250_defs.h"
/*
* Generic Bus Region Configuration Registers (Table 11-4)
*/
#define S_IO_RDY_ACTIVE 0
#define M_IO_RDY_ACTIVE _SB_MAKEMASK1(S_IO_RDY_ACTIVE)
#define S_IO_ENA_RDY 1
#define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY)
#define S_IO_WIDTH_SEL 2
#define M_IO_WIDTH_SEL _SB_MAKEMASK(2, S_IO_WIDTH_SEL)
#define K_IO_WIDTH_SEL_1 0
#define K_IO_WIDTH_SEL_2 1
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
|| SIBYTE_HDR_FEATURE_CHIP(1480)
#define K_IO_WIDTH_SEL_1L 2
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
#define K_IO_WIDTH_SEL_4 3
#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x, S_IO_WIDTH_SEL)
#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x, S_IO_WIDTH_SEL, M_IO_WIDTH_SEL)
#define S_IO_PARITY_ENA 4
#define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
|| SIBYTE_HDR_FEATURE_CHIP(1480)
#define S_IO_BURST_EN 5
#define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN)
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
#define S_IO_PARITY_ODD 6
#define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD)
#define S_IO_NONMUX 7
#define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX)
#define S_IO_TIMEOUT 8
#define M_IO_TIMEOUT _SB_MAKEMASK(8, S_IO_TIMEOUT)
#define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x, S_IO_TIMEOUT)
#define G_IO_TIMEOUT(x) _SB_GETVALUE(x, S_IO_TIMEOUT, M_IO_TIMEOUT)
/*
* Generic Bus Region Size register (Table 11-5)
*/
#define S_IO_MULT_SIZE 0
#define M_IO_MULT_SIZE _SB_MAKEMASK(12, S_IO_MULT_SIZE)
#define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x, S_IO_MULT_SIZE)
#define G_IO_MULT_SIZE(x) _SB_GETVALUE(x, S_IO_MULT_SIZE, M_IO_MULT_SIZE)
#define S_IO_REGSIZE 16 /* # bits to shift size for this reg */
/*
* Generic Bus Region Address (Table 11-6)
*/
#define S_IO_START_ADDR 0
#define M_IO_START_ADDR _SB_MAKEMASK(14, S_IO_START_ADDR)
#define V_IO_START_ADDR(x) _SB_MAKEVALUE(x, S_IO_START_ADDR)
#define G_IO_START_ADDR(x) _SB_GETVALUE(x, S_IO_START_ADDR, M_IO_START_ADDR)
#define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */
#define M_IO_BLK_CACHE _SB_MAKEMASK1(15)
/*
* Generic Bus Timing 0 Registers (Table 11-7)
*/
#define S_IO_ALE_WIDTH 0
#define M_IO_ALE_WIDTH _SB_MAKEMASK(3, S_IO_ALE_WIDTH)
#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_ALE_WIDTH)
#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x, S_IO_ALE_WIDTH, M_IO_ALE_WIDTH)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
|| SIBYTE_HDR_FEATURE_CHIP(1480)
#define M_IO_EARLY_CS _SB_MAKEMASK1(3)
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
#define S_IO_ALE_TO_CS 4
#define M_IO_ALE_TO_CS _SB_MAKEMASK(2, S_IO_ALE_TO_CS)
#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_CS)
#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x, S_IO_ALE_TO_CS, M_IO_ALE_TO_CS)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
|| SIBYTE_HDR_FEATURE_CHIP(1480)
#define S_IO_BURST_WIDTH _SB_MAKE64(6)
#define M_IO_BURST_WIDTH _SB_MAKEMASK(2, S_IO_BURST_WIDTH)
#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x, S_IO_BURST_WIDTH)
#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x, S_IO_BURST_WIDTH, M_IO_BURST_WIDTH)
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
#define S_IO_CS_WIDTH 8
#define M_IO_CS_WIDTH _SB_MAKEMASK(5, S_IO_CS_WIDTH)
#define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x, S_IO_CS_WIDTH)
#define G_IO_CS_WIDTH(x) _SB_GETVALUE(x, S_IO_CS_WIDTH, M_IO_CS_WIDTH)
#define S_IO_RDY_SMPLE 13
#define M_IO_RDY_SMPLE _SB_MAKEMASK(3, S_IO_RDY_SMPLE)
#define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x, S_IO_RDY_SMPLE)
#define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x, S_IO_RDY_SMPLE, M_IO_RDY_SMPLE)
/*
* Generic Bus Timing 1 Registers (Table 11-8)
*/
#define S_IO_ALE_TO_WRITE 0
#define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3, S_IO_ALE_TO_WRITE)
#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x, S_IO_ALE_TO_WRITE)
#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x, S_IO_ALE_TO_WRITE, M_IO_ALE_TO_WRITE)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
|| SIBYTE_HDR_FEATURE_CHIP(1480)
#define M_IO_RDY_SYNC _SB_MAKEMASK1(3)
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
#define S_IO_WRITE_WIDTH 4
#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4, S_IO_WRITE_WIDTH)
#define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x, S_IO_WRITE_WIDTH)
#define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x, S_IO_WRITE_WIDTH, M_IO_WRITE_WIDTH)
#define S_IO_IDLE_CYCLE 8
#define M_IO_IDLE_CYCLE _SB_MAKEMASK(4, S_IO_IDLE_CYCLE)
#define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x, S_IO_IDLE_CYCLE)
#define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x, S_IO_IDLE_CYCLE, M_IO_IDLE_CYCLE)
#define S_IO_OE_TO_CS 12
#define M_IO_OE_TO_CS _SB_MAKEMASK(2, S_IO_OE_TO_CS)
#define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x, S_IO_OE_TO_CS)
#define G_IO_OE_TO_CS(x) _SB_GETVALUE(x, S_IO_OE_TO_CS, M_IO_OE_TO_CS)
#define S_IO_CS_TO_OE 14
#define M_IO_CS_TO_OE _SB_MAKEMASK(2, S_IO_CS_TO_OE)
#define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x, S_IO_CS_TO_OE)
#define G_IO_CS_TO_OE(x) _SB_GETVALUE(x, S_IO_CS_TO_OE, M_IO_CS_TO_OE)
/*
* Generic Bus Interrupt Status Register (Table 11-9)
*/
#define M_IO_CS_ERR_INT _SB_MAKEMASK(0, 8)
#define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0)
#define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1)
#define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2)
#define M_IO_CS3_ERR_INT _SB_MAKEMASK1(3)
#define M_IO_CS4_ERR_INT _SB_MAKEMASK1(4)
#define M_IO_CS5_ERR_INT _SB_MAKEMASK1(5)
#define M_IO_CS6_ERR_INT _SB_MAKEMASK1(6)
#define M_IO_CS7_ERR_INT _SB_MAKEMASK1(7)
#define M_IO_RD_PAR_INT _SB_MAKEMASK1(9)
#define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10)
#define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11)
#define M_IO_MULT_CS_INT _SB_MAKEMASK1(12)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define M_IO_COH_ERR _SB_MAKEMASK1(14)
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
/*
* Generic Bus Output Drive Control Register 0 (Table 14-18)
*/
#define S_IO_SLEW0 0
#define M_IO_SLEW0 _SB_MAKEMASK(2, S_IO_SLEW0)
#define V_IO_SLEW0(x) _SB_MAKEVALUE(x, S_IO_SLEW0)
#define G_IO_SLEW0(x) _SB_GETVALUE(x, S_IO_SLEW0, M_IO_SLEW0)
#define S_IO_DRV_A 2
#define M_IO_DRV_A _SB_MAKEMASK(2, S_IO_DRV_A)
#define V_IO_DRV_A(x) _SB_MAKEVALUE(x, S_IO_DRV_A)
#define G_IO_DRV_A(x) _SB_GETVALUE(x, S_IO_DRV_A, M_IO_DRV_A)
#define S_IO_DRV_B 6
#define M_IO_DRV_B _SB_MAKEMASK(2, S_IO_DRV_B)
#define V_IO_DRV_B(x) _SB_MAKEVALUE(x, S_IO_DRV_B)
#define G_IO_DRV_B(x) _SB_GETVALUE(x, S_IO_DRV_B, M_IO_DRV_B)
#define S_IO_DRV_C 10
#define M_IO_DRV_C _SB_MAKEMASK(2, S_IO_DRV_C)
#define V_IO_DRV_C(x) _SB_MAKEVALUE(x, S_IO_DRV_C)
#define G_IO_DRV_C(x) _SB_GETVALUE(x, S_IO_DRV_C, M_IO_DRV_C)
#define S_IO_DRV_D 14
#define M_IO_DRV_D _SB_MAKEMASK(2, S_IO_DRV_D)
#define V_IO_DRV_D(x) _SB_MAKEVALUE(x, S_IO_DRV_D)
#define G_IO_DRV_D(x) _SB_GETVALUE(x, S_IO_DRV_D, M_IO_DRV_D)
/*
* Generic Bus Output Drive Control Register 1 (Table 14-19)
*/
#define S_IO_DRV_E 2
#define M_IO_DRV_E _SB_MAKEMASK(2, S_IO_DRV_E)
#define V_IO_DRV_E(x) _SB_MAKEVALUE(x, S_IO_DRV_E)
#define G_IO_DRV_E(x) _SB_GETVALUE(x, S_IO_DRV_E, M_IO_DRV_E)
#define S_IO_DRV_F 6
#define M_IO_DRV_F _SB_MAKEMASK(2, S_IO_DRV_F)
#define V_IO_DRV_F(x) _SB_MAKEVALUE(x, S_IO_DRV_F)
#define G_IO_DRV_F(x) _SB_GETVALUE(x, S_IO_DRV_F, M_IO_DRV_F)
#define S_IO_SLEW1 8
#define M_IO_SLEW1 _SB_MAKEMASK(2, S_IO_SLEW1)
#define V_IO_SLEW1(x) _SB_MAKEVALUE(x, S_IO_SLEW1)
#define G_IO_SLEW1(x) _SB_GETVALUE(x, S_IO_SLEW1, M_IO_SLEW1)
#define S_IO_DRV_G 10
#define M_IO_DRV_G _SB_MAKEMASK(2, S_IO_DRV_G)
#define V_IO_DRV_G(x) _SB_MAKEVALUE(x, S_IO_DRV_G)
#define G_IO_DRV_G(x) _SB_GETVALUE(x, S_IO_DRV_G, M_IO_DRV_G)
#define S_IO_SLEW2 12
#define M_IO_SLEW2 _SB_MAKEMASK(2, S_IO_SLEW2)
#define V_IO_SLEW2(x) _SB_MAKEVALUE(x, S_IO_SLEW2)
#define G_IO_SLEW2(x) _SB_GETVALUE(x, S_IO_SLEW2, M_IO_SLEW2)
#define S_IO_DRV_H 14
#define M_IO_DRV_H _SB_MAKEMASK(2, S_IO_DRV_H)
#define V_IO_DRV_H(x) _SB_MAKEVALUE(x, S_IO_DRV_H)
#define G_IO_DRV_H(x) _SB_GETVALUE(x, S_IO_DRV_H, M_IO_DRV_H)
/*
* Generic Bus Output Drive Control Register 2 (Table 14-20)
*/
#define S_IO_DRV_J 2
#define M_IO_DRV_J _SB_MAKEMASK(2, S_IO_DRV_J)
#define V_IO_DRV_J(x) _SB_MAKEVALUE(x, S_IO_DRV_J)
#define G_IO_DRV_J(x) _SB_GETVALUE(x, S_IO_DRV_J, M_IO_DRV_J)
#define S_IO_DRV_K 6
#define M_IO_DRV_K _SB_MAKEMASK(2, S_IO_DRV_K)
#define V_IO_DRV_K(x) _SB_MAKEVALUE(x, S_IO_DRV_K)
#define G_IO_DRV_K(x) _SB_GETVALUE(x, S_IO_DRV_K, M_IO_DRV_K)
#define S_IO_DRV_L 10
#define M_IO_DRV_L _SB_MAKEMASK(2, S_IO_DRV_L)
#define V_IO_DRV_L(x) _SB_MAKEVALUE(x, S_IO_DRV_L)
#define G_IO_DRV_L(x) _SB_GETVALUE(x, S_IO_DRV_L, M_IO_DRV_L)
#define S_IO_DRV_M 14
#define M_IO_DRV_M _SB_MAKEMASK(2, S_IO_DRV_M)
#define V_IO_DRV_M(x) _SB_MAKEVALUE(x, S_IO_DRV_M)
#define G_IO_DRV_M(x) _SB_GETVALUE(x, S_IO_DRV_M, M_IO_DRV_M)
/*
* Generic Bus Output Drive Control Register 3 (Table 14-21)
*/
#define S_IO_SLEW3 0
#define M_IO_SLEW3 _SB_MAKEMASK(2, S_IO_SLEW3)
#define V_IO_SLEW3(x) _SB_MAKEVALUE(x, S_IO_SLEW3)
#define G_IO_SLEW3(x) _SB_GETVALUE(x, S_IO_SLEW3, M_IO_SLEW3)
#define S_IO_DRV_N 2
#define M_IO_DRV_N _SB_MAKEMASK(2, S_IO_DRV_N)
#define V_IO_DRV_N(x) _SB_MAKEVALUE(x, S_IO_DRV_N)
#define G_IO_DRV_N(x) _SB_GETVALUE(x, S_IO_DRV_N, M_IO_DRV_N)
#define S_IO_DRV_P 6
#define M_IO_DRV_P _SB_MAKEMASK(2, S_IO_DRV_P)
#define V_IO_DRV_P(x) _SB_MAKEVALUE(x, S_IO_DRV_P)
#define G_IO_DRV_P(x) _SB_GETVALUE(x, S_IO_DRV_P, M_IO_DRV_P)
#define S_IO_DRV_Q 10
#define M_IO_DRV_Q _SB_MAKEMASK(2, S_IO_DRV_Q)
#define V_IO_DRV_Q(x) _SB_MAKEVALUE(x, S_IO_DRV_Q)
#define G_IO_DRV_Q(x) _SB_GETVALUE(x, S_IO_DRV_Q, M_IO_DRV_Q)
#define S_IO_DRV_R 14
#define M_IO_DRV_R _SB_MAKEMASK(2, S_IO_DRV_R)
#define V_IO_DRV_R(x) _SB_MAKEVALUE(x, S_IO_DRV_R)
#define G_IO_DRV_R(x) _SB_GETVALUE(x, S_IO_DRV_R, M_IO_DRV_R)
/*
* PCMCIA configuration register (Table 12-6)
*/
#define M_PCMCIA_CFG_ATTRMEM _SB_MAKEMASK1(0)
#define M_PCMCIA_CFG_3VEN _SB_MAKEMASK1(1)
#define M_PCMCIA_CFG_5VEN _SB_MAKEMASK1(2)
#define M_PCMCIA_CFG_VPPEN _SB_MAKEMASK1(3)
#define M_PCMCIA_CFG_RESET _SB_MAKEMASK1(4)
#define M_PCMCIA_CFG_APWRONEN _SB_MAKEMASK1(5)
#define M_PCMCIA_CFG_CDMASK _SB_MAKEMASK1(6)
#define M_PCMCIA_CFG_WPMASK _SB_MAKEMASK1(7)
#define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8)
#define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9)
#if SIBYTE_HDR_FEATURE_CHIP(1480)
#define S_PCMCIA_MODE 16
#define M_PCMCIA_MODE _SB_MAKEMASK(3, S_PCMCIA_MODE)
#define V_PCMCIA_MODE(x) _SB_MAKEVALUE(x, S_PCMCIA_MODE)
#define G_PCMCIA_MODE(x) _SB_GETVALUE(x, S_PCMCIA_MODE, M_PCMCIA_MODE)
#define K_PCMCIA_MODE_PCMA_NOB 0 /* standard PCMCIA "A", no "B" */
#define K_PCMCIA_MODE_IDEA_NOB 1 /* IDE "A", no "B" */
#define K_PCMCIA_MODE_PCMIOA_NOB 2 /* PCMCIA with I/O "A", no "B" */
#define K_PCMCIA_MODE_PCMA_PCMB 4 /* standard PCMCIA "A", standard PCMCIA "B" */
#define K_PCMCIA_MODE_IDEA_PCMB 5 /* IDE "A", standard PCMCIA "B" */
#define K_PCMCIA_MODE_PCMA_IDEB 6 /* standard PCMCIA "A", IDE "B" */
#define K_PCMCIA_MODE_IDEA_IDEB 7 /* IDE "A", IDE "B" */
#endif
/*
* PCMCIA status register (Table 12-7)
*/
#define M_PCMCIA_STATUS_CD1 _SB_MAKEMASK1(0)
#define M_PCMCIA_STATUS_CD2 _SB_MAKEMASK1(1)
#define M_PCMCIA_STATUS_VS1 _SB_MAKEMASK1(2)
#define M_PCMCIA_STATUS_VS2 _SB_MAKEMASK1(3)
#define M_PCMCIA_STATUS_WP _SB_MAKEMASK1(4)
#define M_PCMCIA_STATUS_RDY _SB_MAKEMASK1(5)
#define M_PCMCIA_STATUS_3VEN _SB_MAKEMASK1(6)
#define M_PCMCIA_STATUS_5VEN _SB_MAKEMASK1(7)
#define M_PCMCIA_STATUS_CDCHG _SB_MAKEMASK1(8)
#define M_PCMCIA_STATUS_WPCHG _SB_MAKEMASK1(9)
#define M_PCMCIA_STATUS_RDYCHG _SB_MAKEMASK1(10)
/*
* GPIO Interrupt Type Register (table 13-3)
*/
#define K_GPIO_INTR_DISABLE 0
#define K_GPIO_INTR_EDGE 1
#define K_GPIO_INTR_LEVEL 2
#define K_GPIO_INTR_SPLIT 3
#define S_GPIO_INTR_TYPEX(n) (((n)/2)*2)
#define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_TYPEX(n))
#define V_GPIO_INTR_TYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPEX(n))
#define G_GPIO_INTR_TYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_TYPEX(n), M_GPIO_INTR_TYPEX(n))
#define S_GPIO_INTR_TYPE0 0
#define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE0)
#define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE0)
#define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE0, M_GPIO_INTR_TYPE0)
#define S_GPIO_INTR_TYPE2 2
#define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE2)
#define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE2)
#define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE2, M_GPIO_INTR_TYPE2)
#define S_GPIO_INTR_TYPE4 4
#define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE4)
#define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE4)
#define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE4, M_GPIO_INTR_TYPE4)
#define S_GPIO_INTR_TYPE6 6
#define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE6)
#define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE6)
#define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE6, M_GPIO_INTR_TYPE6)
#define S_GPIO_INTR_TYPE8 8
#define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE8)
#define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE8)
#define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE8, M_GPIO_INTR_TYPE8)
#define S_GPIO_INTR_TYPE10 10
#define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE10)
#define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE10)
#define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE10, M_GPIO_INTR_TYPE10)
#define S_GPIO_INTR_TYPE12 12
#define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE12)
#define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE12)
#define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE12, M_GPIO_INTR_TYPE12)
#define S_GPIO_INTR_TYPE14 14
#define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_TYPE14)
#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE14)
#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_TYPE14, M_GPIO_INTR_TYPE14)
#if SIBYTE_HDR_FEATURE_CHIP(1480)
/*
* GPIO Interrupt Additional Type Register
*/
#define K_GPIO_INTR_BOTHEDGE 0
#define K_GPIO_INTR_RISEEDGE 1
#define K_GPIO_INTR_UNPRED1 2
#define K_GPIO_INTR_UNPRED2 3
#define S_GPIO_INTR_ATYPEX(n) (((n)/2)*2)
#define M_GPIO_INTR_ATYPEX(n) _SB_MAKEMASK(2, S_GPIO_INTR_ATYPEX(n))
#define V_GPIO_INTR_ATYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPEX(n))
#define G_GPIO_INTR_ATYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPEX(n), M_GPIO_INTR_ATYPEX(n))
#define S_GPIO_INTR_ATYPE0 0
#define M_GPIO_INTR_ATYPE0 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE0)
#define V_GPIO_INTR_ATYPE0(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE0)
#define G_GPIO_INTR_ATYPE0(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE0, M_GPIO_INTR_ATYPE0)
#define S_GPIO_INTR_ATYPE2 2
#define M_GPIO_INTR_ATYPE2 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE2)
#define V_GPIO_INTR_ATYPE2(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE2)
#define G_GPIO_INTR_ATYPE2(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE2, M_GPIO_INTR_ATYPE2)
#define S_GPIO_INTR_ATYPE4 4
#define M_GPIO_INTR_ATYPE4 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE4)
#define V_GPIO_INTR_ATYPE4(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE4)
#define G_GPIO_INTR_ATYPE4(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE4, M_GPIO_INTR_ATYPE4)
#define S_GPIO_INTR_ATYPE6 6
#define M_GPIO_INTR_ATYPE6 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE6)
#define V_GPIO_INTR_ATYPE6(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE6)
#define G_GPIO_INTR_ATYPE6(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE6, M_GPIO_INTR_ATYPE6)
#define S_GPIO_INTR_ATYPE8 8
#define M_GPIO_INTR_ATYPE8 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE8)
#define V_GPIO_INTR_ATYPE8(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE8)
#define G_GPIO_INTR_ATYPE8(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE8, M_GPIO_INTR_ATYPE8)
#define S_GPIO_INTR_ATYPE10 10
#define M_GPIO_INTR_ATYPE10 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE10)
#define V_GPIO_INTR_ATYPE10(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE10)
#define G_GPIO_INTR_ATYPE10(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE10, M_GPIO_INTR_ATYPE10)
#define S_GPIO_INTR_ATYPE12 12
#define M_GPIO_INTR_ATYPE12 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE12)
#define V_GPIO_INTR_ATYPE12(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE12)
#define G_GPIO_INTR_ATYPE12(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE12, M_GPIO_INTR_ATYPE12)
#define S_GPIO_INTR_ATYPE14 14
#define M_GPIO_INTR_ATYPE14 _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE14)
#define V_GPIO_INTR_ATYPE14(x) _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE14)
#define G_GPIO_INTR_ATYPE14(x) _SB_GETVALUE(x, S_GPIO_INTR_ATYPE14, M_GPIO_INTR_ATYPE14)
#endif
#endif

248
kernel/arch/mips/include/asm/sibyte/sb1250_int.h Normal file
View File

@@ -0,0 +1,248 @@
/* *********************************************************************
* SB1250 Board Support Package
*
* Interrupt Mapper definitions File: sb1250_int.h
*
* This module contains constants for manipulating the SB1250's
* interrupt mapper and definitions for the interrupt sources.
*
* SB1250 specification level: User's manual 1/02/02
*
*********************************************************************
*
* Copyright 2000, 2001, 2002, 2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_INT_H
#define _SB1250_INT_H
#include "sb1250_defs.h"
/* *********************************************************************
* Interrupt Mapper Constants
********************************************************************* */
/*
* Interrupt sources (Table 4-8, UM 0.2)
*
* First, the interrupt numbers.
*/
#define K_INT_SOURCES 64
#define K_INT_WATCHDOG_TIMER_0 0
#define K_INT_WATCHDOG_TIMER_1 1
#define K_INT_TIMER_0 2
#define K_INT_TIMER_1 3
#define K_INT_TIMER_2 4
#define K_INT_TIMER_3 5
#define K_INT_SMB_0 6
#define K_INT_SMB_1 7
#define K_INT_UART_0 8
#define K_INT_UART_1 9
#define K_INT_SER_0 10
#define K_INT_SER_1 11
#define K_INT_PCMCIA 12
#define K_INT_ADDR_TRAP 13
#define K_INT_PERF_CNT 14
#define K_INT_TRACE_FREEZE 15
#define K_INT_BAD_ECC 16
#define K_INT_COR_ECC 17
#define K_INT_IO_BUS 18
#define K_INT_MAC_0 19
#define K_INT_MAC_1 20
#define K_INT_MAC_2 21
#define K_INT_DM_CH_0 22
#define K_INT_DM_CH_1 23
#define K_INT_DM_CH_2 24
#define K_INT_DM_CH_3 25
#define K_INT_MBOX_0 26
#define K_INT_MBOX_1 27
#define K_INT_MBOX_2 28
#define K_INT_MBOX_3 29
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define K_INT_CYCLE_CP0_INT 30
#define K_INT_CYCLE_CP1_INT 31
#endif /* 1250 PASS2 || 112x PASS1 */
#define K_INT_GPIO_0 32
#define K_INT_GPIO_1 33
#define K_INT_GPIO_2 34
#define K_INT_GPIO_3 35
#define K_INT_GPIO_4 36
#define K_INT_GPIO_5 37
#define K_INT_GPIO_6 38
#define K_INT_GPIO_7 39
#define K_INT_GPIO_8 40
#define K_INT_GPIO_9 41
#define K_INT_GPIO_10 42
#define K_INT_GPIO_11 43
#define K_INT_GPIO_12 44
#define K_INT_GPIO_13 45
#define K_INT_GPIO_14 46
#define K_INT_GPIO_15 47
#define K_INT_LDT_FATAL 48
#define K_INT_LDT_NONFATAL 49
#define K_INT_LDT_SMI 50
#define K_INT_LDT_NMI 51
#define K_INT_LDT_INIT 52
#define K_INT_LDT_STARTUP 53
#define K_INT_LDT_EXT 54
#define K_INT_PCI_ERROR 55
#define K_INT_PCI_INTA 56
#define K_INT_PCI_INTB 57
#define K_INT_PCI_INTC 58
#define K_INT_PCI_INTD 59
#define K_INT_SPARE_2 60
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define K_INT_MAC_0_CH1 61
#define K_INT_MAC_1_CH1 62
#define K_INT_MAC_2_CH1 63
#endif /* 1250 PASS2 || 112x PASS1 */
/*
* Mask values for each interrupt
*/
#define M_INT_WATCHDOG_TIMER_0 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
#define M_INT_WATCHDOG_TIMER_1 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
#define M_INT_TIMER_0 _SB_MAKEMASK1(K_INT_TIMER_0)
#define M_INT_TIMER_1 _SB_MAKEMASK1(K_INT_TIMER_1)
#define M_INT_TIMER_2 _SB_MAKEMASK1(K_INT_TIMER_2)
#define M_INT_TIMER_3 _SB_MAKEMASK1(K_INT_TIMER_3)
#define M_INT_SMB_0 _SB_MAKEMASK1(K_INT_SMB_0)
#define M_INT_SMB_1 _SB_MAKEMASK1(K_INT_SMB_1)
#define M_INT_UART_0 _SB_MAKEMASK1(K_INT_UART_0)
#define M_INT_UART_1 _SB_MAKEMASK1(K_INT_UART_1)
#define M_INT_SER_0 _SB_MAKEMASK1(K_INT_SER_0)
#define M_INT_SER_1 _SB_MAKEMASK1(K_INT_SER_1)
#define M_INT_PCMCIA _SB_MAKEMASK1(K_INT_PCMCIA)
#define M_INT_ADDR_TRAP _SB_MAKEMASK1(K_INT_ADDR_TRAP)
#define M_INT_PERF_CNT _SB_MAKEMASK1(K_INT_PERF_CNT)
#define M_INT_TRACE_FREEZE _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
#define M_INT_BAD_ECC _SB_MAKEMASK1(K_INT_BAD_ECC)
#define M_INT_COR_ECC _SB_MAKEMASK1(K_INT_COR_ECC)
#define M_INT_IO_BUS _SB_MAKEMASK1(K_INT_IO_BUS)
#define M_INT_MAC_0 _SB_MAKEMASK1(K_INT_MAC_0)
#define M_INT_MAC_1 _SB_MAKEMASK1(K_INT_MAC_1)
#define M_INT_MAC_2 _SB_MAKEMASK1(K_INT_MAC_2)
#define M_INT_DM_CH_0 _SB_MAKEMASK1(K_INT_DM_CH_0)
#define M_INT_DM_CH_1 _SB_MAKEMASK1(K_INT_DM_CH_1)
#define M_INT_DM_CH_2 _SB_MAKEMASK1(K_INT_DM_CH_2)
#define M_INT_DM_CH_3 _SB_MAKEMASK1(K_INT_DM_CH_3)
#define M_INT_MBOX_0 _SB_MAKEMASK1(K_INT_MBOX_0)
#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1)
#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2)
#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3)
#define M_INT_MBOX_ALL _SB_MAKEMASK(4, K_INT_MBOX_0)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
#define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
#endif /* 1250 PASS2 || 112x PASS1 */
#define M_INT_GPIO_0 _SB_MAKEMASK1(K_INT_GPIO_0)
#define M_INT_GPIO_1 _SB_MAKEMASK1(K_INT_GPIO_1)
#define M_INT_GPIO_2 _SB_MAKEMASK1(K_INT_GPIO_2)
#define M_INT_GPIO_3 _SB_MAKEMASK1(K_INT_GPIO_3)
#define M_INT_GPIO_4 _SB_MAKEMASK1(K_INT_GPIO_4)
#define M_INT_GPIO_5 _SB_MAKEMASK1(K_INT_GPIO_5)
#define M_INT_GPIO_6 _SB_MAKEMASK1(K_INT_GPIO_6)
#define M_INT_GPIO_7 _SB_MAKEMASK1(K_INT_GPIO_7)
#define M_INT_GPIO_8 _SB_MAKEMASK1(K_INT_GPIO_8)
#define M_INT_GPIO_9 _SB_MAKEMASK1(K_INT_GPIO_9)
#define M_INT_GPIO_10 _SB_MAKEMASK1(K_INT_GPIO_10)
#define M_INT_GPIO_11 _SB_MAKEMASK1(K_INT_GPIO_11)
#define M_INT_GPIO_12 _SB_MAKEMASK1(K_INT_GPIO_12)
#define M_INT_GPIO_13 _SB_MAKEMASK1(K_INT_GPIO_13)
#define M_INT_GPIO_14 _SB_MAKEMASK1(K_INT_GPIO_14)
#define M_INT_GPIO_15 _SB_MAKEMASK1(K_INT_GPIO_15)
#define M_INT_LDT_FATAL _SB_MAKEMASK1(K_INT_LDT_FATAL)
#define M_INT_LDT_NONFATAL _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
#define M_INT_LDT_SMI _SB_MAKEMASK1(K_INT_LDT_SMI)
#define M_INT_LDT_NMI _SB_MAKEMASK1(K_INT_LDT_NMI)
#define M_INT_LDT_INIT _SB_MAKEMASK1(K_INT_LDT_INIT)
#define M_INT_LDT_STARTUP _SB_MAKEMASK1(K_INT_LDT_STARTUP)
#define M_INT_LDT_EXT _SB_MAKEMASK1(K_INT_LDT_EXT)
#define M_INT_PCI_ERROR _SB_MAKEMASK1(K_INT_PCI_ERROR)
#define M_INT_PCI_INTA _SB_MAKEMASK1(K_INT_PCI_INTA)
#define M_INT_PCI_INTB _SB_MAKEMASK1(K_INT_PCI_INTB)
#define M_INT_PCI_INTC _SB_MAKEMASK1(K_INT_PCI_INTC)
#define M_INT_PCI_INTD _SB_MAKEMASK1(K_INT_PCI_INTD)
#define M_INT_SPARE_2 _SB_MAKEMASK1(K_INT_SPARE_2)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_INT_MAC_0_CH1 _SB_MAKEMASK1(K_INT_MAC_0_CH1)
#define M_INT_MAC_1_CH1 _SB_MAKEMASK1(K_INT_MAC_1_CH1)
#define M_INT_MAC_2_CH1 _SB_MAKEMASK1(K_INT_MAC_2_CH1)
#endif /* 1250 PASS2 || 112x PASS1 */
/*
* Interrupt mappings
*/
#define K_INT_MAP_I0 0 /* interrupt pins on processor */
#define K_INT_MAP_I1 1
#define K_INT_MAP_I2 2
#define K_INT_MAP_I3 3
#define K_INT_MAP_I4 4
#define K_INT_MAP_I5 5
#define K_INT_MAP_NMI 6 /* nonmaskable */
#define K_INT_MAP_DINT 7 /* debug interrupt */
/*
* LDT Interrupt Set Register (table 4-5)
*/
#define S_INT_LDT_INTMSG 0
#define M_INT_LDT_INTMSG _SB_MAKEMASK(3, S_INT_LDT_INTMSG)
#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x, S_INT_LDT_INTMSG)
#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x, S_INT_LDT_INTMSG, M_INT_LDT_INTMSG)
#define K_INT_LDT_INTMSG_FIXED 0
#define K_INT_LDT_INTMSG_ARBITRATED 1
#define K_INT_LDT_INTMSG_SMI 2
#define K_INT_LDT_INTMSG_NMI 3
#define K_INT_LDT_INTMSG_INIT 4
#define K_INT_LDT_INTMSG_STARTUP 5
#define K_INT_LDT_INTMSG_EXTINT 6
#define K_INT_LDT_INTMSG_RESERVED 7
#define M_INT_LDT_EDGETRIGGER 0
#define M_INT_LDT_LEVELTRIGGER _SB_MAKEMASK1(3)
#define M_INT_LDT_PHYSICALDEST 0
#define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4)
#define S_INT_LDT_INTDEST 5
#define M_INT_LDT_INTDEST _SB_MAKEMASK(10, S_INT_LDT_INTDEST)
#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x, S_INT_LDT_INTDEST)
#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x, S_INT_LDT_INTDEST, M_INT_LDT_INTDEST)
#define S_INT_LDT_VECTOR 13
#define M_INT_LDT_VECTOR _SB_MAKEMASK(8, S_INT_LDT_VECTOR)
#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x, S_INT_LDT_VECTOR)
#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x, S_INT_LDT_VECTOR, M_INT_LDT_VECTOR)
/*
* Vector format (Table 4-6)
*/
#define M_LDTVECT_RAISEINT 0x00
#define M_LDTVECT_RAISEMBOX 0x40
#endif /* 1250/112x */

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/* *********************************************************************
* SB1250 Board Support Package
*
* L2 Cache constants and macros File: sb1250_l2c.h
*
* This module contains constants useful for manipulating the
* level 2 cache.
*
* SB1250 specification level: User's manual 1/02/02
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_L2C_H
#define _SB1250_L2C_H
#include "sb1250_defs.h"
/*
* Level 2 Cache Tag register (Table 5-3)
*/
#define S_L2C_TAG_MBZ 0
#define M_L2C_TAG_MBZ _SB_MAKEMASK(5, S_L2C_TAG_MBZ)
#define S_L2C_TAG_INDEX 5
#define M_L2C_TAG_INDEX _SB_MAKEMASK(12, S_L2C_TAG_INDEX)
#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x, S_L2C_TAG_INDEX)
#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x, S_L2C_TAG_INDEX, M_L2C_TAG_INDEX)
#define S_L2C_TAG_TAG 17
#define M_L2C_TAG_TAG _SB_MAKEMASK(23, S_L2C_TAG_TAG)
#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x, S_L2C_TAG_TAG)
#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x, S_L2C_TAG_TAG, M_L2C_TAG_TAG)
#define S_L2C_TAG_ECC 40
#define M_L2C_TAG_ECC _SB_MAKEMASK(6, S_L2C_TAG_ECC)
#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x, S_L2C_TAG_ECC)
#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x, S_L2C_TAG_ECC, M_L2C_TAG_ECC)
#define S_L2C_TAG_WAY 46
#define M_L2C_TAG_WAY _SB_MAKEMASK(2, S_L2C_TAG_WAY)
#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x, S_L2C_TAG_WAY)
#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x, S_L2C_TAG_WAY, M_L2C_TAG_WAY)
#define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48)
#define M_L2C_TAG_VALID _SB_MAKEMASK1(49)
/*
* Format of level 2 cache management address (table 5-2)
*/
#define S_L2C_MGMT_INDEX 5
#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12, S_L2C_MGMT_INDEX)
#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x, S_L2C_MGMT_INDEX)
#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x, S_L2C_MGMT_INDEX, M_L2C_MGMT_INDEX)
#define S_L2C_MGMT_QUADRANT 15
#define M_L2C_MGMT_QUADRANT _SB_MAKEMASK(2, S_L2C_MGMT_QUADRANT)
#define V_L2C_MGMT_QUADRANT(x) _SB_MAKEVALUE(x, S_L2C_MGMT_QUADRANT)
#define G_L2C_MGMT_QUADRANT(x) _SB_GETVALUE(x, S_L2C_MGMT_QUADRANT, M_L2C_MGMT_QUADRANT)
#define S_L2C_MGMT_HALF 16
#define M_L2C_MGMT_HALF _SB_MAKEMASK(1, S_L2C_MGMT_HALF)
#define S_L2C_MGMT_WAY 17
#define M_L2C_MGMT_WAY _SB_MAKEMASK(2, S_L2C_MGMT_WAY)
#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x, S_L2C_MGMT_WAY)
#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x, S_L2C_MGMT_WAY, M_L2C_MGMT_WAY)
#define S_L2C_MGMT_ECC_DIAG 21
#define M_L2C_MGMT_ECC_DIAG _SB_MAKEMASK(2, S_L2C_MGMT_ECC_DIAG)
#define V_L2C_MGMT_ECC_DIAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_ECC_DIAG)
#define G_L2C_MGMT_ECC_DIAG(x) _SB_GETVALUE(x, S_L2C_MGMT_ECC_DIAG, M_L2C_MGMT_ECC_DIAG)
#define S_L2C_MGMT_TAG 23
#define M_L2C_MGMT_TAG _SB_MAKEMASK(4, S_L2C_MGMT_TAG)
#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x, S_L2C_MGMT_TAG)
#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x, S_L2C_MGMT_TAG, M_L2C_MGMT_TAG)
#define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19)
#define M_L2C_MGMT_VALID _SB_MAKEMASK1(20)
#define A_L2C_MGMT_TAG_BASE 0x00D0000000
#define L2C_ENTRIES_PER_WAY 4096
#define L2C_NUM_WAYS 4
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
/*
* L2 Read Misc. register (A_L2_READ_MISC)
*/
#define S_L2C_MISC_NO_WAY 10
#define M_L2C_MISC_NO_WAY _SB_MAKEMASK(4, S_L2C_MISC_NO_WAY)
#define V_L2C_MISC_NO_WAY(x) _SB_MAKEVALUE(x, S_L2C_MISC_NO_WAY)
#define G_L2C_MISC_NO_WAY(x) _SB_GETVALUE(x, S_L2C_MISC_NO_WAY, M_L2C_MISC_NO_WAY)
#define M_L2C_MISC_ECC_CLEANUP_DIS _SB_MAKEMASK1(9)
#define M_L2C_MISC_MC_PRIO_LOW _SB_MAKEMASK1(8)
#define M_L2C_MISC_SOFT_DISABLE_T _SB_MAKEMASK1(7)
#define M_L2C_MISC_SOFT_DISABLE_B _SB_MAKEMASK1(6)
#define M_L2C_MISC_SOFT_DISABLE_R _SB_MAKEMASK1(5)
#define M_L2C_MISC_SOFT_DISABLE_L _SB_MAKEMASK1(4)
#define M_L2C_MISC_SCACHE_DISABLE_T _SB_MAKEMASK1(3)
#define M_L2C_MISC_SCACHE_DISABLE_B _SB_MAKEMASK1(2)
#define M_L2C_MISC_SCACHE_DISABLE_R _SB_MAKEMASK1(1)
#define M_L2C_MISC_SCACHE_DISABLE_L _SB_MAKEMASK1(0)
#endif /* 1250 PASS3 || 112x PASS1 */
#endif

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/* *********************************************************************
* SB1250 Board Support Package
*
* LDT constants File: sb1250_ldt.h
*
* This module contains constants and macros to describe
* the LDT interface on the SB1250.
*
* SB1250 specification level: User's manual 1/02/02
*
*********************************************************************
*
* Copyright 2000, 2001, 2002, 2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_LDT_H
#define _SB1250_LDT_H
#include "sb1250_defs.h"
#define K_LDT_VENDOR_SIBYTE 0x166D
#define K_LDT_DEVICE_SB1250 0x0002
/*
* LDT Interface Type 1 (bridge) configuration header
*/
#define R_LDT_TYPE1_DEVICEID 0x0000
#define R_LDT_TYPE1_CMDSTATUS 0x0004
#define R_LDT_TYPE1_CLASSREV 0x0008
#define R_LDT_TYPE1_DEVHDR 0x000C
#define R_LDT_TYPE1_BAR0 0x0010 /* not used */
#define R_LDT_TYPE1_BAR1 0x0014 /* not used */
#define R_LDT_TYPE1_BUSID 0x0018 /* bus ID register */
#define R_LDT_TYPE1_SECSTATUS 0x001C /* secondary status / I/O base/limit */
#define R_LDT_TYPE1_MEMLIMIT 0x0020
#define R_LDT_TYPE1_PREFETCH 0x0024
#define R_LDT_TYPE1_PREF_BASE 0x0028
#define R_LDT_TYPE1_PREF_LIMIT 0x002C
#define R_LDT_TYPE1_IOLIMIT 0x0030
#define R_LDT_TYPE1_CAPPTR 0x0034
#define R_LDT_TYPE1_ROMADDR 0x0038
#define R_LDT_TYPE1_BRCTL 0x003C
#define R_LDT_TYPE1_CMD 0x0040
#define R_LDT_TYPE1_LINKCTRL 0x0044
#define R_LDT_TYPE1_LINKFREQ 0x0048
#define R_LDT_TYPE1_RESERVED1 0x004C
#define R_LDT_TYPE1_SRICMD 0x0050
#define R_LDT_TYPE1_SRITXNUM 0x0054
#define R_LDT_TYPE1_SRIRXNUM 0x0058
#define R_LDT_TYPE1_ERRSTATUS 0x0068
#define R_LDT_TYPE1_SRICTRL 0x006C
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define R_LDT_TYPE1_ADDSTATUS 0x0070
#endif /* 1250 PASS2 || 112x PASS1 */
#define R_LDT_TYPE1_TXBUFCNT 0x00C8
#define R_LDT_TYPE1_EXPCRC 0x00DC
#define R_LDT_TYPE1_RXCRC 0x00F0
/*
* LDT Device ID register
*/
#define S_LDT_DEVICEID_VENDOR 0
#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16, S_LDT_DEVICEID_VENDOR)
#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_VENDOR)
#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_VENDOR, M_LDT_DEVICEID_VENDOR)
#define S_LDT_DEVICEID_DEVICEID 16
#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16, S_LDT_DEVICEID_DEVICEID)
#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_DEVICEID)
#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x, S_LDT_DEVICEID_DEVICEID, M_LDT_DEVICEID_DEVICEID)
/*
* LDT Command Register (Table 8-13)
*/
#define M_LDT_CMD_IOSPACE_EN _SB_MAKEMASK1_32(0)
#define M_LDT_CMD_MEMSPACE_EN _SB_MAKEMASK1_32(1)
#define M_LDT_CMD_MASTER_EN _SB_MAKEMASK1_32(2)
#define M_LDT_CMD_SPECCYC_EN _SB_MAKEMASK1_32(3)
#define M_LDT_CMD_MEMWRINV_EN _SB_MAKEMASK1_32(4)
#define M_LDT_CMD_VGAPALSNP_EN _SB_MAKEMASK1_32(5)
#define M_LDT_CMD_PARERRRESP _SB_MAKEMASK1_32(6)
#define M_LDT_CMD_WAITCYCCTRL _SB_MAKEMASK1_32(7)
#define M_LDT_CMD_SERR_EN _SB_MAKEMASK1_32(8)
#define M_LDT_CMD_FASTB2B_EN _SB_MAKEMASK1_32(9)
/*
* LDT class and revision registers
*/
#define S_LDT_CLASSREV_REV 0
#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8, S_LDT_CLASSREV_REV)
#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_REV)
#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_REV, M_LDT_CLASSREV_REV)
#define S_LDT_CLASSREV_CLASS 8
#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24, S_LDT_CLASSREV_CLASS)
#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_CLASS)
#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x, S_LDT_CLASSREV_CLASS, M_LDT_CLASSREV_CLASS)
#define K_LDT_REV 0x01
#define K_LDT_CLASS 0x060000
/*
* Device Header (offset 0x0C)
*/
#define S_LDT_DEVHDR_CLINESZ 0
#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8, S_LDT_DEVHDR_CLINESZ)
#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_CLINESZ)
#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_CLINESZ, M_LDT_DEVHDR_CLINESZ)
#define S_LDT_DEVHDR_LATTMR 8
#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8, S_LDT_DEVHDR_LATTMR)
#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_LATTMR)
#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_LATTMR, M_LDT_DEVHDR_LATTMR)
#define S_LDT_DEVHDR_HDRTYPE 16
#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8, S_LDT_DEVHDR_HDRTYPE)
#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_HDRTYPE)
#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_HDRTYPE, M_LDT_DEVHDR_HDRTYPE)
#define K_LDT_DEVHDR_HDRTYPE_TYPE1 1
#define S_LDT_DEVHDR_BIST 24
#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8, S_LDT_DEVHDR_BIST)
#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_BIST)
#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x, S_LDT_DEVHDR_BIST, M_LDT_DEVHDR_BIST)
/*
* LDT Status Register (Table 8-14). Note that these constants
* assume you've read the command and status register
* together (32-bit read at offset 0x04)
*
* These bits also apply to the secondary status
* register (Table 8-15), offset 0x1C
*/
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_LDT_STATUS_VGAEN _SB_MAKEMASK1_32(3)
#endif /* 1250 PASS2 || 112x PASS1 */
#define M_LDT_STATUS_CAPLIST _SB_MAKEMASK1_32(20)
#define M_LDT_STATUS_66MHZCAP _SB_MAKEMASK1_32(21)
#define M_LDT_STATUS_RESERVED2 _SB_MAKEMASK1_32(22)
#define M_LDT_STATUS_FASTB2BCAP _SB_MAKEMASK1_32(23)
#define M_LDT_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24)
#define S_LDT_STATUS_DEVSELTIMING 25
#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2, S_LDT_STATUS_DEVSELTIMING)
#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x, S_LDT_STATUS_DEVSELTIMING)
#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x, S_LDT_STATUS_DEVSELTIMING, M_LDT_STATUS_DEVSELTIMING)
#define M_LDT_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27)
#define M_LDT_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28)
#define M_LDT_STATUS_RCVDMSTRABORT _SB_MAKEMASK1_32(29)
#define M_LDT_STATUS_SIGDSERR _SB_MAKEMASK1_32(30)
#define M_LDT_STATUS_DETPARERR _SB_MAKEMASK1_32(31)
/*
* Bridge Control Register (Table 8-16). Note that these
* constants assume you've read the register as a 32-bit
* read (offset 0x3C)
*/
#define M_LDT_BRCTL_PARERRRESP_EN _SB_MAKEMASK1_32(16)
#define M_LDT_BRCTL_SERR_EN _SB_MAKEMASK1_32(17)
#define M_LDT_BRCTL_ISA_EN _SB_MAKEMASK1_32(18)
#define M_LDT_BRCTL_VGA_EN _SB_MAKEMASK1_32(19)
#define M_LDT_BRCTL_MSTRABORTMODE _SB_MAKEMASK1_32(21)
#define M_LDT_BRCTL_SECBUSRESET _SB_MAKEMASK1_32(22)
#define M_LDT_BRCTL_FASTB2B_EN _SB_MAKEMASK1_32(23)
#define M_LDT_BRCTL_PRIDISCARD _SB_MAKEMASK1_32(24)
#define M_LDT_BRCTL_SECDISCARD _SB_MAKEMASK1_32(25)
#define M_LDT_BRCTL_DISCARDSTAT _SB_MAKEMASK1_32(26)
#define M_LDT_BRCTL_DISCARDSERR_EN _SB_MAKEMASK1_32(27)
/*
* LDT Command Register (Table 8-17). Note that these constants
* assume you've read the command and status register together
* 32-bit read at offset 0x40
*/
#define M_LDT_CMD_WARMRESET _SB_MAKEMASK1_32(16)
#define M_LDT_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17)
#define S_LDT_CMD_CAPTYPE 29
#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3, S_LDT_CMD_CAPTYPE)
#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x, S_LDT_CMD_CAPTYPE)
#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x, S_LDT_CMD_CAPTYPE, M_LDT_CMD_CAPTYPE)
/*
* LDT link control register (Table 8-18), and (Table 8-19)
*/
#define M_LDT_LINKCTRL_CAPSYNCFLOOD_EN _SB_MAKEMASK1_32(1)
#define M_LDT_LINKCTRL_CRCSTARTTEST _SB_MAKEMASK1_32(2)
#define M_LDT_LINKCTRL_CRCFORCEERR _SB_MAKEMASK1_32(3)
#define M_LDT_LINKCTRL_LINKFAIL _SB_MAKEMASK1_32(4)
#define M_LDT_LINKCTRL_INITDONE _SB_MAKEMASK1_32(5)
#define M_LDT_LINKCTRL_EOC _SB_MAKEMASK1_32(6)
#define M_LDT_LINKCTRL_XMITOFF _SB_MAKEMASK1_32(7)
#define S_LDT_LINKCTRL_CRCERR 8
#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4, S_LDT_LINKCTRL_CRCERR)
#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_CRCERR)
#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_CRCERR, M_LDT_LINKCTRL_CRCERR)
#define S_LDT_LINKCTRL_MAXIN 16
#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXIN)
#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXIN)
#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXIN, M_LDT_LINKCTRL_MAXIN)
#define M_LDT_LINKCTRL_DWFCLN _SB_MAKEMASK1_32(19)
#define S_LDT_LINKCTRL_MAXOUT 20
#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXOUT)
#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXOUT)
#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXOUT, M_LDT_LINKCTRL_MAXOUT)
#define M_LDT_LINKCTRL_DWFCOUT _SB_MAKEMASK1_32(23)
#define S_LDT_LINKCTRL_WIDTHIN 24
#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHIN)
#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN)
#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN, M_LDT_LINKCTRL_WIDTHIN)
#define M_LDT_LINKCTRL_DWFCLIN_EN _SB_MAKEMASK1_32(27)
#define S_LDT_LINKCTRL_WIDTHOUT 28
#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHOUT)
#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT)
#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT, M_LDT_LINKCTRL_WIDTHOUT)
#define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31)
/*
* LDT Link frequency register (Table 8-20) offset 0x48
*/
#define S_LDT_LINKFREQ_FREQ 8
#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4, S_LDT_LINKFREQ_FREQ)
#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x, S_LDT_LINKFREQ_FREQ)
#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x, S_LDT_LINKFREQ_FREQ, M_LDT_LINKFREQ_FREQ)
#define K_LDT_LINKFREQ_200MHZ 0
#define K_LDT_LINKFREQ_300MHZ 1
#define K_LDT_LINKFREQ_400MHZ 2
#define K_LDT_LINKFREQ_500MHZ 3
#define K_LDT_LINKFREQ_600MHZ 4
#define K_LDT_LINKFREQ_800MHZ 5
#define K_LDT_LINKFREQ_1000MHZ 6
/*
* LDT SRI Command Register (Table 8-21). Note that these constants
* assume you've read the command and status register together
* 32-bit read at offset 0x50
*/
#define M_LDT_SRICMD_SIPREADY _SB_MAKEMASK1_32(16)
#define M_LDT_SRICMD_SYNCPTRCTL _SB_MAKEMASK1_32(17)
#define M_LDT_SRICMD_REDUCESYNCZERO _SB_MAKEMASK1_32(18)
#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
#define M_LDT_SRICMD_DISSTARVATIONCNT _SB_MAKEMASK1_32(19) /* PASS1 */
#endif /* up to 1250 PASS1 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_LDT_SRICMD_DISMULTTXVLD _SB_MAKEMASK1_32(19)
#define M_LDT_SRICMD_EXPENDIAN _SB_MAKEMASK1_32(26)
#endif /* 1250 PASS2 || 112x PASS1 */
#define S_LDT_SRICMD_RXMARGIN 20
#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5, S_LDT_SRICMD_RXMARGIN)
#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_RXMARGIN)
#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_RXMARGIN, M_LDT_SRICMD_RXMARGIN)
#define M_LDT_SRICMD_LDTPLLCOMPAT _SB_MAKEMASK1_32(25)
#define S_LDT_SRICMD_TXINITIALOFFSET 28
#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3, S_LDT_SRICMD_TXINITIALOFFSET)
#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET)
#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET, M_LDT_SRICMD_TXINITIALOFFSET)
#define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31)
/*
* LDT Error control and status register (Table 8-22) (Table 8-23)
*/
#define M_LDT_ERRCTL_PROTFATAL_EN _SB_MAKEMASK1_32(0)
#define M_LDT_ERRCTL_PROTNONFATAL_EN _SB_MAKEMASK1_32(1)
#define M_LDT_ERRCTL_PROTSYNCFLOOD_EN _SB_MAKEMASK1_32(2)
#define M_LDT_ERRCTL_OVFFATAL_EN _SB_MAKEMASK1_32(3)
#define M_LDT_ERRCTL_OVFNONFATAL_EN _SB_MAKEMASK1_32(4)
#define M_LDT_ERRCTL_OVFSYNCFLOOD_EN _SB_MAKEMASK1_32(5)
#define M_LDT_ERRCTL_EOCNXAFATAL_EN _SB_MAKEMASK1_32(6)
#define M_LDT_ERRCTL_EOCNXANONFATAL_EN _SB_MAKEMASK1_32(7)
#define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN _SB_MAKEMASK1_32(8)
#define M_LDT_ERRCTL_CRCFATAL_EN _SB_MAKEMASK1_32(9)
#define M_LDT_ERRCTL_CRCNONFATAL_EN _SB_MAKEMASK1_32(10)
#define M_LDT_ERRCTL_SERRFATAL_EN _SB_MAKEMASK1_32(11)
#define M_LDT_ERRCTL_SRCTAGFATAL_EN _SB_MAKEMASK1_32(12)
#define M_LDT_ERRCTL_SRCTAGNONFATAL_EN _SB_MAKEMASK1_32(13)
#define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN _SB_MAKEMASK1_32(14)
#define M_LDT_ERRCTL_MAPNXAFATAL_EN _SB_MAKEMASK1_32(15)
#define M_LDT_ERRCTL_MAPNXANONFATAL_EN _SB_MAKEMASK1_32(16)
#define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN _SB_MAKEMASK1_32(17)
#define M_LDT_ERRCTL_PROTOERR _SB_MAKEMASK1_32(24)
#define M_LDT_ERRCTL_OVFERR _SB_MAKEMASK1_32(25)
#define M_LDT_ERRCTL_EOCNXAERR _SB_MAKEMASK1_32(26)
#define M_LDT_ERRCTL_SRCTAGERR _SB_MAKEMASK1_32(27)
#define M_LDT_ERRCTL_MAPNXAERR _SB_MAKEMASK1_32(28)
/*
* SRI Control register (Table 8-24, 8-25) Offset 0x6C
*/
#define S_LDT_SRICTRL_NEEDRESP 0
#define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDRESP)
#define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDRESP)
#define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDRESP, M_LDT_SRICTRL_NEEDRESP)
#define S_LDT_SRICTRL_NEEDNPREQ 2
#define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDNPREQ)
#define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ)
#define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ, M_LDT_SRICTRL_NEEDNPREQ)
#define S_LDT_SRICTRL_NEEDPREQ 4
#define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDPREQ)
#define V_LDT_SRICTRL_NEEDPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ)
#define G_LDT_SRICTRL_NEEDPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ, M_LDT_SRICTRL_NEEDPREQ)
#define S_LDT_SRICTRL_WANTRESP 8
#define M_LDT_SRICTRL_WANTRESP _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTRESP)
#define V_LDT_SRICTRL_WANTRESP(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTRESP)
#define G_LDT_SRICTRL_WANTRESP(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTRESP, M_LDT_SRICTRL_WANTRESP)
#define S_LDT_SRICTRL_WANTNPREQ 10
#define M_LDT_SRICTRL_WANTNPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTNPREQ)
#define V_LDT_SRICTRL_WANTNPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ)
#define G_LDT_SRICTRL_WANTNPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ, M_LDT_SRICTRL_WANTNPREQ)
#define S_LDT_SRICTRL_WANTPREQ 12
#define M_LDT_SRICTRL_WANTPREQ _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTPREQ)
#define V_LDT_SRICTRL_WANTPREQ(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTPREQ)
#define G_LDT_SRICTRL_WANTPREQ(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTPREQ, M_LDT_SRICTRL_WANTPREQ)
#define S_LDT_SRICTRL_BUFRELSPACE 16
#define M_LDT_SRICTRL_BUFRELSPACE _SB_MAKEMASK_32(4, S_LDT_SRICTRL_BUFRELSPACE)
#define V_LDT_SRICTRL_BUFRELSPACE(x) _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE)
#define G_LDT_SRICTRL_BUFRELSPACE(x) _SB_GETVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE, M_LDT_SRICTRL_BUFRELSPACE)
/*
* LDT SRI Transmit Buffer Count register (Table 8-26)
*/
#define S_LDT_TXBUFCNT_PCMD 0
#define M_LDT_TXBUFCNT_PCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PCMD)
#define V_LDT_TXBUFCNT_PCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PCMD)
#define G_LDT_TXBUFCNT_PCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PCMD, M_LDT_TXBUFCNT_PCMD)
#define S_LDT_TXBUFCNT_PDATA 4
#define M_LDT_TXBUFCNT_PDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PDATA)
#define V_LDT_TXBUFCNT_PDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PDATA)
#define G_LDT_TXBUFCNT_PDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PDATA, M_LDT_TXBUFCNT_PDATA)
#define S_LDT_TXBUFCNT_NPCMD 8
#define M_LDT_TXBUFCNT_NPCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPCMD)
#define V_LDT_TXBUFCNT_NPCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPCMD)
#define G_LDT_TXBUFCNT_NPCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPCMD, M_LDT_TXBUFCNT_NPCMD)
#define S_LDT_TXBUFCNT_NPDATA 12
#define M_LDT_TXBUFCNT_NPDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPDATA)
#define V_LDT_TXBUFCNT_NPDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPDATA)
#define G_LDT_TXBUFCNT_NPDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPDATA, M_LDT_TXBUFCNT_NPDATA)
#define S_LDT_TXBUFCNT_RCMD 16
#define M_LDT_TXBUFCNT_RCMD _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RCMD)
#define V_LDT_TXBUFCNT_RCMD(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RCMD)
#define G_LDT_TXBUFCNT_RCMD(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RCMD, M_LDT_TXBUFCNT_RCMD)
#define S_LDT_TXBUFCNT_RDATA 20
#define M_LDT_TXBUFCNT_RDATA _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RDATA)
#define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RDATA)
#define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RDATA, M_LDT_TXBUFCNT_RDATA)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
/*
* Additional Status Register
*/
#define S_LDT_ADDSTATUS_TGTDONE 0
#define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8, S_LDT_ADDSTATUS_TGTDONE)
#define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE)
#define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE, M_LDT_ADDSTATUS_TGTDONE)
#endif /* 1250 PASS2 || 112x PASS1 */
#endif

656
kernel/arch/mips/include/asm/sibyte/sb1250_mac.h Normal file
View File

@@ -0,0 +1,656 @@
/* *********************************************************************
* SB1250 Board Support Package
*
* MAC constants and macros File: sb1250_mac.h
*
* This module contains constants and macros for the SB1250's
* ethernet controllers.
*
* SB1250 specification level: User's manual 1/02/02
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_MAC_H
#define _SB1250_MAC_H
#include "sb1250_defs.h"
/* *********************************************************************
* Ethernet MAC Registers
********************************************************************* */
/*
* MAC Configuration Register (Table 9-13)
* Register: MAC_CFG_0
* Register: MAC_CFG_1
* Register: MAC_CFG_2
*/
#define M_MAC_RESERVED0 _SB_MAKEMASK1(0)
#define M_MAC_TX_HOLD_SOP_EN _SB_MAKEMASK1(1)
#define M_MAC_RETRY_EN _SB_MAKEMASK1(2)
#define M_MAC_RET_DRPREQ_EN _SB_MAKEMASK1(3)
#define M_MAC_RET_UFL_EN _SB_MAKEMASK1(4)
#define M_MAC_BURST_EN _SB_MAKEMASK1(5)
#define S_MAC_TX_PAUSE _SB_MAKE64(6)
#define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3, S_MAC_TX_PAUSE)
#define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x, S_MAC_TX_PAUSE)
#define K_MAC_TX_PAUSE_CNT_512 0
#define K_MAC_TX_PAUSE_CNT_1K 1
#define K_MAC_TX_PAUSE_CNT_2K 2
#define K_MAC_TX_PAUSE_CNT_4K 3
#define K_MAC_TX_PAUSE_CNT_8K 4
#define K_MAC_TX_PAUSE_CNT_16K 5
#define K_MAC_TX_PAUSE_CNT_32K 6
#define K_MAC_TX_PAUSE_CNT_64K 7
#define V_MAC_TX_PAUSE_CNT_512 V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512)
#define V_MAC_TX_PAUSE_CNT_1K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K)
#define V_MAC_TX_PAUSE_CNT_2K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K)
#define V_MAC_TX_PAUSE_CNT_4K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K)
#define V_MAC_TX_PAUSE_CNT_8K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K)
#define V_MAC_TX_PAUSE_CNT_16K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K)
#define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K)
#define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K)
#define M_MAC_RESERVED1 _SB_MAKEMASK(8, 9)
#define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17)
#if SIBYTE_HDR_FEATURE_CHIP(1480)
#define M_MAC_TIMESTAMP _SB_MAKEMASK1(18)
#endif
#define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19)
#define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20)
#define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21)
#define M_MAC_DRP_DRBLERRPKT_EN _SB_MAKEMASK1(22)
#define M_MAC_DRP_RNTPKT_EN _SB_MAKEMASK1(23)
#define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24)
#define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25)
#define M_MAC_RESERVED3 _SB_MAKEMASK(6, 26)
#define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32)
#define M_MAC_HDX_EN _SB_MAKEMASK1(33)
#define S_MAC_SPEED_SEL _SB_MAKE64(34)
#define M_MAC_SPEED_SEL _SB_MAKEMASK(2, S_MAC_SPEED_SEL)
#define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x, S_MAC_SPEED_SEL)
#define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x, S_MAC_SPEED_SEL, M_MAC_SPEED_SEL)
#define K_MAC_SPEED_SEL_10MBPS 0
#define K_MAC_SPEED_SEL_100MBPS 1
#define K_MAC_SPEED_SEL_1000MBPS 2
#define K_MAC_SPEED_SEL_RESERVED 3
#define V_MAC_SPEED_SEL_10MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS)
#define V_MAC_SPEED_SEL_100MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS)
#define V_MAC_SPEED_SEL_1000MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS)
#define V_MAC_SPEED_SEL_RESERVED V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED)
#define M_MAC_TX_CLK_EDGE_SEL _SB_MAKEMASK1(36)
#define M_MAC_LOOPBACK_SEL _SB_MAKEMASK1(37)
#define M_MAC_FAST_SYNC _SB_MAKEMASK1(38)
#define M_MAC_SS_EN _SB_MAKEMASK1(39)
#define S_MAC_BYPASS_CFG _SB_MAKE64(40)
#define M_MAC_BYPASS_CFG _SB_MAKEMASK(2, S_MAC_BYPASS_CFG)
#define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_CFG)
#define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_CFG, M_MAC_BYPASS_CFG)
#define K_MAC_BYPASS_GMII 0
#define K_MAC_BYPASS_ENCODED 1
#define K_MAC_BYPASS_SOP 2
#define K_MAC_BYPASS_EOP 3
#define M_MAC_BYPASS_16 _SB_MAKEMASK1(42)
#define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44)
#endif /* 1250 PASS2 || 112x PASS1 || 1480*/
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45)
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
#define S_MAC_BYPASS_IFG _SB_MAKE64(46)
#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8, S_MAC_BYPASS_IFG)
#define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x, S_MAC_BYPASS_IFG)
#define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x, S_MAC_BYPASS_IFG, M_MAC_BYPASS_IFG)
#define K_MAC_FC_CMD_DISABLED 0
#define K_MAC_FC_CMD_ENABLED 1
#define K_MAC_FC_CMD_ENAB_FALSECARR 2
#define V_MAC_FC_CMD_DISABLED V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED)
#define V_MAC_FC_CMD_ENABLED V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED)
#define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR)
#define M_MAC_FC_SEL _SB_MAKEMASK1(54)
#define S_MAC_FC_CMD _SB_MAKE64(55)
#define M_MAC_FC_CMD _SB_MAKEMASK(2, S_MAC_FC_CMD)
#define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x, S_MAC_FC_CMD)
#define G_MAC_FC_CMD(x) _SB_GETVALUE(x, S_MAC_FC_CMD, M_MAC_FC_CMD)
#define S_MAC_RX_CH_SEL _SB_MAKE64(57)
#define M_MAC_RX_CH_SEL _SB_MAKEMASK(7, S_MAC_RX_CH_SEL)
#define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_SEL)
#define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_SEL, M_MAC_RX_CH_SEL)
/*
* MAC Enable Registers
* Register: MAC_ENABLE_0
* Register: MAC_ENABLE_1
* Register: MAC_ENABLE_2
*/
#define M_MAC_RXDMA_EN0 _SB_MAKEMASK1(0)
#define M_MAC_RXDMA_EN1 _SB_MAKEMASK1(1)
#define M_MAC_TXDMA_EN0 _SB_MAKEMASK1(4)
#define M_MAC_TXDMA_EN1 _SB_MAKEMASK1(5)
#define M_MAC_PORT_RESET _SB_MAKEMASK1(8)
#if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x))
#define M_MAC_RX_ENABLE _SB_MAKEMASK1(10)
#define M_MAC_TX_ENABLE _SB_MAKEMASK1(11)
#define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12)
#define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13)
#endif
/*
* MAC reset information register (1280/1255)
*/
#if SIBYTE_HDR_FEATURE_CHIP(1480)
#define M_MAC_RX_CH0_PAUSE_ON _SB_MAKEMASK1(8)
#define M_MAC_RX_CH1_PAUSE_ON _SB_MAKEMASK1(16)
#define M_MAC_TX_CH0_PAUSE_ON _SB_MAKEMASK1(24)
#define M_MAC_TX_CH1_PAUSE_ON _SB_MAKEMASK1(32)
#endif
/*
* MAC DMA Control Register
* Register: MAC_TXD_CTL_0
* Register: MAC_TXD_CTL_1
* Register: MAC_TXD_CTL_2
*/
#define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0)
#define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT0)
#define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT0)
#define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT0, M_MAC_TXD_WEIGHT0)
#define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4)
#define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT1)
#define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT1)
#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1)
/*
* MAC Fifo Threshold registers (Table 9-14)
* Register: MAC_THRSH_CFG_0
* Register: MAC_THRSH_CFG_1
* Register: MAC_THRSH_CFG_2
*/
#define S_MAC_TX_WR_THRSH _SB_MAKE64(0)
#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
/* XXX: Can't enable, as it has the same name as a pass2+ define below. */
/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6, S_MAC_TX_WR_THRSH) */
#endif /* up to 1250 PASS1 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7, S_MAC_TX_WR_THRSH)
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_WR_THRSH)
#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_WR_THRSH, M_MAC_TX_WR_THRSH)
#define S_MAC_TX_RD_THRSH _SB_MAKE64(8)
#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
/* XXX: Can't enable, as it has the same name as a pass2+ define below. */
/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6, S_MAC_TX_RD_THRSH) */
#endif /* up to 1250 PASS1 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7, S_MAC_TX_RD_THRSH)
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RD_THRSH)
#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RD_THRSH, M_MAC_TX_RD_THRSH)
#define S_MAC_TX_RL_THRSH _SB_MAKE64(16)
#define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4, S_MAC_TX_RL_THRSH)
#define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_TX_RL_THRSH)
#define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_TX_RL_THRSH, M_MAC_TX_RL_THRSH)
#define S_MAC_RX_PL_THRSH _SB_MAKE64(24)
#define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6, S_MAC_RX_PL_THRSH)
#define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_PL_THRSH)
#define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_PL_THRSH, M_MAC_RX_PL_THRSH)
#define S_MAC_RX_RD_THRSH _SB_MAKE64(32)
#define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6, S_MAC_RX_RD_THRSH)
#define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RD_THRSH)
#define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RD_THRSH, M_MAC_RX_RD_THRSH)
#define S_MAC_RX_RL_THRSH _SB_MAKE64(40)
#define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6, S_MAC_RX_RL_THRSH)
#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x, S_MAC_RX_RL_THRSH)
#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x, S_MAC_RX_RL_THRSH, M_MAC_RX_RL_THRSH)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56)
#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6, S_MAC_ENC_FC_THRSH)
#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x, S_MAC_ENC_FC_THRSH)
#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x, S_MAC_ENC_FC_THRSH, M_MAC_ENC_FC_THRSH)
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
/*
* MAC Frame Configuration Registers (Table 9-15)
* Register: MAC_FRAME_CFG_0
* Register: MAC_FRAME_CFG_1
* Register: MAC_FRAME_CFG_2
*/
/* XXXCGD: ??? Unused in pass2? */
#define S_MAC_IFG_RX _SB_MAKE64(0)
#define M_MAC_IFG_RX _SB_MAKEMASK(6, S_MAC_IFG_RX)
#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x, S_MAC_IFG_RX)
#define G_MAC_IFG_RX(x) _SB_GETVALUE(x, S_MAC_IFG_RX, M_MAC_IFG_RX)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define S_MAC_PRE_LEN _SB_MAKE64(0)
#define M_MAC_PRE_LEN _SB_MAKEMASK(6, S_MAC_PRE_LEN)
#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x, S_MAC_PRE_LEN)
#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x, S_MAC_PRE_LEN, M_MAC_PRE_LEN)
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
#define S_MAC_IFG_TX _SB_MAKE64(6)
#define M_MAC_IFG_TX _SB_MAKEMASK(6, S_MAC_IFG_TX)
#define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x, S_MAC_IFG_TX)
#define G_MAC_IFG_TX(x) _SB_GETVALUE(x, S_MAC_IFG_TX, M_MAC_IFG_TX)
#define S_MAC_IFG_THRSH _SB_MAKE64(12)
#define M_MAC_IFG_THRSH _SB_MAKEMASK(6, S_MAC_IFG_THRSH)
#define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x, S_MAC_IFG_THRSH)
#define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x, S_MAC_IFG_THRSH, M_MAC_IFG_THRSH)
#define S_MAC_BACKOFF_SEL _SB_MAKE64(18)
#define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4, S_MAC_BACKOFF_SEL)
#define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x, S_MAC_BACKOFF_SEL)
#define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x, S_MAC_BACKOFF_SEL, M_MAC_BACKOFF_SEL)
#define S_MAC_LFSR_SEED _SB_MAKE64(22)
#define M_MAC_LFSR_SEED _SB_MAKEMASK(8, S_MAC_LFSR_SEED)
#define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x, S_MAC_LFSR_SEED)
#define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x, S_MAC_LFSR_SEED, M_MAC_LFSR_SEED)
#define S_MAC_SLOT_SIZE _SB_MAKE64(30)
#define M_MAC_SLOT_SIZE _SB_MAKEMASK(10, S_MAC_SLOT_SIZE)
#define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x, S_MAC_SLOT_SIZE)
#define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x, S_MAC_SLOT_SIZE, M_MAC_SLOT_SIZE)
#define S_MAC_MIN_FRAMESZ _SB_MAKE64(40)
#define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8, S_MAC_MIN_FRAMESZ)
#define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MIN_FRAMESZ)
#define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MIN_FRAMESZ, M_MAC_MIN_FRAMESZ)
#define S_MAC_MAX_FRAMESZ _SB_MAKE64(48)
#define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16, S_MAC_MAX_FRAMESZ)
#define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x, S_MAC_MAX_FRAMESZ)
#define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x, S_MAC_MAX_FRAMESZ, M_MAC_MAX_FRAMESZ)
/*
* These constants are used to configure the fields within the Frame
* Configuration Register.
*/
#define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */
#define K_MAC_IFG_RX_100 _SB_MAKE64(0)
#define K_MAC_IFG_RX_1000 _SB_MAKE64(0)
#define K_MAC_IFG_TX_10 _SB_MAKE64(20)
#define K_MAC_IFG_TX_100 _SB_MAKE64(20)
#define K_MAC_IFG_TX_1000 _SB_MAKE64(8)
#define K_MAC_IFG_THRSH_10 _SB_MAKE64(4)
#define K_MAC_IFG_THRSH_100 _SB_MAKE64(4)
#define K_MAC_IFG_THRSH_1000 _SB_MAKE64(0)
#define K_MAC_SLOT_SIZE_10 _SB_MAKE64(0)
#define K_MAC_SLOT_SIZE_100 _SB_MAKE64(0)
#define K_MAC_SLOT_SIZE_1000 _SB_MAKE64(0)
#define V_MAC_IFG_RX_10 V_MAC_IFG_RX(K_MAC_IFG_RX_10)
#define V_MAC_IFG_RX_100 V_MAC_IFG_RX(K_MAC_IFG_RX_100)
#define V_MAC_IFG_RX_1000 V_MAC_IFG_RX(K_MAC_IFG_RX_1000)
#define V_MAC_IFG_TX_10 V_MAC_IFG_TX(K_MAC_IFG_TX_10)
#define V_MAC_IFG_TX_100 V_MAC_IFG_TX(K_MAC_IFG_TX_100)
#define V_MAC_IFG_TX_1000 V_MAC_IFG_TX(K_MAC_IFG_TX_1000)
#define V_MAC_IFG_THRSH_10 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_10)
#define V_MAC_IFG_THRSH_100 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_100)
#define V_MAC_IFG_THRSH_1000 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_1000)
#define V_MAC_SLOT_SIZE_10 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_10)
#define V_MAC_SLOT_SIZE_100 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100)
#define V_MAC_SLOT_SIZE_1000 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000)
#define K_MAC_MIN_FRAMESZ_FIFO _SB_MAKE64(9)
#define K_MAC_MIN_FRAMESZ_DEFAULT _SB_MAKE64(64)
#define K_MAC_MAX_FRAMESZ_DEFAULT _SB_MAKE64(1518)
#define K_MAC_MAX_FRAMESZ_JUMBO _SB_MAKE64(9216)
#define V_MAC_MIN_FRAMESZ_FIFO V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO)
#define V_MAC_MIN_FRAMESZ_DEFAULT V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT)
#define V_MAC_MAX_FRAMESZ_DEFAULT V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT)
#define V_MAC_MAX_FRAMESZ_JUMBO V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO)
/*
* MAC VLAN Tag Registers (Table 9-16)
* Register: MAC_VLANTAG_0
* Register: MAC_VLANTAG_1
* Register: MAC_VLANTAG_2
*/
#define S_MAC_VLAN_TAG _SB_MAKE64(0)
#define M_MAC_VLAN_TAG _SB_MAKEMASK(32, S_MAC_VLAN_TAG)
#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x, S_MAC_VLAN_TAG)
#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x, S_MAC_VLAN_TAG, M_MAC_VLAN_TAG)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32)
#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_TX_PKT_OFFSET)
#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_PKT_OFFSET)
#define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_PKT_OFFSET, M_MAC_TX_PKT_OFFSET)
#define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40)
#define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_TX_CRC_OFFSET)
#define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_TX_CRC_OFFSET)
#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_TX_CRC_OFFSET, M_MAC_TX_CRC_OFFSET)
#define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48)
#endif /* 1250 PASS3 || 112x PASS1 */
/*
* MAC Status Registers (Table 9-17)
* Also used for the MAC Interrupt Mask Register (Table 9-18)
* Register: MAC_STATUS_0
* Register: MAC_STATUS_1
* Register: MAC_STATUS_2
* Register: MAC_INT_MASK_0
* Register: MAC_INT_MASK_1
* Register: MAC_INT_MASK_2
*/
/*
* Use these constants to shift the appropriate channel
* into the CH0 position so the same tests can be used
* on each channel.
*/
#define S_MAC_RX_CH0 _SB_MAKE64(0)
#define S_MAC_RX_CH1 _SB_MAKE64(8)
#define S_MAC_TX_CH0 _SB_MAKE64(16)
#define S_MAC_TX_CH1 _SB_MAKE64(24)
#define S_MAC_TXCHANNELS _SB_MAKE64(16) /* this is 1st TX chan */
#define S_MAC_CHANWIDTH _SB_MAKE64(8) /* bits between channels */
/*
* These are the same as RX channel 0. The idea here
* is that you'll use one of the "S_" things above
* and pass just the six bits to a DMA-channel-specific ISR
*/
#define M_MAC_INT_CHANNEL _SB_MAKEMASK(8, 0)
#define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0)
#define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1)
#define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2)
#define M_MAC_INT_HWM _SB_MAKEMASK1(3)
#define M_MAC_INT_LWM _SB_MAKEMASK1(4)
#define M_MAC_INT_DSCR _SB_MAKEMASK1(5)
#define M_MAC_INT_ERR _SB_MAKEMASK1(6)
#define M_MAC_INT_DZERO _SB_MAKEMASK1(7) /* only for TX channels */
#define M_MAC_INT_DROP _SB_MAKEMASK1(7) /* only for RX channels */
/*
* In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see
* also DMA_TX/DMA_RX in sb_regs.h).
*/
#define S_MAC_STATUS_CH_OFFSET(ch, txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH)
#define M_MAC_STATUS_CHANNEL(ch, txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8, 0), S_MAC_STATUS_CH_OFFSET(ch, txrx))
#define M_MAC_STATUS_EOP_COUNT(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT, S_MAC_STATUS_CH_OFFSET(ch, txrx))
#define M_MAC_STATUS_EOP_TIMER(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER, S_MAC_STATUS_CH_OFFSET(ch, txrx))
#define M_MAC_STATUS_EOP_SEEN(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN, S_MAC_STATUS_CH_OFFSET(ch, txrx))
#define M_MAC_STATUS_HWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_HWM, S_MAC_STATUS_CH_OFFSET(ch, txrx))
#define M_MAC_STATUS_LWM(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_LWM, S_MAC_STATUS_CH_OFFSET(ch, txrx))
#define M_MAC_STATUS_DSCR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR, S_MAC_STATUS_CH_OFFSET(ch, txrx))
#define M_MAC_STATUS_ERR(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_ERR, S_MAC_STATUS_CH_OFFSET(ch, txrx))
#define M_MAC_STATUS_DZERO(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO, S_MAC_STATUS_CH_OFFSET(ch, txrx))
#define M_MAC_STATUS_DROP(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_DROP, S_MAC_STATUS_CH_OFFSET(ch, txrx))
#define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7, 0), 40)
#define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40)
#define M_MAC_RX_OVRFL _SB_MAKEMASK1(41)
#define M_MAC_TX_UNDRFL _SB_MAKEMASK1(42)
#define M_MAC_TX_OVRFL _SB_MAKEMASK1(43)
#define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44)
#define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45)
#define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
#define S_MAC_COUNTER_ADDR _SB_MAKE64(47)
#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5, S_MAC_COUNTER_ADDR)
#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x, S_MAC_COUNTER_ADDR)
#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x, S_MAC_COUNTER_ADDR, M_MAC_COUNTER_ADDR)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52)
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
/*
* MAC Fifo Pointer Registers (Table 9-19) [Debug register]
* Register: MAC_FIFO_PTRS_0
* Register: MAC_FIFO_PTRS_1
* Register: MAC_FIFO_PTRS_2
*/
#define S_MAC_TX_WRPTR _SB_MAKE64(0)
#define M_MAC_TX_WRPTR _SB_MAKEMASK(6, S_MAC_TX_WRPTR)
#define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_WRPTR)
#define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x, S_MAC_TX_WRPTR, M_MAC_TX_WRPTR)
#define S_MAC_TX_RDPTR _SB_MAKE64(8)
#define M_MAC_TX_RDPTR _SB_MAKEMASK(6, S_MAC_TX_RDPTR)
#define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_TX_RDPTR)
#define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x, S_MAC_TX_RDPTR, M_MAC_TX_RDPTR)
#define S_MAC_RX_WRPTR _SB_MAKE64(16)
#define M_MAC_RX_WRPTR _SB_MAKEMASK(6, S_MAC_RX_WRPTR)
#define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_WRPTR)
#define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x, S_MAC_RX_WRPTR, M_MAC_TX_WRPTR)
#define S_MAC_RX_RDPTR _SB_MAKE64(24)
#define M_MAC_RX_RDPTR _SB_MAKEMASK(6, S_MAC_RX_RDPTR)
#define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x, S_MAC_RX_RDPTR)
#define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x, S_MAC_RX_RDPTR, M_MAC_TX_RDPTR)
/*
* MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register]
* Register: MAC_EOPCNT_0
* Register: MAC_EOPCNT_1
* Register: MAC_EOPCNT_2
*/
#define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0)
#define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_TX_EOP_COUNTER)
#define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_TX_EOP_COUNTER)
#define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_TX_EOP_COUNTER, M_MAC_TX_EOP_COUNTER)
#define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8)
#define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6, S_MAC_RX_EOP_COUNTER)
#define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x, S_MAC_RX_EOP_COUNTER)
#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER)
/*
* MAC Receive Address Filter Exact Match Registers (Table 9-21)
* Registers: MAC_ADDR0_0 through MAC_ADDR7_0
* Registers: MAC_ADDR0_1 through MAC_ADDR7_1
* Registers: MAC_ADDR0_2 through MAC_ADDR7_2
*/
/* No bitfields */
/*
* MAC Receive Address Filter Mask Registers
* Registers: MAC_ADDRMASK0_0 and MAC_ADDRMASK0_1
* Registers: MAC_ADDRMASK1_0 and MAC_ADDRMASK1_1
* Registers: MAC_ADDRMASK2_0 and MAC_ADDRMASK2_1
*/
/* No bitfields */
/*
* MAC Receive Address Filter Hash Match Registers (Table 9-22)
* Registers: MAC_HASH0_0 through MAC_HASH7_0
* Registers: MAC_HASH0_1 through MAC_HASH7_1
* Registers: MAC_HASH0_2 through MAC_HASH7_2
*/
/* No bitfields */
/*
* MAC Transmit Source Address Registers (Table 9-23)
* Register: MAC_ETHERNET_ADDR_0
* Register: MAC_ETHERNET_ADDR_1
* Register: MAC_ETHERNET_ADDR_2
*/
/* No bitfields */
/*
* MAC Packet Type Configuration Register
* Register: MAC_TYPE_CFG_0
* Register: MAC_TYPE_CFG_1
* Register: MAC_TYPE_CFG_2
*/
#define S_TYPECFG_TYPESIZE _SB_MAKE64(16)
#define S_TYPECFG_TYPE0 _SB_MAKE64(0)
#define M_TYPECFG_TYPE0 _SB_MAKEMASK(16, S_TYPECFG_TYPE0)
#define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE0)
#define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x, S_TYPECFG_TYPE0, M_TYPECFG_TYPE0)
#define S_TYPECFG_TYPE1 _SB_MAKE64(0)
#define M_TYPECFG_TYPE1 _SB_MAKEMASK(16, S_TYPECFG_TYPE1)
#define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE1)
#define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x, S_TYPECFG_TYPE1, M_TYPECFG_TYPE1)
#define S_TYPECFG_TYPE2 _SB_MAKE64(0)
#define M_TYPECFG_TYPE2 _SB_MAKEMASK(16, S_TYPECFG_TYPE2)
#define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE2)
#define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x, S_TYPECFG_TYPE2, M_TYPECFG_TYPE2)
#define S_TYPECFG_TYPE3 _SB_MAKE64(0)
#define M_TYPECFG_TYPE3 _SB_MAKEMASK(16, S_TYPECFG_TYPE3)
#define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x, S_TYPECFG_TYPE3)
#define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x, S_TYPECFG_TYPE3, M_TYPECFG_TYPE3)
/*
* MAC Receive Address Filter Control Registers (Table 9-24)
* Register: MAC_ADFILTER_CFG_0
* Register: MAC_ADFILTER_CFG_1
* Register: MAC_ADFILTER_CFG_2
*/
#define M_MAC_ALLPKT_EN _SB_MAKEMASK1(0)
#define M_MAC_UCAST_EN _SB_MAKEMASK1(1)
#define M_MAC_UCAST_INV _SB_MAKEMASK1(2)
#define M_MAC_MCAST_EN _SB_MAKEMASK1(3)
#define M_MAC_MCAST_INV _SB_MAKEMASK1(4)
#define M_MAC_BCAST_EN _SB_MAKEMASK1(5)
#define M_MAC_DIRECT_INV _SB_MAKEMASK1(6)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7)
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
#define S_MAC_IPHDR_OFFSET _SB_MAKE64(8)
#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8, S_MAC_IPHDR_OFFSET)
#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_IPHDR_OFFSET)
#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x, S_MAC_IPHDR_OFFSET, M_MAC_IPHDR_OFFSET)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16)
#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8, S_MAC_RX_CRC_OFFSET)
#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_CRC_OFFSET)
#define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_CRC_OFFSET, M_MAC_RX_CRC_OFFSET)
#define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24)
#define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8, S_MAC_RX_PKT_OFFSET)
#define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_PKT_OFFSET)
#define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_PKT_OFFSET, M_MAC_RX_PKT_OFFSET)
#define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32)
#define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33)
#define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34)
#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8, S_MAC_RX_CH_MSN_SEL)
#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_MSN_SEL)
#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_MSN_SEL, M_MAC_RX_CH_MSN_SEL)
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
/*
* MAC Receive Channel Select Registers (Table 9-25)
*/
/* no bitfields */
/*
* MAC MII Management Interface Registers (Table 9-26)
* Register: MAC_MDIO_0
* Register: MAC_MDIO_1
* Register: MAC_MDIO_2
*/
#define S_MAC_MDC 0
#define S_MAC_MDIO_DIR 1
#define S_MAC_MDIO_OUT 2
#define S_MAC_GENC 3
#define S_MAC_MDIO_IN 4
#define M_MAC_MDC _SB_MAKEMASK1(S_MAC_MDC)
#define M_MAC_MDIO_DIR _SB_MAKEMASK1(S_MAC_MDIO_DIR)
#define M_MAC_MDIO_DIR_INPUT _SB_MAKEMASK1(S_MAC_MDIO_DIR)
#define M_MAC_MDIO_OUT _SB_MAKEMASK1(S_MAC_MDIO_OUT)
#define M_MAC_GENC _SB_MAKEMASK1(S_MAC_GENC)
#define M_MAC_MDIO_IN _SB_MAKEMASK1(S_MAC_MDIO_IN)
#endif

550
kernel/arch/mips/include/asm/sibyte/sb1250_mc.h Normal file
View File

@@ -0,0 +1,550 @@
/* *********************************************************************
* SB1250 Board Support Package
*
* Memory Controller constants File: sb1250_mc.h
*
* This module contains constants and macros useful for
* programming the memory controller.
*
* SB1250 specification level: User's manual 1/02/02
*
*********************************************************************
*
* Copyright 2000, 2001, 2002, 2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_MC_H
#define _SB1250_MC_H
#include "sb1250_defs.h"
/*
* Memory Channel Config Register (table 6-14)
*/
#define S_MC_RESERVED0 0
#define M_MC_RESERVED0 _SB_MAKEMASK(8, S_MC_RESERVED0)
#define S_MC_CHANNEL_SEL 8
#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8, S_MC_CHANNEL_SEL)
#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL)
#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL)
#define S_MC_BANK0_MAP 16
#define M_MC_BANK0_MAP _SB_MAKEMASK(4, S_MC_BANK0_MAP)
#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK0_MAP)
#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP)
#define K_MC_BANK0_MAP_DEFAULT 0x00
#define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT)
#define S_MC_BANK1_MAP 20
#define M_MC_BANK1_MAP _SB_MAKEMASK(4, S_MC_BANK1_MAP)
#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK1_MAP)
#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP)
#define K_MC_BANK1_MAP_DEFAULT 0x08
#define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT)
#define S_MC_BANK2_MAP 24
#define M_MC_BANK2_MAP _SB_MAKEMASK(4, S_MC_BANK2_MAP)
#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK2_MAP)
#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x, S_MC_BANK2_MAP, M_MC_BANK2_MAP)
#define K_MC_BANK2_MAP_DEFAULT 0x09
#define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT)
#define S_MC_BANK3_MAP 28
#define M_MC_BANK3_MAP _SB_MAKEMASK(4, S_MC_BANK3_MAP)
#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x, S_MC_BANK3_MAP)
#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x, S_MC_BANK3_MAP, M_MC_BANK3_MAP)
#define K_MC_BANK3_MAP_DEFAULT 0x0C
#define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT)
#define M_MC_RESERVED1 _SB_MAKEMASK(8, 32)
#define S_MC_QUEUE_SIZE 40
#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4, S_MC_QUEUE_SIZE)
#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x, S_MC_QUEUE_SIZE)
#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x, S_MC_QUEUE_SIZE, M_MC_QUEUE_SIZE)
#define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A)
#define S_MC_AGE_LIMIT 44
#define M_MC_AGE_LIMIT _SB_MAKEMASK(4, S_MC_AGE_LIMIT)
#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x, S_MC_AGE_LIMIT)
#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x, S_MC_AGE_LIMIT, M_MC_AGE_LIMIT)
#define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8)
#define S_MC_WR_LIMIT 48
#define M_MC_WR_LIMIT _SB_MAKEMASK(4, S_MC_WR_LIMIT)
#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x, S_MC_WR_LIMIT)
#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x, S_MC_WR_LIMIT, M_MC_WR_LIMIT)
#define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5)
#define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52)
#define M_MC_RESERVED2 _SB_MAKEMASK(3, 53)
#define S_MC_CS_MODE 56
#define M_MC_CS_MODE _SB_MAKEMASK(4, S_MC_CS_MODE)
#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x, S_MC_CS_MODE)
#define G_MC_CS_MODE(x) _SB_GETVALUE(x, S_MC_CS_MODE, M_MC_CS_MODE)
#define K_MC_CS_MODE_MSB_CS 0
#define K_MC_CS_MODE_INTLV_CS 15
#define K_MC_CS_MODE_MIXED_CS_10 12
#define K_MC_CS_MODE_MIXED_CS_30 6
#define K_MC_CS_MODE_MIXED_CS_32 3
#define V_MC_CS_MODE_MSB_CS V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS)
#define V_MC_CS_MODE_INTLV_CS V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS)
#define V_MC_CS_MODE_MIXED_CS_10 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10)
#define V_MC_CS_MODE_MIXED_CS_30 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30)
#define V_MC_CS_MODE_MIXED_CS_32 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32)
#define M_MC_ECC_DISABLE _SB_MAKEMASK1(60)
#define M_MC_BERR_DISABLE _SB_MAKEMASK1(61)
#define M_MC_FORCE_SEQ _SB_MAKEMASK1(62)
#define M_MC_DEBUG _SB_MAKEMASK1(63)
#define V_MC_CONFIG_DEFAULT V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \
V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \
V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \
M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT
/*
* Memory clock config register (Table 6-15)
*
* Note: this field has been updated to be consistent with the errata to 0.2
*/
#define S_MC_CLK_RATIO 0
#define M_MC_CLK_RATIO _SB_MAKEMASK(4, S_MC_CLK_RATIO)
#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x, S_MC_CLK_RATIO)
#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x, S_MC_CLK_RATIO, M_MC_CLK_RATIO)
#define K_MC_CLK_RATIO_2X 4
#define K_MC_CLK_RATIO_25X 5
#define K_MC_CLK_RATIO_3X 6
#define K_MC_CLK_RATIO_35X 7
#define K_MC_CLK_RATIO_4X 8
#define K_MC_CLK_RATIO_45X 9
#define V_MC_CLK_RATIO_2X V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X)
#define V_MC_CLK_RATIO_25X V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X)
#define V_MC_CLK_RATIO_3X V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X)
#define V_MC_CLK_RATIO_35X V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X)
#define V_MC_CLK_RATIO_4X V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X)
#define V_MC_CLK_RATIO_45X V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X)
#define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X
#define S_MC_REF_RATE 8
#define M_MC_REF_RATE _SB_MAKEMASK(8, S_MC_REF_RATE)
#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x, S_MC_REF_RATE)
#define G_MC_REF_RATE(x) _SB_GETVALUE(x, S_MC_REF_RATE, M_MC_REF_RATE)
#define K_MC_REF_RATE_100MHz 0x62
#define K_MC_REF_RATE_133MHz 0x81
#define K_MC_REF_RATE_200MHz 0xC4
#define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz)
#define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz)
#define V_MC_REF_RATE_200MHz V_MC_REF_RATE(K_MC_REF_RATE_200MHz)
#define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz
#define S_MC_CLOCK_DRIVE 16
#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4, S_MC_CLOCK_DRIVE)
#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x, S_MC_CLOCK_DRIVE)
#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x, S_MC_CLOCK_DRIVE, M_MC_CLOCK_DRIVE)
#define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF)
#define S_MC_DATA_DRIVE 20
#define M_MC_DATA_DRIVE _SB_MAKEMASK(4, S_MC_DATA_DRIVE)
#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x, S_MC_DATA_DRIVE)
#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x, S_MC_DATA_DRIVE, M_MC_DATA_DRIVE)
#define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0)
#define S_MC_ADDR_DRIVE 24
#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4, S_MC_ADDR_DRIVE)
#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x, S_MC_ADDR_DRIVE)
#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x, S_MC_ADDR_DRIVE, M_MC_ADDR_DRIVE)
#define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_MC_REF_DISABLE _SB_MAKEMASK1(30)
#endif /* 1250 PASS3 || 112x PASS1 */
#define M_MC_DLL_BYPASS _SB_MAKEMASK1(31)
#define S_MC_DQI_SKEW 32
#define M_MC_DQI_SKEW _SB_MAKEMASK(8, S_MC_DQI_SKEW)
#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQI_SKEW)
#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x, S_MC_DQI_SKEW, M_MC_DQI_SKEW)
#define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0)
#define S_MC_DQO_SKEW 40
#define M_MC_DQO_SKEW _SB_MAKEMASK(8, S_MC_DQO_SKEW)
#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x, S_MC_DQO_SKEW)
#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x, S_MC_DQO_SKEW, M_MC_DQO_SKEW)
#define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0)
#define S_MC_ADDR_SKEW 48
#define M_MC_ADDR_SKEW _SB_MAKEMASK(8, S_MC_ADDR_SKEW)
#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x, S_MC_ADDR_SKEW)
#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x, S_MC_ADDR_SKEW, M_MC_ADDR_SKEW)
#define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F)
#define S_MC_DLL_DEFAULT 56
#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8, S_MC_DLL_DEFAULT)
#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x, S_MC_DLL_DEFAULT)
#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x, S_MC_DLL_DEFAULT, M_MC_DLL_DEFAULT)
#define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10)
#define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \
V_MC_ADDR_SKEW_DEFAULT | \
V_MC_DQO_SKEW_DEFAULT | \
V_MC_DQI_SKEW_DEFAULT | \
V_MC_ADDR_DRIVE_DEFAULT | \
V_MC_DATA_DRIVE_DEFAULT | \
V_MC_CLOCK_DRIVE_DEFAULT | \
V_MC_REF_RATE_DEFAULT
/*
* DRAM Command Register (Table 6-13)
*/
#define S_MC_COMMAND 0
#define M_MC_COMMAND _SB_MAKEMASK(4, S_MC_COMMAND)
#define V_MC_COMMAND(x) _SB_MAKEVALUE(x, S_MC_COMMAND)
#define G_MC_COMMAND(x) _SB_GETVALUE(x, S_MC_COMMAND, M_MC_COMMAND)
#define K_MC_COMMAND_EMRS 0
#define K_MC_COMMAND_MRS 1
#define K_MC_COMMAND_PRE 2
#define K_MC_COMMAND_AR 3
#define K_MC_COMMAND_SETRFSH 4
#define K_MC_COMMAND_CLRRFSH 5
#define K_MC_COMMAND_SETPWRDN 6
#define K_MC_COMMAND_CLRPWRDN 7
#define V_MC_COMMAND_EMRS V_MC_COMMAND(K_MC_COMMAND_EMRS)
#define V_MC_COMMAND_MRS V_MC_COMMAND(K_MC_COMMAND_MRS)
#define V_MC_COMMAND_PRE V_MC_COMMAND(K_MC_COMMAND_PRE)
#define V_MC_COMMAND_AR V_MC_COMMAND(K_MC_COMMAND_AR)
#define V_MC_COMMAND_SETRFSH V_MC_COMMAND(K_MC_COMMAND_SETRFSH)
#define V_MC_COMMAND_CLRRFSH V_MC_COMMAND(K_MC_COMMAND_CLRRFSH)
#define V_MC_COMMAND_SETPWRDN V_MC_COMMAND(K_MC_COMMAND_SETPWRDN)
#define V_MC_COMMAND_CLRPWRDN V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN)
#define M_MC_CS0 _SB_MAKEMASK1(4)
#define M_MC_CS1 _SB_MAKEMASK1(5)
#define M_MC_CS2 _SB_MAKEMASK1(6)
#define M_MC_CS3 _SB_MAKEMASK1(7)
/*
* DRAM Mode Register (Table 6-14)
*/
#define S_MC_EMODE 0
#define M_MC_EMODE _SB_MAKEMASK(15, S_MC_EMODE)
#define V_MC_EMODE(x) _SB_MAKEVALUE(x, S_MC_EMODE)
#define G_MC_EMODE(x) _SB_GETVALUE(x, S_MC_EMODE, M_MC_EMODE)
#define V_MC_EMODE_DEFAULT V_MC_EMODE(0)
#define S_MC_MODE 16
#define M_MC_MODE _SB_MAKEMASK(15, S_MC_MODE)
#define V_MC_MODE(x) _SB_MAKEVALUE(x, S_MC_MODE)
#define G_MC_MODE(x) _SB_GETVALUE(x, S_MC_MODE, M_MC_MODE)
#define V_MC_MODE_DEFAULT V_MC_MODE(0x22)
#define S_MC_DRAM_TYPE 32
#define M_MC_DRAM_TYPE _SB_MAKEMASK(3, S_MC_DRAM_TYPE)
#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x, S_MC_DRAM_TYPE)
#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x, S_MC_DRAM_TYPE, M_MC_DRAM_TYPE)
#define K_MC_DRAM_TYPE_JEDEC 0
#define K_MC_DRAM_TYPE_FCRAM 1
#define K_MC_DRAM_TYPE_SGRAM 2
#define V_MC_DRAM_TYPE_JEDEC V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC)
#define V_MC_DRAM_TYPE_FCRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM)
#define V_MC_DRAM_TYPE_SGRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM)
#define M_MC_EXTERNALDECODE _SB_MAKEMASK1(35)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36)
#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(37)
#endif /* 1250 PASS3 || 112x PASS1 */
/*
* SDRAM Timing Register (Table 6-15)
*/
#define M_MC_w2rIDLE_TWOCYCLES _SB_MAKEMASK1(60)
#define M_MC_r2wIDLE_TWOCYCLES _SB_MAKEMASK1(61)
#define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62)
#define S_MC_tFIFO 56
#define M_MC_tFIFO _SB_MAKEMASK(4, S_MC_tFIFO)
#define V_MC_tFIFO(x) _SB_MAKEVALUE(x, S_MC_tFIFO)
#define G_MC_tFIFO(x) _SB_GETVALUE(x, S_MC_tFIFO, M_MC_tFIFO)
#define K_MC_tFIFO_DEFAULT 1
#define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT)
#define S_MC_tRFC 52
#define M_MC_tRFC _SB_MAKEMASK(4, S_MC_tRFC)
#define V_MC_tRFC(x) _SB_MAKEVALUE(x, S_MC_tRFC)
#define G_MC_tRFC(x) _SB_GETVALUE(x, S_MC_tRFC, M_MC_tRFC)
#define K_MC_tRFC_DEFAULT 12
#define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT)
#if SIBYTE_HDR_FEATURE(1250, PASS3)
#define M_MC_tRFC_PLUS16 _SB_MAKEMASK1(51) /* 1250C3 and later. */
#endif
#define S_MC_tCwCr 40
#define M_MC_tCwCr _SB_MAKEMASK(4, S_MC_tCwCr)
#define V_MC_tCwCr(x) _SB_MAKEVALUE(x, S_MC_tCwCr)
#define G_MC_tCwCr(x) _SB_GETVALUE(x, S_MC_tCwCr, M_MC_tCwCr)
#define K_MC_tCwCr_DEFAULT 4
#define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT)
#define S_MC_tRCr 28
#define M_MC_tRCr _SB_MAKEMASK(4, S_MC_tRCr)
#define V_MC_tRCr(x) _SB_MAKEVALUE(x, S_MC_tRCr)
#define G_MC_tRCr(x) _SB_GETVALUE(x, S_MC_tRCr, M_MC_tRCr)
#define K_MC_tRCr_DEFAULT 9
#define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT)
#define S_MC_tRCw 24
#define M_MC_tRCw _SB_MAKEMASK(4, S_MC_tRCw)
#define V_MC_tRCw(x) _SB_MAKEVALUE(x, S_MC_tRCw)
#define G_MC_tRCw(x) _SB_GETVALUE(x, S_MC_tRCw, M_MC_tRCw)
#define K_MC_tRCw_DEFAULT 10
#define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT)
#define S_MC_tRRD 20
#define M_MC_tRRD _SB_MAKEMASK(4, S_MC_tRRD)
#define V_MC_tRRD(x) _SB_MAKEVALUE(x, S_MC_tRRD)
#define G_MC_tRRD(x) _SB_GETVALUE(x, S_MC_tRRD, M_MC_tRRD)
#define K_MC_tRRD_DEFAULT 2
#define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT)
#define S_MC_tRP 16
#define M_MC_tRP _SB_MAKEMASK(4, S_MC_tRP)
#define V_MC_tRP(x) _SB_MAKEVALUE(x, S_MC_tRP)
#define G_MC_tRP(x) _SB_GETVALUE(x, S_MC_tRP, M_MC_tRP)
#define K_MC_tRP_DEFAULT 4
#define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT)
#define S_MC_tCwD 8
#define M_MC_tCwD _SB_MAKEMASK(4, S_MC_tCwD)
#define V_MC_tCwD(x) _SB_MAKEVALUE(x, S_MC_tCwD)
#define G_MC_tCwD(x) _SB_GETVALUE(x, S_MC_tCwD, M_MC_tCwD)
#define K_MC_tCwD_DEFAULT 1
#define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT)
#define M_tCrDh _SB_MAKEMASK1(7)
#define M_MC_tCrDh M_tCrDh
#define S_MC_tCrD 4
#define M_MC_tCrD _SB_MAKEMASK(3, S_MC_tCrD)
#define V_MC_tCrD(x) _SB_MAKEVALUE(x, S_MC_tCrD)
#define G_MC_tCrD(x) _SB_GETVALUE(x, S_MC_tCrD, M_MC_tCrD)
#define K_MC_tCrD_DEFAULT 2
#define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT)
#define S_MC_tRCD 0
#define M_MC_tRCD _SB_MAKEMASK(4, S_MC_tRCD)
#define V_MC_tRCD(x) _SB_MAKEVALUE(x, S_MC_tRCD)
#define G_MC_tRCD(x) _SB_GETVALUE(x, S_MC_tRCD, M_MC_tRCD)
#define K_MC_tRCD_DEFAULT 3
#define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT)
#define V_MC_TIMING_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \
V_MC_tRFC(K_MC_tRFC_DEFAULT) | \
V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \
V_MC_tRCr(K_MC_tRCr_DEFAULT) | \
V_MC_tRCw(K_MC_tRCw_DEFAULT) | \
V_MC_tRRD(K_MC_tRRD_DEFAULT) | \
V_MC_tRP(K_MC_tRP_DEFAULT) | \
V_MC_tCwD(K_MC_tCwD_DEFAULT) | \
V_MC_tCrD(K_MC_tCrD_DEFAULT) | \
V_MC_tRCD(K_MC_tRCD_DEFAULT) | \
M_MC_r2rIDLE_TWOCYCLES
/*
* Errata says these are not the default
* M_MC_w2rIDLE_TWOCYCLES | \
* M_MC_r2wIDLE_TWOCYCLES | \
*/
/*
* Chip Select Start Address Register (Table 6-17)
*/
#define S_MC_CS0_START 0
#define M_MC_CS0_START _SB_MAKEMASK(16, S_MC_CS0_START)
#define V_MC_CS0_START(x) _SB_MAKEVALUE(x, S_MC_CS0_START)
#define G_MC_CS0_START(x) _SB_GETVALUE(x, S_MC_CS0_START, M_MC_CS0_START)
#define S_MC_CS1_START 16
#define M_MC_CS1_START _SB_MAKEMASK(16, S_MC_CS1_START)
#define V_MC_CS1_START(x) _SB_MAKEVALUE(x, S_MC_CS1_START)
#define G_MC_CS1_START(x) _SB_GETVALUE(x, S_MC_CS1_START, M_MC_CS1_START)
#define S_MC_CS2_START 32
#define M_MC_CS2_START _SB_MAKEMASK(16, S_MC_CS2_START)
#define V_MC_CS2_START(x) _SB_MAKEVALUE(x, S_MC_CS2_START)
#define G_MC_CS2_START(x) _SB_GETVALUE(x, S_MC_CS2_START, M_MC_CS2_START)
#define S_MC_CS3_START 48
#define M_MC_CS3_START _SB_MAKEMASK(16, S_MC_CS3_START)
#define V_MC_CS3_START(x) _SB_MAKEVALUE(x, S_MC_CS3_START)
#define G_MC_CS3_START(x) _SB_GETVALUE(x, S_MC_CS3_START, M_MC_CS3_START)
/*
* Chip Select End Address Register (Table 6-18)
*/
#define S_MC_CS0_END 0
#define M_MC_CS0_END _SB_MAKEMASK(16, S_MC_CS0_END)
#define V_MC_CS0_END(x) _SB_MAKEVALUE(x, S_MC_CS0_END)
#define G_MC_CS0_END(x) _SB_GETVALUE(x, S_MC_CS0_END, M_MC_CS0_END)
#define S_MC_CS1_END 16
#define M_MC_CS1_END _SB_MAKEMASK(16, S_MC_CS1_END)
#define V_MC_CS1_END(x) _SB_MAKEVALUE(x, S_MC_CS1_END)
#define G_MC_CS1_END(x) _SB_GETVALUE(x, S_MC_CS1_END, M_MC_CS1_END)
#define S_MC_CS2_END 32
#define M_MC_CS2_END _SB_MAKEMASK(16, S_MC_CS2_END)
#define V_MC_CS2_END(x) _SB_MAKEVALUE(x, S_MC_CS2_END)
#define G_MC_CS2_END(x) _SB_GETVALUE(x, S_MC_CS2_END, M_MC_CS2_END)
#define S_MC_CS3_END 48
#define M_MC_CS3_END _SB_MAKEMASK(16, S_MC_CS3_END)
#define V_MC_CS3_END(x) _SB_MAKEVALUE(x, S_MC_CS3_END)
#define G_MC_CS3_END(x) _SB_GETVALUE(x, S_MC_CS3_END, M_MC_CS3_END)
/*
* Chip Select Interleave Register (Table 6-19)
*/
#define S_MC_INTLV_RESERVED 0
#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5, S_MC_INTLV_RESERVED)
#define S_MC_INTERLEAVE 7
#define M_MC_INTERLEAVE _SB_MAKEMASK(18, S_MC_INTERLEAVE)
#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x, S_MC_INTERLEAVE)
#define S_MC_INTLV_MBZ 25
#define M_MC_INTLV_MBZ _SB_MAKEMASK(39, S_MC_INTLV_MBZ)
/*
* Row Address Bits Register (Table 6-20)
*/
#define S_MC_RAS_RESERVED 0
#define M_MC_RAS_RESERVED _SB_MAKEMASK(5, S_MC_RAS_RESERVED)
#define S_MC_RAS_SELECT 12
#define M_MC_RAS_SELECT _SB_MAKEMASK(25, S_MC_RAS_SELECT)
#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_RAS_SELECT)
#define S_MC_RAS_MBZ 37
#define M_MC_RAS_MBZ _SB_MAKEMASK(27, S_MC_RAS_MBZ)
/*
* Column Address Bits Register (Table 6-21)
*/
#define S_MC_CAS_RESERVED 0
#define M_MC_CAS_RESERVED _SB_MAKEMASK(5, S_MC_CAS_RESERVED)
#define S_MC_CAS_SELECT 5
#define M_MC_CAS_SELECT _SB_MAKEMASK(18, S_MC_CAS_SELECT)
#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x, S_MC_CAS_SELECT)
#define S_MC_CAS_MBZ 23
#define M_MC_CAS_MBZ _SB_MAKEMASK(41, S_MC_CAS_MBZ)
/*
* Bank Address Address Bits Register (Table 6-22)
*/
#define S_MC_BA_RESERVED 0
#define M_MC_BA_RESERVED _SB_MAKEMASK(5, S_MC_BA_RESERVED)
#define S_MC_BA_SELECT 5
#define M_MC_BA_SELECT _SB_MAKEMASK(20, S_MC_BA_SELECT)
#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x, S_MC_BA_SELECT)
#define S_MC_BA_MBZ 25
#define M_MC_BA_MBZ _SB_MAKEMASK(39, S_MC_BA_MBZ)
/*
* Chip Select Attribute Register (Table 6-23)
*/
#define K_MC_CS_ATTR_CLOSED 0
#define K_MC_CS_ATTR_CASCHECK 1
#define K_MC_CS_ATTR_HINT 2
#define K_MC_CS_ATTR_OPEN 3
#define S_MC_CS0_PAGE 0
#define M_MC_CS0_PAGE _SB_MAKEMASK(2, S_MC_CS0_PAGE)
#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS0_PAGE)
#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x, S_MC_CS0_PAGE, M_MC_CS0_PAGE)
#define S_MC_CS1_PAGE 16
#define M_MC_CS1_PAGE _SB_MAKEMASK(2, S_MC_CS1_PAGE)
#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS1_PAGE)
#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x, S_MC_CS1_PAGE, M_MC_CS1_PAGE)
#define S_MC_CS2_PAGE 32
#define M_MC_CS2_PAGE _SB_MAKEMASK(2, S_MC_CS2_PAGE)
#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS2_PAGE)
#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x, S_MC_CS2_PAGE, M_MC_CS2_PAGE)
#define S_MC_CS3_PAGE 48
#define M_MC_CS3_PAGE _SB_MAKEMASK(2, S_MC_CS3_PAGE)
#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x, S_MC_CS3_PAGE)
#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x, S_MC_CS3_PAGE, M_MC_CS3_PAGE)
/*
* ECC Test ECC Register (Table 6-25)
*/
#define S_MC_ECC_INVERT 0
#define M_MC_ECC_INVERT _SB_MAKEMASK(8, S_MC_ECC_INVERT)
#endif

893
kernel/arch/mips/include/asm/sibyte/sb1250_regs.h Normal file
View File

@@ -0,0 +1,893 @@
/* *********************************************************************
* SB1250 Board Support Package
*
* Register Definitions File: sb1250_regs.h
*
* This module contains the addresses of the on-chip peripherals
* on the SB1250.
*
* SB1250 specification level: 01/02/2002
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_REGS_H
#define _SB1250_REGS_H
#include "sb1250_defs.h"
/* *********************************************************************
* Some general notes:
*
* For the most part, when there is more than one peripheral
* of the same type on the SOC, the constants below will be
* offsets from the base of each peripheral. For example,
* the MAC registers are described as offsets from the first
* MAC register, and there will be a MAC_REGISTER() macro
* to calculate the base address of a given MAC.
*
* The information in this file is based on the SB1250 SOC
* manual version 0.2, July 2000.
********************************************************************* */
/* *********************************************************************
* Memory Controller Registers
********************************************************************* */
/*
* XXX: can't remove MC base 0 if 112x, since it's used by other macros,
* since there is one reg there (but it could get its addr/offset constant).
*/
#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */
#define A_MC_BASE_0 0x0010051000
#define A_MC_BASE_1 0x0010052000
#define MC_REGISTER_SPACING 0x1000
#define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0)
#define A_MC_REGISTER(ctlid, reg) (A_MC_BASE(ctlid)+(reg))
#define R_MC_CONFIG 0x0000000100
#define R_MC_DRAMCMD 0x0000000120
#define R_MC_DRAMMODE 0x0000000140
#define R_MC_TIMING1 0x0000000160
#define R_MC_TIMING2 0x0000000180
#define R_MC_CS_START 0x00000001A0
#define R_MC_CS_END 0x00000001C0
#define R_MC_CS_INTERLEAVE 0x00000001E0
#define S_MC_CS_STARTEND 16
#define R_MC_CSX_BASE 0x0000000200
#define R_MC_CSX_ROW 0x0000000000 /* relative to CSX_BASE, above */
#define R_MC_CSX_COL 0x0000000020 /* relative to CSX_BASE, above */
#define R_MC_CSX_BA 0x0000000040 /* relative to CSX_BASE, above */
#define MC_CSX_SPACING 0x0000000060 /* relative to CSX_BASE, above */
#define R_MC_CS0_ROW 0x0000000200
#define R_MC_CS0_COL 0x0000000220
#define R_MC_CS0_BA 0x0000000240
#define R_MC_CS1_ROW 0x0000000260
#define R_MC_CS1_COL 0x0000000280
#define R_MC_CS1_BA 0x00000002A0
#define R_MC_CS2_ROW 0x00000002C0
#define R_MC_CS2_COL 0x00000002E0
#define R_MC_CS2_BA 0x0000000300
#define R_MC_CS3_ROW 0x0000000320
#define R_MC_CS3_COL 0x0000000340
#define R_MC_CS3_BA 0x0000000360
#define R_MC_CS_ATTR 0x0000000380
#define R_MC_TEST_DATA 0x0000000400
#define R_MC_TEST_ECC 0x0000000420
#define R_MC_MCLK_CFG 0x0000000500
#endif /* 1250 & 112x */
/* *********************************************************************
* L2 Cache Control Registers
********************************************************************* */
#if SIBYTE_HDR_FEATURE_1250_112x /* This L2C only on 1250/112x */
#define A_L2_READ_TAG 0x0010040018
#define A_L2_ECC_TAG 0x0010040038
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_L2_READ_MISC 0x0010040058
#endif /* 1250 PASS3 || 112x PASS1 */
#define A_L2_WAY_DISABLE 0x0010041000
#define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8))
#define A_L2_MGMT_TAG_BASE 0x00D0000000
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_L2_CACHE_DISABLE 0x0010042000
#define A_L2_MAKECACHEDISABLE(x) (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8))
#define A_L2_MISC_CONFIG 0x0010043000
#endif /* 1250 PASS2 || 112x PASS1 */
/* Backward-compatibility definitions. */
/* XXX: discourage people from using these constants. */
#define A_L2_READ_ADDRESS A_L2_READ_TAG
#define A_L2_EEC_ADDRESS A_L2_ECC_TAG
#endif
/* *********************************************************************
* PCI Interface Registers
********************************************************************* */
#if SIBYTE_HDR_FEATURE_1250_112x /* This PCI/HT only on 1250/112x */
#define A_PCI_TYPE00_HEADER 0x00DE000000
#define A_PCI_TYPE01_HEADER 0x00DE000800
#endif
/* *********************************************************************
* Ethernet DMA and MACs
********************************************************************* */
#define A_MAC_BASE_0 0x0010064000
#define A_MAC_BASE_1 0x0010065000
#if SIBYTE_HDR_FEATURE_CHIP(1250)
#define A_MAC_BASE_2 0x0010066000
#endif /* 1250 */
#define MAC_SPACING 0x1000
#define MAC_DMA_TXRX_SPACING 0x0400
#define MAC_DMA_CHANNEL_SPACING 0x0100
#define DMA_RX 0
#define DMA_TX 1
#define MAC_NUM_DMACHAN 2 /* channels per direction */
/* XXX: not correct; depends on SOC type. */
#define MAC_NUM_PORTS 3
#define A_MAC_CHANNEL_BASE(macnum) \
(A_MAC_BASE_0 + \
MAC_SPACING*(macnum))
#define A_MAC_REGISTER(macnum,reg) \
(A_MAC_BASE_0 + \
MAC_SPACING*(macnum) + (reg))
#define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */
#define A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) \
((A_MAC_CHANNEL_BASE(macnum)) + \
R_MAC_DMA_CHANNELS + \
(MAC_DMA_TXRX_SPACING*(txrx)) + \
(MAC_DMA_CHANNEL_SPACING*(chan)))
#define R_MAC_DMA_CHANNEL_BASE(txrx, chan) \
(R_MAC_DMA_CHANNELS + \
(MAC_DMA_TXRX_SPACING*(txrx)) + \
(MAC_DMA_CHANNEL_SPACING*(chan)))
#define A_MAC_DMA_REGISTER(macnum, txrx, chan, reg) \
(A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) + \
(reg))
#define R_MAC_DMA_REGISTER(txrx, chan, reg) \
(R_MAC_DMA_CHANNEL_BASE(txrx, chan) + \
(reg))
/*
* DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE
*/
#define R_MAC_DMA_CONFIG0 0x00000000
#define R_MAC_DMA_CONFIG1 0x00000008
#define R_MAC_DMA_DSCR_BASE 0x00000010
#define R_MAC_DMA_DSCR_CNT 0x00000018
#define R_MAC_DMA_CUR_DSCRA 0x00000020
#define R_MAC_DMA_CUR_DSCRB 0x00000028
#define R_MAC_DMA_CUR_DSCRADDR 0x00000030
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define R_MAC_DMA_OODPKTLOST_RX 0x00000038 /* rx only */
#endif /* 1250 PASS3 || 112x PASS1 */
/*
* RMON Counters
*/
#define R_MAC_RMON_TX_BYTES 0x00000000
#define R_MAC_RMON_COLLISIONS 0x00000008
#define R_MAC_RMON_LATE_COL 0x00000010
#define R_MAC_RMON_EX_COL 0x00000018
#define R_MAC_RMON_FCS_ERROR 0x00000020
#define R_MAC_RMON_TX_ABORT 0x00000028
/* Counter #6 (0x30) now reserved */
#define R_MAC_RMON_TX_BAD 0x00000038
#define R_MAC_RMON_TX_GOOD 0x00000040
#define R_MAC_RMON_TX_RUNT 0x00000048
#define R_MAC_RMON_TX_OVERSIZE 0x00000050
#define R_MAC_RMON_RX_BYTES 0x00000080
#define R_MAC_RMON_RX_MCAST 0x00000088
#define R_MAC_RMON_RX_BCAST 0x00000090
#define R_MAC_RMON_RX_BAD 0x00000098
#define R_MAC_RMON_RX_GOOD 0x000000A0
#define R_MAC_RMON_RX_RUNT 0x000000A8
#define R_MAC_RMON_RX_OVERSIZE 0x000000B0
#define R_MAC_RMON_RX_FCS_ERROR 0x000000B8
#define R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0
#define R_MAC_RMON_RX_CODE_ERROR 0x000000C8
#define R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0
/* Updated to spec 0.2 */
#define R_MAC_CFG 0x00000100
#define R_MAC_THRSH_CFG 0x00000108
#define R_MAC_VLANTAG 0x00000110
#define R_MAC_FRAMECFG 0x00000118
#define R_MAC_EOPCNT 0x00000120
#define R_MAC_FIFO_PTRS 0x00000128
#define R_MAC_ADFILTER_CFG 0x00000200
#define R_MAC_ETHERNET_ADDR 0x00000208
#define R_MAC_PKT_TYPE 0x00000210
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define R_MAC_ADMASK0 0x00000218
#define R_MAC_ADMASK1 0x00000220
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
#define R_MAC_HASH_BASE 0x00000240
#define R_MAC_ADDR_BASE 0x00000280
#define R_MAC_CHLO0_BASE 0x00000300
#define R_MAC_CHUP0_BASE 0x00000320
#define R_MAC_ENABLE 0x00000400
#define R_MAC_STATUS 0x00000408
#define R_MAC_INT_MASK 0x00000410
#define R_MAC_TXD_CTL 0x00000420
#define R_MAC_MDIO 0x00000428
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define R_MAC_STATUS1 0x00000430
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
#define R_MAC_DEBUG_STATUS 0x00000448
#define MAC_HASH_COUNT 8
#define MAC_ADDR_COUNT 8
#define MAC_CHMAP_COUNT 4
/* *********************************************************************
* DUART Registers
********************************************************************* */
#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */
#define R_DUART_NUM_PORTS 2
#define A_DUART 0x0010060000
#define DUART_CHANREG_SPACING 0x100
#define A_DUART_CHANREG(chan, reg) \
(A_DUART + DUART_CHANREG_SPACING * ((chan) + 1) + (reg))
#endif /* 1250 & 112x */
#define R_DUART_MODE_REG_1 0x000
#define R_DUART_MODE_REG_2 0x010
#define R_DUART_STATUS 0x020
#define R_DUART_CLK_SEL 0x030
#define R_DUART_CMD 0x050
#define R_DUART_RX_HOLD 0x060
#define R_DUART_TX_HOLD 0x070
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define R_DUART_FULL_CTL 0x040
#define R_DUART_OPCR_X 0x080
#define R_DUART_AUXCTL_X 0x090
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
/*
* The IMR and ISR can't be addressed with A_DUART_CHANREG,
* so use these macros instead.
*/
#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */
#define DUART_IMRISR_SPACING 0x20
#define DUART_INCHNG_SPACING 0x10
#define A_DUART_CTRLREG(reg) \
(A_DUART + DUART_CHANREG_SPACING * 3 + (reg))
#define R_DUART_IMRREG(chan) \
(R_DUART_IMR_A + (chan) * DUART_IMRISR_SPACING)
#define R_DUART_ISRREG(chan) \
(R_DUART_ISR_A + (chan) * DUART_IMRISR_SPACING)
#define R_DUART_INCHREG(chan) \
(R_DUART_IN_CHNG_A + (chan) * DUART_INCHNG_SPACING)
#define A_DUART_IMRREG(chan) A_DUART_CTRLREG(R_DUART_IMRREG(chan))
#define A_DUART_ISRREG(chan) A_DUART_CTRLREG(R_DUART_ISRREG(chan))
#define A_DUART_INCHREG(chan) A_DUART_CTRLREG(R_DUART_INCHREG(chan))
#endif /* 1250 & 112x */
#define R_DUART_AUX_CTRL 0x010
#define R_DUART_ISR_A 0x020
#define R_DUART_IMR_A 0x030
#define R_DUART_ISR_B 0x040
#define R_DUART_IMR_B 0x050
#define R_DUART_OUT_PORT 0x060
#define R_DUART_OPCR 0x070
#define R_DUART_IN_PORT 0x080
#define R_DUART_SET_OPR 0x0B0
#define R_DUART_CLEAR_OPR 0x0C0
#define R_DUART_IN_CHNG_A 0x0D0
#define R_DUART_IN_CHNG_B 0x0E0
/*
* These constants are the absolute addresses.
*/
#define A_DUART_MODE_REG_1_A 0x0010060100
#define A_DUART_MODE_REG_2_A 0x0010060110
#define A_DUART_STATUS_A 0x0010060120
#define A_DUART_CLK_SEL_A 0x0010060130
#define A_DUART_CMD_A 0x0010060150
#define A_DUART_RX_HOLD_A 0x0010060160
#define A_DUART_TX_HOLD_A 0x0010060170
#define A_DUART_MODE_REG_1_B 0x0010060200
#define A_DUART_MODE_REG_2_B 0x0010060210
#define A_DUART_STATUS_B 0x0010060220
#define A_DUART_CLK_SEL_B 0x0010060230
#define A_DUART_CMD_B 0x0010060250
#define A_DUART_RX_HOLD_B 0x0010060260
#define A_DUART_TX_HOLD_B 0x0010060270
#define A_DUART_INPORT_CHNG 0x0010060300
#define A_DUART_AUX_CTRL 0x0010060310
#define A_DUART_ISR_A 0x0010060320
#define A_DUART_IMR_A 0x0010060330
#define A_DUART_ISR_B 0x0010060340
#define A_DUART_IMR_B 0x0010060350
#define A_DUART_OUT_PORT 0x0010060360
#define A_DUART_OPCR 0x0010060370
#define A_DUART_IN_PORT 0x0010060380
#define A_DUART_ISR 0x0010060390
#define A_DUART_IMR 0x00100603A0
#define A_DUART_SET_OPR 0x00100603B0
#define A_DUART_CLEAR_OPR 0x00100603C0
#define A_DUART_INPORT_CHNG_A 0x00100603D0
#define A_DUART_INPORT_CHNG_B 0x00100603E0
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_DUART_FULL_CTL_A 0x0010060140
#define A_DUART_FULL_CTL_B 0x0010060240
#define A_DUART_OPCR_A 0x0010060180
#define A_DUART_OPCR_B 0x0010060280
#define A_DUART_INPORT_CHNG_DEBUG 0x00100603F0
#endif /* 1250 PASS2 || 112x PASS1 */
/* *********************************************************************
* Synchronous Serial Registers
********************************************************************* */
#if SIBYTE_HDR_FEATURE_1250_112x /* sync serial only on 1250/112x */
#define A_SER_BASE_0 0x0010060400
#define A_SER_BASE_1 0x0010060800
#define SER_SPACING 0x400
#define SER_DMA_TXRX_SPACING 0x80
#define SER_NUM_PORTS 2
#define A_SER_CHANNEL_BASE(sernum) \
(A_SER_BASE_0 + \
SER_SPACING*(sernum))
#define A_SER_REGISTER(sernum,reg) \
(A_SER_BASE_0 + \
SER_SPACING*(sernum) + (reg))
#define R_SER_DMA_CHANNELS 0 /* Relative to A_SER_BASE_x */
#define A_SER_DMA_CHANNEL_BASE(sernum,txrx) \
((A_SER_CHANNEL_BASE(sernum)) + \
R_SER_DMA_CHANNELS + \
(SER_DMA_TXRX_SPACING*(txrx)))
#define A_SER_DMA_REGISTER(sernum, txrx, reg) \
(A_SER_DMA_CHANNEL_BASE(sernum, txrx) + \
(reg))
/*
* DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE
*/
#define R_SER_DMA_CONFIG0 0x00000000
#define R_SER_DMA_CONFIG1 0x00000008
#define R_SER_DMA_DSCR_BASE 0x00000010
#define R_SER_DMA_DSCR_CNT 0x00000018
#define R_SER_DMA_CUR_DSCRA 0x00000020
#define R_SER_DMA_CUR_DSCRB 0x00000028
#define R_SER_DMA_CUR_DSCRADDR 0x00000030
#define R_SER_DMA_CONFIG0_RX 0x00000000
#define R_SER_DMA_CONFIG1_RX 0x00000008
#define R_SER_DMA_DSCR_BASE_RX 0x00000010
#define R_SER_DMA_DSCR_COUNT_RX 0x00000018
#define R_SER_DMA_CUR_DSCR_A_RX 0x00000020
#define R_SER_DMA_CUR_DSCR_B_RX 0x00000028
#define R_SER_DMA_CUR_DSCR_ADDR_RX 0x00000030
#define R_SER_DMA_CONFIG0_TX 0x00000080
#define R_SER_DMA_CONFIG1_TX 0x00000088
#define R_SER_DMA_DSCR_BASE_TX 0x00000090
#define R_SER_DMA_DSCR_COUNT_TX 0x00000098
#define R_SER_DMA_CUR_DSCR_A_TX 0x000000A0
#define R_SER_DMA_CUR_DSCR_B_TX 0x000000A8
#define R_SER_DMA_CUR_DSCR_ADDR_TX 0x000000B0
#define R_SER_MODE 0x00000100
#define R_SER_MINFRM_SZ 0x00000108
#define R_SER_MAXFRM_SZ 0x00000110
#define R_SER_ADDR 0x00000118
#define R_SER_USR0_ADDR 0x00000120
#define R_SER_USR1_ADDR 0x00000128
#define R_SER_USR2_ADDR 0x00000130
#define R_SER_USR3_ADDR 0x00000138
#define R_SER_CMD 0x00000140
#define R_SER_TX_RD_THRSH 0x00000160
#define R_SER_TX_WR_THRSH 0x00000168
#define R_SER_RX_RD_THRSH 0x00000170
#define R_SER_LINE_MODE 0x00000178
#define R_SER_DMA_ENABLE 0x00000180
#define R_SER_INT_MASK 0x00000190
#define R_SER_STATUS 0x00000188
#define R_SER_STATUS_DEBUG 0x000001A8
#define R_SER_RX_TABLE_BASE 0x00000200
#define SER_RX_TABLE_COUNT 16
#define R_SER_TX_TABLE_BASE 0x00000300
#define SER_TX_TABLE_COUNT 16
/* RMON Counters */
#define R_SER_RMON_TX_BYTE_LO 0x000001C0
#define R_SER_RMON_TX_BYTE_HI 0x000001C8
#define R_SER_RMON_RX_BYTE_LO 0x000001D0
#define R_SER_RMON_RX_BYTE_HI 0x000001D8
#define R_SER_RMON_TX_UNDERRUN 0x000001E0
#define R_SER_RMON_RX_OVERFLOW 0x000001E8
#define R_SER_RMON_RX_ERRORS 0x000001F0
#define R_SER_RMON_RX_BADADDR 0x000001F8
#endif /* 1250/112x */
/* *********************************************************************
* Generic Bus Registers
********************************************************************* */
#define IO_EXT_CFG_COUNT 8
#define A_IO_EXT_BASE 0x0010061000
#define A_IO_EXT_REG(r) (A_IO_EXT_BASE + (r))
#define A_IO_EXT_CFG_BASE 0x0010061000
#define A_IO_EXT_MULT_SIZE_BASE 0x0010061100
#define A_IO_EXT_START_ADDR_BASE 0x0010061200
#define A_IO_EXT_TIME_CFG0_BASE 0x0010061600
#define A_IO_EXT_TIME_CFG1_BASE 0x0010061700
#define IO_EXT_REGISTER_SPACING 8
#define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs))
#define R_IO_EXT_REG(reg, cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg))
#define R_IO_EXT_CFG 0x0000
#define R_IO_EXT_MULT_SIZE 0x0100
#define R_IO_EXT_START_ADDR 0x0200
#define R_IO_EXT_TIME_CFG0 0x0600
#define R_IO_EXT_TIME_CFG1 0x0700
#define A_IO_INTERRUPT_STATUS 0x0010061A00
#define A_IO_INTERRUPT_DATA0 0x0010061A10
#define A_IO_INTERRUPT_DATA1 0x0010061A18
#define A_IO_INTERRUPT_DATA2 0x0010061A20
#define A_IO_INTERRUPT_DATA3 0x0010061A28
#define A_IO_INTERRUPT_ADDR0 0x0010061A30
#define A_IO_INTERRUPT_ADDR1 0x0010061A40
#define A_IO_INTERRUPT_PARITY 0x0010061A50
#define A_IO_PCMCIA_CFG 0x0010061A60
#define A_IO_PCMCIA_STATUS 0x0010061A70
#define A_IO_DRIVE_0 0x0010061300
#define A_IO_DRIVE_1 0x0010061308
#define A_IO_DRIVE_2 0x0010061310
#define A_IO_DRIVE_3 0x0010061318
#define A_IO_DRIVE_BASE A_IO_DRIVE_0
#define IO_DRIVE_REGISTER_SPACING 8
#define R_IO_DRIVE(x) ((x)*IO_DRIVE_REGISTER_SPACING)
#define A_IO_DRIVE(x) (A_IO_DRIVE_BASE + R_IO_DRIVE(x))
#define R_IO_INTERRUPT_STATUS 0x0A00
#define R_IO_INTERRUPT_DATA0 0x0A10
#define R_IO_INTERRUPT_DATA1 0x0A18
#define R_IO_INTERRUPT_DATA2 0x0A20
#define R_IO_INTERRUPT_DATA3 0x0A28
#define R_IO_INTERRUPT_ADDR0 0x0A30
#define R_IO_INTERRUPT_ADDR1 0x0A40
#define R_IO_INTERRUPT_PARITY 0x0A50
#define R_IO_PCMCIA_CFG 0x0A60
#define R_IO_PCMCIA_STATUS 0x0A70
/* *********************************************************************
* GPIO Registers
********************************************************************* */
#define A_GPIO_CLR_EDGE 0x0010061A80
#define A_GPIO_INT_TYPE 0x0010061A88
#define A_GPIO_INPUT_INVERT 0x0010061A90
#define A_GPIO_GLITCH 0x0010061A98
#define A_GPIO_READ 0x0010061AA0
#define A_GPIO_DIRECTION 0x0010061AA8
#define A_GPIO_PIN_CLR 0x0010061AB0
#define A_GPIO_PIN_SET 0x0010061AB8
#define A_GPIO_BASE 0x0010061A80
#define R_GPIO_CLR_EDGE 0x00
#define R_GPIO_INT_TYPE 0x08
#define R_GPIO_INPUT_INVERT 0x10
#define R_GPIO_GLITCH 0x18
#define R_GPIO_READ 0x20
#define R_GPIO_DIRECTION 0x28
#define R_GPIO_PIN_CLR 0x30
#define R_GPIO_PIN_SET 0x38
/* *********************************************************************
* SMBus Registers
********************************************************************* */
#define A_SMB_XTRA_0 0x0010060000
#define A_SMB_XTRA_1 0x0010060008
#define A_SMB_FREQ_0 0x0010060010
#define A_SMB_FREQ_1 0x0010060018
#define A_SMB_STATUS_0 0x0010060020
#define A_SMB_STATUS_1 0x0010060028
#define A_SMB_CMD_0 0x0010060030
#define A_SMB_CMD_1 0x0010060038
#define A_SMB_START_0 0x0010060040
#define A_SMB_START_1 0x0010060048
#define A_SMB_DATA_0 0x0010060050
#define A_SMB_DATA_1 0x0010060058
#define A_SMB_CONTROL_0 0x0010060060
#define A_SMB_CONTROL_1 0x0010060068
#define A_SMB_PEC_0 0x0010060070
#define A_SMB_PEC_1 0x0010060078
#define A_SMB_0 0x0010060000
#define A_SMB_1 0x0010060008
#define SMB_REGISTER_SPACING 0x8
#define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING)
#define A_SMB_REGISTER(idx, reg) (A_SMB_BASE(idx)+(reg))
#define R_SMB_XTRA 0x0000000000
#define R_SMB_FREQ 0x0000000010
#define R_SMB_STATUS 0x0000000020
#define R_SMB_CMD 0x0000000030
#define R_SMB_START 0x0000000040
#define R_SMB_DATA 0x0000000050
#define R_SMB_CONTROL 0x0000000060
#define R_SMB_PEC 0x0000000070
/* *********************************************************************
* Timer Registers
********************************************************************* */
/*
* Watchdog timers
*/
#define A_SCD_WDOG_0 0x0010020050
#define A_SCD_WDOG_1 0x0010020150
#define SCD_WDOG_SPACING 0x100
#define SCD_NUM_WDOGS 2
#define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w))
#define A_SCD_WDOG_REGISTER(w, r) (A_SCD_WDOG_BASE(w) + (r))
#define R_SCD_WDOG_INIT 0x0000000000
#define R_SCD_WDOG_CNT 0x0000000008
#define R_SCD_WDOG_CFG 0x0000000010
#define A_SCD_WDOG_INIT_0 0x0010020050
#define A_SCD_WDOG_CNT_0 0x0010020058
#define A_SCD_WDOG_CFG_0 0x0010020060
#define A_SCD_WDOG_INIT_1 0x0010020150
#define A_SCD_WDOG_CNT_1 0x0010020158
#define A_SCD_WDOG_CFG_1 0x0010020160
/*
* Generic timers
*/
#define A_SCD_TIMER_0 0x0010020070
#define A_SCD_TIMER_1 0x0010020078
#define A_SCD_TIMER_2 0x0010020170
#define A_SCD_TIMER_3 0x0010020178
#define SCD_NUM_TIMERS 4
#define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1))
#define A_SCD_TIMER_REGISTER(w, r) (A_SCD_TIMER_BASE(w) + (r))
#define R_SCD_TIMER_INIT 0x0000000000
#define R_SCD_TIMER_CNT 0x0000000010
#define R_SCD_TIMER_CFG 0x0000000020
#define A_SCD_TIMER_INIT_0 0x0010020070
#define A_SCD_TIMER_CNT_0 0x0010020080
#define A_SCD_TIMER_CFG_0 0x0010020090
#define A_SCD_TIMER_INIT_1 0x0010020078
#define A_SCD_TIMER_CNT_1 0x0010020088
#define A_SCD_TIMER_CFG_1 0x0010020098
#define A_SCD_TIMER_INIT_2 0x0010020170
#define A_SCD_TIMER_CNT_2 0x0010020180
#define A_SCD_TIMER_CFG_2 0x0010020190
#define A_SCD_TIMER_INIT_3 0x0010020178
#define A_SCD_TIMER_CNT_3 0x0010020188
#define A_SCD_TIMER_CFG_3 0x0010020198
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_SCD_SCRATCH 0x0010020C10
#endif /* 1250 PASS2 || 112x PASS1 */
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000
#define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00
#define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08
#endif
/* *********************************************************************
* System Control Registers
********************************************************************* */
#define A_SCD_SYSTEM_REVISION 0x0010020000
#define A_SCD_SYSTEM_CFG 0x0010020008
#define A_SCD_SYSTEM_MANUF 0x0010038000
/* *********************************************************************
* System Address Trap Registers
********************************************************************* */
#define A_ADDR_TRAP_INDEX 0x00100200B0
#define A_ADDR_TRAP_REG 0x00100200B8
#define A_ADDR_TRAP_UP_0 0x0010020400
#define A_ADDR_TRAP_UP_1 0x0010020408
#define A_ADDR_TRAP_UP_2 0x0010020410
#define A_ADDR_TRAP_UP_3 0x0010020418
#define A_ADDR_TRAP_DOWN_0 0x0010020420
#define A_ADDR_TRAP_DOWN_1 0x0010020428
#define A_ADDR_TRAP_DOWN_2 0x0010020430
#define A_ADDR_TRAP_DOWN_3 0x0010020438
#define A_ADDR_TRAP_CFG_0 0x0010020440
#define A_ADDR_TRAP_CFG_1 0x0010020448
#define A_ADDR_TRAP_CFG_2 0x0010020450
#define A_ADDR_TRAP_CFG_3 0x0010020458
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define A_ADDR_TRAP_REG_DEBUG 0x0010020460
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
#define ADDR_TRAP_SPACING 8
#define NUM_ADDR_TRAP 4
#define A_ADDR_TRAP_UP(n) (A_ADDR_TRAP_UP_0 + ((n) * ADDR_TRAP_SPACING))
#define A_ADDR_TRAP_DOWN(n) (A_ADDR_TRAP_DOWN_0 + ((n) * ADDR_TRAP_SPACING))
#define A_ADDR_TRAP_CFG(n) (A_ADDR_TRAP_CFG_0 + ((n) * ADDR_TRAP_SPACING))
/* *********************************************************************
* System Interrupt Mapper Registers
********************************************************************* */
#define A_IMR_CPU0_BASE 0x0010020000
#define A_IMR_CPU1_BASE 0x0010022000
#define IMR_REGISTER_SPACING 0x2000
#define IMR_REGISTER_SPACING_SHIFT 13
#define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING)
#define A_IMR_REGISTER(cpu, reg) (A_IMR_MAPPER(cpu)+(reg))
#define R_IMR_INTERRUPT_DIAG 0x0010
#define R_IMR_INTERRUPT_LDT 0x0018
#define R_IMR_INTERRUPT_MASK 0x0028
#define R_IMR_INTERRUPT_TRACE 0x0038
#define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040
#define R_IMR_LDT_INTERRUPT_SET 0x0048
#define R_IMR_LDT_INTERRUPT 0x0018
#define R_IMR_LDT_INTERRUPT_CLR 0x0020
#define R_IMR_MAILBOX_CPU 0x00c0
#define R_IMR_ALIAS_MAILBOX_CPU 0x1000
#define R_IMR_MAILBOX_SET_CPU 0x00C8
#define R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008
#define R_IMR_MAILBOX_CLR_CPU 0x00D0
#define R_IMR_INTERRUPT_STATUS_BASE 0x0100
#define R_IMR_INTERRUPT_STATUS_COUNT 7
#define R_IMR_INTERRUPT_MAP_BASE 0x0200
#define R_IMR_INTERRUPT_MAP_COUNT 64
/*
* these macros work together to build the address of a mailbox
* register, e.g., A_MAILBOX_REGISTER(R_IMR_MAILBOX_SET_CPU,1)
* for mbox_0_set_cpu2 returns 0x00100240C8
*/
#define A_MAILBOX_REGISTER(reg,cpu) \
(A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPACING) + reg)
/* *********************************************************************
* System Performance Counter Registers
********************************************************************* */
#define A_SCD_PERF_CNT_CFG 0x00100204C0
#define A_SCD_PERF_CNT_0 0x00100204D0
#define A_SCD_PERF_CNT_1 0x00100204D8
#define A_SCD_PERF_CNT_2 0x00100204E0
#define A_SCD_PERF_CNT_3 0x00100204E8
#define SCD_NUM_PERF_CNT 4
#define SCD_PERF_CNT_SPACING 8
#define A_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*SCD_PERF_CNT_SPACING))
/* *********************************************************************
* System Bus Watcher Registers
********************************************************************* */
#define A_SCD_BUS_ERR_STATUS 0x0010020880
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0
#define A_BUS_ERR_STATUS_DEBUG 0x00100208D0
#endif /* 1250 PASS2 || 112x PASS1 */
#define A_BUS_ERR_DATA_0 0x00100208A0
#define A_BUS_ERR_DATA_1 0x00100208A8
#define A_BUS_ERR_DATA_2 0x00100208B0
#define A_BUS_ERR_DATA_3 0x00100208B8
#define A_BUS_L2_ERRORS 0x00100208C0
#define A_BUS_MEM_IO_ERRORS 0x00100208C8
/* *********************************************************************
* System Debug Controller Registers
********************************************************************* */
#define A_SCD_JTAG_BASE 0x0010000000
/* *********************************************************************
* System Trace Buffer Registers
********************************************************************* */
#define A_SCD_TRACE_CFG 0x0010020A00
#define A_SCD_TRACE_READ 0x0010020A08
#define A_SCD_TRACE_EVENT_0 0x0010020A20
#define A_SCD_TRACE_EVENT_1 0x0010020A28
#define A_SCD_TRACE_EVENT_2 0x0010020A30
#define A_SCD_TRACE_EVENT_3 0x0010020A38
#define A_SCD_TRACE_SEQUENCE_0 0x0010020A40
#define A_SCD_TRACE_SEQUENCE_1 0x0010020A48
#define A_SCD_TRACE_SEQUENCE_2 0x0010020A50
#define A_SCD_TRACE_SEQUENCE_3 0x0010020A58
#define A_SCD_TRACE_EVENT_4 0x0010020A60
#define A_SCD_TRACE_EVENT_5 0x0010020A68
#define A_SCD_TRACE_EVENT_6 0x0010020A70
#define A_SCD_TRACE_EVENT_7 0x0010020A78
#define A_SCD_TRACE_SEQUENCE_4 0x0010020A80
#define A_SCD_TRACE_SEQUENCE_5 0x0010020A88
#define A_SCD_TRACE_SEQUENCE_6 0x0010020A90
#define A_SCD_TRACE_SEQUENCE_7 0x0010020A98
#define TRACE_REGISTER_SPACING 8
#define TRACE_NUM_REGISTERS 8
#define A_SCD_TRACE_EVENT(n) (((n) & 4) ? \
(A_SCD_TRACE_EVENT_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \
(A_SCD_TRACE_EVENT_0 + ((n) * TRACE_REGISTER_SPACING)))
#define A_SCD_TRACE_SEQUENCE(n) (((n) & 4) ? \
(A_SCD_TRACE_SEQUENCE_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \
(A_SCD_TRACE_SEQUENCE_0 + ((n) * TRACE_REGISTER_SPACING)))
/* *********************************************************************
* System Generic DMA Registers
********************************************************************* */
#define A_DM_0 0x0010020B00
#define A_DM_1 0x0010020B20
#define A_DM_2 0x0010020B40
#define A_DM_3 0x0010020B60
#define DM_REGISTER_SPACING 0x20
#define DM_NUM_CHANNELS 4
#define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING))
#define A_DM_REGISTER(idx, reg) (A_DM_BASE(idx) + (reg))
#define R_DM_DSCR_BASE 0x0000000000
#define R_DM_DSCR_COUNT 0x0000000008
#define R_DM_CUR_DSCR_ADDR 0x0000000010
#define R_DM_DSCR_BASE_DEBUG 0x0000000018
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_DM_PARTIAL_0 0x0010020ba0
#define A_DM_PARTIAL_1 0x0010020ba8
#define A_DM_PARTIAL_2 0x0010020bb0
#define A_DM_PARTIAL_3 0x0010020bb8
#define DM_PARTIAL_REGISTER_SPACING 0x8
#define A_DM_PARTIAL(idx) (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING))
#endif /* 1250 PASS3 || 112x PASS1 */
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define A_DM_CRC_0 0x0010020b80
#define A_DM_CRC_1 0x0010020b90
#define DM_CRC_REGISTER_SPACING 0x10
#define DM_CRC_NUM_CHANNELS 2
#define A_DM_CRC_BASE(idx) (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING))
#define A_DM_CRC_REGISTER(idx, reg) (A_DM_CRC_BASE(idx) + (reg))
#define R_CRC_DEF_0 0x00
#define R_CTCP_DEF_0 0x08
#endif /* 1250 PASS3 || 112x PASS1 */
/* *********************************************************************
* Physical Address Map
********************************************************************* */
#if SIBYTE_HDR_FEATURE_1250_112x
#define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000)
#define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024))
#define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000)
#define A_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000)
#define A_PHYS_GENBUS _SB_MAKE64(0x0010090000)
#define A_PHYS_GENBUS_END _SB_MAKE64(0x0040000000)
#define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000)
#define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000)
#define A_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000)
#define A_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000)
#define A_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000)
#define A_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000)
#define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000)
#define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000)
#define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000)
#define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000)
#define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MAKE64(0x00FC000000)
#define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000)
#define A_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000)
#define A_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024))
#define A_PHYS_LDT_EXP _SB_MAKE64(0x8000000000)
#define A_PHYS_PCI_FULLACCESS_BYTES _SB_MAKE64(0xF000000000)
#define A_PHYS_PCI_FULLACCESS_BITS _SB_MAKE64(0xF100000000)
#define A_PHYS_RESERVED _SB_MAKE64(0xF200000000)
#define A_PHYS_RESERVED_SPECIAL_LDT _SB_MAKE64(0xFD00000000)
#define A_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000)
#define PHYS_L2CACHE_NUM_WAYS 4
#define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000080000)
#define A_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0180000)
#define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000)
#define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000)
#define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000)
#endif
#endif

654
kernel/arch/mips/include/asm/sibyte/sb1250_scd.h Normal file
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@@ -0,0 +1,654 @@
/* *********************************************************************
* SB1250 Board Support Package
*
* SCD Constants and Macros File: sb1250_scd.h
*
* This module contains constants and macros useful for
* manipulating the System Control and Debug module on the 1250.
*
* SB1250 specification level: User's manual 1/02/02
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003,2004,2005
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_SCD_H
#define _SB1250_SCD_H
#include "sb1250_defs.h"
/* *********************************************************************
* System control/debug registers
********************************************************************* */
/*
* System Revision Register (Table 4-1)
*/
#define M_SYS_RESERVED _SB_MAKEMASK(8, 0)
#define S_SYS_REVISION _SB_MAKE64(8)
#define M_SYS_REVISION _SB_MAKEMASK(8, S_SYS_REVISION)
#define V_SYS_REVISION(x) _SB_MAKEVALUE(x, S_SYS_REVISION)
#define G_SYS_REVISION(x) _SB_GETVALUE(x, S_SYS_REVISION, M_SYS_REVISION)
#define K_SYS_REVISION_BCM1250_PASS1 0x01
#define K_SYS_REVISION_BCM1250_PASS2 0x03
#define K_SYS_REVISION_BCM1250_A1 0x03 /* Pass 2.0 WB */
#define K_SYS_REVISION_BCM1250_A2 0x04 /* Pass 2.0 FC */
#define K_SYS_REVISION_BCM1250_A3 0x05 /* Pass 2.1 FC */
#define K_SYS_REVISION_BCM1250_A4 0x06 /* Pass 2.1 WB */
#define K_SYS_REVISION_BCM1250_A6 0x07 /* OR 0x04 (A2) w/WID != 0 */
#define K_SYS_REVISION_BCM1250_A8 0x0b /* A8/A10 */
#define K_SYS_REVISION_BCM1250_A9 0x08
#define K_SYS_REVISION_BCM1250_A10 K_SYS_REVISION_BCM1250_A8
#define K_SYS_REVISION_BCM1250_PASS2_2 0x10
#define K_SYS_REVISION_BCM1250_B0 K_SYS_REVISION_BCM1250_B1
#define K_SYS_REVISION_BCM1250_B1 0x10
#define K_SYS_REVISION_BCM1250_B2 0x11
#define K_SYS_REVISION_BCM1250_C0 0x20
#define K_SYS_REVISION_BCM1250_C1 0x21
#define K_SYS_REVISION_BCM1250_C2 0x22
#define K_SYS_REVISION_BCM1250_C3 0x23
#if SIBYTE_HDR_FEATURE_CHIP(1250)
/* XXX: discourage people from using these constants. */
#define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1
#define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2
#define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2
#define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3
#define K_SYS_REVISION_BCM1250_PASS3 K_SYS_REVISION_BCM1250_C0
#endif /* 1250 */
#define K_SYS_REVISION_BCM112x_A1 0x20
#define K_SYS_REVISION_BCM112x_A2 0x21
#define K_SYS_REVISION_BCM112x_A3 0x22
#define K_SYS_REVISION_BCM112x_A4 0x23
#define K_SYS_REVISION_BCM112x_B0 0x30
#define K_SYS_REVISION_BCM1480_S0 0x01
#define K_SYS_REVISION_BCM1480_A1 0x02
#define K_SYS_REVISION_BCM1480_A2 0x03
#define K_SYS_REVISION_BCM1480_A3 0x04
#define K_SYS_REVISION_BCM1480_B0 0x11
/*Cache size - 23:20 of revision register*/
#define S_SYS_L2C_SIZE _SB_MAKE64(20)
#define M_SYS_L2C_SIZE _SB_MAKEMASK(4, S_SYS_L2C_SIZE)
#define V_SYS_L2C_SIZE(x) _SB_MAKEVALUE(x, S_SYS_L2C_SIZE)
#define G_SYS_L2C_SIZE(x) _SB_GETVALUE(x, S_SYS_L2C_SIZE, M_SYS_L2C_SIZE)
#define K_SYS_L2C_SIZE_1MB 0
#define K_SYS_L2C_SIZE_512KB 5
#define K_SYS_L2C_SIZE_256KB 2
#define K_SYS_L2C_SIZE_128KB 1
#define K_SYS_L2C_SIZE_BCM1250 K_SYS_L2C_SIZE_512KB
#define K_SYS_L2C_SIZE_BCM1125 K_SYS_L2C_SIZE_256KB
#define K_SYS_L2C_SIZE_BCM1122 K_SYS_L2C_SIZE_128KB
/* Number of CPU cores, bits 27:24 of revision register*/
#define S_SYS_NUM_CPUS _SB_MAKE64(24)
#define M_SYS_NUM_CPUS _SB_MAKEMASK(4, S_SYS_NUM_CPUS)
#define V_SYS_NUM_CPUS(x) _SB_MAKEVALUE(x, S_SYS_NUM_CPUS)
#define G_SYS_NUM_CPUS(x) _SB_GETVALUE(x, S_SYS_NUM_CPUS, M_SYS_NUM_CPUS)
/* XXX: discourage people from using these constants. */
#define S_SYS_PART _SB_MAKE64(16)
#define M_SYS_PART _SB_MAKEMASK(16, S_SYS_PART)
#define V_SYS_PART(x) _SB_MAKEVALUE(x, S_SYS_PART)
#define G_SYS_PART(x) _SB_GETVALUE(x, S_SYS_PART, M_SYS_PART)
/* XXX: discourage people from using these constants. */
#define K_SYS_PART_SB1250 0x1250
#define K_SYS_PART_BCM1120 0x1121
#define K_SYS_PART_BCM1125 0x1123
#define K_SYS_PART_BCM1125H 0x1124
#define K_SYS_PART_BCM1122 0x1113
/* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */
#define S_SYS_SOC_TYPE _SB_MAKE64(16)
#define M_SYS_SOC_TYPE _SB_MAKEMASK(4, S_SYS_SOC_TYPE)
#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x, S_SYS_SOC_TYPE)
#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x, S_SYS_SOC_TYPE, M_SYS_SOC_TYPE)
#define K_SYS_SOC_TYPE_BCM1250 0x0
#define K_SYS_SOC_TYPE_BCM1120 0x1
#define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */
#define K_SYS_SOC_TYPE_BCM1125 0x3
#define K_SYS_SOC_TYPE_BCM1125H 0x4
#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */
#define K_SYS_SOC_TYPE_BCM1x80 0x6
#define K_SYS_SOC_TYPE_BCM1x55 0x7
/*
* Calculate correct SOC type given a copy of system revision register.
*
* (For the assembler version, sysrev and dest may be the same register.
* Also, it clobbers AT.)
*/
#ifdef __ASSEMBLER__
#define SYS_SOC_TYPE(dest, sysrev) \
.set push ; \
.set reorder ; \
dsrl dest, sysrev, S_SYS_SOC_TYPE ; \
andi dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE); \
beq dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ; \
beq dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f ; \
b 992f ; \
991: li dest, K_SYS_SOC_TYPE_BCM1250 ; \
992: \
.set pop
#else
#define SYS_SOC_TYPE(sysrev) \
((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT \
|| G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2) \
? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev))
#endif
#define S_SYS_WID _SB_MAKE64(32)
#define M_SYS_WID _SB_MAKEMASK(32, S_SYS_WID)
#define V_SYS_WID(x) _SB_MAKEVALUE(x, S_SYS_WID)
#define G_SYS_WID(x) _SB_GETVALUE(x, S_SYS_WID, M_SYS_WID)
/*
* System Manufacturing Register
* Register: SCD_SYSTEM_MANUF
*/
#if SIBYTE_HDR_FEATURE_1250_112x
/* Wafer ID: bits 31:0 */
#define S_SYS_WAFERID1_200 _SB_MAKE64(0)
#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32, S_SYS_WAFERID1_200)
#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID1_200)
#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x, S_SYS_WAFERID1_200, M_SYS_WAFERID1_200)
#define S_SYS_BIN _SB_MAKE64(32)
#define M_SYS_BIN _SB_MAKEMASK(4, S_SYS_BIN)
#define V_SYS_BIN(x) _SB_MAKEVALUE(x, S_SYS_BIN)
#define G_SYS_BIN(x) _SB_GETVALUE(x, S_SYS_BIN, M_SYS_BIN)
/* Wafer ID: bits 39:36 */
#define S_SYS_WAFERID2_200 _SB_MAKE64(36)
#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4, S_SYS_WAFERID2_200)
#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x, S_SYS_WAFERID2_200)
#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x, S_SYS_WAFERID2_200, M_SYS_WAFERID2_200)
/* Wafer ID: bits 39:0 */
#define S_SYS_WAFERID_300 _SB_MAKE64(0)
#define M_SYS_WAFERID_300 _SB_MAKEMASK(40, S_SYS_WAFERID_300)
#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x, S_SYS_WAFERID_300)
#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x, S_SYS_WAFERID_300, M_SYS_WAFERID_300)
#define S_SYS_XPOS _SB_MAKE64(40)
#define M_SYS_XPOS _SB_MAKEMASK(6, S_SYS_XPOS)
#define V_SYS_XPOS(x) _SB_MAKEVALUE(x, S_SYS_XPOS)
#define G_SYS_XPOS(x) _SB_GETVALUE(x, S_SYS_XPOS, M_SYS_XPOS)
#define S_SYS_YPOS _SB_MAKE64(46)
#define M_SYS_YPOS _SB_MAKEMASK(6, S_SYS_YPOS)
#define V_SYS_YPOS(x) _SB_MAKEVALUE(x, S_SYS_YPOS)
#define G_SYS_YPOS(x) _SB_GETVALUE(x, S_SYS_YPOS, M_SYS_YPOS)
#endif
/*
* System Config Register (Table 4-2)
* Register: SCD_SYSTEM_CFG
*/
#if SIBYTE_HDR_FEATURE_1250_112x
#define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3)
#define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4)
#define M_SYS_IOB0_DIV _SB_MAKEMASK1(5)
#define M_SYS_IOB1_DIV _SB_MAKEMASK1(6)
#define S_SYS_PLL_DIV _SB_MAKE64(7)
#define M_SYS_PLL_DIV _SB_MAKEMASK(5, S_SYS_PLL_DIV)
#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_SYS_PLL_DIV)
#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_SYS_PLL_DIV, M_SYS_PLL_DIV)
#define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12)
#define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13)
#define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14)
#define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15)
#define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16)
#define S_SYS_BOOT_MODE _SB_MAKE64(17)
#define M_SYS_BOOT_MODE _SB_MAKEMASK(2, S_SYS_BOOT_MODE)
#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_SYS_BOOT_MODE)
#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_SYS_BOOT_MODE, M_SYS_BOOT_MODE)
#define K_SYS_BOOT_MODE_ROM32 0
#define K_SYS_BOOT_MODE_ROM8 1
#define K_SYS_BOOT_MODE_SMBUS_SMALL 2
#define K_SYS_BOOT_MODE_SMBUS_BIG 3
#define M_SYS_PCI_HOST _SB_MAKEMASK1(19)
#define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20)
#define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21)
#define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22)
#define M_SYS_GENCLK_EN _SB_MAKEMASK1(23)
#define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24)
#define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25)
#define S_SYS_CONFIG 26
#define M_SYS_CONFIG _SB_MAKEMASK(6, S_SYS_CONFIG)
#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_SYS_CONFIG)
#define G_SYS_CONFIG(x) _SB_GETVALUE(x, S_SYS_CONFIG, M_SYS_CONFIG)
/* The following bits are writeable by JTAG only. */
#define M_SYS_CLKSTOP _SB_MAKEMASK1(32)
#define M_SYS_CLKSTEP _SB_MAKEMASK1(33)
#define S_SYS_CLKCOUNT 34
#define M_SYS_CLKCOUNT _SB_MAKEMASK(8, S_SYS_CLKCOUNT)
#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x, S_SYS_CLKCOUNT)
#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x, S_SYS_CLKCOUNT, M_SYS_CLKCOUNT)
#define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42)
#define S_SYS_PLL_IREF 43
#define M_SYS_PLL_IREF _SB_MAKEMASK(2, S_SYS_PLL_IREF)
#define S_SYS_PLL_VCO 45
#define M_SYS_PLL_VCO _SB_MAKEMASK(2, S_SYS_PLL_VCO)
#define S_SYS_PLL_VREG 47
#define M_SYS_PLL_VREG _SB_MAKEMASK(2, S_SYS_PLL_VREG)
#define M_SYS_MEM_RESET _SB_MAKEMASK1(49)
#define M_SYS_L2C_RESET _SB_MAKEMASK1(50)
#define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51)
#define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52)
#define M_SYS_SCD_RESET _SB_MAKEMASK1(53)
/* End of bits writable by JTAG only. */
#define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54)
#define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55)
#define M_SYS_UNICPU0 _SB_MAKEMASK1(56)
#define M_SYS_UNICPU1 _SB_MAKEMASK1(57)
#define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58)
#define M_SYS_EXT_RESET _SB_MAKEMASK1(59)
#define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60)
#define M_SYS_MISR_MODE _SB_MAKEMASK1(61)
#define M_SYS_MISR_RESET _SB_MAKEMASK1(62)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
#define M_SYS_SW_FLAG _SB_MAKEMASK1(63)
#endif /* 1250 PASS2 || 112x PASS1 */
#endif
/*
* Mailbox Registers (Table 4-3)
* Registers: SCD_MBOX_CPU_x
*/
#define S_MBOX_INT_3 0
#define M_MBOX_INT_3 _SB_MAKEMASK(16, S_MBOX_INT_3)
#define S_MBOX_INT_2 16
#define M_MBOX_INT_2 _SB_MAKEMASK(16, S_MBOX_INT_2)
#define S_MBOX_INT_1 32
#define M_MBOX_INT_1 _SB_MAKEMASK(16, S_MBOX_INT_1)
#define S_MBOX_INT_0 48
#define M_MBOX_INT_0 _SB_MAKEMASK(16, S_MBOX_INT_0)
/*
* Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10)
* Registers: SCD_WDOG_INIT_CNT_x
*/
#define V_SCD_WDOG_FREQ 1000000
#define S_SCD_WDOG_INIT 0
#define M_SCD_WDOG_INIT _SB_MAKEMASK(23, S_SCD_WDOG_INIT)
#define S_SCD_WDOG_CNT 0
#define M_SCD_WDOG_CNT _SB_MAKEMASK(23, S_SCD_WDOG_CNT)
#define S_SCD_WDOG_ENABLE 0
#define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE)
#define S_SCD_WDOG_RESET_TYPE 2
#define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3, S_SCD_WDOG_RESET_TYPE)
#define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_SCD_WDOG_RESET_TYPE)
#define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_SCD_WDOG_RESET_TYPE, M_SCD_WDOG_RESET_TYPE)
#define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */
#define K_SCD_WDOG_RESET_SOFT 1
#define K_SCD_WDOG_RESET_CPU0 3
#define K_SCD_WDOG_RESET_CPU1 5
#define K_SCD_WDOG_RESET_BOTH_CPUS 7
/* This feature is present in 1250 C0 and later, but *not* in 112x A revs. */
#if SIBYTE_HDR_FEATURE(1250, PASS3)
#define S_SCD_WDOG_HAS_RESET 8
#define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET)
#endif
/*
* Timer Registers (Table 4-11) (Table 4-12) (Table 4-13)
*/
#define V_SCD_TIMER_FREQ 1000000
#define S_SCD_TIMER_INIT 0
#define M_SCD_TIMER_INIT _SB_MAKEMASK(23, S_SCD_TIMER_INIT)
#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_INIT)
#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x, S_SCD_TIMER_INIT, M_SCD_TIMER_INIT)
#define V_SCD_TIMER_WIDTH 23
#define S_SCD_TIMER_CNT 0
#define M_SCD_TIMER_CNT _SB_MAKEMASK(V_SCD_TIMER_WIDTH, S_SCD_TIMER_CNT)
#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x, S_SCD_TIMER_CNT)
#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x, S_SCD_TIMER_CNT, M_SCD_TIMER_CNT)
#define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0)
#define M_SCD_TIMER_MODE _SB_MAKEMASK1(1)
#define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE
/*
* System Performance Counters
*/
#define S_SPC_CFG_SRC0 0
#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8, S_SPC_CFG_SRC0)
#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC0)
#define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x, S_SPC_CFG_SRC0, M_SPC_CFG_SRC0)
#define S_SPC_CFG_SRC1 8
#define M_SPC_CFG_SRC1 _SB_MAKEMASK(8, S_SPC_CFG_SRC1)
#define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC1)
#define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x, S_SPC_CFG_SRC1, M_SPC_CFG_SRC1)
#define S_SPC_CFG_SRC2 16
#define M_SPC_CFG_SRC2 _SB_MAKEMASK(8, S_SPC_CFG_SRC2)
#define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC2)
#define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x, S_SPC_CFG_SRC2, M_SPC_CFG_SRC2)
#define S_SPC_CFG_SRC3 24
#define M_SPC_CFG_SRC3 _SB_MAKEMASK(8, S_SPC_CFG_SRC3)
#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC3)
#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x, S_SPC_CFG_SRC3, M_SPC_CFG_SRC3)
#if SIBYTE_HDR_FEATURE_1250_112x
#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32)
#define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33)
#endif
/*
* Bus Watcher
*/
#define S_SCD_BERR_TID 8
#define M_SCD_BERR_TID _SB_MAKEMASK(10, S_SCD_BERR_TID)
#define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x, S_SCD_BERR_TID)
#define G_SCD_BERR_TID(x) _SB_GETVALUE(x, S_SCD_BERR_TID, M_SCD_BERR_TID)
#define S_SCD_BERR_RID 18
#define M_SCD_BERR_RID _SB_MAKEMASK(4, S_SCD_BERR_RID)
#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x, S_SCD_BERR_RID)
#define G_SCD_BERR_RID(x) _SB_GETVALUE(x, S_SCD_BERR_RID, M_SCD_BERR_RID)
#define S_SCD_BERR_DCODE 22
#define M_SCD_BERR_DCODE _SB_MAKEMASK(3, S_SCD_BERR_DCODE)
#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x, S_SCD_BERR_DCODE)
#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x, S_SCD_BERR_DCODE, M_SCD_BERR_DCODE)
#define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30)
#define S_SCD_L2ECC_CORR_D 0
#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_D)
#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_D)
#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_D, M_SCD_L2ECC_CORR_D)
#define S_SCD_L2ECC_BAD_D 8
#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_D)
#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_D)
#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_D, M_SCD_L2ECC_BAD_D)
#define S_SCD_L2ECC_CORR_T 16
#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_T)
#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_T)
#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_CORR_T, M_SCD_L2ECC_CORR_T)
#define S_SCD_L2ECC_BAD_T 24
#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_T)
#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_T)
#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x, S_SCD_L2ECC_BAD_T, M_SCD_L2ECC_BAD_T)
#define S_SCD_MEM_ECC_CORR 0
#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8, S_SCD_MEM_ECC_CORR)
#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_CORR)
#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_CORR, M_SCD_MEM_ECC_CORR)
#define S_SCD_MEM_ECC_BAD 8
#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8, S_SCD_MEM_ECC_BAD)
#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x, S_SCD_MEM_ECC_BAD)
#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x, S_SCD_MEM_ECC_BAD, M_SCD_MEM_ECC_BAD)
#define S_SCD_MEM_BUSERR 16
#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8, S_SCD_MEM_BUSERR)
#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x, S_SCD_MEM_BUSERR)
#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x, S_SCD_MEM_BUSERR, M_SCD_MEM_BUSERR)
/*
* Address Trap Registers
*/
#if SIBYTE_HDR_FEATURE_1250_112x
#define M_ATRAP_INDEX _SB_MAKEMASK(4, 0)
#define M_ATRAP_ADDRESS _SB_MAKEMASK(40, 0)
#define S_ATRAP_CFG_CNT 0
#define M_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_ATRAP_CFG_CNT)
#define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_CNT)
#define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_ATRAP_CFG_CNT, M_ATRAP_CFG_CNT)
#define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3)
#define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4)
#define M_ATRAP_CFG_INV _SB_MAKEMASK1(5)
#define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6)
#define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7)
#define S_ATRAP_CFG_AGENTID 8
#define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_ATRAP_CFG_AGENTID)
#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_AGENTID)
#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_ATRAP_CFG_AGENTID, M_ATRAP_CFG_AGENTID)
#define K_BUS_AGENT_CPU0 0
#define K_BUS_AGENT_CPU1 1
#define K_BUS_AGENT_IOB0 2
#define K_BUS_AGENT_IOB1 3
#define K_BUS_AGENT_SCD 4
#define K_BUS_AGENT_L2C 6
#define K_BUS_AGENT_MC 7
#define S_ATRAP_CFG_CATTR 12
#define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3, S_ATRAP_CFG_CATTR)
#define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_CATTR)
#define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_ATRAP_CFG_CATTR, M_ATRAP_CFG_CATTR)
#define K_ATRAP_CFG_CATTR_IGNORE 0
#define K_ATRAP_CFG_CATTR_UNC 1
#define K_ATRAP_CFG_CATTR_CACHEABLE 2
#define K_ATRAP_CFG_CATTR_NONCOH 3
#define K_ATRAP_CFG_CATTR_COHERENT 4
#define K_ATRAP_CFG_CATTR_NOTUNC 5
#define K_ATRAP_CFG_CATTR_NOTNONCOH 6
#define K_ATRAP_CFG_CATTR_NOTCOHERENT 7
#endif /* 1250/112x */
/*
* Trace Buffer Config register
*/
#define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0)
#define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1)
#define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2)
#define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3)
#define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4)
#define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
#define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6)
#define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8)
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
/*
* This field is the same on the 1250/112x and 1480, just located in
* a slightly different place in the register.
*/
#if SIBYTE_HDR_FEATURE_1250_112x
#define S_SCD_TRACE_CFG_CUR_ADDR 10
#else
#if SIBYTE_HDR_FEATURE_CHIP(1480)
#define S_SCD_TRACE_CFG_CUR_ADDR 24
#endif /* 1480 */
#endif /* 1250/112x */
#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8, S_SCD_TRACE_CFG_CUR_ADDR)
#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR)
#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR, M_SCD_TRACE_CFG_CUR_ADDR)
/*
* Trace Event registers
*/
#define S_SCD_TREVT_ADDR_MATCH 0
#define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4, S_SCD_TREVT_ADDR_MATCH)
#define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x, S_SCD_TREVT_ADDR_MATCH)
#define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x, S_SCD_TREVT_ADDR_MATCH, M_SCD_TREVT_ADDR_MATCH)
#define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4)
#define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5)
#define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6)
#define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7)
#define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9)
#define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10)
#define M_SCD_TREVT_READ _SB_MAKEMASK1(11)
#define S_SCD_TREVT_REQID 12
#define M_SCD_TREVT_REQID _SB_MAKEMASK(4, S_SCD_TREVT_REQID)
#define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_REQID)
#define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x, S_SCD_TREVT_REQID, M_SCD_TREVT_REQID)
#define S_SCD_TREVT_RESPID 16
#define M_SCD_TREVT_RESPID _SB_MAKEMASK(4, S_SCD_TREVT_RESPID)
#define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_RESPID)
#define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x, S_SCD_TREVT_RESPID, M_SCD_TREVT_RESPID)
#define S_SCD_TREVT_DATAID 20
#define M_SCD_TREVT_DATAID _SB_MAKEMASK(4, S_SCD_TREVT_DATAID)
#define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x, S_SCD_TREVT_DATAID)
#define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x, S_SCD_TREVT_DATAID, M_SCD_TREVT_DATID)
#define S_SCD_TREVT_COUNT 24
#define M_SCD_TREVT_COUNT _SB_MAKEMASK(8, S_SCD_TREVT_COUNT)
#define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x, S_SCD_TREVT_COUNT)
#define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x, S_SCD_TREVT_COUNT, M_SCD_TREVT_COUNT)
/*
* Trace Sequence registers
*/
#define S_SCD_TRSEQ_EVENT4 0
#define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT4)
#define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT4)
#define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT4, M_SCD_TRSEQ_EVENT4)
#define S_SCD_TRSEQ_EVENT3 4
#define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT3)
#define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT3)
#define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT3, M_SCD_TRSEQ_EVENT3)
#define S_SCD_TRSEQ_EVENT2 8
#define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT2)
#define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT2)
#define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT2, M_SCD_TRSEQ_EVENT2)
#define S_SCD_TRSEQ_EVENT1 12
#define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT1)
#define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT1)
#define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT1, M_SCD_TRSEQ_EVENT1)
#define K_SCD_TRSEQ_E0 0
#define K_SCD_TRSEQ_E1 1
#define K_SCD_TRSEQ_E2 2
#define K_SCD_TRSEQ_E3 3
#define K_SCD_TRSEQ_E0_E1 4
#define K_SCD_TRSEQ_E1_E2 5
#define K_SCD_TRSEQ_E2_E3 6
#define K_SCD_TRSEQ_E0_E1_E2 7
#define K_SCD_TRSEQ_E0_E1_E2_E3 8
#define K_SCD_TRSEQ_E0E1 9
#define K_SCD_TRSEQ_E0E1E2 10
#define K_SCD_TRSEQ_E0E1E2E3 11
#define K_SCD_TRSEQ_E0E1_E2 12
#define K_SCD_TRSEQ_E0E1_E2E3 13
#define K_SCD_TRSEQ_E0E1_E2_E3 14
#define K_SCD_TRSEQ_IGNORED 15
#define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \
V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \
V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \
V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED))
#define S_SCD_TRSEQ_FUNCTION 16
#define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4, S_SCD_TRSEQ_FUNCTION)
#define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x, S_SCD_TRSEQ_FUNCTION)
#define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x, S_SCD_TRSEQ_FUNCTION, M_SCD_TRSEQ_FUNCTION)
#define K_SCD_TRSEQ_FUNC_NOP 0
#define K_SCD_TRSEQ_FUNC_START 1
#define K_SCD_TRSEQ_FUNC_STOP 2
#define K_SCD_TRSEQ_FUNC_FREEZE 3
#define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP)
#define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START)
#define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP)
#define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE)
#define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18)
#define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19)
#define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20)
#define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21)
#define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22)
#define M_SCD_TRSEQ_ALLD_A _SB_MAKEMASK1(23)
#define M_SCD_TRSEQ_ALL_A _SB_MAKEMASK1(24)
#endif

204
kernel/arch/mips/include/asm/sibyte/sb1250_smbus.h Normal file
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@@ -0,0 +1,204 @@
/* *********************************************************************
* SB1250 Board Support Package
*
* SMBUS Constants File: sb1250_smbus.h
*
* This module contains constants and macros useful for
* manipulating the SB1250's SMbus devices.
*
* SB1250 specification level: 10/21/02
* BCM1280 specification level: 11/24/03
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_SMBUS_H
#define _SB1250_SMBUS_H
#include "sb1250_defs.h"
/*
* SMBus Clock Frequency Register (Table 14-2)
*/
#define S_SMB_FREQ_DIV 0
#define M_SMB_FREQ_DIV _SB_MAKEMASK(13, S_SMB_FREQ_DIV)
#define V_SMB_FREQ_DIV(x) _SB_MAKEVALUE(x, S_SMB_FREQ_DIV)
#define K_SMB_FREQ_400KHZ 0x1F
#define K_SMB_FREQ_100KHZ 0x7D
#define K_SMB_FREQ_10KHZ 1250
#define S_SMB_CMD 0
#define M_SMB_CMD _SB_MAKEMASK(8, S_SMB_CMD)
#define V_SMB_CMD(x) _SB_MAKEVALUE(x, S_SMB_CMD)
/*
* SMBus control register (Table 14-4)
*/
#define M_SMB_ERR_INTR _SB_MAKEMASK1(0)
#define M_SMB_FINISH_INTR _SB_MAKEMASK1(1)
#define S_SMB_DATA_OUT 4
#define M_SMB_DATA_OUT _SB_MAKEMASK1(S_SMB_DATA_OUT)
#define V_SMB_DATA_OUT(x) _SB_MAKEVALUE(x, S_SMB_DATA_OUT)
#define M_SMB_DATA_DIR _SB_MAKEMASK1(5)
#define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR
#define M_SMB_CLK_OUT _SB_MAKEMASK1(6)
#define M_SMB_DIRECT_ENABLE _SB_MAKEMASK1(7)
/*
* SMBus status registers (Table 14-5)
*/
#define M_SMB_BUSY _SB_MAKEMASK1(0)
#define M_SMB_ERROR _SB_MAKEMASK1(1)
#define M_SMB_ERROR_TYPE _SB_MAKEMASK1(2)
#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define S_SMB_SCL_IN 5
#define M_SMB_SCL_IN _SB_MAKEMASK1(S_SMB_SCL_IN)
#define V_SMB_SCL_IN(x) _SB_MAKEVALUE(x, S_SMB_SCL_IN)
#define G_SMB_SCL_IN(x) _SB_GETVALUE(x, S_SMB_SCL_IN, M_SMB_SCL_IN)
#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
#define S_SMB_REF 6
#define M_SMB_REF _SB_MAKEMASK1(S_SMB_REF)
#define V_SMB_REF(x) _SB_MAKEVALUE(x, S_SMB_REF)
#define G_SMB_REF(x) _SB_GETVALUE(x, S_SMB_REF, M_SMB_REF)
#define S_SMB_DATA_IN 7
#define M_SMB_DATA_IN _SB_MAKEMASK1(S_SMB_DATA_IN)
#define V_SMB_DATA_IN(x) _SB_MAKEVALUE(x, S_SMB_DATA_IN)
#define G_SMB_DATA_IN(x) _SB_GETVALUE(x, S_SMB_DATA_IN, M_SMB_DATA_IN)
/*
* SMBus Start/Command registers (Table 14-9)
*/
#define S_SMB_ADDR 0
#define M_SMB_ADDR _SB_MAKEMASK(7, S_SMB_ADDR)
#define V_SMB_ADDR(x) _SB_MAKEVALUE(x, S_SMB_ADDR)
#define G_SMB_ADDR(x) _SB_GETVALUE(x, S_SMB_ADDR, M_SMB_ADDR)
#define M_SMB_QDATA _SB_MAKEMASK1(7)
#define S_SMB_TT 8
#define M_SMB_TT _SB_MAKEMASK(3, S_SMB_TT)
#define V_SMB_TT(x) _SB_MAKEVALUE(x, S_SMB_TT)
#define G_SMB_TT(x) _SB_GETVALUE(x, S_SMB_TT, M_SMB_TT)
#define K_SMB_TT_WR1BYTE 0
#define K_SMB_TT_WR2BYTE 1
#define K_SMB_TT_WR3BYTE 2
#define K_SMB_TT_CMD_RD1BYTE 3
#define K_SMB_TT_CMD_RD2BYTE 4
#define K_SMB_TT_RD1BYTE 5
#define K_SMB_TT_QUICKCMD 6
#define K_SMB_TT_EEPROMREAD 7
#define V_SMB_TT_WR1BYTE V_SMB_TT(K_SMB_TT_WR1BYTE)
#define V_SMB_TT_WR2BYTE V_SMB_TT(K_SMB_TT_WR2BYTE)
#define V_SMB_TT_WR3BYTE V_SMB_TT(K_SMB_TT_WR3BYTE)
#define V_SMB_TT_CMD_RD1BYTE V_SMB_TT(K_SMB_TT_CMD_RD1BYTE)
#define V_SMB_TT_CMD_RD2BYTE V_SMB_TT(K_SMB_TT_CMD_RD2BYTE)
#define V_SMB_TT_RD1BYTE V_SMB_TT(K_SMB_TT_RD1BYTE)
#define V_SMB_TT_QUICKCMD V_SMB_TT(K_SMB_TT_QUICKCMD)
#define V_SMB_TT_EEPROMREAD V_SMB_TT(K_SMB_TT_EEPROMREAD)
#define M_SMB_PEC _SB_MAKEMASK1(15)
/*
* SMBus Data Register (Table 14-6) and SMBus Extra Register (Table 14-7)
*/
#define S_SMB_LB 0
#define M_SMB_LB _SB_MAKEMASK(8, S_SMB_LB)
#define V_SMB_LB(x) _SB_MAKEVALUE(x, S_SMB_LB)
#define S_SMB_MB 8
#define M_SMB_MB _SB_MAKEMASK(8, S_SMB_MB)
#define V_SMB_MB(x) _SB_MAKEVALUE(x, S_SMB_MB)
/*
* SMBus Packet Error Check register (Table 14-8)
*/
#define S_SPEC_PEC 0
#define M_SPEC_PEC _SB_MAKEMASK(8, S_SPEC_PEC)
#define V_SPEC_MB(x) _SB_MAKEVALUE(x, S_SPEC_PEC)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
#define S_SMB_CMDH 8
#define M_SMB_CMDH _SB_MAKEMASK(8, S_SMB_CMDH)
#define V_SMB_CMDH(x) _SB_MAKEVALUE(x, S_SMB_CMDH)
#define M_SMB_EXTEND _SB_MAKEMASK1(14)
#define S_SMB_DFMT 8
#define M_SMB_DFMT _SB_MAKEMASK(3, S_SMB_DFMT)
#define V_SMB_DFMT(x) _SB_MAKEVALUE(x, S_SMB_DFMT)
#define G_SMB_DFMT(x) _SB_GETVALUE(x, S_SMB_DFMT, M_SMB_DFMT)
#define K_SMB_DFMT_1BYTE 0
#define K_SMB_DFMT_2BYTE 1
#define K_SMB_DFMT_3BYTE 2
#define K_SMB_DFMT_4BYTE 3
#define K_SMB_DFMT_NODATA 4
#define K_SMB_DFMT_CMD4BYTE 5
#define K_SMB_DFMT_CMD5BYTE 6
#define K_SMB_DFMT_RESERVED 7
#define V_SMB_DFMT_1BYTE V_SMB_DFMT(K_SMB_DFMT_1BYTE)
#define V_SMB_DFMT_2BYTE V_SMB_DFMT(K_SMB_DFMT_2BYTE)
#define V_SMB_DFMT_3BYTE V_SMB_DFMT(K_SMB_DFMT_3BYTE)
#define V_SMB_DFMT_4BYTE V_SMB_DFMT(K_SMB_DFMT_4BYTE)
#define V_SMB_DFMT_NODATA V_SMB_DFMT(K_SMB_DFMT_NODATA)
#define V_SMB_DFMT_CMD4BYTE V_SMB_DFMT(K_SMB_DFMT_CMD4BYTE)
#define V_SMB_DFMT_CMD5BYTE V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE)
#define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED)
#define S_SMB_AFMT 11
#define M_SMB_AFMT _SB_MAKEMASK(2, S_SMB_AFMT)
#define V_SMB_AFMT(x) _SB_MAKEVALUE(x, S_SMB_AFMT)
#define G_SMB_AFMT(x) _SB_GETVALUE(x, S_SMB_AFMT, M_SMB_AFMT)
#define K_SMB_AFMT_NONE 0
#define K_SMB_AFMT_ADDR 1
#define K_SMB_AFMT_ADDR_CMD1BYTE 2
#define K_SMB_AFMT_ADDR_CMD2BYTE 3
#define V_SMB_AFMT_NONE V_SMB_AFMT(K_SMB_AFMT_NONE)
#define V_SMB_AFMT_ADDR V_SMB_AFMT(K_SMB_AFMT_ADDR)
#define V_SMB_AFMT_ADDR_CMD1BYTE V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD1BYTE)
#define V_SMB_AFMT_ADDR_CMD2BYTE V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD2BYTE)
#define M_SMB_DIR _SB_MAKEMASK1(13)
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
#endif

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kernel/arch/mips/include/asm/sibyte/sb1250_syncser.h Normal file
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/* *********************************************************************
* SB1250 Board Support Package
*
* Synchronous Serial Constants File: sb1250_syncser.h
*
* This module contains constants and macros useful for
* manipulating the SB1250's Synchronous Serial
*
* SB1250 specification level: User's manual 1/02/02
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_SYNCSER_H
#define _SB1250_SYNCSER_H
#include "sb1250_defs.h"
/*
* Serial Mode Configuration Register
*/
#define M_SYNCSER_CRC_MODE _SB_MAKEMASK1(0)
#define M_SYNCSER_MSB_FIRST _SB_MAKEMASK1(1)
#define S_SYNCSER_FLAG_NUM 2
#define M_SYNCSER_FLAG_NUM _SB_MAKEMASK(4, S_SYNCSER_FLAG_NUM)
#define V_SYNCSER_FLAG_NUM _SB_MAKEVALUE(x, S_SYNCSER_FLAG_NUM)
#define M_SYNCSER_FLAG_EN _SB_MAKEMASK1(6)
#define M_SYNCSER_HDLC_EN _SB_MAKEMASK1(7)
#define M_SYNCSER_LOOP_MODE _SB_MAKEMASK1(8)
#define M_SYNCSER_LOOPBACK _SB_MAKEMASK1(9)
/*
* Serial Clock Source and Line Interface Mode Register
*/
#define M_SYNCSER_RXCLK_INV _SB_MAKEMASK1(0)
#define M_SYNCSER_RXCLK_EXT _SB_MAKEMASK1(1)
#define S_SYNCSER_RXSYNC_DLY 2
#define M_SYNCSER_RXSYNC_DLY _SB_MAKEMASK(2, S_SYNCSER_RXSYNC_DLY)
#define V_SYNCSER_RXSYNC_DLY(x) _SB_MAKEVALUE(x, S_SYNCSER_RXSYNC_DLY)
#define M_SYNCSER_RXSYNC_LOW _SB_MAKEMASK1(4)
#define M_SYNCSER_RXSTRB_LOW _SB_MAKEMASK1(5)
#define M_SYNCSER_RXSYNC_EDGE _SB_MAKEMASK1(6)
#define M_SYNCSER_RXSYNC_INT _SB_MAKEMASK1(7)
#define M_SYNCSER_TXCLK_INV _SB_MAKEMASK1(8)
#define M_SYNCSER_TXCLK_EXT _SB_MAKEMASK1(9)
#define S_SYNCSER_TXSYNC_DLY 10
#define M_SYNCSER_TXSYNC_DLY _SB_MAKEMASK(2, S_SYNCSER_TXSYNC_DLY)
#define V_SYNCSER_TXSYNC_DLY(x) _SB_MAKEVALUE(x, S_SYNCSER_TXSYNC_DLY)
#define M_SYNCSER_TXSYNC_LOW _SB_MAKEMASK1(12)
#define M_SYNCSER_TXSTRB_LOW _SB_MAKEMASK1(13)
#define M_SYNCSER_TXSYNC_EDGE _SB_MAKEMASK1(14)
#define M_SYNCSER_TXSYNC_INT _SB_MAKEMASK1(15)
/*
* Serial Command Register
*/
#define M_SYNCSER_CMD_RX_EN _SB_MAKEMASK1(0)
#define M_SYNCSER_CMD_TX_EN _SB_MAKEMASK1(1)
#define M_SYNCSER_CMD_RX_RESET _SB_MAKEMASK1(2)
#define M_SYNCSER_CMD_TX_RESET _SB_MAKEMASK1(3)
#define M_SYNCSER_CMD_TX_PAUSE _SB_MAKEMASK1(5)
/*
* Serial DMA Enable Register
*/
#define M_SYNCSER_DMA_RX_EN _SB_MAKEMASK1(0)
#define M_SYNCSER_DMA_TX_EN _SB_MAKEMASK1(4)
/*
* Serial Status Register
*/
#define M_SYNCSER_RX_CRCERR _SB_MAKEMASK1(0)
#define M_SYNCSER_RX_ABORT _SB_MAKEMASK1(1)
#define M_SYNCSER_RX_OCTET _SB_MAKEMASK1(2)
#define M_SYNCSER_RX_LONGFRM _SB_MAKEMASK1(3)
#define M_SYNCSER_RX_SHORTFRM _SB_MAKEMASK1(4)
#define M_SYNCSER_RX_OVERRUN _SB_MAKEMASK1(5)
#define M_SYNCSER_RX_SYNC_ERR _SB_MAKEMASK1(6)
#define M_SYNCSER_TX_CRCERR _SB_MAKEMASK1(8)
#define M_SYNCSER_TX_UNDERRUN _SB_MAKEMASK1(9)
#define M_SYNCSER_TX_SYNC_ERR _SB_MAKEMASK1(10)
#define M_SYNCSER_TX_PAUSE_COMPLETE _SB_MAKEMASK1(11)
#define M_SYNCSER_RX_EOP_COUNT _SB_MAKEMASK1(16)
#define M_SYNCSER_RX_EOP_TIMER _SB_MAKEMASK1(17)
#define M_SYNCSER_RX_EOP_SEEN _SB_MAKEMASK1(18)
#define M_SYNCSER_RX_HWM _SB_MAKEMASK1(19)
#define M_SYNCSER_RX_LWM _SB_MAKEMASK1(20)
#define M_SYNCSER_RX_DSCR _SB_MAKEMASK1(21)
#define M_SYNCSER_RX_DERR _SB_MAKEMASK1(22)
#define M_SYNCSER_TX_EOP_COUNT _SB_MAKEMASK1(24)
#define M_SYNCSER_TX_EOP_TIMER _SB_MAKEMASK1(25)
#define M_SYNCSER_TX_EOP_SEEN _SB_MAKEMASK1(26)
#define M_SYNCSER_TX_HWM _SB_MAKEMASK1(27)
#define M_SYNCSER_TX_LWM _SB_MAKEMASK1(28)
#define M_SYNCSER_TX_DSCR _SB_MAKEMASK1(29)
#define M_SYNCSER_TX_DERR _SB_MAKEMASK1(30)
#define M_SYNCSER_TX_DZERO _SB_MAKEMASK1(31)
/*
* Sequencer Table Entry format
*/
#define M_SYNCSER_SEQ_LAST _SB_MAKEMASK1(0)
#define M_SYNCSER_SEQ_BYTE _SB_MAKEMASK1(1)
#define S_SYNCSER_SEQ_COUNT 2
#define M_SYNCSER_SEQ_COUNT _SB_MAKEMASK(4, S_SYNCSER_SEQ_COUNT)
#define V_SYNCSER_SEQ_COUNT(x) _SB_MAKEVALUE(x, S_SYNCSER_SEQ_COUNT)
#define M_SYNCSER_SEQ_ENABLE _SB_MAKEMASK1(6)
#define M_SYNCSER_SEQ_STROBE _SB_MAKEMASK1(7)
#endif

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kernel/arch/mips/include/asm/sibyte/sb1250_uart.h Normal file
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/* *********************************************************************
* SB1250 Board Support Package
*
* UART Constants File: sb1250_uart.h
*
* This module contains constants and macros useful for
* manipulating the SB1250's UARTs
*
* SB1250 specification level: User's manual 1/02/02
*
*********************************************************************
*
* Copyright 2000,2001,2002,2003
* Broadcom Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
********************************************************************* */
#ifndef _SB1250_UART_H
#define _SB1250_UART_H
#include "sb1250_defs.h"
/* **********************************************************************
* DUART Registers
********************************************************************** */
/*
* DUART Mode Register #1 (Table 10-3)
* Register: DUART_MODE_REG_1_A
* Register: DUART_MODE_REG_1_B
*/
#define S_DUART_BITS_PER_CHAR 0
#define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR)
#define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR)
#define K_DUART_BITS_PER_CHAR_RSV0 0
#define K_DUART_BITS_PER_CHAR_RSV1 1
#define K_DUART_BITS_PER_CHAR_7 2
#define K_DUART_BITS_PER_CHAR_8 3
#define V_DUART_BITS_PER_CHAR_RSV0 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0)
#define V_DUART_BITS_PER_CHAR_RSV1 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1)
#define V_DUART_BITS_PER_CHAR_7 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7)
#define V_DUART_BITS_PER_CHAR_8 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8)
#define M_DUART_PARITY_TYPE_EVEN 0x00
#define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2)
#define S_DUART_PARITY_MODE 3
#define M_DUART_PARITY_MODE _SB_MAKEMASK(2, S_DUART_PARITY_MODE)
#define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x, S_DUART_PARITY_MODE)
#define K_DUART_PARITY_MODE_ADD 0
#define K_DUART_PARITY_MODE_ADD_FIXED 1
#define K_DUART_PARITY_MODE_NONE 2
#define V_DUART_PARITY_MODE_ADD V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD)
#define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED)
#define V_DUART_PARITY_MODE_NONE V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE)
#define M_DUART_TX_IRQ_SEL_TXRDY 0
#define M_DUART_TX_IRQ_SEL_TXEMPT _SB_MAKEMASK1(5)
#define M_DUART_RX_IRQ_SEL_RXRDY 0
#define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6)
#define M_DUART_RX_RTS_ENA _SB_MAKEMASK1(7)
/*
* DUART Mode Register #2 (Table 10-4)
* Register: DUART_MODE_REG_2_A
* Register: DUART_MODE_REG_2_B
*/
#define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3, 0) /* ignored */
#define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3)
#define M_DUART_STOP_BIT_LEN_1 0
#define M_DUART_TX_CTS_ENA _SB_MAKEMASK1(4)
#define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */
#define S_DUART_CHAN_MODE 6
#define M_DUART_CHAN_MODE _SB_MAKEMASK(2, S_DUART_CHAN_MODE)
#define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x, S_DUART_CHAN_MODE)
#define K_DUART_CHAN_MODE_NORMAL 0
#define K_DUART_CHAN_MODE_LCL_LOOP 2
#define K_DUART_CHAN_MODE_REM_LOOP 3
#define V_DUART_CHAN_MODE_NORMAL V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL)
#define V_DUART_CHAN_MODE_LCL_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP)
#define V_DUART_CHAN_MODE_REM_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP)
/*
* DUART Command Register (Table 10-5)
* Register: DUART_CMD_A
* Register: DUART_CMD_B
*/
#define M_DUART_RX_EN _SB_MAKEMASK1(0)
#define M_DUART_RX_DIS _SB_MAKEMASK1(1)
#define M_DUART_TX_EN _SB_MAKEMASK1(2)
#define M_DUART_TX_DIS _SB_MAKEMASK1(3)
#define S_DUART_MISC_CMD 4
#define M_DUART_MISC_CMD _SB_MAKEMASK(3, S_DUART_MISC_CMD)
#define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x, S_DUART_MISC_CMD)
#define K_DUART_MISC_CMD_NOACTION0 0
#define K_DUART_MISC_CMD_NOACTION1 1
#define K_DUART_MISC_CMD_RESET_RX 2
#define K_DUART_MISC_CMD_RESET_TX 3
#define K_DUART_MISC_CMD_NOACTION4 4
#define K_DUART_MISC_CMD_RESET_BREAK_INT 5
#define K_DUART_MISC_CMD_START_BREAK 6
#define K_DUART_MISC_CMD_STOP_BREAK 7
#define V_DUART_MISC_CMD_NOACTION0 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0)
#define V_DUART_MISC_CMD_NOACTION1 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1)
#define V_DUART_MISC_CMD_RESET_RX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX)
#define V_DUART_MISC_CMD_RESET_TX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX)
#define V_DUART_MISC_CMD_NOACTION4 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4)
#define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT)
#define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK)
#define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK)
#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7)
/*
* DUART Status Register (Table 10-6)
* Register: DUART_STATUS_A
* Register: DUART_STATUS_B
* READ-ONLY
*/
#define M_DUART_RX_RDY _SB_MAKEMASK1(0)
#define M_DUART_RX_FFUL _SB_MAKEMASK1(1)
#define M_DUART_TX_RDY _SB_MAKEMASK1(2)
#define M_DUART_TX_EMT _SB_MAKEMASK1(3)
#define M_DUART_OVRUN_ERR _SB_MAKEMASK1(4)
#define M_DUART_PARITY_ERR _SB_MAKEMASK1(5)
#define M_DUART_FRM_ERR _SB_MAKEMASK1(6)
#define M_DUART_RCVD_BRK _SB_MAKEMASK1(7)
/*
* DUART Baud Rate Register (Table 10-7)
* Register: DUART_CLK_SEL_A
* Register: DUART_CLK_SEL_B
*/
#define M_DUART_CLK_COUNTER _SB_MAKEMASK(12, 0)
#define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1)
/*
* DUART Data Registers (Table 10-8 and 10-9)
* Register: DUART_RX_HOLD_A
* Register: DUART_RX_HOLD_B
* Register: DUART_TX_HOLD_A
* Register: DUART_TX_HOLD_B
*/
#define M_DUART_RX_DATA _SB_MAKEMASK(8, 0)
#define M_DUART_TX_DATA _SB_MAKEMASK(8, 0)
/*
* DUART Input Port Register (Table 10-10)
* Register: DUART_IN_PORT
*/
#define M_DUART_IN_PIN0_VAL _SB_MAKEMASK1(0)
#define M_DUART_IN_PIN1_VAL _SB_MAKEMASK1(1)
#define M_DUART_IN_PIN2_VAL _SB_MAKEMASK1(2)
#define M_DUART_IN_PIN3_VAL _SB_MAKEMASK1(3)
#define M_DUART_IN_PIN4_VAL _SB_MAKEMASK1(4)
#define M_DUART_IN_PIN5_VAL _SB_MAKEMASK1(5)
#define M_DUART_RIN0_PIN _SB_MAKEMASK1(6)
#define M_DUART_RIN1_PIN _SB_MAKEMASK1(7)
/*
* DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13)
* Register: DUART_INPORT_CHNG
*/
#define S_DUART_IN_PIN_VAL 0
#define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL)
#define S_DUART_IN_PIN_CHNG 4
#define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG)
/*
* DUART Output port control register (Table 10-14)
* Register: DUART_OPCR
*/
#define M_DUART_OPCR_RESERVED0 _SB_MAKEMASK1(0) /* must be zero */
#define M_DUART_OPC2_SEL _SB_MAKEMASK1(1)
#define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */
#define M_DUART_OPC3_SEL _SB_MAKEMASK1(3)
#define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4, 4) /* must be zero */
/*
* DUART Aux Control Register (Table 10-15)
* Register: DUART_AUX_CTRL
*/
#define M_DUART_IP0_CHNG_ENA _SB_MAKEMASK1(0)
#define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1)
#define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2)
#define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3)
#define M_DUART_ACR_RESERVED _SB_MAKEMASK(4, 4)
#define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0)
#define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2)
/*
* DUART Interrupt Status Register (Table 10-16)
* Register: DUART_ISR
*/
#define M_DUART_ISR_TX_A _SB_MAKEMASK1(0)
#define S_DUART_ISR_RX_A 1
#define M_DUART_ISR_RX_A _SB_MAKEMASK1(S_DUART_ISR_RX_A)
#define V_DUART_ISR_RX_A(x) _SB_MAKEVALUE(x, S_DUART_ISR_RX_A)
#define G_DUART_ISR_RX_A(x) _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A)
#define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2)
#define M_DUART_ISR_IN_A _SB_MAKEMASK1(3)
#define M_DUART_ISR_ALL_A _SB_MAKEMASK(4, 0)
#define M_DUART_ISR_TX_B _SB_MAKEMASK1(4)
#define M_DUART_ISR_RX_B _SB_MAKEMASK1(5)
#define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6)
#define M_DUART_ISR_IN_B _SB_MAKEMASK1(7)
#define M_DUART_ISR_ALL_B _SB_MAKEMASK(4, 4)
/*
* DUART Channel A Interrupt Status Register (Table 10-17)
* DUART Channel B Interrupt Status Register (Table 10-18)
* Register: DUART_ISR_A
* Register: DUART_ISR_B
*/
#define M_DUART_ISR_TX _SB_MAKEMASK1(0)
#define M_DUART_ISR_RX _SB_MAKEMASK1(1)
#define M_DUART_ISR_BRK _SB_MAKEMASK1(2)
#define M_DUART_ISR_IN _SB_MAKEMASK1(3)
#define M_DUART_ISR_ALL _SB_MAKEMASK(4, 0)
#define M_DUART_ISR_RESERVED _SB_MAKEMASK(4, 4)
/*
* DUART Interrupt Mask Register (Table 10-19)
* Register: DUART_IMR
*/
#define M_DUART_IMR_TX_A _SB_MAKEMASK1(0)
#define M_DUART_IMR_RX_A _SB_MAKEMASK1(1)
#define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2)
#define M_DUART_IMR_IN_A _SB_MAKEMASK1(3)
#define M_DUART_IMR_ALL_A _SB_MAKEMASK(4, 0)
#define M_DUART_IMR_TX_B _SB_MAKEMASK1(4)
#define M_DUART_IMR_RX_B _SB_MAKEMASK1(5)
#define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6)
#define M_DUART_IMR_IN_B _SB_MAKEMASK1(7)
#define M_DUART_IMR_ALL_B _SB_MAKEMASK(4, 4)
/*
* DUART Channel A Interrupt Mask Register (Table 10-20)
* DUART Channel B Interrupt Mask Register (Table 10-21)
* Register: DUART_IMR_A
* Register: DUART_IMR_B
*/
#define M_DUART_IMR_TX _SB_MAKEMASK1(0)
#define M_DUART_IMR_RX _SB_MAKEMASK1(1)
#define M_DUART_IMR_BRK _SB_MAKEMASK1(2)
#define M_DUART_IMR_IN _SB_MAKEMASK1(3)
#define M_DUART_IMR_ALL _SB_MAKEMASK(4, 0)
#define M_DUART_IMR_RESERVED _SB_MAKEMASK(4, 4)
/*
* DUART Output Port Set Register (Table 10-22)
* Register: DUART_SET_OPR
*/
#define M_DUART_SET_OPR0 _SB_MAKEMASK1(0)
#define M_DUART_SET_OPR1 _SB_MAKEMASK1(1)
#define M_DUART_SET_OPR2 _SB_MAKEMASK1(2)
#define M_DUART_SET_OPR3 _SB_MAKEMASK1(3)
#define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4, 4)
/*
* DUART Output Port Clear Register (Table 10-23)
* Register: DUART_CLEAR_OPR
*/
#define M_DUART_CLR_OPR0 _SB_MAKEMASK1(0)
#define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1)
#define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2)
#define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3)
#define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4, 4)
/*
* DUART Output Port RTS Register (Table 10-24)
* Register: DUART_OUT_PORT
*/
#define M_DUART_OUT_PIN_SET0 _SB_MAKEMASK1(0)
#define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1)
#define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2)
#define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3)
#define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4, 4)
#define M_DUART_OUT_PIN_SET(chan) \
(chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1)
#define M_DUART_OUT_PIN_CLR(chan) \
(chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1)
#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
/*
* Full Interrupt Control Register
*/
#define S_DUART_SIG_FULL _SB_MAKE64(0)
#define M_DUART_SIG_FULL _SB_MAKEMASK(4, S_DUART_SIG_FULL)
#define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x, S_DUART_SIG_FULL)
#define G_DUART_SIG_FULL(x) _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL)
#define S_DUART_INT_TIME _SB_MAKE64(4)
#define M_DUART_INT_TIME _SB_MAKEMASK(4, S_DUART_INT_TIME)
#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x, S_DUART_INT_TIME)
#define G_DUART_INT_TIME(x) _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME)
#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
/* ********************************************************************** */
#endif

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kernel/arch/mips/include/asm/sibyte/sentosa.h Normal file
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/*
* Copyright (C) 2000, 2001 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef __ASM_SIBYTE_SENTOSA_H
#define __ASM_SIBYTE_SENTOSA_H
#include <asm/sibyte/sb1250.h>
#include <asm/sibyte/sb1250_int.h>
#ifdef CONFIG_SIBYTE_SENTOSA
#define SIBYTE_BOARD_NAME "BCM91250E (Sentosa)"
#endif
#ifdef CONFIG_SIBYTE_RHONE
#define SIBYTE_BOARD_NAME "BCM91125E (Rhone)"
#endif
/* Generic bus chip selects */
#ifdef CONFIG_SIBYTE_RHONE
#define LEDS_CS 6
#define LEDS_PHYS 0x1d0a0000
#endif
/* GPIOs */
#define K_GPIO_DBG_LED 0
#endif /* __ASM_SIBYTE_SENTOSA_H */

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kernel/arch/mips/include/asm/sibyte/swarm.h Normal file
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/*
* Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef __ASM_SIBYTE_SWARM_H
#define __ASM_SIBYTE_SWARM_H
#include <asm/sibyte/sb1250.h>
#include <asm/sibyte/sb1250_int.h>
#ifdef CONFIG_SIBYTE_SWARM
#define SIBYTE_BOARD_NAME "BCM91250A (SWARM)"
#define SIBYTE_HAVE_PCMCIA 1
#define SIBYTE_HAVE_IDE 1
#endif
#ifdef CONFIG_SIBYTE_LITTLESUR
#define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)"
#define SIBYTE_HAVE_PCMCIA 0
#define SIBYTE_HAVE_IDE 1
#define SIBYTE_DEFAULT_CONSOLE "cfe0"
#endif
#ifdef CONFIG_SIBYTE_CRHONE
#define SIBYTE_BOARD_NAME "BCM91125C (CRhone)"
#define SIBYTE_HAVE_PCMCIA 0
#define SIBYTE_HAVE_IDE 0
#endif
#ifdef CONFIG_SIBYTE_CRHINE
#define SIBYTE_BOARD_NAME "BCM91120C (CRhine)"
#define SIBYTE_HAVE_PCMCIA 0
#define SIBYTE_HAVE_IDE 0
#endif
/* Generic bus chip selects */
#define LEDS_CS 3
#define LEDS_PHYS 0x100a0000
#ifdef SIBYTE_HAVE_IDE
#define IDE_CS 4
#define IDE_PHYS 0x100b0000
#define K_GPIO_GB_IDE 4
#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE)
#endif
#ifdef SIBYTE_HAVE_PCMCIA
#define PCMCIA_CS 6
#define PCMCIA_PHYS 0x11000000
#define K_GPIO_PC_READY 9
#define K_INT_PC_READY (K_INT_GPIO_0 + K_GPIO_PC_READY)
#endif
#endif /* __ASM_SIBYTE_SWARM_H */