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2024-09-09 08:52:07 +00:00
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54
kernel/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003, 07 Ralf Baechle
*/
#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
/*
* IP27 only comes with R10000 family processors all using the same config
*/
#define cpu_has_watch 1
#define cpu_has_mips16 0
#define cpu_has_divec 0
#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 0
#define cpu_has_cache_cdex_s 0
#define cpu_has_prefetch 1
#define cpu_has_mcheck 0
#define cpu_has_ejtag 0
#define cpu_has_llsc 1
#define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_dsp 0
#define cpu_icache_snoops_remote_store 1
#define cpu_has_mipsmt 0
#define cpu_has_userlocal 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1
#define cpu_has_4kex 1
#define cpu_has_3k_cache 0
#define cpu_has_6k_cache 0
#define cpu_has_4k_cache 1
#define cpu_has_8k_cache 0
#define cpu_has_tx39_cache 0
#define cpu_has_inclusive_pcaches 1
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 64
#define cpu_scache_line_size() 128
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */

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kernel/arch/mips/include/asm/mach-ip27/dma-coherence.h Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
*
*/
#ifndef __ASM_MACH_IP27_DMA_COHERENCE_H
#define __ASM_MACH_IP27_DMA_COHERENCE_H
#include <asm/pci/bridge.h>
#define pdev_to_baddr(pdev, addr) \
(BRIDGE_CONTROLLER(pdev->bus)->baddr + (addr))
#define dev_to_baddr(dev, addr) \
pdev_to_baddr(to_pci_dev(dev), (addr))
struct device;
static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
size_t size)
{
dma_addr_t pa = dev_to_baddr(dev, virt_to_phys(addr));
return pa;
}
static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
struct page *page)
{
dma_addr_t pa = dev_to_baddr(dev, page_to_phys(page));
return pa;
}
static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
dma_addr_t dma_addr)
{
return dma_addr & ~(0xffUL << 56);
}
static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction)
{
}
static inline int plat_dma_supported(struct device *dev, u64 mask)
{
/*
* we fall back to GFP_DMA when the mask isn't all 1s,
* so we can't guarantee allocations that must be
* within a tighter range than GFP_DMA..
*/
if (mask < DMA_BIT_MASK(24))
return 0;
return 1;
}
static inline void plat_extra_sync_for_device(struct device *dev)
{
}
static inline int plat_dma_mapping_error(struct device *dev,
dma_addr_t dma_addr)
{
return 0;
}
static inline int plat_device_is_coherent(struct device *dev)
{
return 1; /* IP27 non-cohernet mode is unsupported */
}
#endif /* __ASM_MACH_IP27_DMA_COHERENCE_H */

22
kernel/arch/mips/include/asm/mach-ip27/irq.h Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999, 2000, 01, 02, 03 by Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
* Copyright (C) 2001 Kanoj Sarcar
*/
#ifndef __ASM_MACH_IP27_IRQ_H
#define __ASM_MACH_IP27_IRQ_H
/*
* A hardwired interrupt number is completly stupid for this system - a
* large configuration might have thousands if not tenthousands of
* interrupts.
*/
#define NR_IRQS 256
#include_next <irq.h>
#endif /* __ASM_MACH_IP27_IRQ_H */

59
kernel/arch/mips/include/asm/mach-ip27/kernel-entry-init.h Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000 Silicon Graphics, Inc.
* Copyright (C) 2005 Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MACH_IP27_KERNEL_ENTRY_H
#define __ASM_MACH_IP27_KERNEL_ENTRY_H
#include <asm/sn/addrs.h>
#include <asm/sn/sn0/hubni.h>
#include <asm/sn/klkernvars.h>
/*
* Returns the local nasid into res.
*/
.macro GET_NASID_ASM res
dli \res, LOCAL_HUB_ADDR(NI_STATUS_REV_ID)
ld \res, (\res)
and \res, NSRI_NODEID_MASK
dsrl \res, NSRI_NODEID_SHFT
.endm
/*
* Intentionally empty macro, used in head.S. Override in
* arch/mips/mach-xxx/kernel-entry-init.h when necessary.
*/
.macro kernel_entry_setup
GET_NASID_ASM t1
move t2, t1 # text and data are here
MAPPED_KERNEL_SETUP_TLB
.endm
/*
* Do SMP slave processor setup necessary before we can savely execute C code.
*/
.macro smp_slave_setup
GET_NASID_ASM t1
dli t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + \
KLDIR_OFF_POINTER + CAC_BASE
dsll t1, NASID_SHFT
or t0, t0, t1
ld t0, 0(t0) # t0 points to kern_vars struct
lh t1, KV_RO_NASID_OFFSET(t0)
lh t2, KV_RW_NASID_OFFSET(t0)
MAPPED_KERNEL_SETUP_TLB
/*
* We might not get launched at the address the kernel is linked to,
* so we jump there.
*/
PTR_LA t0, 0f
jr t0
0:
.endm
#endif /* __ASM_MACH_IP27_KERNEL_ENTRY_H */

8
kernel/arch/mips/include/asm/mach-ip27/kmalloc.h Normal file
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#ifndef __ASM_MACH_IP27_KMALLOC_H
#define __ASM_MACH_IP27_KMALLOC_H
/*
* All happy, no need to define ARCH_DMA_MINALIGN
*/
#endif /* __ASM_MACH_IP27_KMALLOC_H */

25
kernel/arch/mips/include/asm/mach-ip27/mangle-port.h Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003, 2004 Ralf Baechle
*/
#ifndef __ASM_MACH_IP27_MANGLE_PORT_H
#define __ASM_MACH_IP27_MANGLE_PORT_H
#define __swizzle_addr_b(port) (port)
#define __swizzle_addr_w(port) ((port) ^ 2)
#define __swizzle_addr_l(port) (port)
#define __swizzle_addr_q(port) (port)
# define ioswabb(a, x) (x)
# define __mem_ioswabb(a, x) (x)
# define ioswabw(a, x) (x)
# define __mem_ioswabw(a, x) cpu_to_le16(x)
# define ioswabl(a, x) (x)
# define __mem_ioswabl(a, x) cpu_to_le32(x)
# define ioswabq(a, x) (x)
# define __mem_ioswabq(a, x) cpu_to_le32(x)
#endif /* __ASM_MACH_IP27_MANGLE_PORT_H */

36
kernel/arch/mips/include/asm/mach-ip27/mmzone.h Normal file
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#ifndef _ASM_MACH_MMZONE_H
#define _ASM_MACH_MMZONE_H
#include <asm/sn/addrs.h>
#include <asm/sn/arch.h>
#include <asm/sn/hub.h>
#define pa_to_nid(addr) NASID_TO_COMPACT_NODEID(NASID_GET(addr))
#define LEVELS_PER_SLICE 128
struct slice_data {
unsigned long irq_enable_mask[2];
int level_to_irq[LEVELS_PER_SLICE];
};
struct hub_data {
kern_vars_t kern_vars;
DECLARE_BITMAP(h_bigwin_used, HUB_NUM_BIG_WINDOW);
cpumask_t h_cpus;
unsigned long slice_map;
unsigned long irq_alloc_mask[2];
struct slice_data slice[2];
};
struct node_data {
struct pglist_data pglist;
struct hub_data hub;
};
extern struct node_data *__node_data[];
#define NODE_DATA(n) (&__node_data[(n)]->pglist)
#define hub_data(n) (&__node_data[(n)]->hub)
#endif /* _ASM_MACH_MMZONE_H */

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kernel/arch/mips/include/asm/mach-ip27/spaces.h Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996, 99 Ralf Baechle
* Copyright (C) 2000, 2002 Maciej W. Rozycki
* Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
*/
#ifndef _ASM_MACH_IP27_SPACES_H
#define _ASM_MACH_IP27_SPACES_H
/*
* IP27 uses the R10000's uncached attribute feature. Attribute 3 selects
* uncached memory addressing.
*/
#define HSPEC_BASE 0x9000000000000000
#define IO_BASE 0x9200000000000000
#define MSPEC_BASE 0x9400000000000000
#define UNCAC_BASE 0x9600000000000000
#define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK))
#define TO_HSPEC(x) (HSPEC_BASE | ((x) & TO_PHYS_MASK))
#define HIGHMEM_START (~0UL)
#include <asm/mach-generic/spaces.h>
#endif /* _ASM_MACH_IP27_SPACES_H */

58
kernel/arch/mips/include/asm/mach-ip27/topology.h Normal file
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#ifndef _ASM_MACH_TOPOLOGY_H
#define _ASM_MACH_TOPOLOGY_H 1
#include <asm/sn/hub.h>
#include <asm/sn/types.h>
#include <asm/mmzone.h>
struct cpuinfo_ip27 {
// cpuid_t p_cpuid; /* PROM assigned cpuid */
cnodeid_t p_nodeid; /* my node ID in compact-id-space */
nasid_t p_nasid; /* my node ID in numa-as-id-space */
unsigned char p_slice; /* Physical position on node board */
#if 0
unsigned long loops_per_sec;
unsigned long ipi_count;
unsigned long irq_attempt[NR_IRQS];
unsigned long smp_local_irq_count;
unsigned long prof_multiplier;
unsigned long prof_counter;
#endif
};
extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS];
#define cpu_to_node(cpu) (sn_cpu_info[(cpu)].p_nodeid)
#define parent_node(node) (node)
#define cpumask_of_node(node) ((node) == -1 ? \
cpu_all_mask : \
&hub_data(node)->h_cpus)
struct pci_bus;
extern int pcibus_to_node(struct pci_bus *);
#define cpumask_of_pcibus(bus) (cpu_online_mask)
extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
#define node_distance(from, to) (__node_distances[(from)][(to)])
/* sched_domains SD_NODE_INIT for SGI IP27 machines */
#define SD_NODE_INIT (struct sched_domain) { \
.parent = NULL, \
.child = NULL, \
.groups = NULL, \
.min_interval = 8, \
.max_interval = 32, \
.busy_factor = 32, \
.imbalance_pct = 125, \
.cache_nice_tries = 1, \
.flags = SD_LOAD_BALANCE | \
SD_BALANCE_EXEC, \
.last_balance = jiffies, \
.balance_interval = 1, \
.nr_balance_failed = 0, \
}
#include <asm-generic/topology.h>
#endif /* _ASM_MACH_TOPOLOGY_H */

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kernel/arch/mips/include/asm/mach-ip27/war.h Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
*/
#ifndef __ASM_MIPS_MACH_IP27_WAR_H
#define __ASM_MIPS_MACH_IP27_WAR_H
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define R5432_CP0_INTERRUPT_WAR 0
#define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define RM9000_CDEX_SMP_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0
#define R10000_LLSC_WAR 1
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP27_WAR_H */