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kernel/arch/blackfin/mach-bf561/include/mach/anomaly.h Normal file
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/*
* DO NOT EDIT THIS FILE
* This file is under version control at
* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
* Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
* - Revision S, 05/23/2011; ADSP-BF561 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
#endif
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
/* TESTSET Instructions Restricted to 32-Bit Aligned Memory Locations */
#define ANOMALY_05000120 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* SIGNBITS Instruction Not Functional under Certain Conditions */
#define ANOMALY_05000127 (1)
/* IMDMA S1/D1 Channel May Stall */
#define ANOMALY_05000149 (1)
/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
#define ANOMALY_05000166 (1)
/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
#define ANOMALY_05000167 (1)
/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
/* Boot-ROM Modifies SICA_IWRx Wakeup Registers */
#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
/* Cache Fill Buffer Data lost */
#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
/* Overlapping Sequencer and Memory Stalls */
#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
#define ANOMALY_05000180 (1)
/* Disabling the PPI Resets the PPI Configuration Registers */
#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
/* Internal Memory DMA Does Not Operate at Full Speed */
#define ANOMALY_05000182 (1)
/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
/* Upper PPI Pins Driven when PPI Packing Enabled and Data Length >8 Bits */
#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
/* IMDMA Corrupted Data after a Halt */
#define ANOMALY_05000187 (1)
/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
/* False Protection Exceptions when Speculative Fetch Is Cancelled */
#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
/* PPI Not Functional at Core Voltage < 1Volt */
#define ANOMALY_05000190 (1)
/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
/* Restarting SPORT in Specific Modes May Cause Data Corruption */
#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
/* Failing MMR Accesses when Preceding Memory Read Stalls */
#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
/* Current DMA Address Shows Wrong Value During Carry Fix */
#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
/* Possible Infinite Stall with Specific Dual-DAG Situation */
#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
/* Specific Sequence that Can Cause DMA Error or DMA Stopping */
#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
/* Recovery from "Brown-Out" Condition */
#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
#define ANOMALY_05000208 (1)
/* Speed Path in Computational Unit Affects Certain Instructions */
#define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
/* UART TX Interrupt Masked Erroneously */
#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
/* NMI Event at Boot Time Results in Unpredictable State */
#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
/* Incorrect Pulse-Width of UART Start Bit */
#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
/* Scratchpad Memory Bank Reads May Return Incorrect Data */
#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
/* UART STB Bit Incorrectly Affects Receiver Setting */
#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
/* SPORT Data Transmit Lines Are Incorrectly Driven in Multichannel Mode */
#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
/* TESTSET Operation Forces Stall on the Other Core */
#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
/* Exception Not Generated for MMR Accesses in Reserved Region */
#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
/* Maximum External Clock Speed for Timers */
#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
/* Tempoary work around for kgdb bug 6333 in SMP kernel. It looks coreb hangs in exception
* without handling anomaly 05000257 properly on bf561 v0.5. This work around may change
* after the behavior and the root cause are confirmed with hardware team.
*/
#define ANOMALY_05000257 (__SILICON_REVISION__ < 5 || (__SILICON_REVISION__ == 5 && CONFIG_SMP))
/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
/* ICPLB_STATUS MMR Register May Be Corrupted */
#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
/* Stores To Data Cache May Be Lost */
#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
/* Hardware Loop Corrupted When Taking an ICPLB Exception */
#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
/* IMDMA Destination IRQ Status Must Be Read Prior to Using IMDMA */
#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
/* IMDMA May Corrupt Data under Certain Conditions */
#define ANOMALY_05000267 (1)
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
#define ANOMALY_05000269 (1)
/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
#define ANOMALY_05000270 (1)
/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
#define ANOMALY_05000272 (1)
/* Data Cache Write Back to External Synchronous Memory May Be Lost */
#define ANOMALY_05000274 (1)
/* PPI Timing and Sampling Information Updates */
#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
#define ANOMALY_05000277 (__SILICON_REVISION__ < 5)
/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
/* False Hardware Error when ISR Context Is Not Restored */
/* Temporarily walk around for bug 5423 till this issue is confirmed by
* official anomaly document. It looks 05000281 still exists on bf561
* v0.5.
*/
#define ANOMALY_05000281 (__SILICON_REVISION__ <= 5)
/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
#define ANOMALY_05000283 (1)
/* Reads Will Receive Incorrect Data under Certain Conditions */
#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
/* SPORTs May Receive Bad Data If FIFOs Fill Up */
#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
#define ANOMALY_05000301 (1)
/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
#define ANOMALY_05000302 (1)
/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
/* SCKELOW Bit Does Not Maintain State Through Hibernate */
#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
#define ANOMALY_05000312 (1)
/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
#define ANOMALY_05000313 (1)
/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
#define ANOMALY_05000315 (1)
/* PF2 Output Remains Asserted after SPI Master Boot */
#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
/* Erroneous GPIO Flag Pin Operations under Specific Sequences */
#define ANOMALY_05000323 (1)
/* SPORT Secondary Receive Channel Not Functional when Word Length >16 Bits */
#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
/* 24-Bit SPI Boot Mode Is Not Functional */
#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
/* Slave SPI Boot Mode Is Not Functional */
#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
/* Flag Data Register Writes One SCLK Cycle after Edge Is Detected May Clear Interrupt Status */
#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
/* ALT_TIMING Bit in PLL_CTL Register Is Not Functional */
#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
#define ANOMALY_05000357 (1)
/* Conflicting Column Address Widths Causes SDRAM Errors */
#define ANOMALY_05000362 (1)
/* UART Break Signal Issues */
#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
#define ANOMALY_05000371 (1)
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
#define ANOMALY_05000403 (1)
/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
#define ANOMALY_05000412 (1)
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000416 (1)
/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
#define ANOMALY_05000425 (1)
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_05000426 (1)
/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */
#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* SCKELOW Feature Is Not Functional */
#define ANOMALY_05000458 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
#define ANOMALY_05000462 (1)
/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
#define ANOMALY_05000471 (1)
/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
#define ANOMALY_05000473 (1)
/* Possible Lockup Condition when Modifying PLL from External Memory */
#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* PLL May Latch Incorrect Values Coming Out of Reset */
#define ANOMALY_05000489 (1)
/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
#define ANOMALY_05000491 (1)
/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
#define ANOMALY_05000494 (1)
/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
#define ANOMALY_05000501 (1)
/*
* These anomalies have been "phased" out of analog.com anomaly sheets and are
* here to show running on older silicon just isn't feasible.
*/
/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
/* Erroneous Exception when Enabling Cache */
#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
/* Stall in multi-unit DMA operations */
#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
/* Allowing the SPORT RX FIFO to fill will cause an overflow */
#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
/* DMA and TESTSET conflict when both are accessing external memory */
#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
/* MDMA may lose the first few words of a descriptor chain */
#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
/* DMA engine may lose data due to incorrect handshaking */
#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
/* DMA stalls when all three controllers read data from the same source */
#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
/* Execution stall when executing in L2 and doing external accesses */
#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
/* Frame Delay in SPORT Multichannel Mode */
#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
/* A read from external memory may return a wrong value with data cache enabled */
#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
/* DMEM_CONTROL<12> is not set on Reset */
#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
/* DSPID register values incorrect */
#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
/* DMA vs Core accesses to external memory */
#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000119 (0)
#define ANOMALY_05000158 (0)
#define ANOMALY_05000183 (0)
#define ANOMALY_05000233 (0)
#define ANOMALY_05000234 (0)
#define ANOMALY_05000273 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000353 (1)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
#define ANOMALY_05000440 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0)
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
#define ANOMALY_05000480 (0)
#define ANOMALY_05000485 (0)
#endif

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/*
* SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
*
* Copyright 2005-2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __MACH_BF561_H__
#define __MACH_BF561_H__
#define OFFSET_(x) ((x) & 0x0000FFFF)
/*some misc defines*/
#define IMASK_IVG15 0x8000
#define IMASK_IVG14 0x4000
#define IMASK_IVG13 0x2000
#define IMASK_IVG12 0x1000
#define IMASK_IVG11 0x0800
#define IMASK_IVG10 0x0400
#define IMASK_IVG9 0x0200
#define IMASK_IVG8 0x0100
#define IMASK_IVG7 0x0080
#define IMASK_IVGTMR 0x0040
#define IMASK_IVGHW 0x0020
/***************************
* Blackfin Cache setup
*/
#define BFIN_ISUBBANKS 4
#define BFIN_IWAYS 4
#define BFIN_ILINES 32
#define BFIN_DSUBBANKS 4
#define BFIN_DWAYS 2
#define BFIN_DLINES 64
#define WAY0_L 0x1
#define WAY1_L 0x2
#define WAY01_L 0x3
#define WAY2_L 0x4
#define WAY02_L 0x5
#define WAY12_L 0x6
#define WAY012_L 0x7
#define WAY3_L 0x8
#define WAY03_L 0x9
#define WAY13_L 0xA
#define WAY013_L 0xB
#define WAY32_L 0xC
#define WAY320_L 0xD
#define WAY321_L 0xE
#define WAYALL_L 0xF
#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
/* IAR0 BIT FIELDS */
#define PLL_WAKEUP_BIT 0xFFFFFFFF
#define DMA1_ERROR_BIT 0xFFFFFF0F
#define DMA2_ERROR_BIT 0xFFFFF0FF
#define IMDMA_ERROR_BIT 0xFFFF0FFF
#define PPI1_ERROR_BIT 0xFFF0FFFF
#define PPI2_ERROR_BIT 0xFF0FFFFF
#define SPORT0_ERROR_BIT 0xF0FFFFFF
#define SPORT1_ERROR_BIT 0x0FFFFFFF
/* IAR1 BIT FIELDS */
#define SPI_ERROR_BIT 0xFFFFFFFF
#define UART_ERROR_BIT 0xFFFFFF0F
#define RESERVED_ERROR_BIT 0xFFFFF0FF
#define DMA1_0_BIT 0xFFFF0FFF
#define DMA1_1_BIT 0xFFF0FFFF
#define DMA1_2_BIT 0xFF0FFFFF
#define DMA1_3_BIT 0xF0FFFFFF
#define DMA1_4_BIT 0x0FFFFFFF
/* IAR2 BIT FIELDS */
#define DMA1_5_BIT 0xFFFFFFFF
#define DMA1_6_BIT 0xFFFFFF0F
#define DMA1_7_BIT 0xFFFFF0FF
#define DMA1_8_BIT 0xFFFF0FFF
#define DMA1_9_BIT 0xFFF0FFFF
#define DMA1_10_BIT 0xFF0FFFFF
#define DMA1_11_BIT 0xF0FFFFFF
#define DMA2_0_BIT 0x0FFFFFFF
/* IAR3 BIT FIELDS */
#define DMA2_1_BIT 0xFFFFFFFF
#define DMA2_2_BIT 0xFFFFFF0F
#define DMA2_3_BIT 0xFFFFF0FF
#define DMA2_4_BIT 0xFFFF0FFF
#define DMA2_5_BIT 0xFFF0FFFF
#define DMA2_6_BIT 0xFF0FFFFF
#define DMA2_7_BIT 0xF0FFFFFF
#define DMA2_8_BIT 0x0FFFFFFF
/* IAR4 BIT FIELDS */
#define DMA2_9_BIT 0xFFFFFFFF
#define DMA2_10_BIT 0xFFFFFF0F
#define DMA2_11_BIT 0xFFFFF0FF
#define TIMER0_BIT 0xFFFF0FFF
#define TIMER1_BIT 0xFFF0FFFF
#define TIMER2_BIT 0xFF0FFFFF
#define TIMER3_BIT 0xF0FFFFFF
#define TIMER4_BIT 0x0FFFFFFF
/* IAR5 BIT FIELDS */
#define TIMER5_BIT 0xFFFFFFFF
#define TIMER6_BIT 0xFFFFFF0F
#define TIMER7_BIT 0xFFFFF0FF
#define TIMER8_BIT 0xFFFF0FFF
#define TIMER9_BIT 0xFFF0FFFF
#define TIMER10_BIT 0xFF0FFFFF
#define TIMER11_BIT 0xF0FFFFFF
#define PROG0_INTA_BIT 0x0FFFFFFF
/* IAR6 BIT FIELDS */
#define PROG0_INTB_BIT 0xFFFFFFFF
#define PROG1_INTA_BIT 0xFFFFFF0F
#define PROG1_INTB_BIT 0xFFFFF0FF
#define PROG2_INTA_BIT 0xFFFF0FFF
#define PROG2_INTB_BIT 0xFFF0FFFF
#define DMA1_WRRD0_BIT 0xFF0FFFFF
#define DMA1_WRRD1_BIT 0xF0FFFFFF
#define DMA2_WRRD0_BIT 0x0FFFFFFF
/* IAR7 BIT FIELDS */
#define DMA2_WRRD1_BIT 0xFFFFFFFF
#define IMDMA_WRRD0_BIT 0xFFFFFF0F
#define IMDMA_WRRD1_BIT 0xFFFFF0FF
#define WATCH_BIT 0xFFFF0FFF
#define RESERVED_1_BIT 0xFFF0FFFF
#define RESERVED_2_BIT 0xFF0FFFFF
#define SUPPLE_0_BIT 0xF0FFFFFF
#define SUPPLE_1_BIT 0x0FFFFFFF
/* Miscellaneous Values */
/****************************** EBIU Settings ********************************/
#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
#if defined(CONFIG_C_AMBEN_ALL)
#define V_AMBEN AMBEN_ALL
#elif defined(CONFIG_C_AMBEN)
#define V_AMBEN 0x0
#elif defined(CONFIG_C_AMBEN_B0)
#define V_AMBEN AMBEN_B0
#elif defined(CONFIG_C_AMBEN_B0_B1)
#define V_AMBEN AMBEN_B0_B1
#elif defined(CONFIG_C_AMBEN_B0_B1_B2)
#define V_AMBEN AMBEN_B0_B1_B2
#endif
#ifdef CONFIG_C_AMCKEN
#define V_AMCKEN AMCKEN
#else
#define V_AMCKEN 0x0
#endif
#ifdef CONFIG_C_B0PEN
#define V_B0PEN 0x10
#else
#define V_B0PEN 0x00
#endif
#ifdef CONFIG_C_B1PEN
#define V_B1PEN 0x20
#else
#define V_B1PEN 0x00
#endif
#ifdef CONFIG_C_B2PEN
#define V_B2PEN 0x40
#else
#define V_B2PEN 0x00
#endif
#ifdef CONFIG_C_B3PEN
#define V_B3PEN 0x80
#else
#define V_B3PEN 0x00
#endif
#ifdef CONFIG_C_CDPRIO
#define V_CDPRIO 0x100
#else
#define V_CDPRIO 0x0
#endif
#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002)
#ifdef CONFIG_BF561
#define CPU "BF561"
#define CPUID 0x27bb
#endif
#ifndef CPU
#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
#endif
#endif /* __MACH_BF561_H__ */

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/*
* mach/bfin_serial.h - Blackfin UART/Serial definitions
*
* Copyright 2006-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __BFIN_MACH_SERIAL_H__
#define __BFIN_MACH_SERIAL_H__
#define BFIN_UART_NR_PORTS 1
#endif

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/*
* Copyright 2005-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_BLACKFIN_H_
#define _MACH_BLACKFIN_H_
#define BF561_FAMILY
#include "bf561.h"
#include "anomaly.h"
#include <asm/def_LPBlackfin.h>
#include "defBF561.h"
#ifndef __ASSEMBLY__
# include <asm/cdef_LPBlackfin.h>
# include "cdefBF561.h"
#endif
#define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D()
#define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val)
#define bfin_read_FIO_DIR() bfin_read_FIO0_DIR()
#define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val)
#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
/* Weird muxer funcs which pick SIC regs from IMASK base */
#define __SIC_MUX(base, x) ((base) + ((x) << 2))
#define bfin_read_SIC_IMASK(x) bfin_read32(__SIC_MUX(SIC_IMASK0, x))
#define bfin_write_SIC_IMASK(x, val) bfin_write32(__SIC_MUX(SIC_IMASK0, x), val)
#define bfin_read_SICB_IMASK(x) bfin_read32(__SIC_MUX(SICB_IMASK0, x))
#define bfin_write_SICB_IMASK(x, val) bfin_write32(__SIC_MUX(SICB_IMASK0, x), val)
#define bfin_read_SIC_ISR(x) bfin_read32(__SIC_MUX(SIC_ISR0, x))
#define bfin_write_SIC_ISR(x, val) bfin_write32(__SIC_MUX(SIC_ISR0, x), val)
#define bfin_read_SICB_ISR(x) bfin_read32(__SIC_MUX(SICB_ISR0, x))
#define bfin_write_SICB_ISR(x, val) bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
#endif /* _MACH_BLACKFIN_H_ */

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/* mach/dma.h - arch-specific DMA defines
*
* Copyright 2004-2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_DMA_H_
#define _MACH_DMA_H_
#define MAX_DMA_CHANNELS 36
/* [#4267] IMDMA channels have no PERIPHERAL_MAP MMR */
#define MAX_DMA_SUSPEND_CHANNELS 32
#define CH_PPI0 0
#define CH_PPI (CH_PPI0)
#define CH_PPI1 1
#define CH_SPORT0_RX 12
#define CH_SPORT0_TX 13
#define CH_SPORT1_RX 14
#define CH_SPORT1_TX 15
#define CH_SPI 16
#define CH_UART_RX 17
#define CH_UART_TX 18
#define CH_MEM_STREAM0_DEST 24 /* TX */
#define CH_MEM_STREAM0_SRC 25 /* RX */
#define CH_MEM_STREAM1_DEST 26 /* TX */
#define CH_MEM_STREAM1_SRC 27 /* RX */
#define CH_MEM_STREAM2_DEST 28
#define CH_MEM_STREAM2_SRC 29
#define CH_MEM_STREAM3_DEST 30
#define CH_MEM_STREAM3_SRC 31
#define CH_IMEM_STREAM0_DEST 32
#define CH_IMEM_STREAM0_SRC 33
#define CH_IMEM_STREAM1_DEST 34
#define CH_IMEM_STREAM1_SRC 35
#endif

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/*
* Copyright (C) 2008 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_GPIO_H_
#define _MACH_GPIO_H_
#define MAX_BLACKFIN_GPIOS 48
#define GPIO_PF0 0
#define GPIO_PF1 1
#define GPIO_PF2 2
#define GPIO_PF3 3
#define GPIO_PF4 4
#define GPIO_PF5 5
#define GPIO_PF6 6
#define GPIO_PF7 7
#define GPIO_PF8 8
#define GPIO_PF9 9
#define GPIO_PF10 10
#define GPIO_PF11 11
#define GPIO_PF12 12
#define GPIO_PF13 13
#define GPIO_PF14 14
#define GPIO_PF15 15
#define GPIO_PF16 16
#define GPIO_PF17 17
#define GPIO_PF18 18
#define GPIO_PF19 19
#define GPIO_PF20 20
#define GPIO_PF21 21
#define GPIO_PF22 22
#define GPIO_PF23 23
#define GPIO_PF24 24
#define GPIO_PF25 25
#define GPIO_PF26 26
#define GPIO_PF27 27
#define GPIO_PF28 28
#define GPIO_PF29 29
#define GPIO_PF30 30
#define GPIO_PF31 31
#define GPIO_PF32 32
#define GPIO_PF33 33
#define GPIO_PF34 34
#define GPIO_PF35 35
#define GPIO_PF36 36
#define GPIO_PF37 37
#define GPIO_PF38 38
#define GPIO_PF39 39
#define GPIO_PF40 40
#define GPIO_PF41 41
#define GPIO_PF42 42
#define GPIO_PF43 43
#define GPIO_PF44 44
#define GPIO_PF45 45
#define GPIO_PF46 46
#define GPIO_PF47 47
#define PORT_FIO0 GPIO_PF0
#define PORT_FIO1 GPIO_PF16
#define PORT_FIO2 GPIO_PF32
#include <mach-common/ports-f.h>
#endif /* _MACH_GPIO_H_ */

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/*
* Copyright 2005-2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef _BF561_IRQ_H_
#define _BF561_IRQ_H_
#include <mach-common/irq.h>
#define NR_PERI_INTS (2 * 32)
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
#define IRQ_DMA1_ERROR BFIN_IRQ(1) /* DMA1 Error (general) */
#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
#define IRQ_DMA2_ERROR BFIN_IRQ(2) /* DMA2 Error (general) */
#define IRQ_IMDMA_ERROR BFIN_IRQ(3) /* IMDMA Error Interrupt */
#define IRQ_PPI1_ERROR BFIN_IRQ(4) /* PPI1 Error Interrupt */
#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
#define IRQ_PPI2_ERROR BFIN_IRQ(5) /* PPI2 Error Interrupt */
#define IRQ_SPORT0_ERROR BFIN_IRQ(6) /* SPORT0 Error Interrupt */
#define IRQ_SPORT1_ERROR BFIN_IRQ(7) /* SPORT1 Error Interrupt */
#define IRQ_SPI_ERROR BFIN_IRQ(8) /* SPI Error Interrupt */
#define IRQ_UART_ERROR BFIN_IRQ(9) /* UART Error Interrupt */
#define IRQ_RESERVED_ERROR BFIN_IRQ(10) /* Reversed */
#define IRQ_DMA1_0 BFIN_IRQ(11) /* DMA1 0 Interrupt(PPI1) */
#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
#define IRQ_DMA1_1 BFIN_IRQ(12) /* DMA1 1 Interrupt(PPI2) */
#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
#define IRQ_DMA1_2 BFIN_IRQ(13) /* DMA1 2 Interrupt */
#define IRQ_DMA1_3 BFIN_IRQ(14) /* DMA1 3 Interrupt */
#define IRQ_DMA1_4 BFIN_IRQ(15) /* DMA1 4 Interrupt */
#define IRQ_DMA1_5 BFIN_IRQ(16) /* DMA1 5 Interrupt */
#define IRQ_DMA1_6 BFIN_IRQ(17) /* DMA1 6 Interrupt */
#define IRQ_DMA1_7 BFIN_IRQ(18) /* DMA1 7 Interrupt */
#define IRQ_DMA1_8 BFIN_IRQ(19) /* DMA1 8 Interrupt */
#define IRQ_DMA1_9 BFIN_IRQ(20) /* DMA1 9 Interrupt */
#define IRQ_DMA1_10 BFIN_IRQ(21) /* DMA1 10 Interrupt */
#define IRQ_DMA1_11 BFIN_IRQ(22) /* DMA1 11 Interrupt */
#define IRQ_DMA2_0 BFIN_IRQ(23) /* DMA2 0 (SPORT0 RX) */
#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
#define IRQ_DMA2_1 BFIN_IRQ(24) /* DMA2 1 (SPORT0 TX) */
#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
#define IRQ_DMA2_2 BFIN_IRQ(25) /* DMA2 2 (SPORT1 RX) */
#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
#define IRQ_DMA2_3 BFIN_IRQ(26) /* DMA2 3 (SPORT2 TX) */
#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
#define IRQ_DMA2_4 BFIN_IRQ(27) /* DMA2 4 (SPI) */
#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
#define IRQ_DMA2_5 BFIN_IRQ(28) /* DMA2 5 (UART RX) */
#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
#define IRQ_DMA2_6 BFIN_IRQ(29) /* DMA2 6 (UART TX) */
#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
#define IRQ_DMA2_7 BFIN_IRQ(30) /* DMA2 7 Interrupt */
#define IRQ_DMA2_8 BFIN_IRQ(31) /* DMA2 8 Interrupt */
#define IRQ_DMA2_9 BFIN_IRQ(32) /* DMA2 9 Interrupt */
#define IRQ_DMA2_10 BFIN_IRQ(33) /* DMA2 10 Interrupt */
#define IRQ_DMA2_11 BFIN_IRQ(34) /* DMA2 11 Interrupt */
#define IRQ_TIMER0 BFIN_IRQ(35) /* TIMER 0 Interrupt */
#define IRQ_TIMER1 BFIN_IRQ(36) /* TIMER 1 Interrupt */
#define IRQ_TIMER2 BFIN_IRQ(37) /* TIMER 2 Interrupt */
#define IRQ_TIMER3 BFIN_IRQ(38) /* TIMER 3 Interrupt */
#define IRQ_TIMER4 BFIN_IRQ(39) /* TIMER 4 Interrupt */
#define IRQ_TIMER5 BFIN_IRQ(40) /* TIMER 5 Interrupt */
#define IRQ_TIMER6 BFIN_IRQ(41) /* TIMER 6 Interrupt */
#define IRQ_TIMER7 BFIN_IRQ(42) /* TIMER 7 Interrupt */
#define IRQ_TIMER8 BFIN_IRQ(43) /* TIMER 8 Interrupt */
#define IRQ_TIMER9 BFIN_IRQ(44) /* TIMER 9 Interrupt */
#define IRQ_TIMER10 BFIN_IRQ(45) /* TIMER 10 Interrupt */
#define IRQ_TIMER11 BFIN_IRQ(46) /* TIMER 11 Interrupt */
#define IRQ_PROG0_INTA BFIN_IRQ(47) /* Programmable Flags0 A (8) */
#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
#define IRQ_PROG0_INTB BFIN_IRQ(48) /* Programmable Flags0 B (8) */
#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
#define IRQ_PROG1_INTA BFIN_IRQ(49) /* Programmable Flags1 A (8) */
#define IRQ_PROG1_INTB BFIN_IRQ(50) /* Programmable Flags1 B (8) */
#define IRQ_PROG2_INTA BFIN_IRQ(51) /* Programmable Flags2 A (8) */
#define IRQ_PROG2_INTB BFIN_IRQ(52) /* Programmable Flags2 B (8) */
#define IRQ_DMA1_WRRD0 BFIN_IRQ(53) /* MDMA1 0 write/read INT */
#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0
#define IRQ_DMA1_WRRD1 BFIN_IRQ(54) /* MDMA1 1 write/read INT */
#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */
#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1
#define IRQ_DMA2_WRRD0 BFIN_IRQ(55) /* MDMA2 0 write/read INT */
#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0
#define IRQ_DMA2_WRRD1 BFIN_IRQ(56) /* MDMA2 1 write/read INT */
#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1
#define IRQ_IMDMA_WRRD0 BFIN_IRQ(57) /* IMDMA 0 write/read INT */
#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0
#define IRQ_IMDMA_WRRD1 BFIN_IRQ(58) /* IMDMA 1 write/read INT */
#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1
#define IRQ_WATCH BFIN_IRQ(59) /* Watch Dog Timer */
#define IRQ_RESERVED_1 BFIN_IRQ(60) /* Reserved interrupt */
#define IRQ_RESERVED_2 BFIN_IRQ(61) /* Reserved interrupt */
#define IRQ_SUPPLE_0 BFIN_IRQ(62) /* Supplemental interrupt 0 */
#define IRQ_SUPPLE_1 BFIN_IRQ(63) /* supplemental interrupt 1 */
#define SYS_IRQS 71
#define IRQ_PF0 73
#define IRQ_PF1 74
#define IRQ_PF2 75
#define IRQ_PF3 76
#define IRQ_PF4 77
#define IRQ_PF5 78
#define IRQ_PF6 79
#define IRQ_PF7 80
#define IRQ_PF8 81
#define IRQ_PF9 82
#define IRQ_PF10 83
#define IRQ_PF11 84
#define IRQ_PF12 85
#define IRQ_PF13 86
#define IRQ_PF14 87
#define IRQ_PF15 88
#define IRQ_PF16 89
#define IRQ_PF17 90
#define IRQ_PF18 91
#define IRQ_PF19 92
#define IRQ_PF20 93
#define IRQ_PF21 94
#define IRQ_PF22 95
#define IRQ_PF23 96
#define IRQ_PF24 97
#define IRQ_PF25 98
#define IRQ_PF26 99
#define IRQ_PF27 100
#define IRQ_PF28 101
#define IRQ_PF29 102
#define IRQ_PF30 103
#define IRQ_PF31 104
#define IRQ_PF32 105
#define IRQ_PF33 106
#define IRQ_PF34 107
#define IRQ_PF35 108
#define IRQ_PF36 109
#define IRQ_PF37 110
#define IRQ_PF38 111
#define IRQ_PF39 112
#define IRQ_PF40 113
#define IRQ_PF41 114
#define IRQ_PF42 115
#define IRQ_PF43 116
#define IRQ_PF44 117
#define IRQ_PF45 118
#define IRQ_PF46 119
#define IRQ_PF47 120
#define GPIO_IRQ_BASE IRQ_PF0
#define NR_MACH_IRQS (IRQ_PF47 + 1)
/* IAR0 BIT FIELDS */
#define IRQ_PLL_WAKEUP_POS 0
#define IRQ_DMA1_ERROR_POS 4
#define IRQ_DMA2_ERROR_POS 8
#define IRQ_IMDMA_ERROR_POS 12
#define IRQ_PPI0_ERROR_POS 16
#define IRQ_PPI1_ERROR_POS 20
#define IRQ_SPORT0_ERROR_POS 24
#define IRQ_SPORT1_ERROR_POS 28
/* IAR1 BIT FIELDS */
#define IRQ_SPI_ERROR_POS 0
#define IRQ_UART_ERROR_POS 4
#define IRQ_RESERVED_ERROR_POS 8
#define IRQ_DMA1_0_POS 12
#define IRQ_DMA1_1_POS 16
#define IRQ_DMA1_2_POS 20
#define IRQ_DMA1_3_POS 24
#define IRQ_DMA1_4_POS 28
/* IAR2 BIT FIELDS */
#define IRQ_DMA1_5_POS 0
#define IRQ_DMA1_6_POS 4
#define IRQ_DMA1_7_POS 8
#define IRQ_DMA1_8_POS 12
#define IRQ_DMA1_9_POS 16
#define IRQ_DMA1_10_POS 20
#define IRQ_DMA1_11_POS 24
#define IRQ_DMA2_0_POS 28
/* IAR3 BIT FIELDS */
#define IRQ_DMA2_1_POS 0
#define IRQ_DMA2_2_POS 4
#define IRQ_DMA2_3_POS 8
#define IRQ_DMA2_4_POS 12
#define IRQ_DMA2_5_POS 16
#define IRQ_DMA2_6_POS 20
#define IRQ_DMA2_7_POS 24
#define IRQ_DMA2_8_POS 28
/* IAR4 BIT FIELDS */
#define IRQ_DMA2_9_POS 0
#define IRQ_DMA2_10_POS 4
#define IRQ_DMA2_11_POS 8
#define IRQ_TIMER0_POS 12
#define IRQ_TIMER1_POS 16
#define IRQ_TIMER2_POS 20
#define IRQ_TIMER3_POS 24
#define IRQ_TIMER4_POS 28
/* IAR5 BIT FIELDS */
#define IRQ_TIMER5_POS 0
#define IRQ_TIMER6_POS 4
#define IRQ_TIMER7_POS 8
#define IRQ_TIMER8_POS 12
#define IRQ_TIMER9_POS 16
#define IRQ_TIMER10_POS 20
#define IRQ_TIMER11_POS 24
#define IRQ_PROG0_INTA_POS 28
/* IAR6 BIT FIELDS */
#define IRQ_PROG0_INTB_POS 0
#define IRQ_PROG1_INTA_POS 4
#define IRQ_PROG1_INTB_POS 8
#define IRQ_PROG2_INTA_POS 12
#define IRQ_PROG2_INTB_POS 16
#define IRQ_DMA1_WRRD0_POS 20
#define IRQ_DMA1_WRRD1_POS 24
#define IRQ_DMA2_WRRD0_POS 28
/* IAR7 BIT FIELDS */
#define IRQ_DMA2_WRRD1_POS 0
#define IRQ_IMDMA_WRRD0_POS 4
#define IRQ_IMDMA_WRRD1_POS 8
#define IRQ_WDTIMER_POS 12
#define IRQ_RESERVED_1_POS 16
#define IRQ_RESERVED_2_POS 20
#define IRQ_SUPPLE_0_POS 24
#define IRQ_SUPPLE_1_POS 28
#endif

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/*
* BF561 memory map
*
* Copyright 2004-2009 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
#ifndef __BFIN_MACH_MEM_MAP_H__
#define __BFIN_MACH_MEM_MAP_H__
#ifndef __BFIN_MEM_MAP_H__
# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
#endif
/* Async Memory Banks */
#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
/* Boot ROM Memory */
#define BOOT_ROM_START 0xEF000000
#define BOOT_ROM_LENGTH 0x800
/* Level 1 Memory */
#ifdef CONFIG_BFIN_ICACHE
#define BFIN_ICACHESIZE (16*1024)
#else
#define BFIN_ICACHESIZE (0*1024)
#endif
/* Memory Map for ADSP-BF561 processors */
#define COREA_L1_CODE_START 0xFFA00000
#define COREA_L1_DATA_A_START 0xFF800000
#define COREA_L1_DATA_B_START 0xFF900000
#define COREB_L1_CODE_START 0xFF600000
#define COREB_L1_DATA_A_START 0xFF400000
#define COREB_L1_DATA_B_START 0xFF500000
#define L1_CODE_START COREA_L1_CODE_START
#define L1_DATA_A_START COREA_L1_DATA_A_START
#define L1_DATA_B_START COREA_L1_DATA_B_START
#define L1_CODE_LENGTH 0x4000
#ifdef CONFIG_BFIN_DCACHE
#ifdef CONFIG_BFIN_DCACHE_BANKA
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH 0x8000
#define BFIN_DCACHESIZE (16*1024)
#define BFIN_DSUPBANKS 1
#else
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
#define BFIN_DCACHESIZE (32*1024)
#define BFIN_DSUPBANKS 2
#endif
#else
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH 0x8000
#define L1_DATA_B_LENGTH 0x8000
#define BFIN_DCACHESIZE (0*1024)
#define BFIN_DSUPBANKS 0
#endif /*CONFIG_BFIN_DCACHE*/
/*
* If we are in SMP mode, then the cache settings of Core B will match
* the settings of Core A. If we aren't, then we assume Core B is not
* using any cache. This allows the rest of the kernel to work with
* the core in either mode as we are only loading user code into it and
* it is the user's problem to make sure they aren't doing something
* stupid there.
*
* Note that we treat the L1 code region as a contiguous blob to make
* the rest of the kernel simpler. Easier to check one region than a
* bunch of small ones. Again, possible misbehavior here is the fault
* of the user -- don't try to use memory that doesn't exist.
*/
#ifdef CONFIG_SMP
# define COREB_L1_CODE_LENGTH L1_CODE_LENGTH
# define COREB_L1_DATA_A_LENGTH L1_DATA_A_LENGTH
# define COREB_L1_DATA_B_LENGTH L1_DATA_B_LENGTH
#else
# define COREB_L1_CODE_LENGTH 0x14000
# define COREB_L1_DATA_A_LENGTH 0x8000
# define COREB_L1_DATA_B_LENGTH 0x8000
#endif
/* Level 2 Memory */
#define L2_START 0xFEB00000
#define L2_LENGTH 0x20000
/* Scratch Pad Memory */
#define COREA_L1_SCRATCH_START 0xFFB00000
#define COREB_L1_SCRATCH_START 0xFF700000
#ifdef CONFIG_SMP
/*
* The following macros both return the address of the PDA for the
* current core.
*
* In its first safe (and hairy) form, the macro neither clobbers any
* register aside of the output Preg, nor uses the stack, since it
* could be called with an invalid stack pointer, or the current stack
* space being uncovered by any CPLB (e.g. early exception handling).
*
* The constraints on the second form are a bit relaxed, and the code
* is allowed to use the specified Dreg for determining the PDA
* address to be returned into Preg.
*/
# define GET_PDA_SAFE(preg) \
preg.l = lo(DSPID); \
preg.h = hi(DSPID); \
preg = [preg]; \
preg = preg << 2; \
preg = preg << 2; \
preg = preg << 2; \
preg = preg << 2; \
preg = preg << 2; \
preg = preg << 2; \
preg = preg << 2; \
preg = preg << 2; \
preg = preg << 2; \
preg = preg << 2; \
preg = preg << 2; \
preg = preg << 2; \
if cc jump 2f; \
cc = preg == 0x0; \
preg.l = _cpu_pda; \
preg.h = _cpu_pda; \
if !cc jump 3f; \
1: \
/* preg = 0x0; */ \
cc = !cc; /* restore cc to 0 */ \
jump 4f; \
2: \
cc = preg == 0x0; \
preg.l = _cpu_pda; \
preg.h = _cpu_pda; \
if cc jump 4f; \
/* preg = 0x1000000; */ \
cc = !cc; /* restore cc to 1 */ \
3: \
preg = [preg]; \
4:
# define GET_PDA(preg, dreg) \
preg.l = lo(DSPID); \
preg.h = hi(DSPID); \
dreg = [preg]; \
preg.l = _cpu_pda; \
preg.h = _cpu_pda; \
cc = bittst(dreg, 0); \
if !cc jump 1f; \
preg = [preg]; \
1: \
# define GET_CPUID(preg, dreg) \
preg.l = lo(DSPID); \
preg.h = hi(DSPID); \
dreg = [preg]; \
dreg = ROT dreg BY -1; \
dreg = CC;
# ifndef __ASSEMBLY__
# include <asm/processor.h>
static inline unsigned long get_l1_scratch_start_cpu(int cpu)
{
return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;
}
static inline unsigned long get_l1_code_start_cpu(int cpu)
{
return cpu ? COREB_L1_CODE_START : COREA_L1_CODE_START;
}
static inline unsigned long get_l1_data_a_start_cpu(int cpu)
{
return cpu ? COREB_L1_DATA_A_START : COREA_L1_DATA_A_START;
}
static inline unsigned long get_l1_data_b_start_cpu(int cpu)
{
return cpu ? COREB_L1_DATA_B_START : COREA_L1_DATA_B_START;
}
static inline unsigned long get_l1_scratch_start(void)
{
return get_l1_scratch_start_cpu(blackfin_core_id());
}
static inline unsigned long get_l1_code_start(void)
{
return get_l1_code_start_cpu(blackfin_core_id());
}
static inline unsigned long get_l1_data_a_start(void)
{
return get_l1_data_a_start_cpu(blackfin_core_id());
}
static inline unsigned long get_l1_data_b_start(void)
{
return get_l1_data_b_start_cpu(blackfin_core_id());
}
# endif /* __ASSEMBLY__ */
#endif /* CONFIG_SMP */
#endif

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/*
* Copyright 2005-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_PLL_H
#define _MACH_PLL_H
#ifndef __ASSEMBLY__
#ifdef CONFIG_SMP
#include <asm/blackfin.h>
#include <asm/irqflags.h>
#include <mach/irq.h>
#define SUPPLE_0_WAKEUP ((IRQ_SUPPLE_0 - (IRQ_CORETMR + 1)) % 32)
#define SUPPLE_1_WAKEUP ((IRQ_SUPPLE_1 - (IRQ_CORETMR + 1)) % 32)
static inline void
bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
{
unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
bfin_write32(SIC_IWR0 + SICA_SICB_OFF, iwr0);
bfin_write32(SIC_IWR1 + SICA_SICB_OFF, iwr1);
}
#define bfin_iwr_restore bfin_iwr_restore
static inline void
bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
{
unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
*iwr0 = bfin_read32(SIC_IWR0 + SICA_SICB_OFF);
*iwr1 = bfin_read32(SIC_IWR1 + SICA_SICB_OFF);
bfin_iwr_restore(niwr0, niwr1, niwr2);
}
#define bfin_iwr_save bfin_iwr_save
static inline void
bfin_iwr_set_sup0(unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
{
bfin_iwr_save(0, IWR_ENABLE(SUPPLE_0_WAKEUP) |
IWR_ENABLE(SUPPLE_1_WAKEUP), 0, iwr0, iwr1, iwr2);
}
#endif
#endif
#include <mach-common/pll.h>
#endif

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/*
* Copyright 2007-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
#define P_PPI0_CLK (P_DONTCARE)
#define P_PPI0_FS1 (P_DONTCARE)
#define P_PPI0_FS2 (P_DONTCARE)
#define P_PPI0_FS3 (P_DONTCARE)
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47))
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46))
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45))
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44))
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43))
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42))
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41))
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40))
#define P_PPI0_D0 (P_DONTCARE)
#define P_PPI0_D1 (P_DONTCARE)
#define P_PPI0_D2 (P_DONTCARE)
#define P_PPI0_D3 (P_DONTCARE)
#define P_PPI0_D4 (P_DONTCARE)
#define P_PPI0_D5 (P_DONTCARE)
#define P_PPI0_D6 (P_DONTCARE)
#define P_PPI0_D7 (P_DONTCARE)
#define P_PPI1_CLK (P_DONTCARE)
#define P_PPI1_FS1 (P_DONTCARE)
#define P_PPI1_FS2 (P_DONTCARE)
#define P_PPI1_FS3 (P_DONTCARE)
#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39))
#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38))
#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37))
#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36))
#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35))
#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34))
#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33))
#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32))
#define P_PPI1_D0 (P_DONTCARE)
#define P_PPI1_D1 (P_DONTCARE)
#define P_PPI1_D2 (P_DONTCARE)
#define P_PPI1_D3 (P_DONTCARE)
#define P_PPI1_D4 (P_DONTCARE)
#define P_PPI1_D5 (P_DONTCARE)
#define P_PPI1_D6 (P_DONTCARE)
#define P_PPI1_D7 (P_DONTCARE)
#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31))
#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30))
#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29))
#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28))
#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27))
#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26))
#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25))
#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24))
#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23))
#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22))
#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21))
#define P_SPORT1_DRPRI (P_DONTCARE)
#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20))
#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19))
#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18))
#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17))
#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16))
#define P_SPORT0_DRPRI (P_DONTCARE)
#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15))
#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
#define P_TMR11 (P_DONTCARE)
#define P_TMR10 (P_DONTCARE)
#define P_TMR9 (P_DONTCARE)
#define P_TMR8 (P_DONTCARE)
#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7))
#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6))
#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5))
#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4))
#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3))
#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2))
#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1))
#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0))
#define P_SPI0_MOSI (P_DONTCARE)
#define P_SPI0_MISO (P_DONTCARE)
#define P_SPI0_SCK (P_DONTCARE)
#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
#endif /* _MACH_PORTMUX_H_ */

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/*
* Copyright 2007-2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_BF561_SMP
#define _MACH_BF561_SMP
/* This header has to stand alone to avoid circular deps */
struct task_struct;
void platform_init_cpus(void);
void platform_prepare_cpus(unsigned int max_cpus);
int platform_boot_secondary(unsigned int cpu, struct task_struct *idle);
void platform_secondary_init(unsigned int cpu);
void platform_request_ipi(int irq, /*irq_handler_t*/ void *handler);
void platform_send_ipi(cpumask_t callmap, int irq);
void platform_send_ipi_cpu(unsigned int cpu, int irq);
void platform_clear_ipi(unsigned int cpu, int irq);
void bfin_local_timer_setup(void);
#endif /* !_MACH_BF561_SMP */