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170
kernel/arch/blackfin/mach-bf518/include/mach/anomaly.h Normal file
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/*
* DO NOT EDIT THIS FILE
* This file is under version control at
* svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
* Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
* - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
*/
#if __SILICON_REVISION__ < 0
# error will not work on BF518 silicon version
#endif
#ifndef _MACH_ANOMALY_H_
#define _MACH_ANOMALY_H_
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
#define ANOMALY_05000074 (1)
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
#define ANOMALY_05000119 (1)
/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
#define ANOMALY_05000122 (1)
/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
#define ANOMALY_05000245 (1)
/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
#define ANOMALY_05000254 (1)
/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
#define ANOMALY_05000265 (1)
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
#define ANOMALY_05000310 (1)
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
#define ANOMALY_05000366 (1)
/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
#define ANOMALY_05000405 (1)
/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
#define ANOMALY_05000408 (1)
/* Speculative Fetches Can Cause Undesired External FIFO Operations */
#define ANOMALY_05000416 (1)
/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
#define ANOMALY_05000421 (1)
/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
#define ANOMALY_05000422 (1)
/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
#define ANOMALY_05000426 (1)
/* Software System Reset Corrupts PLL_LOCKCNT Register */
#define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
#define ANOMALY_05000431 (1)
/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
#define ANOMALY_05000434 (1)
/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
#define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
#define ANOMALY_05000438 (__SILICON_REVISION__ < 1)
/* Preboot Cannot be Used to Alter the PLL_DIV Register */
#define ANOMALY_05000439 (__SILICON_REVISION__ < 1)
/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
#define ANOMALY_05000440 (__SILICON_REVISION__ < 1)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
/* Incorrect L1 Instruction Bank B Memory Map Location */
#define ANOMALY_05000444 (__SILICON_REVISION__ < 1)
/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
/* PWM_TRIPB Signal Not Available on PG10 */
#define ANOMALY_05000453 (__SILICON_REVISION__ < 1)
/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
#define ANOMALY_05000455 (__SILICON_REVISION__ < 1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
#define ANOMALY_05000462 (__SILICON_REVISION__ < 2)
/* Incorrect Default MSEL Value in PLL_CTL */
#define ANOMALY_05000472 (__SILICON_REVISION__ < 2)
/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
#define ANOMALY_05000473 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* PLL Latches Incorrect Settings During Reset */
#define ANOMALY_05000482 (__SILICON_REVISION__ < 2)
/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
#define ANOMALY_05000485 (__SILICON_REVISION__ < 2)
/* SPI Master Boot Can Fail Under Certain Conditions */
#define ANOMALY_05000490 (1)
/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
#define ANOMALY_05000491 (1)
/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
#define ANOMALY_05000494 (1)
/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
#define ANOMALY_05000498 (1)
/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
#define ANOMALY_05000501 (1)
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000099 (0)
#define ANOMALY_05000120 (0)
#define ANOMALY_05000125 (0)
#define ANOMALY_05000149 (0)
#define ANOMALY_05000158 (0)
#define ANOMALY_05000171 (0)
#define ANOMALY_05000179 (0)
#define ANOMALY_05000182 (0)
#define ANOMALY_05000183 (0)
#define ANOMALY_05000189 (0)
#define ANOMALY_05000198 (0)
#define ANOMALY_05000202 (0)
#define ANOMALY_05000215 (0)
#define ANOMALY_05000219 (0)
#define ANOMALY_05000220 (0)
#define ANOMALY_05000227 (0)
#define ANOMALY_05000230 (0)
#define ANOMALY_05000231 (0)
#define ANOMALY_05000233 (0)
#define ANOMALY_05000234 (0)
#define ANOMALY_05000242 (0)
#define ANOMALY_05000244 (0)
#define ANOMALY_05000248 (0)
#define ANOMALY_05000250 (0)
#define ANOMALY_05000257 (0)
#define ANOMALY_05000261 (0)
#define ANOMALY_05000263 (0)
#define ANOMALY_05000266 (0)
#define ANOMALY_05000273 (0)
#define ANOMALY_05000274 (0)
#define ANOMALY_05000278 (0)
#define ANOMALY_05000281 (0)
#define ANOMALY_05000283 (0)
#define ANOMALY_05000285 (0)
#define ANOMALY_05000287 (0)
#define ANOMALY_05000301 (0)
#define ANOMALY_05000305 (0)
#define ANOMALY_05000307 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000312 (0)
#define ANOMALY_05000315 (0)
#define ANOMALY_05000323 (0)
#define ANOMALY_05000353 (0)
#define ANOMALY_05000357 (0)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000371 (0)
#define ANOMALY_05000380 (0)
#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (0)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000402 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
#define ANOMALY_05000450 (0)
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
#define ANOMALY_05000475 (0)
#define ANOMALY_05000480 (0)
#endif

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kernel/arch/blackfin/mach-bf518/include/mach/bf518.h Normal file
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/*
* Copyright 2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __MACH_BF518_H__
#define __MACH_BF518_H__
#define OFFSET_(x) ((x) & 0x0000FFFF)
/*some misc defines*/
#define IMASK_IVG15 0x8000
#define IMASK_IVG14 0x4000
#define IMASK_IVG13 0x2000
#define IMASK_IVG12 0x1000
#define IMASK_IVG11 0x0800
#define IMASK_IVG10 0x0400
#define IMASK_IVG9 0x0200
#define IMASK_IVG8 0x0100
#define IMASK_IVG7 0x0080
#define IMASK_IVGTMR 0x0040
#define IMASK_IVGHW 0x0020
/***************************/
#define BFIN_DSUBBANKS 4
#define BFIN_DWAYS 2
#define BFIN_DLINES 64
#define BFIN_ISUBBANKS 4
#define BFIN_IWAYS 4
#define BFIN_ILINES 32
#define WAY0_L 0x1
#define WAY1_L 0x2
#define WAY01_L 0x3
#define WAY2_L 0x4
#define WAY02_L 0x5
#define WAY12_L 0x6
#define WAY012_L 0x7
#define WAY3_L 0x8
#define WAY03_L 0x9
#define WAY13_L 0xA
#define WAY013_L 0xB
#define WAY32_L 0xC
#define WAY320_L 0xD
#define WAY321_L 0xE
#define WAYALL_L 0xF
#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
/********************************* EBIU Settings ************************************/
#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
#ifdef CONFIG_C_AMBEN_ALL
#define V_AMBEN AMBEN_ALL
#endif
#ifdef CONFIG_C_AMBEN
#define V_AMBEN 0x0
#endif
#ifdef CONFIG_C_AMBEN_B0
#define V_AMBEN AMBEN_B0
#endif
#ifdef CONFIG_C_AMBEN_B0_B1
#define V_AMBEN AMBEN_B0_B1
#endif
#ifdef CONFIG_C_AMBEN_B0_B1_B2
#define V_AMBEN AMBEN_B0_B1_B2
#endif
#ifdef CONFIG_C_AMCKEN
#define V_AMCKEN AMCKEN
#else
#define V_AMCKEN 0x0
#endif
#ifdef CONFIG_C_CDPRIO
#define V_CDPRIO 0x100
#else
#define V_CDPRIO 0x0
#endif
#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
/**************************** Hysteresis Settings ****************************/
#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
#ifdef CONFIG_GPIO_HYST_PORTF_0_7
#define HYST_PORTF_0_7 (1 << 0)
#else
#define HYST_PORTF_0_7 (0 << 0)
#endif
#ifdef CONFIG_GPIO_HYST_PORTF_8_9
#define HYST_PORTF_8_9 (1 << 2)
#else
#define HYST_PORTF_8_9 (0 << 2)
#endif
#ifdef CONFIG_GPIO_HYST_PORTF_10
#define HYST_PORTF_10 (1 << 4)
#else
#define HYST_PORTF_10 (0 << 4)
#endif
#ifdef CONFIG_GPIO_HYST_PORTF_11
#define HYST_PORTF_11 (1 << 6)
#else
#define HYST_PORTF_11 (0 << 6)
#endif
#ifdef CONFIG_GPIO_HYST_PORTF_12_13
#define HYST_PORTF_12_13 (1 << 8)
#else
#define HYST_PORTF_12_13 (0 << 8)
#endif
#ifdef CONFIG_GPIO_HYST_PORTF_14_15
#define HYST_PORTF_14_15 (1 << 10)
#else
#define HYST_PORTF_14_15 (0 << 10)
#endif
#define HYST_PORTF_0_15 (HYST_PORTF_0_7 | HYST_PORTF_8_9 | HYST_PORTF_10 | \
HYST_PORTF_11 | HYST_PORTF_12_13 | HYST_PORTF_14_15)
#ifdef CONFIG_GPIO_HYST_PORTG_0
#define HYST_PORTG_0 (1 << 0)
#else
#define HYST_PORTG_0 (0 << 0)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_1_4
#define HYST_PORTG_1_4 (1 << 2)
#else
#define HYST_PORTG_1_4 (0 << 2)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_5_6
#define HYST_PORTG_5_6 (1 << 4)
#else
#define HYST_PORTG_5_6 (0 << 4)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_7_8
#define HYST_PORTG_7_8 (1 << 6)
#else
#define HYST_PORTG_7_8 (0 << 6)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_9
#define HYST_PORTG_9 (1 << 8)
#else
#define HYST_PORTG_9 (0 << 8)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_10
#define HYST_PORTG_10 (1 << 10)
#else
#define HYST_PORTG_10 (0 << 10)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_11_13
#define HYST_PORTG_11_13 (1 << 12)
#else
#define HYST_PORTG_11_13 (0 << 12)
#endif
#ifdef CONFIG_GPIO_HYST_PORTG_14_15
#define HYST_PORTG_14_15 (1 << 14)
#else
#define HYST_PORTG_14_15 (0 << 14)
#endif
#define HYST_PORTG_0_15 (HYST_PORTG_0 | HYST_PORTG_1_4 | HYST_PORTG_5_6 | \
HYST_PORTG_7_8 | HYST_PORTG_9 | HYST_PORTG_10 | \
HYST_PORTG_11_13 | HYST_PORTG_14_15)
#ifdef CONFIG_GPIO_HYST_PORTH_0_7
#define HYST_PORTH_0_7 (1 << 0)
#else
#define HYST_PORTH_0_7 (0 << 0)
#endif
#define HYST_PORTH_0_15 (HYST_PORTH_0_7)
#ifdef CONFIG_NONEGPIO_HYST_NMI_RST_BMODE
#define HYST_NMI_RST_BMODE (1 << 2)
#else
#define HYST_NMI_RST_BMODE (0 << 2)
#endif
#ifdef CONFIG_NONEGPIO_HYST_JTAG
#define HYST_JTAG (1 << 4)
#else
#define HYST_JTAG (0 << 4)
#endif
#define HYST_NONEGPIO (HYST_NMI_RST_BMODE | HYST_JTAG)
#define HYST_NONEGPIO_MASK (0x3C)
#endif /* CONFIG_BFIN_HYSTERESIS_CONTROL */
#ifdef CONFIG_BF518
#define CPU "BF518"
#define CPUID 0x27e8
#endif
#ifdef CONFIG_BF516
#define CPU "BF516"
#define CPUID 0x27e8
#endif
#ifdef CONFIG_BF514
#define CPU "BF514"
#define CPUID 0x27e8
#endif
#ifdef CONFIG_BF512
#define CPU "BF512"
#define CPUID 0x27e8
#endif
#ifndef CPU
#error "Unknown CPU type - This kernel doesn't seem to be configured properly"
#endif
#endif /* __MACH_BF518_H__ */

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kernel/arch/blackfin/mach-bf518/include/mach/bfin_serial.h Normal file
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/*
* mach/bfin_serial.h - Blackfin UART/Serial definitions
*
* Copyright 2006-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef __BFIN_MACH_SERIAL_H__
#define __BFIN_MACH_SERIAL_H__
#define BFIN_UART_NR_PORTS 2
#endif

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kernel/arch/blackfin/mach-bf518/include/mach/blackfin.h Normal file
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/*
* Copyright 2008-2010 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_BLACKFIN_H_
#define _MACH_BLACKFIN_H_
#include "bf518.h"
#include "anomaly.h"
#include <asm/def_LPBlackfin.h>
#ifdef CONFIG_BF512
# include "defBF512.h"
#endif
#ifdef CONFIG_BF514
# include "defBF514.h"
#endif
#ifdef CONFIG_BF516
# include "defBF516.h"
#endif
#ifdef CONFIG_BF518
# include "defBF518.h"
#endif
#ifndef __ASSEMBLY__
# include <asm/cdef_LPBlackfin.h>
# ifdef CONFIG_BF512
# include "cdefBF512.h"
# endif
# ifdef CONFIG_BF514
# include "cdefBF514.h"
# endif
# ifdef CONFIG_BF516
# include "cdefBF516.h"
# endif
# ifdef CONFIG_BF518
# include "cdefBF518.h"
# endif
#endif
#endif

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kernel/arch/blackfin/mach-bf518/include/mach/cdefBF512.h Normal file
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kernel/arch/blackfin/mach-bf518/include/mach/cdefBF514.h Normal file
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/*
* Copyright 2008-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
*/
#ifndef _CDEF_BF514_H
#define _CDEF_BF514_H
/* BF514 is BF512 + RSI */
#include "cdefBF512.h"
/* Removable Storage Interface Registers */
#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL)
#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val)
#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL)
#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val)
#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT)
#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val)
#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK)
#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val)
#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4)
#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val)
#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5)
#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val)
#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6)
#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val)
#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7)
#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val)
#endif /* _CDEF_BF514_H */

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/*
* Copyright 2008-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
*/
#ifndef _CDEF_BF516_H
#define _CDEF_BF516_H
/* BF516 is BF514 + EMAC */
#include "cdefBF514.h"
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
#endif /* _CDEF_BF516_H */

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/*
* Copyright 2008-2010 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
*/
#ifndef _CDEF_BF518_H
#define _CDEF_BF518_H
/* BF518 is BF516 + IEEE-1588 */
#include "cdefBF516.h"
/* PTP TSYNC Registers */
#define bfin_read_EMAC_PTP_CTL() bfin_read16(EMAC_PTP_CTL)
#define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val)
#define bfin_read_EMAC_PTP_IE() bfin_read16(EMAC_PTP_IE)
#define bfin_write_EMAC_PTP_IE(val) bfin_write16(EMAC_PTP_IE, val)
#define bfin_read_EMAC_PTP_ISTAT() bfin_read16(EMAC_PTP_ISTAT)
#define bfin_write_EMAC_PTP_ISTAT(val) bfin_write16(EMAC_PTP_ISTAT, val)
#define bfin_read_EMAC_PTP_FOFF() bfin_read32(EMAC_PTP_FOFF)
#define bfin_write_EMAC_PTP_FOFF(val) bfin_write32(EMAC_PTP_FOFF, val)
#define bfin_read_EMAC_PTP_FV1() bfin_read32(EMAC_PTP_FV1)
#define bfin_write_EMAC_PTP_FV1(val) bfin_write32(EMAC_PTP_FV1, val)
#define bfin_read_EMAC_PTP_FV2() bfin_read32(EMAC_PTP_FV2)
#define bfin_write_EMAC_PTP_FV2(val) bfin_write32(EMAC_PTP_FV2, val)
#define bfin_read_EMAC_PTP_FV3() bfin_read32(EMAC_PTP_FV3)
#define bfin_write_EMAC_PTP_FV3(val) bfin_write32(EMAC_PTP_FV3, val)
#define bfin_read_EMAC_PTP_ADDEND() bfin_read32(EMAC_PTP_ADDEND)
#define bfin_write_EMAC_PTP_ADDEND(val) bfin_write32(EMAC_PTP_ADDEND, val)
#define bfin_read_EMAC_PTP_ACCR() bfin_read32(EMAC_PTP_ACCR)
#define bfin_write_EMAC_PTP_ACCR(val) bfin_write32(EMAC_PTP_ACCR, val)
#define bfin_read_EMAC_PTP_OFFSET() bfin_read32(EMAC_PTP_OFFSET)
#define bfin_write_EMAC_PTP_OFFSET(val) bfin_write32(EMAC_PTP_OFFSET, val)
#define bfin_read_EMAC_PTP_TIMELO() bfin_read32(EMAC_PTP_TIMELO)
#define bfin_write_EMAC_PTP_TIMELO(val) bfin_write32(EMAC_PTP_TIMELO, val)
#define bfin_read_EMAC_PTP_TIMEHI() bfin_read32(EMAC_PTP_TIMEHI)
#define bfin_write_EMAC_PTP_TIMEHI(val) bfin_write32(EMAC_PTP_TIMEHI, val)
#define bfin_read_EMAC_PTP_RXSNAPLO() bfin_read32(EMAC_PTP_RXSNAPLO)
#define bfin_read_EMAC_PTP_RXSNAPHI() bfin_read32(EMAC_PTP_RXSNAPHI)
#define bfin_read_EMAC_PTP_TXSNAPLO() bfin_read32(EMAC_PTP_TXSNAPLO)
#define bfin_read_EMAC_PTP_TXSNAPHI() bfin_read32(EMAC_PTP_TXSNAPHI)
#define bfin_read_EMAC_PTP_ALARMLO() bfin_read32(EMAC_PTP_ALARMLO)
#define bfin_write_EMAC_PTP_ALARMLO(val) bfin_write32(EMAC_PTP_ALARMLO, val)
#define bfin_read_EMAC_PTP_ALARMHI() bfin_read32(EMAC_PTP_ALARMHI)
#define bfin_write_EMAC_PTP_ALARMHI(val) bfin_write32(EMAC_PTP_ALARMHI, val)
#define bfin_read_EMAC_PTP_ID_OFF() bfin_read16(EMAC_PTP_ID_OFF)
#define bfin_write_EMAC_PTP_ID_OFF(val) bfin_write16(EMAC_PTP_ID_OFF, val)
#define bfin_read_EMAC_PTP_ID_SNAP() bfin_read32(EMAC_PTP_ID_SNAP)
#define bfin_write_EMAC_PTP_ID_SNAP(val) bfin_write32(EMAC_PTP_ID_SNAP, val)
#define bfin_read_EMAC_PTP_PPS_STARTHI() bfin_read32(EMAC_PTP_PPS_STARTHI)
#define bfin_write_EMAC_PTP_PPS_STARTHI(val) bfin_write32(EMAC_PTP_PPS_STARTHI, val)
#define bfin_read_EMAC_PTP_PPS_PERIOD() bfin_read32(EMAC_PTP_PPS_PERIOD)
#define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val)
#endif /* _CDEF_BF518_H */

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kernel/arch/blackfin/mach-bf518/include/mach/defBF514.h Normal file
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/*
* Copyright 2008-2009 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF514_H
#define _DEF_BF514_H
/* BF514 is BF512 + RSI */
#include "defBF512.h"
/* Removable Storage Interface Registers */
#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
#define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */
#define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */
#define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */
#define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */
#define RSI_PID4 0xFFC038E0 /* RSI Peripheral ID Register 0 */
#define RSI_PID5 0xFFC038E4 /* RSI Peripheral ID Register 1 */
#define RSI_PID6 0xFFC038E8 /* RSI Peripheral ID Register 2 */
#define RSI_PID7 0xFFC038EC /* RSI Peripheral ID Register 3 */
#endif /* _DEF_BF514_H */

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/*
* Copyright 2008-2009 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF516_H
#define _DEF_BF516_H
/* BF516 is BF514 + EMAC */
#include "defBF514.h"
/* The following are the #defines needed by ADSP-BF516 that are not in the common header */
/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
/* Listing for IEEE-Supported Count Registers */
#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
/***********************************************************************************
** System MMR Register Bits And Macros
**
** Disclaimer: All macros are intended to make C and Assembly code more readable.
** Use these macros carefully, as any that do left shifts for field
** depositing will result in the lower order bits being destroyed. Any
** macro that shifts left to properly position the bit-field should be
** used as part of an OR to initialize a register and NOT as a dynamic
** modifier UNLESS the lower order bits are saved and ORed back in when
** the macro is used.
*************************************************************************************/
/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
/* EMAC_OPMODE Masks */
#define RE 0x00000001 /* Receiver Enable */
#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
#define HU 0x00000010 /* Hash Filter Unicast Address */
#define HM 0x00000020 /* Hash Filter Multicast Address */
#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
#define PR 0x00000080 /* Promiscuous Mode Enable */
#define IFE 0x00000100 /* Inverse Filtering Enable */
#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
#define PBF 0x00000400 /* Pass Bad Frames Enable */
#define PSF 0x00000800 /* Pass Short Frames Enable */
#define RAF 0x00001000 /* Receive-All Mode */
#define TE 0x00010000 /* Transmitter Enable */
#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
#define DC 0x00080000 /* Deferral Check */
#define BOLMT 0x00300000 /* Back-Off Limit */
#define BOLMT_10 0x00000000 /* 10-bit range */
#define BOLMT_8 0x00100000 /* 8-bit range */
#define BOLMT_4 0x00200000 /* 4-bit range */
#define BOLMT_1 0x00300000 /* 1-bit range */
#define DRTY 0x00400000 /* Disable TX Retry On Collision */
#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
#define RMII 0x01000000 /* RMII/MII* Mode */
#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
#define LB 0x08000000 /* Internal Loopback Enable */
#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
/* EMAC_STAADD Masks */
#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
#define STADISPRE 0x00000004 /* Disable Preamble Generation */
#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
#define REGAD 0x000007C0 /* STA Register Address */
#define PHYAD 0x0000F800 /* PHY Device Address */
#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
/* EMAC_STADAT Mask */
#define STADATA 0x0000FFFF /* Station Management Data */
/* EMAC_FLC Masks */
#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
#define FLCE 0x00000002 /* Flow Control Enable */
#define PCF 0x00000004 /* Pass Control Frames */
#define BKPRSEN 0x00000008 /* Enable Backpressure */
#define FLCPAUSE 0xFFFF0000 /* Pause Time */
#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
/* EMAC_WKUP_CTL Masks */
#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
#define MPKE 0x00000002 /* Magic Packet Enable */
#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
#define MPKS 0x00000020 /* Magic Packet Received Status */
#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
/* EMAC_WKUP_FFCMD Masks */
#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
/* EMAC_WKUP_FFOFF Masks */
#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
/* Set ALL Offsets */
#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
/* EMAC_WKUP_FFCRC0 Masks */
#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
/* EMAC_WKUP_FFCRC1 Masks */
#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
/* EMAC_SYSCTL Masks */
#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
/* EMAC_SYSTAT Masks */
#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
#define RX_COMP 0x00001000 /* RX Frame Complete */
#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
#define RX_CRC 0x00010000 /* RX Frame CRC Error */
#define RX_LEN 0x00020000 /* RX Frame Length Error */
#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
#define RX_PHY 0x00200000 /* RX Frame PHY Error */
#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
#define TX_COMP 0x00000001 /* TX Frame Complete */
#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
/* EMAC_MMC_CTL Masks */
#define RSTC 0x00000001 /* Reset All Counters */
#define CROLL 0x00000002 /* Counter Roll-Over Enable */
#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
#define MMCE 0x00000008 /* Enable MMC Counter Operation */
/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
#endif /* _DEF_BF516_H */

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/*
* Copyright 2008-2009 Analog Devices Inc.
*
* Licensed under the ADI BSD license or the GPL-2 (or later)
*/
#ifndef _DEF_BF518_H
#define _DEF_BF518_H
/* BF518 is BF516 + IEEE-1588 */
#include "defBF516.h"
/* PTP TSYNC Registers */
#define EMAC_PTP_CTL 0xFFC030A0 /* PTP Block Control */
#define EMAC_PTP_IE 0xFFC030A4 /* PTP Block Interrupt Enable */
#define EMAC_PTP_ISTAT 0xFFC030A8 /* PTP Block Interrupt Status */
#define EMAC_PTP_FOFF 0xFFC030AC /* PTP Filter offset Register */
#define EMAC_PTP_FV1 0xFFC030B0 /* PTP Filter Value Register 1 */
#define EMAC_PTP_FV2 0xFFC030B4 /* PTP Filter Value Register 2 */
#define EMAC_PTP_FV3 0xFFC030B8 /* PTP Filter Value Register 3 */
#define EMAC_PTP_ADDEND 0xFFC030BC /* PTP Addend for Frequency Compensation */
#define EMAC_PTP_ACCR 0xFFC030C0 /* PTP Accumulator for Frequency Compensation */
#define EMAC_PTP_OFFSET 0xFFC030C4 /* PTP Time Offset Register */
#define EMAC_PTP_TIMELO 0xFFC030C8 /* PTP Precision Clock Time Low */
#define EMAC_PTP_TIMEHI 0xFFC030CC /* PTP Precision Clock Time High */
#define EMAC_PTP_RXSNAPLO 0xFFC030D0 /* PTP Receive Snapshot Register Low */
#define EMAC_PTP_RXSNAPHI 0xFFC030D4 /* PTP Receive Snapshot Register High */
#define EMAC_PTP_TXSNAPLO 0xFFC030D8 /* PTP Transmit Snapshot Register Low */
#define EMAC_PTP_TXSNAPHI 0xFFC030DC /* PTP Transmit Snapshot Register High */
#define EMAC_PTP_ALARMLO 0xFFC030E0 /* PTP Alarm time Low */
#define EMAC_PTP_ALARMHI 0xFFC030E4 /* PTP Alarm time High */
#define EMAC_PTP_ID_OFF 0xFFC030E8 /* PTP Capture ID offset register */
#define EMAC_PTP_ID_SNAP 0xFFC030EC /* PTP Capture ID register */
#define EMAC_PTP_PPS_STARTLO 0xFFC030F0 /* PPS Start Time Low */
#define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */
#define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */
/* Bit masks for EMAC_PTP_CTL */
#define PTP_EN 0x1 /* Enable the PTP_TSYNC module */
#define TL 0x2 /* Timestamp lock control */
#define ASEN 0x10 /* Auxiliary snapshot control */
#define PPSEN 0x80 /* Pulse-per-second (PPS) control */
#define CKOEN 0x2000 /* Clock output control */
/* Bit masks for EMAC_PTP_IE */
#define ALIE 0x1 /* Alarm interrupt enable */
#define RXEIE 0x2 /* Receive event interrupt enable */
#define RXGIE 0x4 /* Receive general interrupt enable */
#define TXIE 0x8 /* Transmit interrupt enable */
#define RXOVE 0x10 /* Receive overrun error interrupt enable */
#define TXOVE 0x20 /* Transmit overrun error interrupt enable */
#define ASIE 0x40 /* Auxiliary snapshot interrupt enable */
/* Bit masks for EMAC_PTP_ISTAT */
#define ALS 0x1 /* Alarm status */
#define RXEL 0x2 /* Receive event interrupt status */
#define RXGL 0x4 /* Receive general interrupt status */
#define TXTL 0x8 /* Transmit snapshot status */
#define RXOV 0x10 /* Receive snapshot overrun status */
#define TXOV 0x20 /* Transmit snapshot overrun status */
#define ASL 0x40 /* Auxiliary snapshot interrupt status */
#endif /* _DEF_BF518_H */

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/* mach/dma.h - arch-specific DMA defines
*
* Copyright 2004-2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_DMA_H_
#define _MACH_DMA_H_
#define MAX_DMA_CHANNELS 16
#define CH_PPI 0 /* PPI receive/transmit */
#define CH_EMAC_RX 1 /* Ethernet MAC receive */
#define CH_EMAC_TX 2 /* Ethernet MAC transmit */
#define CH_SPORT0_RX 3 /* SPORT0 receive */
#define CH_SPORT0_TX 4 /* SPORT0 transmit */
#define CH_RSI 4 /* RSI */
#define CH_SPORT1_RX 5 /* SPORT1 receive */
#define CH_SPI1 5 /* SPI1 transmit/receive */
#define CH_SPORT1_TX 6 /* SPORT1 transmit */
#define CH_SPI0 7 /* SPI0 transmit/receive */
#define CH_UART0_RX 8 /* UART0 receive */
#define CH_UART0_TX 9 /* UART0 transmit */
#define CH_UART1_RX 10 /* UART1 receive */
#define CH_UART1_TX 11 /* UART1 transmit */
#define CH_MEM_STREAM0_SRC 12 /* RX */
#define CH_MEM_STREAM0_DEST 13 /* TX */
#define CH_MEM_STREAM1_SRC 14 /* RX */
#define CH_MEM_STREAM1_DEST 15 /* TX */
#endif

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/*
* Copyright (C) 2008 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
#ifndef _MACH_GPIO_H_
#define _MACH_GPIO_H_
#define MAX_BLACKFIN_GPIOS 41
#define GPIO_PF0 0
#define GPIO_PF1 1
#define GPIO_PF2 2
#define GPIO_PF3 3
#define GPIO_PF4 4
#define GPIO_PF5 5
#define GPIO_PF6 6
#define GPIO_PF7 7
#define GPIO_PF8 8
#define GPIO_PF9 9
#define GPIO_PF10 10
#define GPIO_PF11 11
#define GPIO_PF12 12
#define GPIO_PF13 13
#define GPIO_PF14 14
#define GPIO_PF15 15
#define GPIO_PG0 16
#define GPIO_PG1 17
#define GPIO_PG2 18
#define GPIO_PG3 19
#define GPIO_PG4 20
#define GPIO_PG5 21
#define GPIO_PG6 22
#define GPIO_PG7 23
#define GPIO_PG8 24
#define GPIO_PG9 25
#define GPIO_PG10 26
#define GPIO_PG11 27
#define GPIO_PG12 28
#define GPIO_PG13 29
#define GPIO_PG14 30
#define GPIO_PG15 31
#define GPIO_PH0 32
#define GPIO_PH1 33
#define GPIO_PH2 34
#define GPIO_PH3 35
#define GPIO_PH4 36
#define GPIO_PH5 37
#define GPIO_PH6 38
#define GPIO_PH7 39
#define GPIO_PH8 40
#define PORT_F GPIO_PF0
#define PORT_G GPIO_PG0
#define PORT_H GPIO_PH0
#include <mach-common/ports-f.h>
#include <mach-common/ports-g.h>
#include <mach-common/ports-h.h>
#endif /* _MACH_GPIO_H_ */

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/*
* Copyright 2008 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
#ifndef _BF518_IRQ_H_
#define _BF518_IRQ_H_
#include <mach-common/irq.h>
#define NR_PERI_INTS (2 * 32)
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
#define IRQ_DMAR0_BLK BFIN_IRQ(2) /* DMAR0 Block Interrupt */
#define IRQ_DMAR1_BLK BFIN_IRQ(3) /* DMAR1 Block Interrupt */
#define IRQ_DMAR0_OVR BFIN_IRQ(4) /* DMAR0 Overflow Error */
#define IRQ_DMAR1_OVR BFIN_IRQ(5) /* DMAR1 Overflow Error */
#define IRQ_PPI_ERROR BFIN_IRQ(6) /* PPI Error */
#define IRQ_MAC_ERROR BFIN_IRQ(7) /* MAC Status */
#define IRQ_SPORT0_ERROR BFIN_IRQ(8) /* SPORT0 Status */
#define IRQ_SPORT1_ERROR BFIN_IRQ(9) /* SPORT1 Status */
#define IRQ_PTP_ERROR BFIN_IRQ(10) /* PTP Error Interrupt */
#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
#define IRQ_RTC BFIN_IRQ(14) /* RTC */
#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */
#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */
#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */
#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */
#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
#define IRQ_TWI BFIN_IRQ(20) /* TWI */
#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */
#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */
#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */
#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
#define IRQ_TIMER1 BFIN_IRQ(33) /* Timer 1 */
#define IRQ_TIMER2 BFIN_IRQ(34) /* Timer 2 */
#define IRQ_TIMER3 BFIN_IRQ(35) /* Timer 3 */
#define IRQ_TIMER4 BFIN_IRQ(36) /* Timer 4 */
#define IRQ_TIMER5 BFIN_IRQ(37) /* Timer 5 */
#define IRQ_TIMER6 BFIN_IRQ(38) /* Timer 6 */
#define IRQ_TIMER7 BFIN_IRQ(39) /* Timer 7 */
#define IRQ_PORTG_INTA BFIN_IRQ(40) /* Port G Interrupt A */
#define IRQ_PORTG_INTB BFIN_IRQ(41) /* Port G Interrupt B */
#define IRQ_MEM_DMA0 BFIN_IRQ(42) /* MDMA Stream 0 */
#define IRQ_MEM_DMA1 BFIN_IRQ(43) /* MDMA Stream 1 */
#define IRQ_WATCH BFIN_IRQ(44) /* Software Watchdog Timer */
#define IRQ_PORTF_INTA BFIN_IRQ(45) /* Port F Interrupt A */
#define IRQ_PORTF_INTB BFIN_IRQ(46) /* Port F Interrupt B */
#define IRQ_SPI0_ERROR BFIN_IRQ(47) /* SPI0 Status */
#define IRQ_SPI1_ERROR BFIN_IRQ(48) /* SPI1 Error */
#define IRQ_RSI_INT0 BFIN_IRQ(51) /* RSI Interrupt0 */
#define IRQ_RSI_INT1 BFIN_IRQ(52) /* RSI Interrupt1 */
#define IRQ_PWM_TRIP BFIN_IRQ(53) /* PWM Trip Interrupt */
#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */
#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */
#define SYS_IRQS BFIN_IRQ(63) /* 70 */
#define IRQ_PF0 71
#define IRQ_PF1 72
#define IRQ_PF2 73
#define IRQ_PF3 74
#define IRQ_PF4 75
#define IRQ_PF5 76
#define IRQ_PF6 77
#define IRQ_PF7 78
#define IRQ_PF8 79
#define IRQ_PF9 80
#define IRQ_PF10 81
#define IRQ_PF11 82
#define IRQ_PF12 83
#define IRQ_PF13 84
#define IRQ_PF14 85
#define IRQ_PF15 86
#define IRQ_PG0 87
#define IRQ_PG1 88
#define IRQ_PG2 89
#define IRQ_PG3 90
#define IRQ_PG4 91
#define IRQ_PG5 92
#define IRQ_PG6 93
#define IRQ_PG7 94
#define IRQ_PG8 95
#define IRQ_PG9 96
#define IRQ_PG10 97
#define IRQ_PG11 98
#define IRQ_PG12 99
#define IRQ_PG13 100
#define IRQ_PG14 101
#define IRQ_PG15 102
#define IRQ_PH0 103
#define IRQ_PH1 104
#define IRQ_PH2 105
#define IRQ_PH3 106
#define IRQ_PH4 107
#define IRQ_PH5 108
#define IRQ_PH6 109
#define IRQ_PH7 110
#define IRQ_PH8 111
#define IRQ_PH9 112
#define IRQ_PH10 113
#define IRQ_PH11 114
#define IRQ_PH12 115
#define IRQ_PH13 116
#define IRQ_PH14 117
#define IRQ_PH15 118
#define GPIO_IRQ_BASE IRQ_PF0
#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
/* IAR0 BIT FIELDS */
#define IRQ_PLL_WAKEUP_POS 0
#define IRQ_DMA0_ERROR_POS 4
#define IRQ_DMAR0_BLK_POS 8
#define IRQ_DMAR1_BLK_POS 12
#define IRQ_DMAR0_OVR_POS 16
#define IRQ_DMAR1_OVR_POS 20
#define IRQ_PPI_ERROR_POS 24
#define IRQ_MAC_ERROR_POS 28
/* IAR1 BIT FIELDS */
#define IRQ_SPORT0_ERROR_POS 0
#define IRQ_SPORT1_ERROR_POS 4
#define IRQ_PTP_ERROR_POS 8
#define IRQ_UART0_ERROR_POS 16
#define IRQ_UART1_ERROR_POS 20
#define IRQ_RTC_POS 24
#define IRQ_PPI_POS 28
/* IAR2 BIT FIELDS */
#define IRQ_SPORT0_RX_POS 0
#define IRQ_SPORT0_TX_POS 4
#define IRQ_RSI_POS 4
#define IRQ_SPORT1_RX_POS 8
#define IRQ_SPI1_POS 8
#define IRQ_SPORT1_TX_POS 12
#define IRQ_TWI_POS 16
#define IRQ_SPI0_POS 20
#define IRQ_UART0_RX_POS 24
#define IRQ_UART0_TX_POS 28
/* IAR3 BIT FIELDS */
#define IRQ_UART1_RX_POS 0
#define IRQ_UART1_TX_POS 4
#define IRQ_OPTSEC_POS 8
#define IRQ_CNT_POS 12
#define IRQ_MAC_RX_POS 16
#define IRQ_PORTH_INTA_POS 20
#define IRQ_MAC_TX_POS 24
#define IRQ_PORTH_INTB_POS 28
/* IAR4 BIT FIELDS */
#define IRQ_TIMER0_POS 0
#define IRQ_TIMER1_POS 4
#define IRQ_TIMER2_POS 8
#define IRQ_TIMER3_POS 12
#define IRQ_TIMER4_POS 16
#define IRQ_TIMER5_POS 20
#define IRQ_TIMER6_POS 24
#define IRQ_TIMER7_POS 28
/* IAR5 BIT FIELDS */
#define IRQ_PORTG_INTA_POS 0
#define IRQ_PORTG_INTB_POS 4
#define IRQ_MEM_DMA0_POS 8
#define IRQ_MEM_DMA1_POS 12
#define IRQ_WATCH_POS 16
#define IRQ_PORTF_INTA_POS 20
#define IRQ_PORTF_INTB_POS 24
#define IRQ_SPI0_ERROR_POS 28
/* IAR6 BIT FIELDS */
#define IRQ_SPI1_ERROR_POS 0
#define IRQ_RSI_INT0_POS 12
#define IRQ_RSI_INT1_POS 16
#define IRQ_PWM_TRIP_POS 20
#define IRQ_PWM_SYNC_POS 24
#define IRQ_PTP_STAT_POS 28
#endif

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/*
* BF51x memory map
*
* Copyright 2004-2009 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
#ifndef __BFIN_MACH_MEM_MAP_H__
#define __BFIN_MACH_MEM_MAP_H__
#ifndef __BFIN_MEM_MAP_H__
# error "do not include mach/mem_map.h directly -- use asm/mem_map.h"
#endif
/* Async Memory Banks */
#define ASYNC_BANK3_BASE 0x20300000 /* Async Bank 3 */
#define ASYNC_BANK3_SIZE 0x00100000 /* 1M */
#define ASYNC_BANK2_BASE 0x20200000 /* Async Bank 2 */
#define ASYNC_BANK2_SIZE 0x00100000 /* 1M */
#define ASYNC_BANK1_BASE 0x20100000 /* Async Bank 1 */
#define ASYNC_BANK1_SIZE 0x00100000 /* 1M */
#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
#define ASYNC_BANK0_SIZE 0x00100000 /* 1M */
/* Boot ROM Memory */
#define BOOT_ROM_START 0xEF000000
#define BOOT_ROM_LENGTH 0x8000
/* Level 1 Memory */
/* Memory Map for ADSP-BF518/6/4/2 processors */
#ifdef CONFIG_BFIN_ICACHE
#define BFIN_ICACHESIZE (16 * 1024)
#else
#define BFIN_ICACHESIZE (0)
#endif
#define L1_CODE_START 0xFFA00000
#define L1_DATA_A_START 0xFF800000
#define L1_DATA_B_START 0xFF900000
#define L1_CODE_LENGTH 0x8000
#ifdef CONFIG_BFIN_DCACHE
#ifdef CONFIG_BFIN_DCACHE_BANKA
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH 0x8000
#define BFIN_DCACHESIZE (16 * 1024)
#define BFIN_DSUPBANKS 1
#else
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
#define BFIN_DCACHESIZE (32 * 1024)
#define BFIN_DSUPBANKS 2
#endif
#else
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH 0x8000
#define L1_DATA_B_LENGTH 0x8000
#define BFIN_DCACHESIZE 0
#define BFIN_DSUPBANKS 0
#endif /*CONFIG_BFIN_DCACHE */
#endif

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#include <mach-common/pll.h>

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/*
* Copyright 2008-2009 Analog Devices Inc.
*
* Licensed under the GPL-2 or later
*/
#ifndef _MACH_PORTMUX_H_
#define _MACH_PORTMUX_H_
#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
/* EMAC MII/RMII Port Mux */
#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
#define P_MII0_MDC (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
#define P_MII0_MDIO (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
#define P_MII0 {\
P_MII0_ETxD0, \
P_MII0_ETxD1, \
P_MII0_ETxD2, \
P_MII0_ETxD3, \
P_MII0_ETxEN, \
P_MII0_TxCLK, \
P_MII0_PHYINT, \
P_MII0_COL, \
P_MII0_ERxD0, \
P_MII0_ERxD1, \
P_MII0_ERxD2, \
P_MII0_ERxD3, \
P_MII0_ERxDV, \
P_MII0_ERxCLK, \
P_MII0_ERxER, \
P_MII0_CRS, \
P_MII0_MDC, \
P_MII0_MDIO, 0}
#define P_RMII0 {\
P_MII0_ETxD0, \
P_MII0_ETxD1, \
P_MII0_ETxEN, \
P_MII0_ERxD0, \
P_MII0_ERxD1, \
P_MII0_ERxER, \
P_MII0_TxCLK, \
P_MII0_PHYINT, \
P_MII0_CRS, \
P_MII0_MDC, \
P_MII0_MDIO, 0}
/* PPI Port Mux */
#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
#ifndef CONFIG_BF518_PPI_TMR_PG12
#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
#else
#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
#endif
#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
/* SPI Port Mux */
#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
#define P_SPI1_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
#define P_SPI1_SSEL5 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG15
#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
/* SPORT Port Mux */
#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
/* UART Port Mux */
#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
/* Timer */
#ifndef CONFIG_BF518_PPI_TMR_PG12
#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
#else
#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
#endif
#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
/* DMA */
#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
/* TWI */
#define P_TWI0_SCL (P_DONTCARE)
#define P_TWI0_SDA (P_DONTCARE)
/* PWM */
#ifndef CONFIG_BF518_PWM_PORTF_PORTG
#define P_PWM_AH (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
#define P_PWM_AL (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
#define P_PWM_BH (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
#define P_PWM_BL (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
#define P_PWM_CH (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
#define P_PWM_CL (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
#else
#define P_PWM_AH (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
#define P_PWM_AL (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
#define P_PWM_BH (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
#define P_PWM_BL (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
#define P_PWM_CH (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
#define P_PWM_CL (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
#endif
#ifndef CONFIG_BF518_PWM_SYNC_PF15
#define P_PWM_SYNC (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
#else
#define P_PWM_SYNC (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
#endif
#ifndef CONFIG_BF518_PWM_TRIPB_PG14
#define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2))
#else
#define P_PWM_TRIPB (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
#endif
/* RSI */
#define P_RSI_DATA0 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
#define P_RSI_DATA1 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
#define P_RSI_DATA2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
#define P_RSI_DATA3 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
#define P_RSI_DATA4 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
#define P_RSI_DATA5 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
#define P_RSI_DATA6 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
#define P_RSI_DATA7 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
#define P_RSI_CMD (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
#define P_RSI_CLK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
/* PTP */
#define P_PTP_PPS (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
#define P_PTP_CLKOUT (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
/* AMS */
#define P_AMS2 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
#define P_AMS3 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
#define P_HWAIT (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1))
#endif /* _MACH_PORTMUX_H_ */