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2024-09-09 08:52:07 +00:00
commit f9cc65cfda
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kernel/arch/arm/mach-u300/Kconfig
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if ARCH_U300
menu "ST-Ericsson AB U300/U330/U335/U365 Platform"
comment "ST-Ericsson Mobile Platform Products"
config MACH_U300
bool "U300"
select PINCTRL
select PINCTRL_U300
select PINCTRL_COH901
comment "ST-Ericsson U300/U330/U335/U365 Feature Selections"
choice
prompt "U300/U330/U335/U365 system type"
default MACH_U300_BS2X
---help---
You need to select the target system, i.e. the
U300/U330/U335/U365 board that you want to compile your kernel
for.
config MACH_U300_BS2X
bool "S26/S26/B25/B26 Test Products"
depends on MACH_U300
help
Select this if you're developing on the
S26/S25 test products. (Also works on
B26/B25 big boards.)
config MACH_U300_BS330
bool "S330/B330 Test Products"
depends on MACH_U300
help
Select this if you're developing on the
S330/B330 test products.
config MACH_U300_BS335
bool "S335/B335 Test Products"
depends on MACH_U300
help
Select this if you're developing on the
S335/B335 test products.
config MACH_U300_BS365
bool "S365/B365 Test Products"
depends on MACH_U300
help
Select this if you're developing on the
S365/B365 test products.
endchoice
config U300_DEBUG
bool "Debug support for U300"
depends on PM
help
Debug support for U300 in sysfs, procfs etc.
config MACH_U300_SPIDUMMY
bool "SSP/SPI dummy chip"
select SPI
select SPI_MASTER
select SPI_PL022
help
This creates a small kernel module that creates a dummy
SPI device to be used for loopback tests. Regularly used
to test reference designs. If you're not testing SPI,
you don't need it. Selecting this will activate the
SPI framework and ARM PL022 support.
endmenu
endif
kernel/arch/arm/mach-u300/Makefile
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#
# Makefile for the linux kernel, U300 machine.
#
obj-y := core.o clock.o timer.o
obj-m :=
obj-n :=
obj- :=
obj-$(CONFIG_ARCH_U300) += u300.o
obj-$(CONFIG_SPI_PL022) += spi.o
obj-$(CONFIG_MACH_U300_SPIDUMMY) += dummyspichip.o
obj-$(CONFIG_I2C_STU300) += i2c.o
obj-$(CONFIG_REGULATOR_AB3100) += regulator.o
kernel/arch/arm/mach-u300/Makefile.boot
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zreladdr-y += 0x48008000
params_phys-y := 0x48000100
# This isn't used.
#initrd_phys-y := 0x48800000
kernel/arch/arm/mach-u300/clock.c
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kernel/arch/arm/mach-u300/clock.h
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/*
* arch/arm/mach-u300/include/mach/clock.h
*
* Copyright (C) 2004 - 2005 Nokia corporation
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
* Copyright (C) 2007-2009 ST-Ericsson AB
* Adopted to ST-Ericsson U300 platforms by
* Jonas Aaberg <jonas.aberg@stericsson.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __MACH_CLOCK_H
#define __MACH_CLOCK_H
#include <linux/clk.h>
struct clk {
struct list_head node;
struct module *owner;
struct device *dev;
const char *name;
struct clk *parent;
spinlock_t lock;
unsigned long rate;
bool reset;
__u16 clk_val;
__s8 usecount;
void __iomem * res_reg;
__u16 res_mask;
bool hw_ctrld;
void (*recalc) (struct clk *);
int (*set_rate) (struct clk *, unsigned long);
unsigned long (*get_rate) (struct clk *);
unsigned long (*round_rate) (struct clk *, unsigned long);
void (*init) (struct clk *);
void (*enable) (struct clk *);
void (*disable) (struct clk *);
};
int u300_clock_init(void);
#endif
kernel/arch/arm/mach-u300/core.c
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kernel/arch/arm/mach-u300/dummyspichip.c
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/*
* arch/arm/mach-u300/dummyspichip.c
*
* Copyright (C) 2007-2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* This is a dummy loopback SPI "chip" used for testing SPI.
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/sysfs.h>
#include <linux/mutex.h>
#include <linux/spi/spi.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
/*
* WARNING! Do not include this pl022-specific controller header
* for any generic driver. It is only done in this dummy chip
* because we alter the chip configuration in order to test some
* different settings on the loopback device. Normal chip configs
* shall be STATIC and not altered by the driver!
*/
#include <linux/amba/pl022.h>
struct dummy {
struct device *dev;
struct mutex lock;
};
#define DMA_TEST_SIZE 2048
/* When we cat /sys/bus/spi/devices/spi0.0/looptest this will be triggered */
static ssize_t dummy_looptest(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct spi_device *spi = to_spi_device(dev);
struct dummy *p_dummy = dev_get_drvdata(&spi->dev);
/*
* WARNING! Do not dereference the chip-specific data in any normal
* driver for a chip. It is usually STATIC and shall not be read
* or written to. Your chip driver should NOT depend on fields in this
* struct, this is just used here to alter the behaviour of the chip
* in order to perform tests.
*/
int status;
u8 txbuf[14] = {0xDE, 0xAD, 0xBE, 0xEF, 0x2B, 0xAD,
0xCA, 0xFE, 0xBA, 0xBE, 0xB1, 0x05,
0xF0, 0x0D};
u8 rxbuf[14];
u8 *bigtxbuf_virtual;
u8 *bigrxbuf_virtual;
if (mutex_lock_interruptible(&p_dummy->lock))
return -ERESTARTSYS;
bigtxbuf_virtual = kmalloc(DMA_TEST_SIZE, GFP_KERNEL);
if (bigtxbuf_virtual == NULL) {
status = -ENOMEM;
goto out;
}
bigrxbuf_virtual = kmalloc(DMA_TEST_SIZE, GFP_KERNEL);
/* Fill TXBUF with some happy pattern */
memset(bigtxbuf_virtual, 0xAA, DMA_TEST_SIZE);
/*
* Force chip to 8 bit mode
* WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC!
*/
spi->bits_per_word = 8;
/* You should NOT DO THIS EITHER */
spi->master->setup(spi);
/* Now run the tests for 8bit mode */
pr_info("Simple test 1: write 0xAA byte, read back garbage byte "
"in 8bit mode\n");
status = spi_w8r8(spi, 0xAA);
if (status < 0)
pr_warning("Siple test 1: FAILURE: spi_write_then_read "
"failed with status %d\n", status);
else
pr_info("Simple test 1: SUCCESS!\n");
pr_info("Simple test 2: write 8 bytes, read back 8 bytes garbage "
"in 8bit mode (full FIFO)\n");
status = spi_write_then_read(spi, &txbuf[0], 8, &rxbuf[0], 8);
if (status < 0)
pr_warning("Simple test 2: FAILURE: spi_write_then_read() "
"failed with status %d\n", status);
else
pr_info("Simple test 2: SUCCESS!\n");
pr_info("Simple test 3: write 14 bytes, read back 14 bytes garbage "
"in 8bit mode (see if we overflow FIFO)\n");
status = spi_write_then_read(spi, &txbuf[0], 14, &rxbuf[0], 14);
if (status < 0)
pr_warning("Simple test 3: FAILURE: failed with status %d "
"(probably FIFO overrun)\n", status);
else
pr_info("Simple test 3: SUCCESS!\n");
pr_info("Simple test 4: write 8 bytes with spi_write(), read 8 "
"bytes garbage with spi_read() in 8bit mode\n");
status = spi_write(spi, &txbuf[0], 8);
if (status < 0)
pr_warning("Simple test 4 step 1: FAILURE: spi_write() "
"failed with status %d\n", status);
else
pr_info("Simple test 4 step 1: SUCCESS!\n");
status = spi_read(spi, &rxbuf[0], 8);
if (status < 0)
pr_warning("Simple test 4 step 2: FAILURE: spi_read() "
"failed with status %d\n", status);
else
pr_info("Simple test 4 step 2: SUCCESS!\n");
pr_info("Simple test 5: write 14 bytes with spi_write(), read "
"14 bytes garbage with spi_read() in 8bit mode\n");
status = spi_write(spi, &txbuf[0], 14);
if (status < 0)
pr_warning("Simple test 5 step 1: FAILURE: spi_write() "
"failed with status %d (probably FIFO overrun)\n",
status);
else
pr_info("Simple test 5 step 1: SUCCESS!\n");
status = spi_read(spi, &rxbuf[0], 14);
if (status < 0)
pr_warning("Simple test 5 step 2: FAILURE: spi_read() "
"failed with status %d (probably FIFO overrun)\n",
status);
else
pr_info("Simple test 5: SUCCESS!\n");
pr_info("Simple test 6: write %d bytes with spi_write(), "
"read %d bytes garbage with spi_read() in 8bit mode\n",
DMA_TEST_SIZE, DMA_TEST_SIZE);
status = spi_write(spi, &bigtxbuf_virtual[0], DMA_TEST_SIZE);
if (status < 0)
pr_warning("Simple test 6 step 1: FAILURE: spi_write() "
"failed with status %d (probably FIFO overrun)\n",
status);
else
pr_info("Simple test 6 step 1: SUCCESS!\n");
status = spi_read(spi, &bigrxbuf_virtual[0], DMA_TEST_SIZE);
if (status < 0)
pr_warning("Simple test 6 step 2: FAILURE: spi_read() "
"failed with status %d (probably FIFO overrun)\n",
status);
else
pr_info("Simple test 6: SUCCESS!\n");
/*
* Force chip to 16 bit mode
* WARNING: NEVER DO THIS IN REAL DRIVER CODE, THIS SHOULD BE STATIC!
*/
spi->bits_per_word = 16;
/* You should NOT DO THIS EITHER */
spi->master->setup(spi);
pr_info("Simple test 7: write 0xAA byte, read back garbage byte "
"in 16bit bus mode\n");
status = spi_w8r8(spi, 0xAA);
if (status == -EIO)
pr_info("Simple test 7: SUCCESS! (expected failure with "
"status EIO)\n");
else if (status < 0)
pr_warning("Siple test 7: FAILURE: spi_write_then_read "
"failed with status %d\n", status);
else
pr_warning("Siple test 7: FAILURE: spi_write_then_read "
"succeeded but it was expected to fail!\n");
pr_info("Simple test 8: write 8 bytes, read back 8 bytes garbage "
"in 16bit mode (full FIFO)\n");
status = spi_write_then_read(spi, &txbuf[0], 8, &rxbuf[0], 8);
if (status < 0)
pr_warning("Simple test 8: FAILURE: spi_write_then_read() "
"failed with status %d\n", status);
else
pr_info("Simple test 8: SUCCESS!\n");
pr_info("Simple test 9: write 14 bytes, read back 14 bytes garbage "
"in 16bit mode (see if we overflow FIFO)\n");
status = spi_write_then_read(spi, &txbuf[0], 14, &rxbuf[0], 14);
if (status < 0)
pr_warning("Simple test 9: FAILURE: failed with status %d "
"(probably FIFO overrun)\n", status);
else
pr_info("Simple test 9: SUCCESS!\n");
pr_info("Simple test 10: write %d bytes with spi_write(), "
"read %d bytes garbage with spi_read() in 16bit mode\n",
DMA_TEST_SIZE, DMA_TEST_SIZE);
status = spi_write(spi, &bigtxbuf_virtual[0], DMA_TEST_SIZE);
if (status < 0)
pr_warning("Simple test 10 step 1: FAILURE: spi_write() "
"failed with status %d (probably FIFO overrun)\n",
status);
else
pr_info("Simple test 10 step 1: SUCCESS!\n");
status = spi_read(spi, &bigrxbuf_virtual[0], DMA_TEST_SIZE);
if (status < 0)
pr_warning("Simple test 10 step 2: FAILURE: spi_read() "
"failed with status %d (probably FIFO overrun)\n",
status);
else
pr_info("Simple test 10: SUCCESS!\n");
status = sprintf(buf, "loop test complete\n");
kfree(bigrxbuf_virtual);
kfree(bigtxbuf_virtual);
out:
mutex_unlock(&p_dummy->lock);
return status;
}
static DEVICE_ATTR(looptest, S_IRUGO, dummy_looptest, NULL);
static int __devinit pl022_dummy_probe(struct spi_device *spi)
{
struct dummy *p_dummy;
int status;
dev_info(&spi->dev, "probing dummy SPI device\n");
p_dummy = kzalloc(sizeof *p_dummy, GFP_KERNEL);
if (!p_dummy)
return -ENOMEM;
dev_set_drvdata(&spi->dev, p_dummy);
mutex_init(&p_dummy->lock);
/* sysfs hook */
status = device_create_file(&spi->dev, &dev_attr_looptest);
if (status) {
dev_dbg(&spi->dev, "device_create_file looptest failure.\n");
goto out_dev_create_looptest_failed;
}
return 0;
out_dev_create_looptest_failed:
dev_set_drvdata(&spi->dev, NULL);
kfree(p_dummy);
return status;
}
static int __devexit pl022_dummy_remove(struct spi_device *spi)
{
struct dummy *p_dummy = dev_get_drvdata(&spi->dev);
dev_info(&spi->dev, "removing dummy SPI device\n");
device_remove_file(&spi->dev, &dev_attr_looptest);
dev_set_drvdata(&spi->dev, NULL);
kfree(p_dummy);
return 0;
}
static struct spi_driver pl022_dummy_driver = {
.driver = {
.name = "spi-dummy",
.owner = THIS_MODULE,
},
.probe = pl022_dummy_probe,
.remove = __devexit_p(pl022_dummy_remove),
};
static int __init pl022_init_dummy(void)
{
return spi_register_driver(&pl022_dummy_driver);
}
static void __exit pl022_exit_dummy(void)
{
spi_unregister_driver(&pl022_dummy_driver);
}
module_init(pl022_init_dummy);
module_exit(pl022_exit_dummy);
MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
MODULE_DESCRIPTION("PL022 SSP/SPI DUMMY Linux driver");
MODULE_LICENSE("GPL");
kernel/arch/arm/mach-u300/i2c.c
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/*
* arch/arm/mach-u300/i2c.c
*
* Copyright (C) 2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
*
* Register board i2c devices
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#include <linux/kernel.h>
#include <linux/i2c.h>
#include <linux/mfd/abx500.h>
#include <linux/regulator/machine.h>
#include <linux/amba/bus.h>
#include <mach/irqs.h>
/*
* Initial settings of ab3100 registers.
* Common for below LDO regulator settings are that
* bit 7-5 controls voltage. Bit 4 turns regulator ON(1) or OFF(0).
* Bit 3-2 controls sleep enable and bit 1-0 controls sleep mode.
*/
/* LDO_A 0x16: 2.75V, ON, SLEEP_A, SLEEP OFF GND */
#define LDO_A_SETTING 0x16
/* LDO_C 0x10: 2.65V, ON, SLEEP_A or B, SLEEP full power */
#define LDO_C_SETTING 0x10
/* LDO_D 0x10: 2.65V, ON, sleep mode not used */
#define LDO_D_SETTING 0x10
/* LDO_E 0x10: 1.8V, ON, SLEEP_A or B, SLEEP full power */
#define LDO_E_SETTING 0x10
/* LDO_E SLEEP 0x00: 1.8V, not used, SLEEP_A or B, not used */
#define LDO_E_SLEEP_SETTING 0x00
/* LDO_F 0xD0: 2.5V, ON, SLEEP_A or B, SLEEP full power */
#define LDO_F_SETTING 0xD0
/* LDO_G 0x00: 2.85V, OFF, SLEEP_A or B, SLEEP full power */
#define LDO_G_SETTING 0x00
/* LDO_H 0x18: 2.75V, ON, SLEEP_B, SLEEP full power */
#define LDO_H_SETTING 0x18
/* LDO_K 0x00: 2.75V, OFF, SLEEP_A or B, SLEEP full power */
#define LDO_K_SETTING 0x00
/* LDO_EXT 0x00: Voltage not set, OFF, not used, not used */
#define LDO_EXT_SETTING 0x00
/* BUCK 0x7D: 1.2V, ON, SLEEP_A and B, SLEEP low power */
#define BUCK_SETTING 0x7D
/* BUCK SLEEP 0xAC: 1.05V, Not used, SLEEP_A and B, Not used */
#define BUCK_SLEEP_SETTING 0xAC
#ifdef CONFIG_AB3100_CORE
static struct regulator_consumer_supply supply_ldo_c[] = {
{
.dev_name = "ab3100-codec",
.supply = "vaudio", /* Powers the codec */
},
};
/*
* This one needs to be a supply so we can turn it off
* in order to shut down the system.
*/
static struct regulator_consumer_supply supply_ldo_d[] = {
{
.supply = "vana15", /* Powers the SoC (CPU etc) */
},
};
static struct regulator_consumer_supply supply_ldo_g[] = {
{
.dev_name = "mmci",
.supply = "vmmc", /* Powers MMC/SD card */
},
};
static struct regulator_consumer_supply supply_ldo_h[] = {
{
.dev_name = "xgam_pdi",
.supply = "vdisp", /* Powers camera, display etc */
},
};
static struct regulator_consumer_supply supply_ldo_k[] = {
{
.dev_name = "irda",
.supply = "vir", /* Power IrDA */
},
};
/*
* This is a placeholder for whoever wish to use the
* external power.
*/
static struct regulator_consumer_supply supply_ldo_ext[] = {
{
.supply = "vext", /* External power */
},
};
/* Preset (hardware defined) voltages for these regulators */
#define LDO_A_VOLTAGE 2750000
#define LDO_C_VOLTAGE 2650000
#define LDO_D_VOLTAGE 2650000
static struct ab3100_platform_data ab3100_plf_data = {
.reg_constraints = {
/* LDO A routing and constraints */
{
.constraints = {
.name = "vrad",
.min_uV = LDO_A_VOLTAGE,
.max_uV = LDO_A_VOLTAGE,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.always_on = 1,
.boot_on = 1,
},
},
/* LDO C routing and constraints */
{
.constraints = {
.min_uV = LDO_C_VOLTAGE,
.max_uV = LDO_C_VOLTAGE,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
},
.num_consumer_supplies = ARRAY_SIZE(supply_ldo_c),
.consumer_supplies = supply_ldo_c,
},
/* LDO D routing and constraints */
{
.constraints = {
.min_uV = LDO_D_VOLTAGE,
.max_uV = LDO_D_VOLTAGE,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
/*
* Actually this is boot_on but we need
* to reference count it externally to
* be able to shut down the system.
*/
},
.num_consumer_supplies = ARRAY_SIZE(supply_ldo_d),
.consumer_supplies = supply_ldo_d,
},
/* LDO E routing and constraints */
{
.constraints = {
.name = "vio",
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.always_on = 1,
.boot_on = 1,
},
},
/* LDO F routing and constraints */
{
.constraints = {
.name = "vana25",
.min_uV = 2500000,
.max_uV = 2500000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.always_on = 1,
.boot_on = 1,
},
},
/* LDO G routing and constraints */
{
.constraints = {
.min_uV = 1500000,
.max_uV = 2850000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(supply_ldo_g),
.consumer_supplies = supply_ldo_g,
},
/* LDO H routing and constraints */
{
.constraints = {
.min_uV = 1200000,
.max_uV = 2750000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(supply_ldo_h),
.consumer_supplies = supply_ldo_h,
},
/* LDO K routing and constraints */
{
.constraints = {
.min_uV = 1800000,
.max_uV = 2750000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(supply_ldo_k),
.consumer_supplies = supply_ldo_k,
},
/* External regulator interface. No fixed voltage specified.
* If we knew the voltage of the external regulator and it
* was connected on the board, we could add the (fixed)
* voltage for it here.
*/
{
.constraints = {
.min_uV = 0,
.max_uV = 0,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask =
REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(supply_ldo_ext),
.consumer_supplies = supply_ldo_ext,
},
/* Buck converter routing and constraints */
{
.constraints = {
.name = "vcore",
.min_uV = 1200000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE,
.always_on = 1,
.boot_on = 1,
},
},
},
.reg_initvals = {
LDO_A_SETTING,
LDO_C_SETTING,
LDO_E_SETTING,
LDO_E_SLEEP_SETTING,
LDO_F_SETTING,
LDO_G_SETTING,
LDO_H_SETTING,
LDO_K_SETTING,
LDO_EXT_SETTING,
BUCK_SETTING,
BUCK_SLEEP_SETTING,
LDO_D_SETTING,
},
};
#endif
static struct i2c_board_info __initdata bus0_i2c_board_info[] = {
#ifdef CONFIG_AB3100_CORE
{
.type = "ab3100",
.addr = 0x48,
.irq = IRQ_U300_IRQ0_EXT,
.platform_data = &ab3100_plf_data,
},
#else
{ },
#endif
};
static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
#ifdef CONFIG_MACH_U300_BS335
{
.type = "fwcam",
.addr = 0x10,
},
{
.type = "fwcam",
.addr = 0x5d,
},
#else
{ },
#endif
};
void __init u300_i2c_register_board_devices(void)
{
i2c_register_board_info(0, bus0_i2c_board_info,
ARRAY_SIZE(bus0_i2c_board_info));
/*
* This makes the core shut down all unused regulators
* after all the initcalls have completed.
*/
regulator_has_full_constraints();
i2c_register_board_info(1, bus1_i2c_board_info,
ARRAY_SIZE(bus1_i2c_board_info));
}
kernel/arch/arm/mach-u300/i2c.h
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/*
* arch/arm/mach-u300/i2c.h
*
* Copyright (C) 2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
*
* Register board i2c devices
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#ifndef MACH_U300_I2C_H
#define MACH_U300_I2C_H
#ifdef CONFIG_I2C_STU300
void __init u300_i2c_register_board_devices(void);
#else
/* Compile out this stuff if no I2C adapter is available */
static inline void __init u300_i2c_register_board_devices(void)
{
}
#endif
#endif
kernel/arch/arm/mach-u300/include/mach/clkdev.h
+7
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@@ -0,0 +1,7 @@
#ifndef __MACH_CLKDEV_H
#define __MACH_CLKDEV_H
int __clk_get(struct clk *clk);
void __clk_put(struct clk *clk);
#endif
kernel/arch/arm/mach-u300/include/mach/coh901318.h
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/*
*
* include/linux/coh901318.h
*
*
* Copyright (C) 2007-2009 ST-Ericsson
* License terms: GNU General Public License (GPL) version 2
* DMA driver for COH 901 318
* Author: Per Friden <per.friden@stericsson.com>
*/
#ifndef COH901318_H
#define COH901318_H
#include <linux/device.h>
#include <linux/dmaengine.h>
#define MAX_DMA_PACKET_SIZE_SHIFT 11
#define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)
/**
* struct coh901318_lli - linked list item for DMAC
* @control: control settings for DMAC
* @src_addr: transfer source address
* @dst_addr: transfer destination address
* @link_addr: physical address to next lli
* @virt_link_addr: virtual address of next lli (only used by pool_free)
* @phy_this: physical address of current lli (only used by pool_free)
*/
struct coh901318_lli {
u32 control;
dma_addr_t src_addr;
dma_addr_t dst_addr;
dma_addr_t link_addr;
void *virt_link_addr;
dma_addr_t phy_this;
};
/**
* struct coh901318_params - parameters for DMAC configuration
* @config: DMA config register
* @ctrl_lli_last: DMA control register for the last lli in the list
* @ctrl_lli: DMA control register for an lli
* @ctrl_lli_chained: DMA control register for a chained lli
*/
struct coh901318_params {
u32 config;
u32 ctrl_lli_last;
u32 ctrl_lli;
u32 ctrl_lli_chained;
};
/**
* struct coh_dma_channel - dma channel base
* @name: ascii name of dma channel
* @number: channel id number
* @desc_nbr_max: number of preallocated descriptors
* @priority_high: prio of channel, 0 low otherwise high.
* @param: configuration parameters
* @dev_addr: physical address of periphal connected to channel
*/
struct coh_dma_channel {
const char name[32];
const int number;
const int desc_nbr_max;
const int priority_high;
const struct coh901318_params param;
const dma_addr_t dev_addr;
};
/**
* dma_access_memory_state_t - register dma for memory access
*
* @dev: The dma device
* @active: 1 means dma intends to access memory
* 0 means dma wont access memory
*/
typedef void (*dma_access_memory_state_t)(struct device *dev,
bool active);
/**
* struct powersave - DMA power save structure
* @lock: lock protecting data in this struct
* @started_channels: bit mask indicating active dma channels
*/
struct powersave {
spinlock_t lock;
u64 started_channels;
};
/**
* struct coh901318_platform - platform arch structure
* @chans_slave: specifying dma slave channels
* @chans_memcpy: specifying dma memcpy channels
* @access_memory_state: requesting DMA memory access (on / off)
* @chan_conf: dma channel configurations
* @max_channels: max number of dma chanenls
*/
struct coh901318_platform {
const int *chans_slave;
const int *chans_memcpy;
const dma_access_memory_state_t access_memory_state;
const struct coh_dma_channel *chan_conf;
const int max_channels;
};
#ifdef CONFIG_COH901318
/**
* coh901318_filter_id() - DMA channel filter function
* @chan: dma channel handle
* @chan_id: id of dma channel to be filter out
*
* In dma_request_channel() it specifies what channel id to be requested
*/
bool coh901318_filter_id(struct dma_chan *chan, void *chan_id);
#else
static inline bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
{
return false;
}
#endif
/*
* DMA Controller - this access the static mappings of the coh901318 dma.
*
*/
#define COH901318_MOD32_MASK (0x1F)
#define COH901318_WORD_MASK (0xFFFFFFFF)
/* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
#define COH901318_INT_STATUS1 (0x0000)
#define COH901318_INT_STATUS2 (0x0004)
/* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
#define COH901318_TC_INT_STATUS1 (0x0008)
#define COH901318_TC_INT_STATUS2 (0x000C)
/* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
#define COH901318_TC_INT_CLEAR1 (0x0010)
#define COH901318_TC_INT_CLEAR2 (0x0014)
/* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
#define COH901318_RAW_TC_INT_STATUS1 (0x0018)
#define COH901318_RAW_TC_INT_STATUS2 (0x001C)
/* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
#define COH901318_BE_INT_STATUS1 (0x0020)
#define COH901318_BE_INT_STATUS2 (0x0024)
/* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
#define COH901318_BE_INT_CLEAR1 (0x0028)
#define COH901318_BE_INT_CLEAR2 (0x002C)
/* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
#define COH901318_RAW_BE_INT_STATUS1 (0x0030)
#define COH901318_RAW_BE_INT_STATUS2 (0x0034)
/*
* CX_CFG - Channel Configuration Registers 32bit (R/W)
*/
#define COH901318_CX_CFG (0x0100)
#define COH901318_CX_CFG_SPACING (0x04)
/* Channel enable activates tha dma job */
#define COH901318_CX_CFG_CH_ENABLE (0x00000001)
#define COH901318_CX_CFG_CH_DISABLE (0x00000000)
/* Request Mode */
#define COH901318_CX_CFG_RM_MASK (0x00000006)
#define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
#define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
#define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
#define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
#define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
/* Linked channel request field. RM must == 11 */
#define COH901318_CX_CFG_LCRF_SHIFT 3
#define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
#define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
/* Terminal Counter Interrupt Request Mask */
#define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
#define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
/* Bus Error interrupt Mask */
#define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
#define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
/*
* CX_STAT - Channel Status Registers 32bit (R/-)
*/
#define COH901318_CX_STAT (0x0200)
#define COH901318_CX_STAT_SPACING (0x04)
#define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
#define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
#define COH901318_CX_STAT_ACTIVE (0x00000002)
#define COH901318_CX_STAT_ENABLED (0x00000001)
/*
* CX_CTRL - Channel Control Registers 32bit (R/W)
*/
#define COH901318_CX_CTRL (0x0400)
#define COH901318_CX_CTRL_SPACING (0x10)
/* Transfer Count Enable */
#define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
#define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
/* Transfer Count Value 0 - 4095 */
#define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
/* Burst count */
#define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
#define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
/* Source bus size */
#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
/* Source address increment */
#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
/* Destination Bus Size */
#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
/* Destination address increment */
#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
/* Master Mode (Master2 is only connected to MSL) */
#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
/* Terminal Count flag to PER enable */
#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
/* Terminal Count flags to CPU enable */
#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
/* Hand shake to peripheral */
#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
/* DMA mode */
#define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
/* Primary Request Data Destination */
#define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
/*
* CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
*/
#define COH901318_CX_SRC_ADDR (0x0404)
#define COH901318_CX_SRC_ADDR_SPACING (0x10)
/*
* CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
*/
#define COH901318_CX_DST_ADDR (0x0408)
#define COH901318_CX_DST_ADDR_SPACING (0x10)
/*
* CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
*/
#define COH901318_CX_LNK_ADDR (0x040C)
#define COH901318_CX_LNK_ADDR_SPACING (0x10)
#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
#endif /* COH901318_H */
kernel/arch/arm/mach-u300/include/mach/debug-macro.S
+21
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/*
*
* arch-arm/mach-u300/include/mach/debug-macro.S
*
*
* Copyright (C) 2006-2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* Debugging macro include header.
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#include <mach/hardware.h>
.macro addruart, rp, rv, tmp
/* If we move the address using MMU, use this. */
ldr \rp, = U300_SLOW_PER_PHYS_BASE @ MMU off, physical address
ldr \rv, = U300_SLOW_PER_VIRT_BASE @ MMU on, virtual address
orr \rp, \rp, #0x00003000
orr \rv, \rv, #0x00003000
.endm
#include <asm/hardware/debug-pl01x.S>
kernel/arch/arm/mach-u300/include/mach/dma_channels.h
+69
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/*
*
* arch/arm/mach-u300/include/mach/dma_channels.h
*
*
* Copyright (C) 2007-2009 ST-Ericsson
* License terms: GNU General Public License (GPL) version 2
* Map file for the U300 dma driver.
* Author: Per Friden <per.friden@stericsson.com>
*/
#ifndef DMA_CHANNELS_H
#define DMA_CHANNELS_H
#define U300_DMA_MSL_TX_0 0
#define U300_DMA_MSL_TX_1 1
#define U300_DMA_MSL_TX_2 2
#define U300_DMA_MSL_TX_3 3
#define U300_DMA_MSL_TX_4 4
#define U300_DMA_MSL_TX_5 5
#define U300_DMA_MSL_TX_6 6
#define U300_DMA_MSL_RX_0 7
#define U300_DMA_MSL_RX_1 8
#define U300_DMA_MSL_RX_2 9
#define U300_DMA_MSL_RX_3 10
#define U300_DMA_MSL_RX_4 11
#define U300_DMA_MSL_RX_5 12
#define U300_DMA_MSL_RX_6 13
#define U300_DMA_MMCSD_RX_TX 14
#define U300_DMA_MSPRO_TX 15
#define U300_DMA_MSPRO_RX 16
#define U300_DMA_UART0_TX 17
#define U300_DMA_UART0_RX 18
#define U300_DMA_APEX_TX 19
#define U300_DMA_APEX_RX 20
#define U300_DMA_PCM_I2S0_TX 21
#define U300_DMA_PCM_I2S0_RX 22
#define U300_DMA_PCM_I2S1_TX 23
#define U300_DMA_PCM_I2S1_RX 24
#define U300_DMA_XGAM_CDI 25
#define U300_DMA_XGAM_PDI 26
#define U300_DMA_SPI_TX 27
#define U300_DMA_SPI_RX 28
#define U300_DMA_GENERAL_PURPOSE_0 29
#define U300_DMA_GENERAL_PURPOSE_1 30
#define U300_DMA_GENERAL_PURPOSE_2 31
#define U300_DMA_GENERAL_PURPOSE_3 32
#define U300_DMA_GENERAL_PURPOSE_4 33
#define U300_DMA_GENERAL_PURPOSE_5 34
#define U300_DMA_GENERAL_PURPOSE_6 35
#define U300_DMA_GENERAL_PURPOSE_7 36
#define U300_DMA_GENERAL_PURPOSE_8 37
#ifdef CONFIG_MACH_U300_BS335
#define U300_DMA_UART1_TX 38
#define U300_DMA_UART1_RX 39
#else
#define U300_DMA_GENERAL_PURPOSE_9 38
#define U300_DMA_GENERAL_PURPOSE_10 39
#endif
#ifdef CONFIG_MACH_U300_BS335
#define U300_DMA_DEVICE_CHANNELS 32
#else
#define U300_DMA_DEVICE_CHANNELS 30
#endif
#define U300_DMA_CHANNELS 40
#endif /* DMA_CHANNELS_H */
kernel/arch/arm/mach-u300/include/mach/gpio-u300.h
+37
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/*
* Copyright (C) 2007-2011 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* GPIO block resgister definitions and inline macros for
* U300 GPIO COH 901 335 or COH 901 571/3
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#ifndef __MACH_U300_GPIO_U300_H
#define __MACH_U300_GPIO_U300_H
/**
* enum u300_gpio_variant - the type of U300 GPIO employed
*/
enum u300_gpio_variant {
U300_GPIO_COH901335,
U300_GPIO_COH901571_3_BS335,
U300_GPIO_COH901571_3_BS365,
};
/**
* struct u300_gpio_platform - U300 GPIO platform data
* @variant: IP block variant
* @ports: number of GPIO block ports
* @gpio_base: first GPIO number for this block (use a free range)
* @gpio_irq_base: first GPIO IRQ number for this block (use a free range)
* @pinctrl_device: pin control device to spawn as child
*/
struct u300_gpio_platform {
enum u300_gpio_variant variant;
u8 ports;
int gpio_base;
int gpio_irq_base;
struct platform_device *pinctrl_device;
};
#endif /* __MACH_U300_GPIO_U300_H */
kernel/arch/arm/mach-u300/include/mach/gpio.h
+1
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@@ -0,0 +1 @@
/* empty */
kernel/arch/arm/mach-u300/include/mach/hardware.h
+5
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@@ -0,0 +1,5 @@
/*
* arch/arm/mach-u300/include/mach/hardware.h
*/
#include <asm/sizes.h>
#include <mach/u300-regs.h>
kernel/arch/arm/mach-u300/include/mach/irqs.h
+122
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/*
*
* arch/arm/mach-u300/include/mach/irqs.h
*
*
* Copyright (C) 2006-2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* IRQ channel definitions for the U300 platforms.
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#ifndef __MACH_IRQS_H
#define __MACH_IRQS_H
#define IRQ_U300_INTCON0_START 1
#define IRQ_U300_INTCON1_START 33
/* These are on INTCON0 - 30 lines */
#define IRQ_U300_IRQ0_EXT 1
#define IRQ_U300_IRQ1_EXT 2
#define IRQ_U300_DMA 3
#define IRQ_U300_VIDEO_ENC_0 4
#define IRQ_U300_VIDEO_ENC_1 5
#define IRQ_U300_AAIF_RX 6
#define IRQ_U300_AAIF_TX 7
#define IRQ_U300_AAIF_VGPIO 8
#define IRQ_U300_AAIF_WAKEUP 9
#define IRQ_U300_PCM_I2S0_FRAME 10
#define IRQ_U300_PCM_I2S0_FIFO 11
#define IRQ_U300_PCM_I2S1_FRAME 12
#define IRQ_U300_PCM_I2S1_FIFO 13
#define IRQ_U300_XGAM_GAMCON 14
#define IRQ_U300_XGAM_CDI 15
#define IRQ_U300_XGAM_CDICON 16
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
/* MMIACC not used on the DB3210 or DB3350 chips */
#define IRQ_U300_XGAM_MMIACC 17
#endif
#define IRQ_U300_XGAM_PDI 18
#define IRQ_U300_XGAM_PDICON 19
#define IRQ_U300_XGAM_GAMEACC 20
#define IRQ_U300_XGAM_MCIDCT 21
#define IRQ_U300_APEX 22
#define IRQ_U300_UART0 23
#define IRQ_U300_SPI 24
#define IRQ_U300_TIMER_APP_OS 25
#define IRQ_U300_TIMER_APP_DD 26
#define IRQ_U300_TIMER_APP_GP1 27
#define IRQ_U300_TIMER_APP_GP2 28
#define IRQ_U300_TIMER_OS 29
#define IRQ_U300_TIMER_MS 30
#define IRQ_U300_KEYPAD_KEYBF 31
#define IRQ_U300_KEYPAD_KEYBR 32
/* These are on INTCON1 - 32 lines */
#define IRQ_U300_GPIO_PORT0 33
#define IRQ_U300_GPIO_PORT1 34
#define IRQ_U300_GPIO_PORT2 35
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
defined(CONFIG_MACH_U300_BS335)
/* These are for DB3150, DB3200 and DB3350 */
#define IRQ_U300_WDOG 36
#define IRQ_U300_EVHIST 37
#define IRQ_U300_MSPRO 38
#define IRQ_U300_MMCSD_MCIINTR0 39
#define IRQ_U300_MMCSD_MCIINTR1 40
#define IRQ_U300_I2C0 41
#define IRQ_U300_I2C1 42
#define IRQ_U300_RTC 43
#define IRQ_U300_NFIF 44
#define IRQ_U300_NFIF2 45
#endif
/* DB3150 and DB3200 have only 45 IRQs */
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
#define U300_VIC_IRQS_END 46
#endif
/* The DB3350-specific interrupt lines */
#ifdef CONFIG_MACH_U300_BS335
#define IRQ_U300_ISP_F0 46
#define IRQ_U300_ISP_F1 47
#define IRQ_U300_ISP_F2 48
#define IRQ_U300_ISP_F3 49
#define IRQ_U300_ISP_F4 50
#define IRQ_U300_GPIO_PORT3 51
#define IRQ_U300_SYSCON_PLL_LOCK 52
#define IRQ_U300_UART1 53
#define IRQ_U300_GPIO_PORT4 54
#define IRQ_U300_GPIO_PORT5 55
#define IRQ_U300_GPIO_PORT6 56
#define U300_VIC_IRQS_END 57
#endif
/* The DB3210-specific interrupt lines */
#ifdef CONFIG_MACH_U300_BS365
#define IRQ_U300_GPIO_PORT3 36
#define IRQ_U300_GPIO_PORT4 37
#define IRQ_U300_WDOG 38
#define IRQ_U300_EVHIST 39
#define IRQ_U300_MSPRO 40
#define IRQ_U300_MMCSD_MCIINTR0 41
#define IRQ_U300_MMCSD_MCIINTR1 42
#define IRQ_U300_I2C0 43
#define IRQ_U300_I2C1 44
#define IRQ_U300_RTC 45
#define IRQ_U300_NFIF 46
#define IRQ_U300_NFIF2 47
#define IRQ_U300_SYSCON_PLL_LOCK 48
#define U300_VIC_IRQS_END 49
#endif
/* Maximum 8*7 GPIO lines */
#ifdef CONFIG_PINCTRL_COH901
#define IRQ_U300_GPIO_BASE (U300_VIC_IRQS_END)
#define IRQ_U300_GPIO_END (IRQ_U300_GPIO_BASE + 56)
#else
#define IRQ_U300_GPIO_END (U300_VIC_IRQS_END)
#endif
#define NR_IRQS (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
#endif
kernel/arch/arm/mach-u300/include/mach/platform.h
+20
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/*
*
* arch/arm/mach-u300/include/mach/platform.h
*
*
* Copyright (C) 2006-2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* Basic platform init and mapping functions.
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#ifndef __ASSEMBLY__
void u300_map_io(void);
void u300_init_irq(void);
void u300_init_devices(void);
void u300_restart(char, const char *);
extern struct sys_timer u300_timer;
#endif
kernel/arch/arm/mach-u300/include/mach/syscon.h
+614
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/*
*
* arch/arm/mach-u300/include/mach/syscon.h
*
*
* Copyright (C) 2008 ST-Ericsson AB
*
* Author: Rickard Andersson <rickard.andersson@stericsson.com>
*/
#ifndef __MACH_SYSCON_H
#define __MACH_SYSCON_H
/*
* All register defines for SYSCON registers that concerns individual
* block clocks and reset lines are registered here. This is because
* we don't want any other file to try to fool around with this stuff.
*/
/* APP side SYSCON registers */
/* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */
/* CLK Control Register 16bit (R/W) */
#define U300_SYSCON_CCR (0x0000)
#define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040)
#define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020)
#define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01)
#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00)
/* CLK Status Register 16bit (R/W) */
#define U300_SYSCON_CSR (0x0004)
#define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002)
#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001)
/* Reset lines for SLOW devices 16bit (R/W) */
#define U300_SYSCON_RSR (0x0014)
#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200)
#endif
#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100)
#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080)
#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040)
#define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020)
#define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010)
#define U300_SYSCON_RSR_EH_RESET_EN (0x0008)
#define U300_SYSCON_RSR_BTR_RESET_EN (0x0004)
#define U300_SYSCON_RSR_UART_RESET_EN (0x0002)
#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001)
/* Reset lines for FAST devices 16bit (R/W) */
#define U300_SYSCON_RFR (0x0018)
#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080)
#endif
#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040)
#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020)
#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010)
#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008)
#define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004)
#define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002)
#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001)
/* Reset lines for the rest of the peripherals 16bit (R/W) */
#define U300_SYSCON_RRR (0x001c)
#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000)
#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000)
#endif
#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000)
#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800)
#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100)
#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080)
#define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040)
#define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020)
#define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010)
#define U300_SYSCON_RRR_CPU_RESET_EN (0x0008)
#define U300_SYSCON_RRR_APEX_RESET_EN (0x0004)
#define U300_SYSCON_RRR_AHB_RESET_EN (0x0002)
#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001)
/* Clock enable for SLOW peripherals 16bit (R/W) */
#define U300_SYSCON_CESR (0x0020)
#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200)
#endif
#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100)
#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080)
#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040)
#define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010)
#define U300_SYSCON_CESR_EH_CLK_EN (0x0008)
#define U300_SYSCON_CESR_BTR_CLK_EN (0x0004)
#define U300_SYSCON_CESR_UART_CLK_EN (0x0002)
#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001)
/* Clock enable for FAST peripherals 16bit (R/W) */
#define U300_SYSCON_CEFR (0x0024)
#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200)
#endif
#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100)
#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080)
#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040)
#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020)
#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001)
/* Clock enable for the rest of the peripherals 16bit (R/W) */
#define U300_SYSCON_CERR (0x0028)
#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000)
#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000)
#endif
#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800)
#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400)
#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200)
#define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100)
#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080)
#define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040)
#define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020)
#define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010)
#define U300_SYSCON_CERR_CPU_CLK_EN (0x0008)
#define U300_SYSCON_CERR_APEX_CLK_EN (0x0004)
#define U300_SYSCON_CERR_AHB_CLK_EN (0x0002)
#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001)
/* Single block clock enable 16bit (-/W) */
#define U300_SYSCON_SBCER (0x002c)
#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009)
#endif
#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008)
#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007)
#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006)
#define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004)
#define U300_SYSCON_SBCER_EH_CLK_EN (0x0003)
#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002)
#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001)
#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000)
#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019)
#endif
#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018)
#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017)
#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016)
#define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015)
#define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014)
#define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013)
#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012)
#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011)
#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010)
#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D)
#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C)
#endif
#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B)
#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A)
#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029)
#define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028)
#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027)
#define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026)
#define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025)
#define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024)
#define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023)
#define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022)
#define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021)
#define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020)
/* Single block clock disable 16bit (-/W) */
#define U300_SYSCON_SBCDR (0x0030)
/* Same values as above for SBCER */
/* Clock force SLOW peripherals 16bit (R/W) */
#define U300_SYSCON_CFSR (0x003c)
#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200)
#endif
#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100)
#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080)
#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020)
#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010)
#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008)
#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004)
#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002)
#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001)
/* Clock force FAST peripherals 16bit (R/W) */
#define U300_SYSCON_CFFR (0x40)
/* Values not defined. Define if you want to use them. */
/* Clock force the rest of the peripherals 16bit (R/W) */
#define U300_SYSCON_CFRR (0x44)
#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000)
#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000)
#endif
#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800)
#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400)
#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200)
#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100)
#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080)
#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040)
#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020)
#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010)
#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008)
#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004)
#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002)
#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001)
/* PLL208 Frequency Control 16bit (R/W) */
#define U300_SYSCON_PFCR (0x48)
#define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F)
/* Power Management Control 16bit (R/W) */
#define U300_SYSCON_PMCR (0x50)
#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
/*
* All other clocking registers moved to clock.c!
*/
/* Reset Out 16bit (R/W) */
#define U300_SYSCON_RCR (0x6c)
#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001)
/* EMIF Slew Rate Control 16bit (R/W) */
#define U300_SYSCON_SRCLR (0x70)
#define U300_SYSCON_SRCLR_MASK (0x03FF)
#define U300_SYSCON_SRCLR_VALUE (0x03FF)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002)
#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001)
/* EMIF Clock Control Register 16bit (R/W) */
#define U300_SYSCON_ECCR (0x0078)
#define U300_SYSCON_ECCR_MASK (0x000F)
#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008)
#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004)
#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002)
#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001)
/* Step one for killing the applications system 16bit (-/W) */
#define U300_SYSCON_KA1R (0x0080)
#define U300_SYSCON_KA1R_MASK (0xFFFF)
#define U300_SYSCON_KA1R_VALUE (0xFFFF)
/* Step two for killing the application system 16bit (-/W) */
#define U300_SYSCON_KA2R (0x0084)
#define U300_SYSCON_KA2R_MASK (0xFFFF)
#define U300_SYSCON_KA2R_VALUE (0xFFFF)
/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
#define U300_SYSCON_MMF0R (0x90)
#define U300_SYSCON_MMF0R_MASK (0x00FF)
#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0)
#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F)
/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
#define U300_SYSCON_MMF1R (0x94)
#define U300_SYSCON_MMF1R_MASK (0x00FF)
#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0)
#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F)
/* AAIF control register 16 bit (R/W) */
#define U300_SYSCON_AAIFCR (0x98)
#define U300_SYSCON_AAIFCR_MASK (0x0003)
#define U300_SYSCON_AAIFCR_AASW_CTRL_MASK (0x0003)
#define U300_SYSCON_AAIFCR_AASW_CTRL_FUNCTIONAL (0x0000)
#define U300_SYSCON_AAIFCR_AASW_CTRL_MONITORING (0x0001)
#define U300_SYSCON_AAIFCR_AASW_CTRL_ACC_TO_EXT (0x0002)
#define U300_SYSCON_AAIFCR_AASW_CTRL_APP_TO_EXT (0x0003)
/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
#define U300_SYSCON_MMCR (0x9C)
#define U300_SYSCON_MMCR_MASK (0x0003)
#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002)
#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001)
/* Pull up/down control (R/W) */
#define U300_SYSCON_PUCR (0x104)
#define U300_SYSCON_PUCR_EMIF_1_WAIT_N_PU_ENABLE (0x0200)
#define U300_SYSCON_PUCR_EMIF_1_NFIF_READY_PU_ENABLE (0x0100)
#define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE (0x0080)
#define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE (0x0040)
#define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK (0x003F)
/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
#define U300_SYSCON_S0CCR (0x120)
#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF)
#define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000)
#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000)
#define U300_SYSCON_S0CCR_CLOCK_INV (0x0200)
#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0)
#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E)
#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001)
#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1)
#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1)
#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1)
#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1)
#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1)
#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1)
#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1)
#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1)
#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1)
/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
#define U300_SYSCON_S1CCR (0x124)
#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF)
#define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000)
#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000)
#define U300_SYSCON_S1CCR_CLOCK_INV (0x0200)
#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0)
#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E)
#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001)
#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1)
#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1)
#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1)
#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1)
#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1)
#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1)
#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1)
#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1)
#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1)
/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
#define U300_SYSCON_S2CCR (0x128)
#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF)
#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000)
#define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000)
#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000)
#define U300_SYSCON_S2CCR_CLOCK_INV (0x0200)
#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0)
#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E)
#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001)
#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1)
#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1)
#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1)
#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1)
#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1)
#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1)
#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1)
#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1)
#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1)
/* SYS_MISC_CONTROL, miscellaneous 16bit (R/W) */
#define U300_SYSCON_MCR (0x12c)
#define U300_SYSCON_MCR_FIELD_MASK (0x00FF)
#define U300_SYSCON_MCR_PMGEN_CR_4_MASK (0x00C0)
#define U300_SYSCON_MCR_PMGEN_CR_4_GPIO (0x0000)
#define U300_SYSCON_MCR_PMGEN_CR_4_SPI (0x0040)
#define U300_SYSCON_MCR_PMGEN_CR_4_AAIF (0x00C0)
#define U300_SYSCON_MCR_PMGEN_CR_2_MASK (0x0030)
#define U300_SYSCON_MCR_PMGEN_CR_2_GPIO (0x0000)
#define U300_SYSCON_MCR_PMGEN_CR_2_EMIF_1_STATIC (0x0010)
#define U300_SYSCON_MCR_PMGEN_CR_2_DSP (0x0020)
#define U300_SYSCON_MCR_PMGEN_CR_2_AAIF (0x0030)
#define U300_SYSCON_MCR_PMGEN_CR_0_MASK (0x000C)
#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M1 (0x0000)
#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M2 (0x0004)
#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M3 (0x0008)
#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_0_SDRAM (0x000C)
#define U300_SYSCON_MCR_PM1G_MODE_ENABLE (0x0002)
#define U300_SYSCON_MCR_PMTG5_MODE_ENABLE (0x0001)
/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
#define U300_SYSCON_PICR (0x0130)
#define U300_SYSCON_PICR_MASK (0x00FF)
#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080)
#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040)
#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020)
#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010)
#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008)
#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004)
#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002)
#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001)
/* SC_PLL_IRQ_STATUS 16 bit (R/-) */
#define U300_SYSCON_PISR (0x0134)
#define U300_SYSCON_PISR_MASK (0x000F)
#define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008)
#define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004)
#define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002)
#define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001)
/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
#define U300_SYSCON_PICLR (0x0138)
#define U300_SYSCON_PICLR_MASK (0x000F)
#define U300_SYSCON_PICLR_RWMASK (0x0000)
#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008)
#define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004)
#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002)
#define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001)
/* CAMIF_CONTROL 16 bit (-/W) */
#define U300_SYSCON_CICR (0x013C)
#define U300_SYSCON_CICR_MASK (0x0FFF)
#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_MASK (0x0F00)
#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT1 (0x0C00)
#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT0 (0x0300)
#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_MASK (0x00F0)
#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT1 (0x00C0)
#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT0 (0x0030)
#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_MASK (0x000F)
#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT1 (0x000C)
#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT0 (0x0003)
/* Clock activity observability register 0 */
#define U300_SYSCON_C0OAR (0x140)
#define U300_SYSCON_C0OAR_MASK (0xFFFF)
#define U300_SYSCON_C0OAR_VALUE (0xFFFF)
#define U300_SYSCON_C0OAR_BT_H_CLK (0x8000)
#define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000)
#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000)
#define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000)
#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800)
#define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400)
#define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200)
#define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100)
#define U300_SYSCON_C0OAR_APP_52_CLK (0x0080)
#define U300_SYSCON_C0OAR_APP_208_CLK (0x0040)
#define U300_SYSCON_C0OAR_APP_104_CLK (0x0020)
#define U300_SYSCON_C0OAR_APEX_CLK (0x0010)
#define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008)
#define U300_SYSCON_C0OAR_AHB_CLK (0x0004)
#define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002)
#define U300_SYSCON_C0OAR_AAIF_CLK (0x0001)
/* Clock activity observability register 1 */
#define U300_SYSCON_C1OAR (0x144)
#define U300_SYSCON_C1OAR_MASK (0x3FFE)
#define U300_SYSCON_C1OAR_VALUE (0x3FFE)
#define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000)
#define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000)
#define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800)
#define U300_SYSCON_C1OAR_MMC_CLK (0x0400)
#define U300_SYSCON_C1OAR_KP_P_CLK (0x0200)
#define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100)
#define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080)
#define U300_SYSCON_C1OAR_GPIO_CLK (0x0040)
#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020)
#define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010)
#define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008)
#define U300_SYSCON_C1OAR_PPM_CLK (0x0004)
#define U300_SYSCON_C1OAR_DMA_CLK (0x0002)
/* Clock activity observability register 2 */
#define U300_SYSCON_C2OAR (0x148)
#define U300_SYSCON_C2OAR_MASK (0x0FFF)
#define U300_SYSCON_C2OAR_VALUE (0x0FFF)
#define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800)
#define U300_SYSCON_C2OAR_XGAM_CLK (0x0400)
#define U300_SYSCON_C2OAR_VC_H_CLK (0x0200)
#define U300_SYSCON_C2OAR_VC_CLK (0x0100)
#define U300_SYSCON_C2OAR_UA_P_CLK (0x0080)
#define U300_SYSCON_C2OAR_TMR1_CLK (0x0040)
#define U300_SYSCON_C2OAR_TMR0_CLK (0x0020)
#define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010)
#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008)
#define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004)
#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002)
#define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001)
/* Chip ID register 16bit (R/-) */
#define U300_SYSCON_CIDR (0x400)
/* Video IRQ clear 16bit (R/W) */
#define U300_SYSCON_VICR (0x404)
#define U300_SYSCON_VICR_VIDEO1_IRQ_CLEAR_ENABLE (0x0002)
#define U300_SYSCON_VICR_VIDEO0_IRQ_CLEAR_ENABLE (0x0001)
/* SMCR */
#define U300_SYSCON_SMCR (0x4d0)
#define U300_SYSCON_SMCR_FIELD_MASK (0x000e)
#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008)
#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004)
#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002)
/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
#define U300_SYSCON_CSDR (0x4f0)
#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001)
/* PRINT_CONTROL Print Control 16bit (R/-) */
#define U300_SYSCON_PCR (0x4f8)
#define U300_SYSCON_PCR_SERV_IND (0x0001)
/* BOOT_CONTROL 16bit (R/-) */
#define U300_SYSCON_BCR (0x4fc)
#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400)
#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200)
#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC)
#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003)
/* CPU clock defines */
/**
* CPU high frequency in MHz
*/
#define SYSCON_CPU_CLOCK_HIGH 208
/**
* CPU medium frequency in MHz
*/
#define SYSCON_CPU_CLOCK_MEDIUM 52
/**
* CPU low frequency in MHz
*/
#define SYSCON_CPU_CLOCK_LOW 13
/* EMIF clock defines */
/**
* EMIF high frequency in MHz
*/
#define SYSCON_EMIF_CLOCK_HIGH 104
/**
* EMIF medium frequency in MHz
*/
#define SYSCON_EMIF_CLOCK_MEDIUM 52
/**
* EMIF low frequency in MHz
*/
#define SYSCON_EMIF_CLOCK_LOW 13
/* AHB clock defines */
/**
* AHB high frequency in MHz
*/
#define SYSCON_AHB_CLOCK_HIGH 52
/**
* AHB medium frequency in MHz
*/
#define SYSCON_AHB_CLOCK_MEDIUM 26
/**
* AHB low frequency in MHz
*/
#define SYSCON_AHB_CLOCK_LOW 7 /* i.e 13/2=6.5MHz */
enum syscon_busmaster {
SYSCON_BM_DMAC,
SYSCON_BM_XGAM,
SYSCON_BM_VIDEO_ENC
};
/* Selectr a resistor or a set of resistors */
enum syscon_pull_up_down {
SYSCON_PU_KEY_IN_EN,
SYSCON_PU_EMIF_1_8_BIT_EN,
SYSCON_PU_EMIF_1_16_BIT_EN,
SYSCON_PU_EMIF_1_NFIF_READY_EN,
SYSCON_PU_EMIF_1_NFIF_WAIT_N_EN,
};
/*
* Note that this array must match the order of the array "clk_reg"
* in syscon.c
*/
enum syscon_clk {
SYSCON_CLKCONTROL_SLOW_BRIDGE,
SYSCON_CLKCONTROL_UART,
SYSCON_CLKCONTROL_BTR,
SYSCON_CLKCONTROL_EH,
SYSCON_CLKCONTROL_GPIO,
SYSCON_CLKCONTROL_KEYPAD,
SYSCON_CLKCONTROL_APP_TIMER,
SYSCON_CLKCONTROL_ACC_TIMER,
SYSCON_CLKCONTROL_FAST_BRIDGE,
SYSCON_CLKCONTROL_I2C0,
SYSCON_CLKCONTROL_I2C1,
SYSCON_CLKCONTROL_I2S0,
SYSCON_CLKCONTROL_I2S1,
SYSCON_CLKCONTROL_MMC,
SYSCON_CLKCONTROL_SPI,
SYSCON_CLKCONTROL_I2S0_CORE,
SYSCON_CLKCONTROL_I2S1_CORE,
SYSCON_CLKCONTROL_UART1,
SYSCON_CLKCONTROL_AAIF,
SYSCON_CLKCONTROL_AHB,
SYSCON_CLKCONTROL_APEX,
SYSCON_CLKCONTROL_CPU,
SYSCON_CLKCONTROL_DMA,
SYSCON_CLKCONTROL_EMIF,
SYSCON_CLKCONTROL_NAND_IF,
SYSCON_CLKCONTROL_VIDEO_ENC,
SYSCON_CLKCONTROL_XGAM,
SYSCON_CLKCONTROL_SEMI,
SYSCON_CLKCONTROL_AHB_SUBSYS,
SYSCON_CLKCONTROL_MSPRO
};
enum syscon_sysclk_mode {
SYSCON_SYSCLK_DISABLED,
SYSCON_SYSCLK_M_CLK,
SYSCON_SYSCLK_ACC_FSM,
SYSCON_SYSCLK_PLL60_48,
SYSCON_SYSCLK_PLL60_60,
SYSCON_SYSCLK_ACC_PLL208,
SYSCON_SYSCLK_APP_PLL13,
SYSCON_SYSCLK_APP_FSM,
SYSCON_SYSCLK_RTC,
SYSCON_SYSCLK_APP_PLL208
};
enum syscon_sysclk_req {
SYSCON_SYSCLKREQ_DISABLED,
SYSCON_SYSCLKREQ_ACTIVE_LOW,
SYSCON_SYSCLKREQ_MONITOR
};
enum syscon_clk_mode {
SYSCON_CLKMODE_OFF,
SYSCON_CLKMODE_DEFAULT,
SYSCON_CLKMODE_LOW,
SYSCON_CLKMODE_MEDIUM,
SYSCON_CLKMODE_HIGH,
SYSCON_CLKMODE_PERMANENT,
SYSCON_CLKMODE_ON,
};
enum syscon_call_mode {
SYSCON_CLKCALL_NOWAIT,
SYSCON_CLKCALL_WAIT,
};
int syscon_dc_on(bool keep_power_on);
int syscon_set_busmaster_active_state(enum syscon_busmaster busmaster,
bool active);
bool syscon_get_busmaster_active_state(void);
int syscon_set_sleep_mask(enum syscon_clk,
bool sleep_ctrl);
int syscon_config_sysclk(u32 sysclk,
enum syscon_sysclk_mode sysclkmode,
bool inverse,
u32 divisor,
enum syscon_sysclk_req sysclkreq);
bool syscon_can_turn_off_semi_clock(void);
/* This function is restricted to core.c */
int syscon_request_normal_power(bool req);
/* This function is restricted to be used by platform_speed.c */
int syscon_speed_request(enum syscon_call_mode wait_mode,
enum syscon_clk_mode req_clk_mode);
#endif /* __MACH_SYSCON_H */
kernel/arch/arm/mach-u300/include/mach/timex.h
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/*
*
* arch/arm/mach-u300/include/mach/timex.h
*
*
* Copyright (C) 2006-2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* Platform tick rate definition.
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#ifndef __MACH_TIMEX_H
#define __MACH_TIMEX_H
/* This is for the APP OS GP1 (General Purpose 1) timer */
#define CLOCK_TICK_RATE 1000000
#endif
kernel/arch/arm/mach-u300/include/mach/u300-regs.h
+182
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/*
*
* arch/arm/mach-u300/include/mach/u300-regs.h
*
*
* Copyright (C) 2006-2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* Basic register address definitions in physical memory and
* some block definitions for core devices like the timer.
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#ifndef __MACH_U300_REGS_H
#define __MACH_U300_REGS_H
/*
* These are the large blocks of memory allocated for I/O.
* the defines are used for setting up the I/O memory mapping.
*/
/* NAND Flash CS0 */
#define U300_NAND_CS0_PHYS_BASE 0x80000000
/* NFIF */
#define U300_NAND_IF_PHYS_BASE 0x9f800000
/* ALE, CLE offset for FSMC NAND */
#define PLAT_NAND_CLE (1 << 16)
#define PLAT_NAND_ALE (1 << 17)
/* AHB Peripherals */
#define U300_AHB_PER_PHYS_BASE 0xa0000000
#define U300_AHB_PER_VIRT_BASE 0xff010000
/* FAST Peripherals */
#define U300_FAST_PER_PHYS_BASE 0xc0000000
#define U300_FAST_PER_VIRT_BASE 0xff020000
/* SLOW Peripherals */
#define U300_SLOW_PER_PHYS_BASE 0xc0010000
#define U300_SLOW_PER_VIRT_BASE 0xff000000
/* Boot ROM */
#define U300_BOOTROM_PHYS_BASE 0xffff0000
#define U300_BOOTROM_VIRT_BASE 0xffff0000
/* SEMI config base */
#ifdef CONFIG_MACH_U300_BS335
#define U300_SEMI_CONFIG_BASE 0x2FFE0000
#else
#define U300_SEMI_CONFIG_BASE 0x30000000
#endif
/*
* AHB peripherals
*/
/* AHB Peripherals Bridge Controller */
#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000)
/* Vectored Interrupt Controller 0, servicing 32 interrupts */
#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000)
#define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
/* Vectored Interrupt Controller 1, servicing 32 interrupts */
#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000)
#define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
/* Memory Stick Pro (MSPRO) controller */
#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000)
/* EMIF Configuration Area */
#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000)
/*
* FAST peripherals
*/
/* FAST bridge control */
#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000)
/* MMC/SD controller */
#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000)
/* PCM I2S0 controller */
#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000)
/* PCM I2S1 controller */
#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000)
/* I2C0 controller */
#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000)
/* I2C1 controller */
#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000)
/* SPI controller */
#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
#ifdef CONFIG_MACH_U300_BS335
/* Fast UART1 on U335 only */
#define U300_UART1_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
#endif
/*
* SLOW peripherals
*/
/* SLOW bridge control */
#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE)
/* SYSCON */
#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000)
#define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
/* Watchdog */
#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000)
/* UART0 */
#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000)
/* APP side special timer */
#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000)
#define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
/* Keypad */
#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000)
/* GPIO */
#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000)
/* RTC */
#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
/* Bus tracer */
#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000)
/* Event handler (hardware queue) */
#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000)
/* Genric Timer */
#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000)
/* PPM */
#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000)
/*
* REST peripherals
*/
/* ISP (image signal processor) is only available in U335 */
#ifdef CONFIG_MACH_U300_BS335
#define U300_ISP_BASE (0xA0008000)
#endif
/* DMA Controller base */
#define U300_DMAC_BASE (0xC0020000)
/* MSL Base */
#define U300_MSL_BASE (0xc0022000)
/* APEX Base */
#define U300_APEX_BASE (0xc0030000)
/* Video Encoder Base */
#ifdef CONFIG_MACH_U300_BS335
#define U300_VIDEOENC_BASE (0xc0080000)
#else
#define U300_VIDEOENC_BASE (0xc0040000)
#endif
/* XGAM Base */
#define U300_XGAM_BASE (0xd0000000)
/*
* Virtual accessor macros for static devices
*/
#endif
kernel/arch/arm/mach-u300/include/mach/uncompress.h
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/*
* arch/arm/mach-u300/include/mach/uncompress.h
*
* Copyright (C) 2003 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define AMBA_UART_DR (*(volatile unsigned char *)0xc0013000)
#define AMBA_UART_LCRH (*(volatile unsigned char *)0xc001302C)
#define AMBA_UART_CR (*(volatile unsigned char *)0xc0013030)
#define AMBA_UART_FR (*(volatile unsigned char *)0xc0013018)
/*
* This does not append a newline
*/
static inline void putc(int c)
{
while (AMBA_UART_FR & (1 << 5))
barrier();
AMBA_UART_DR = c;
}
static inline void flush(void)
{
while (AMBA_UART_FR & (1 << 3))
barrier();
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()
kernel/arch/arm/mach-u300/regulator.c
+88
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/*
* arch/arm/mach-u300/regulator.c
*
* Copyright (C) 2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* Handle board-bound regulators and board power not related
* to any devices.
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#include <linux/device.h>
#include <linux/signal.h>
#include <linux/err.h>
#include <linux/regulator/consumer.h>
/* Those are just for writing in syscon */
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/syscon.h>
/*
* Regulators that power the board and chip and which are
* not copuled to specific drivers are hogged in these
* instances.
*/
static struct regulator *main_power_15;
/*
* This function is used from pm.h to shut down the system by
* resetting all regulators in turn and then disable regulator
* LDO D (main power).
*/
void u300_pm_poweroff(void)
{
sigset_t old, all;
sigfillset(&all);
if (!sigprocmask(SIG_BLOCK, &all, &old)) {
/* Disable LDO D to shut down the system */
if (main_power_15)
regulator_disable(main_power_15);
else
pr_err("regulator not available to shut down system\n");
(void) sigprocmask(SIG_SETMASK, &old, NULL);
}
return;
}
/*
* Hog the regulators needed to power up the board.
*/
static int __init u300_init_boardpower(void)
{
int err;
u32 val;
pr_info("U300: setting up board power\n");
main_power_15 = regulator_get(NULL, "vana15");
if (IS_ERR(main_power_15)) {
pr_err("could not get vana15");
return PTR_ERR(main_power_15);
}
err = regulator_enable(main_power_15);
if (err) {
pr_err("could not enable vana15\n");
return err;
}
/*
* On U300 a special system controller register pulls up the DC
* until the vana15 (LDO D) regulator comes up. At this point, all
* regulators are set and we do not need power control via
* DC ON anymore. This function will likely be moved whenever
* the rest of the U300 power management is implemented.
*/
pr_info("U300: disable system controller pull-up\n");
val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR);
val &= ~U300_SYSCON_PMCR_DCON_ENABLE;
writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
/* Register globally exported PM poweroff hook */
pm_power_off = u300_pm_poweroff;
return 0;
}
/*
* So at module init time we hog the regulator!
*/
module_init(u300_init_boardpower);
kernel/arch/arm/mach-u300/spi.c
+103
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/*
* arch/arm/mach-u300/spi.c
*
* Copyright (C) 2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
*
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/spi/spi.h>
#include <linux/amba/pl022.h>
#include <linux/err.h>
#include <mach/coh901318.h>
#include <mach/dma_channels.h>
/*
* The following is for the actual devices on the SSP/SPI bus
*/
#ifdef CONFIG_MACH_U300_SPIDUMMY
static void select_dummy_chip(u32 chipselect)
{
pr_debug("CORE: %s called with CS=0x%x (%s)\n",
__func__,
chipselect,
chipselect ? "unselect chip" : "select chip");
/*
* Here you would write the chip select value to the GPIO pins if
* this was a real chip (but this is a loopback dummy).
*/
}
struct pl022_config_chip dummy_chip_info = {
/* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */
.com_mode = DMA_TRANSFER,
.iface = SSP_INTERFACE_MOTOROLA_SPI,
/* We can only act as master but SSP_SLAVE is possible in theory */
.hierarchy = SSP_MASTER,
/* 0 = drive TX even as slave, 1 = do not drive TX as slave */
.slave_tx_disable = 0,
.rx_lev_trig = SSP_RX_4_OR_MORE_ELEM,
.tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC,
.ctrl_len = SSP_BITS_12,
.wait_state = SSP_MWIRE_WAIT_ZERO,
.duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
/*
* This is where you insert a call to a function to enable CS
* (usually GPIO) for a certain chip.
*/
.cs_control = select_dummy_chip,
};
#endif
static struct spi_board_info u300_spi_devices[] = {
#ifdef CONFIG_MACH_U300_SPIDUMMY
{
/* A dummy chip used for loopback tests */
.modalias = "spi-dummy",
/* Really dummy, pass in additional chip config here */
.platform_data = NULL,
/* This defines how the controller shall handle the device */
.controller_data = &dummy_chip_info,
/* .irq - no external IRQ routed from this device */
.max_speed_hz = 1000000,
.bus_num = 0, /* Only one bus on this chip */
.chip_select = 0,
/* Means SPI_CS_HIGH, change if e.g low CS */
.mode = SPI_MODE_1 | SPI_LOOP,
},
#endif
};
static struct pl022_ssp_controller ssp_platform_data = {
/* If you have several SPI buses this varies, we have only bus 0 */
.bus_id = 0,
/*
* On the APP CPU GPIO 4, 5 and 6 are connected as generic
* chip selects for SPI. (Same on U330, U335 and U365.)
* TODO: make sure the GPIO driver can select these properly
* and do padmuxing accordingly too.
*/
.num_chipselect = 3,
#ifdef CONFIG_COH901318
.enable_dma = 1,
.dma_filter = coh901318_filter_id,
.dma_rx_param = (void *) U300_DMA_SPI_RX,
.dma_tx_param = (void *) U300_DMA_SPI_TX,
#else
.enable_dma = 0,
#endif
};
void __init u300_spi_init(struct amba_device *adev)
{
adev->dev.platform_data = &ssp_platform_data;
}
void __init u300_spi_register_board_devices(void)
{
/* Register any SPI devices */
spi_register_board_info(u300_spi_devices, ARRAY_SIZE(u300_spi_devices));
}
kernel/arch/arm/mach-u300/spi.h
+26
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/*
* arch/arm/mach-u300/spi.h
*
* Copyright (C) 2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
*
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#ifndef SPI_H
#define SPI_H
#include <linux/amba/bus.h>
#ifdef CONFIG_SPI_PL022
void __init u300_spi_init(struct amba_device *adev);
void __init u300_spi_register_board_devices(void);
#else
/* Compile out SPI support if PL022 is not selected */
static inline void __init u300_spi_init(struct amba_device *adev)
{
}
static inline void __init u300_spi_register_board_devices(void)
{
}
#endif
#endif
kernel/arch/arm/mach-u300/timer.c
+420
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/*
*
* arch/arm/mach-u300/timer.c
*
*
* Copyright (C) 2007-2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* Timer COH 901 328, runs the OS timer interrupt.
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/timex.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/types.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <mach/hardware.h>
/* Generic stuff */
#include <asm/sched_clock.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
/*
* APP side special timer registers
* This timer contains four timers which can fire an interrupt each.
* OS (operating system) timer @ 32768 Hz
* DD (device driver) timer @ 1 kHz
* GP1 (general purpose 1) timer @ 1MHz
* GP2 (general purpose 2) timer @ 1MHz
*/
/* Reset OS Timer 32bit (-/W) */
#define U300_TIMER_APP_ROST (0x0000)
#define U300_TIMER_APP_ROST_TIMER_RESET (0x00000000)
/* Enable OS Timer 32bit (-/W) */
#define U300_TIMER_APP_EOST (0x0004)
#define U300_TIMER_APP_EOST_TIMER_ENABLE (0x00000000)
/* Disable OS Timer 32bit (-/W) */
#define U300_TIMER_APP_DOST (0x0008)
#define U300_TIMER_APP_DOST_TIMER_DISABLE (0x00000000)
/* OS Timer Mode Register 32bit (-/W) */
#define U300_TIMER_APP_SOSTM (0x000c)
#define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS (0x00000000)
#define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT (0x00000001)
/* OS Timer Status Register 32bit (R/-) */
#define U300_TIMER_APP_OSTS (0x0010)
#define U300_TIMER_APP_OSTS_TIMER_STATE_MASK (0x0000000F)
#define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE (0x00000001)
#define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE (0x00000002)
#define U300_TIMER_APP_OSTS_ENABLE_IND (0x00000010)
#define U300_TIMER_APP_OSTS_MODE_MASK (0x00000020)
#define U300_TIMER_APP_OSTS_MODE_CONTINUOUS (0x00000000)
#define U300_TIMER_APP_OSTS_MODE_ONE_SHOT (0x00000020)
#define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND (0x00000040)
#define U300_TIMER_APP_OSTS_IRQ_PENDING_IND (0x00000080)
/* OS Timer Current Count Register 32bit (R/-) */
#define U300_TIMER_APP_OSTCC (0x0014)
/* OS Timer Terminal Count Register 32bit (R/W) */
#define U300_TIMER_APP_OSTTC (0x0018)
/* OS Timer Interrupt Enable Register 32bit (-/W) */
#define U300_TIMER_APP_OSTIE (0x001c)
#define U300_TIMER_APP_OSTIE_IRQ_DISABLE (0x00000000)
#define U300_TIMER_APP_OSTIE_IRQ_ENABLE (0x00000001)
/* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
#define U300_TIMER_APP_OSTIA (0x0020)
#define U300_TIMER_APP_OSTIA_IRQ_ACK (0x00000080)
/* Reset DD Timer 32bit (-/W) */
#define U300_TIMER_APP_RDDT (0x0040)
#define U300_TIMER_APP_RDDT_TIMER_RESET (0x00000000)
/* Enable DD Timer 32bit (-/W) */
#define U300_TIMER_APP_EDDT (0x0044)
#define U300_TIMER_APP_EDDT_TIMER_ENABLE (0x00000000)
/* Disable DD Timer 32bit (-/W) */
#define U300_TIMER_APP_DDDT (0x0048)
#define U300_TIMER_APP_DDDT_TIMER_DISABLE (0x00000000)
/* DD Timer Mode Register 32bit (-/W) */
#define U300_TIMER_APP_SDDTM (0x004c)
#define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS (0x00000000)
#define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT (0x00000001)
/* DD Timer Status Register 32bit (R/-) */
#define U300_TIMER_APP_DDTS (0x0050)
#define U300_TIMER_APP_DDTS_TIMER_STATE_MASK (0x0000000F)
#define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE (0x00000001)
#define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE (0x00000002)
#define U300_TIMER_APP_DDTS_ENABLE_IND (0x00000010)
#define U300_TIMER_APP_DDTS_MODE_MASK (0x00000020)
#define U300_TIMER_APP_DDTS_MODE_CONTINUOUS (0x00000000)
#define U300_TIMER_APP_DDTS_MODE_ONE_SHOT (0x00000020)
#define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND (0x00000040)
#define U300_TIMER_APP_DDTS_IRQ_PENDING_IND (0x00000080)
/* DD Timer Current Count Register 32bit (R/-) */
#define U300_TIMER_APP_DDTCC (0x0054)
/* DD Timer Terminal Count Register 32bit (R/W) */
#define U300_TIMER_APP_DDTTC (0x0058)
/* DD Timer Interrupt Enable Register 32bit (-/W) */
#define U300_TIMER_APP_DDTIE (0x005c)
#define U300_TIMER_APP_DDTIE_IRQ_DISABLE (0x00000000)
#define U300_TIMER_APP_DDTIE_IRQ_ENABLE (0x00000001)
/* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
#define U300_TIMER_APP_DDTIA (0x0060)
#define U300_TIMER_APP_DDTIA_IRQ_ACK (0x00000080)
/* Reset GP1 Timer 32bit (-/W) */
#define U300_TIMER_APP_RGPT1 (0x0080)
#define U300_TIMER_APP_RGPT1_TIMER_RESET (0x00000000)
/* Enable GP1 Timer 32bit (-/W) */
#define U300_TIMER_APP_EGPT1 (0x0084)
#define U300_TIMER_APP_EGPT1_TIMER_ENABLE (0x00000000)
/* Disable GP1 Timer 32bit (-/W) */
#define U300_TIMER_APP_DGPT1 (0x0088)
#define U300_TIMER_APP_DGPT1_TIMER_DISABLE (0x00000000)
/* GP1 Timer Mode Register 32bit (-/W) */
#define U300_TIMER_APP_SGPT1M (0x008c)
#define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS (0x00000000)
#define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT (0x00000001)
/* GP1 Timer Status Register 32bit (R/-) */
#define U300_TIMER_APP_GPT1S (0x0090)
#define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK (0x0000000F)
#define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE (0x00000001)
#define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE (0x00000002)
#define U300_TIMER_APP_GPT1S_ENABLE_IND (0x00000010)
#define U300_TIMER_APP_GPT1S_MODE_MASK (0x00000020)
#define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS (0x00000000)
#define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT (0x00000020)
#define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND (0x00000040)
#define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND (0x00000080)
/* GP1 Timer Current Count Register 32bit (R/-) */
#define U300_TIMER_APP_GPT1CC (0x0094)
/* GP1 Timer Terminal Count Register 32bit (R/W) */
#define U300_TIMER_APP_GPT1TC (0x0098)
/* GP1 Timer Interrupt Enable Register 32bit (-/W) */
#define U300_TIMER_APP_GPT1IE (0x009c)
#define U300_TIMER_APP_GPT1IE_IRQ_DISABLE (0x00000000)
#define U300_TIMER_APP_GPT1IE_IRQ_ENABLE (0x00000001)
/* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
#define U300_TIMER_APP_GPT1IA (0x00a0)
#define U300_TIMER_APP_GPT1IA_IRQ_ACK (0x00000080)
/* Reset GP2 Timer 32bit (-/W) */
#define U300_TIMER_APP_RGPT2 (0x00c0)
#define U300_TIMER_APP_RGPT2_TIMER_RESET (0x00000000)
/* Enable GP2 Timer 32bit (-/W) */
#define U300_TIMER_APP_EGPT2 (0x00c4)
#define U300_TIMER_APP_EGPT2_TIMER_ENABLE (0x00000000)
/* Disable GP2 Timer 32bit (-/W) */
#define U300_TIMER_APP_DGPT2 (0x00c8)
#define U300_TIMER_APP_DGPT2_TIMER_DISABLE (0x00000000)
/* GP2 Timer Mode Register 32bit (-/W) */
#define U300_TIMER_APP_SGPT2M (0x00cc)
#define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS (0x00000000)
#define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT (0x00000001)
/* GP2 Timer Status Register 32bit (R/-) */
#define U300_TIMER_APP_GPT2S (0x00d0)
#define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK (0x0000000F)
#define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE (0x00000001)
#define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE (0x00000002)
#define U300_TIMER_APP_GPT2S_ENABLE_IND (0x00000010)
#define U300_TIMER_APP_GPT2S_MODE_MASK (0x00000020)
#define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS (0x00000000)
#define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT (0x00000020)
#define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND (0x00000040)
#define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND (0x00000080)
/* GP2 Timer Current Count Register 32bit (R/-) */
#define U300_TIMER_APP_GPT2CC (0x00d4)
/* GP2 Timer Terminal Count Register 32bit (R/W) */
#define U300_TIMER_APP_GPT2TC (0x00d8)
/* GP2 Timer Interrupt Enable Register 32bit (-/W) */
#define U300_TIMER_APP_GPT2IE (0x00dc)
#define U300_TIMER_APP_GPT2IE_IRQ_DISABLE (0x00000000)
#define U300_TIMER_APP_GPT2IE_IRQ_ENABLE (0x00000001)
/* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
#define U300_TIMER_APP_GPT2IA (0x00e0)
#define U300_TIMER_APP_GPT2IA_IRQ_ACK (0x00000080)
/* Clock request control register - all four timers */
#define U300_TIMER_APP_CRC (0x100)
#define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE (0x00000001)
#define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
#define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
/*
* The u300_set_mode() function is always called first, if we
* have oneshot timer active, the oneshot scheduling function
* u300_set_next_event() is called immediately after.
*/
static void u300_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
/* Disable interrupts on GPT1 */
writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
/* Disable GP1 while we're reprogramming it. */
writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
/*
* Set the periodic mode to a certain number of ticks per
* jiffy.
*/
writel(TICKS_PER_JIFFY,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
/*
* Set continuous mode, so the timer keeps triggering
* interrupts.
*/
writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
/* Enable timer interrupts */
writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
/* Then enable the OS timer again */
writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
break;
case CLOCK_EVT_MODE_ONESHOT:
/* Just break; here? */
/*
* The actual event will be programmed by the next event hook,
* so we just set a dummy value somewhere at the end of the
* universe here.
*/
/* Disable interrupts on GPT1 */
writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
/* Disable GP1 while we're reprogramming it. */
writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
/*
* Expire far in the future, u300_set_next_event() will be
* called soon...
*/
writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
/* We run one shot per tick here! */
writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
/* Enable interrupts for this timer */
writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
/* Enable timer */
writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
/* Disable interrupts on GP1 */
writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
/* Disable GP1 */
writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
break;
case CLOCK_EVT_MODE_RESUME:
/* Ignore this call */
break;
}
}
/*
* The app timer in one shot mode obviously has to be reprogrammed
* in EXACTLY this sequence to work properly. Do NOT try to e.g. replace
* the interrupt disable + timer disable commands with a reset command,
* it will fail miserably. Apparently (and I found this the hard way)
* the timer is very sensitive to the instruction order, though you don't
* get that impression from the data sheet.
*/
static int u300_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
/* Disable interrupts on GPT1 */
writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
/* Disable GP1 while we're reprogramming it. */
writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
/* Reset the General Purpose timer 1. */
writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
/* IRQ in n * cycles */
writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
/*
* We run one shot per tick here! (This is necessary to reconfigure,
* the timer will tilt if you don't!)
*/
writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
/* Enable timer interrupts */
writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
/* Then enable the OS timer again */
writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
return 0;
}
/* Use general purpose timer 1 as clock event */
static struct clock_event_device clockevent_u300_1mhz = {
.name = "GPT1",
.rating = 300, /* Reasonably fast and accurate clock event */
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = u300_set_next_event,
.set_mode = u300_set_mode,
};
/* Clock event timer interrupt handler */
static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = &clockevent_u300_1mhz;
/* ACK/Clear timer IRQ for the APP GPT1 Timer */
writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA);
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct irqaction u300_timer_irq = {
.name = "U300 Timer Tick",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.handler = u300_timer_interrupt,
};
/*
* Override the global weak sched_clock symbol with this
* local implementation which uses the clocksource to get some
* better resolution when scheduling the kernel. We accept that
* this wraps around for now, since it is just a relative time
* stamp. (Inspired by OMAP implementation.)
*/
static u32 notrace u300_read_sched_clock(void)
{
return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
}
/*
* This sets up the system timers, clock source and clock event.
*/
static void __init u300_timer_init(void)
{
struct clk *clk;
unsigned long rate;
/* Clock the interrupt controller */
clk = clk_get_sys("apptimer", NULL);
BUG_ON(IS_ERR(clk));
clk_enable(clk);
rate = clk_get_rate(clk);
setup_sched_clock(u300_read_sched_clock, 32, rate);
/*
* Disable the "OS" and "DD" timers - these are designed for Symbian!
* Example usage in cnh1601578 cpu subsystem pd_timer_app.c
*/
writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC);
writel(U300_TIMER_APP_ROST_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST);
writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST);
writel(U300_TIMER_APP_RDDT_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT);
writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT);
/* Reset the General Purpose timer 1. */
writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
/* Set up the IRQ handler */
setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq);
/* Reset the General Purpose timer 2 */
writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2);
/* Set this timer to run around forever */
writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC);
/* Set continuous mode so it wraps around */
writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M);
/* Disable timer interrupts */
writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE);
/* Then enable the GP2 timer to use as a free running us counter */
writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
/* Use general purpose timer 2 as clock source */
if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC,
"GPT2", rate, 300, 32, clocksource_mmio_readl_up))
pr_err("timer: failed to initialize U300 clock source\n");
/* Configure and register the clockevent */
clockevents_config_and_register(&clockevent_u300_1mhz, rate,
1, 0xffffffff);
/*
* TODO: init and register the rest of the timers too, they can be
* used by hrtimers!
*/
}
/*
* Very simple system timer that only register the clock event and
* clock source.
*/
struct sys_timer u300_timer = {
.init = u300_timer_init,
};
kernel/arch/arm/mach-u300/u300-gpio.h
+114
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/*
* Individual pin assignments for the B26/S26. Notice that the
* actual usage of these pins depends on the PAD MUX settings, that
* is why the same number can potentially appear several times.
* In the reference design each pin is only used for one purpose.
* These were determined by inspecting the B26/S26 schematic:
* 2/1911-ROA 128 1603
*/
#ifdef CONFIG_MACH_U300_BS2X
#define U300_GPIO_PIN_UART_RX 0
#define U300_GPIO_PIN_UART_TX 1
#define U300_GPIO_PIN_GPIO02 2 /* Unrouted */
#define U300_GPIO_PIN_GPIO03 3 /* Unrouted */
#define U300_GPIO_PIN_CAM_SLEEP 4
#define U300_GPIO_PIN_CAM_REG_EN 5
#define U300_GPIO_PIN_GPIO06 6 /* Unrouted */
#define U300_GPIO_PIN_GPIO07 7 /* Unrouted */
#define U300_GPIO_PIN_GPIO08 8 /* Service point SP2321 */
#define U300_GPIO_PIN_GPIO09 9 /* Service point SP2322 */
#define U300_GPIO_PIN_PHFSENSE 10 /* Headphone jack sensing */
#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */
#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */
#define U300_GPIO_PIN_FLIPSENSE 13 /* Mechanical flip sensing */
#define U300_GPIO_PIN_GPIO14 14 /* DSP JTAG Port RTCK */
#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */
#define U300_GPIO_PIN_GPIO16 16 /* Unrouted */
#define U300_GPIO_PIN_GPIO17 17 /* Unrouted */
#define U300_GPIO_PIN_GPIO18 18 /* Unrouted */
#define U300_GPIO_PIN_GPIO19 19 /* Unrouted */
#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */
#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */
#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */
#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */
#endif
/*
* Individual pin assignments for the B330/S330 and B365/S365.
* Notice that the actual usage of these pins depends on the
* PAD MUX settings, that is why the same number can potentially
* appear several times. In the reference design each pin is only
* used for one purpose. These were determined by inspecting the
* S365 schematic.
*/
#if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \
defined(CONFIG_MACH_U300_BS335)
#define U300_GPIO_PIN_UART_RX 0
#define U300_GPIO_PIN_UART_TX 1
#define U300_GPIO_PIN_UART_CTS 2
#define U300_GPIO_PIN_UART_RTS 3
#define U300_GPIO_PIN_CAM_MAIN_STANDBY 4 /* Camera MAIN standby */
#define U300_GPIO_PIN_GPIO05 5 /* Unrouted */
#define U300_GPIO_PIN_MS_CD 6 /* Memory Stick Card insertion */
#define U300_GPIO_PIN_GPIO07 7 /* Test point TP2430 */
#define U300_GPIO_PIN_GPIO08 8 /* Test point TP2437 */
#define U300_GPIO_PIN_GPIO09 9 /* Test point TP2431 */
#define U300_GPIO_PIN_GPIO10 10 /* Test point TP2432 */
#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */
#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */
#define U300_GPIO_PIN_CAM_SUB_STANDBY 13 /* Camera SUB standby */
#define U300_GPIO_PIN_GPIO14 14 /* Test point TP2436 */
#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */
#define U300_GPIO_PIN_GPIO16 16 /* Test point TP2438 */
#define U300_GPIO_PIN_PHFSENSE 17 /* Headphone jack sensing */
#define U300_GPIO_PIN_GPIO18 18 /* Test point TP2439 */
#define U300_GPIO_PIN_GPIO19 19 /* Routed somewhere */
#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */
#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */
#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */
#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */
#define U300_GPIO_PIN_GPIO24 24 /* Unrouted */
#define U300_GPIO_PIN_GPIO25 25 /* Unrouted */
#define U300_GPIO_PIN_GPIO26 26 /* Unrouted */
#define U300_GPIO_PIN_GPIO27 27 /* Unrouted */
#define U300_GPIO_PIN_GPIO28 28 /* Unrouted */
#define U300_GPIO_PIN_GPIO29 29 /* Unrouted */
#define U300_GPIO_PIN_GPIO30 30 /* Unrouted */
#define U300_GPIO_PIN_GPIO31 31 /* Unrouted */
#define U300_GPIO_PIN_GPIO32 32 /* Unrouted */
#define U300_GPIO_PIN_GPIO33 33 /* Unrouted */
#define U300_GPIO_PIN_GPIO34 34 /* Unrouted */
#define U300_GPIO_PIN_GPIO35 35 /* Unrouted */
#define U300_GPIO_PIN_GPIO36 36 /* Unrouted */
#define U300_GPIO_PIN_GPIO37 37 /* Unrouted */
#define U300_GPIO_PIN_GPIO38 38 /* Unrouted */
#define U300_GPIO_PIN_GPIO39 39 /* Unrouted */
#ifdef CONFIG_MACH_U300_BS335
#define U300_GPIO_PIN_GPIO40 40 /* Unrouted */
#define U300_GPIO_PIN_GPIO41 41 /* Unrouted */
#define U300_GPIO_PIN_GPIO42 42 /* Unrouted */
#define U300_GPIO_PIN_GPIO43 43 /* Unrouted */
#define U300_GPIO_PIN_GPIO44 44 /* Unrouted */
#define U300_GPIO_PIN_GPIO45 45 /* Unrouted */
#define U300_GPIO_PIN_GPIO46 46 /* Unrouted */
#define U300_GPIO_PIN_GPIO47 47 /* Unrouted */
#define U300_GPIO_PIN_GPIO48 48 /* Unrouted */
#define U300_GPIO_PIN_GPIO49 49 /* Unrouted */
#define U300_GPIO_PIN_GPIO50 50 /* Unrouted */
#define U300_GPIO_PIN_GPIO51 51 /* Unrouted */
#define U300_GPIO_PIN_GPIO52 52 /* Unrouted */
#define U300_GPIO_PIN_GPIO53 53 /* Unrouted */
#define U300_GPIO_PIN_GPIO54 54 /* Unrouted */
#define U300_GPIO_PIN_GPIO55 55 /* Unrouted */
#endif
#endif
kernel/arch/arm/mach-u300/u300.c
+57
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@@ -0,0 +1,57 @@
/*
*
* arch/arm/mach-u300/u300.c
*
*
* Copyright (C) 2006-2009 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* Platform machine definition.
* Author: Linus Walleij <linus.walleij@stericsson.com>
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/memblock.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/platform.h>
#include <asm/hardware/vic.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/memory.h>
static void __init u300_init_machine(void)
{
u300_init_devices();
}
#ifdef CONFIG_MACH_U300_BS2X
#define MACH_U300_STRING "Ericsson AB U300 S25/S26/B25/B26 Prototype Board"
#endif
#ifdef CONFIG_MACH_U300_BS330
#define MACH_U300_STRING "Ericsson AB U330 S330/B330 Prototype Board"
#endif
#ifdef CONFIG_MACH_U300_BS335
#define MACH_U300_STRING "Ericsson AB U335 S335/B335 Prototype Board"
#endif
#ifdef CONFIG_MACH_U300_BS365
#define MACH_U300_STRING "Ericsson AB U365 S365/B365 Prototype Board"
#endif
MACHINE_START(U300, MACH_U300_STRING)
/* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
.atag_offset = 0x100,
.map_io = u300_map_io,
.init_irq = u300_init_irq,
.handle_irq = vic_handle_irq,
.timer = &u300_timer,
.init_machine = u300_init_machine,
.restart = u300_restart,
MACHINE_END