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2024-09-09 08:52:07 +00:00
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33
kernel/arch/arm/mach-s5p64x0/include/mach/debug-macro.S Normal file
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/* linux/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* pull in the relevant register and map files. */
#include <plat/map-base.h>
#include <plat/map-s5p.h>
#include <plat/regs-serial.h>
.macro addruart, rp, rv, tmp
mov \rp, #0xE0000000
orr \rp, \rp, #0x00100000
ldr \rp, [\rp, #0x118 ]
and \rp, \rp, #0xff000
teq \rp, #0x50000 @@ S5P6450
ldreq \rp, =0xEC800000
movne \rp, #0xEC000000 @@ S5P6440
ldrne \rv, = S3C_VA_UART
#if CONFIG_DEBUG_S3C_UART != 0
add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
#endif
.endm
#include <plat/debug-macro.S>

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kernel/arch/arm/mach-s5p64x0/include/mach/dma.h Normal file
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/*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MACH_DMA_H
#define __MACH_DMA_H
/* This platform uses the common common DMA API driver for PL330 */
#include <plat/dma-pl330.h>
#endif /* __MACH_DMA_H */

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kernel/arch/arm/mach-s5p64x0/include/mach/gpio.h Normal file
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/* linux/arch/arm/mach-s5p64x0/include/mach/gpio.h
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 - GPIO lib support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H __FILE__
/* GPIO bank sizes */
#define S5P6440_GPIO_A_NR (6)
#define S5P6440_GPIO_B_NR (7)
#define S5P6440_GPIO_C_NR (8)
#define S5P6440_GPIO_F_NR (16)
#define S5P6440_GPIO_G_NR (7)
#define S5P6440_GPIO_H_NR (10)
#define S5P6440_GPIO_I_NR (16)
#define S5P6440_GPIO_J_NR (12)
#define S5P6440_GPIO_N_NR (16)
#define S5P6440_GPIO_P_NR (8)
#define S5P6440_GPIO_R_NR (15)
#define S5P6450_GPIO_A_NR (6)
#define S5P6450_GPIO_B_NR (7)
#define S5P6450_GPIO_C_NR (8)
#define S5P6450_GPIO_D_NR (8)
#define S5P6450_GPIO_F_NR (16)
#define S5P6450_GPIO_G_NR (14)
#define S5P6450_GPIO_H_NR (10)
#define S5P6450_GPIO_I_NR (16)
#define S5P6450_GPIO_J_NR (12)
#define S5P6450_GPIO_K_NR (5)
#define S5P6450_GPIO_N_NR (16)
#define S5P6450_GPIO_P_NR (11)
#define S5P6450_GPIO_Q_NR (14)
#define S5P6450_GPIO_R_NR (15)
#define S5P6450_GPIO_S_NR (8)
/* GPIO bank numbers */
/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
* space for debugging purposes so that any accidental
* change from one gpio bank to another can be caught.
*/
#define S5P64X0_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
enum s5p6440_gpio_number {
S5P6440_GPIO_A_START = 0,
S5P6440_GPIO_B_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_A),
S5P6440_GPIO_C_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_B),
S5P6440_GPIO_F_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_C),
S5P6440_GPIO_G_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_F),
S5P6440_GPIO_H_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_G),
S5P6440_GPIO_I_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_H),
S5P6440_GPIO_J_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_I),
S5P6440_GPIO_N_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_J),
S5P6440_GPIO_P_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_N),
S5P6440_GPIO_R_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_P),
};
enum s5p6450_gpio_number {
S5P6450_GPIO_A_START = 0,
S5P6450_GPIO_B_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_A),
S5P6450_GPIO_C_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_B),
S5P6450_GPIO_D_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_C),
S5P6450_GPIO_F_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_D),
S5P6450_GPIO_G_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_F),
S5P6450_GPIO_H_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_G),
S5P6450_GPIO_I_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_H),
S5P6450_GPIO_J_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_I),
S5P6450_GPIO_K_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_J),
S5P6450_GPIO_N_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_K),
S5P6450_GPIO_P_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_N),
S5P6450_GPIO_Q_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_P),
S5P6450_GPIO_R_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_Q),
S5P6450_GPIO_S_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_R),
};
/* GPIO number definitions */
#define S5P6440_GPA(_nr) (S5P6440_GPIO_A_START + (_nr))
#define S5P6440_GPB(_nr) (S5P6440_GPIO_B_START + (_nr))
#define S5P6440_GPC(_nr) (S5P6440_GPIO_C_START + (_nr))
#define S5P6440_GPF(_nr) (S5P6440_GPIO_F_START + (_nr))
#define S5P6440_GPG(_nr) (S5P6440_GPIO_G_START + (_nr))
#define S5P6440_GPH(_nr) (S5P6440_GPIO_H_START + (_nr))
#define S5P6440_GPI(_nr) (S5P6440_GPIO_I_START + (_nr))
#define S5P6440_GPJ(_nr) (S5P6440_GPIO_J_START + (_nr))
#define S5P6440_GPN(_nr) (S5P6440_GPIO_N_START + (_nr))
#define S5P6440_GPP(_nr) (S5P6440_GPIO_P_START + (_nr))
#define S5P6440_GPR(_nr) (S5P6440_GPIO_R_START + (_nr))
#define S5P6450_GPA(_nr) (S5P6450_GPIO_A_START + (_nr))
#define S5P6450_GPB(_nr) (S5P6450_GPIO_B_START + (_nr))
#define S5P6450_GPC(_nr) (S5P6450_GPIO_C_START + (_nr))
#define S5P6450_GPD(_nr) (S5P6450_GPIO_D_START + (_nr))
#define S5P6450_GPF(_nr) (S5P6450_GPIO_F_START + (_nr))
#define S5P6450_GPG(_nr) (S5P6450_GPIO_G_START + (_nr))
#define S5P6450_GPH(_nr) (S5P6450_GPIO_H_START + (_nr))
#define S5P6450_GPI(_nr) (S5P6450_GPIO_I_START + (_nr))
#define S5P6450_GPJ(_nr) (S5P6450_GPIO_J_START + (_nr))
#define S5P6450_GPK(_nr) (S5P6450_GPIO_K_START + (_nr))
#define S5P6450_GPN(_nr) (S5P6450_GPIO_N_START + (_nr))
#define S5P6450_GPP(_nr) (S5P6450_GPIO_P_START + (_nr))
#define S5P6450_GPQ(_nr) (S5P6450_GPIO_Q_START + (_nr))
#define S5P6450_GPR(_nr) (S5P6450_GPIO_R_START + (_nr))
#define S5P6450_GPS(_nr) (S5P6450_GPIO_S_START + (_nr))
/* the end of the S5P64X0 specific gpios */
#define S5P6440_GPIO_END (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1)
#define S5P6450_GPIO_END (S5P6450_GPS(S5P6450_GPIO_S_NR) + 1)
#define S5P64X0_GPIO_END (S5P6440_GPIO_END > S5P6450_GPIO_END ? \
S5P6440_GPIO_END : S5P6450_GPIO_END)
#define S3C_GPIO_END S5P64X0_GPIO_END
/* define the number of gpios we need to the one after the last GPIO range */
#define ARCH_NR_GPIOS (S5P64X0_GPIO_END + CONFIG_SAMSUNG_GPIO_EXTRA)
#endif /* __ASM_ARCH_GPIO_H */

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kernel/arch/arm/mach-s5p64x0/include/mach/hardware.h Normal file
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/* linux/arch/arm/mach-s5p64x0/include/mach/hardware.h
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 - Hardware support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H __FILE__
/* currently nothing here, placeholder */
#endif /* __ASM_ARCH_HARDWARE_H */

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kernel/arch/arm/mach-s5p64x0/include/mach/i2c.h Normal file
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/* linux/arch/arm/mach-s5p64x0/include/mach/i2c.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 I2C configuration
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
extern void s5p6440_i2c0_cfg_gpio(struct platform_device *dev);
extern void s5p6440_i2c1_cfg_gpio(struct platform_device *dev);
extern void s5p6450_i2c0_cfg_gpio(struct platform_device *dev);
extern void s5p6450_i2c1_cfg_gpio(struct platform_device *dev);

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kernel/arch/arm/mach-s5p64x0/include/mach/irqs.h Normal file
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/* linux/arch/arm/mach-s5p64x0/include/mach/irqs.h
*
* Copyright 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 - IRQ definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H __FILE__
#include <plat/irqs.h>
/* VIC0 */
#define IRQ_EINT0_3 S5P_IRQ_VIC0(0)
#define IRQ_EINT4_11 S5P_IRQ_VIC0(1)
#define IRQ_RTC_TIC S5P_IRQ_VIC0(2)
#define IRQ_IIS1 S5P_IRQ_VIC0(3) /* for only S5P6450 */
#define IRQ_IIS2 S5P_IRQ_VIC0(4) /* for only S5P6450 */
#define IRQ_IIC1 S5P_IRQ_VIC0(5)
#define IRQ_I2SV40 S5P_IRQ_VIC0(6)
#define IRQ_GPS S5P_IRQ_VIC0(7) /* for only S5P6450 */
#define IRQ_2D S5P_IRQ_VIC0(11)
#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(23)
#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(24)
#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(25)
#define IRQ_WDT S5P_IRQ_VIC0(26)
#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(27)
#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(28)
#define IRQ_DISPCON0 S5P_IRQ_VIC0(29)
#define IRQ_DISPCON1 S5P_IRQ_VIC0(30)
#define IRQ_DISPCON2 S5P_IRQ_VIC0(31)
/* VIC1 */
#define IRQ_EINT12_15 S5P_IRQ_VIC1(0)
#define IRQ_PCM0 S5P_IRQ_VIC1(2)
#define IRQ_PCM1 S5P_IRQ_VIC1(3) /* for only S5P6450 */
#define IRQ_PCM2 S5P_IRQ_VIC1(4) /* for only S5P6450 */
#define IRQ_UART0 S5P_IRQ_VIC1(5)
#define IRQ_UART1 S5P_IRQ_VIC1(6)
#define IRQ_UART2 S5P_IRQ_VIC1(7)
#define IRQ_UART3 S5P_IRQ_VIC1(8)
#define IRQ_DMA0 S5P_IRQ_VIC1(9)
#define IRQ_UART4 S5P_IRQ_VIC1(10) /* S5P6450 */
#define IRQ_UART5 S5P_IRQ_VIC1(11) /* S5P6450 */
#define IRQ_NFC S5P_IRQ_VIC1(13)
#define IRQ_USI S5P_IRQ_VIC1(15) /* S5P6450 */
#define IRQ_SPI0 S5P_IRQ_VIC1(16)
#define IRQ_SPI1 S5P_IRQ_VIC1(17)
#define IRQ_HSMMC2 S5P_IRQ_VIC1(17) /* Shared */
#define IRQ_IIC S5P_IRQ_VIC1(18)
#define IRQ_DISPCON3 S5P_IRQ_VIC1(19)
#define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21)
#define IRQ_PMU S5P_IRQ_VIC1(23) /* S5P6440 */
#define IRQ_HSMMC0 S5P_IRQ_VIC1(24)
#define IRQ_HSMMC1 S5P_IRQ_VIC1(25)
#define IRQ_OTG S5P_IRQ_VIC1(26)
#define IRQ_DSI S5P_IRQ_VIC1(27)
#define IRQ_RTC_ALARM S5P_IRQ_VIC1(28)
#define IRQ_TSI S5P_IRQ_VIC1(29)
#define IRQ_PENDN S5P_IRQ_VIC1(30)
#define IRQ_TC IRQ_PENDN
#define IRQ_ADC S5P_IRQ_VIC1(31)
/* UART interrupts, S5P6450 has 5 UARTs */
#define IRQ_S5P_UART_BASE4 (96)
#define IRQ_S5P_UART_BASE5 (100)
#define IRQ_S5P_UART_RX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_RXD)
#define IRQ_S5P_UART_TX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_TXD)
#define IRQ_S5P_UART_ERR4 (IRQ_S5P_UART_BASE4 + UART_IRQ_ERR)
#define IRQ_S5P_UART_RX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_RXD)
#define IRQ_S5P_UART_TX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_TXD)
#define IRQ_S5P_UART_ERR5 (IRQ_S5P_UART_BASE5 + UART_IRQ_ERR)
/* S3C compatibilty defines */
#define IRQ_S3CUART_RX4 IRQ_S5P_UART_RX4
#define IRQ_S3CUART_RX5 IRQ_S5P_UART_RX5
#define IRQ_I2S0 IRQ_I2SV40
#define IRQ_LCD_FIFO IRQ_DISPCON0
#define IRQ_LCD_VSYNC IRQ_DISPCON1
#define IRQ_LCD_SYSTEM IRQ_DISPCON2
/* S5P6450 EINT feature will be added */
/*
* Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined
* them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place
* after the pair of VICs.
*/
#define S5P_IRQ_EINT_BASE (S5P_IRQ_VIC1(31) + 6)
#define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE)
#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE)
/*
* S5P6440 has 0-15 external interrupts in group 0. Only these can be used
* to wake up from sleep. If request is beyond this range, by mistake, a large
* return value for an irq number should be indication of something amiss.
*/
#define S5P_EINT_BASE2 (0xf0000000)
/*
* Next the external interrupt groups. These are similar to the IRQ_EINT(x)
* that they are sourced from the GPIO pins but with a different scheme for
* priority and source indication.
*
* The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
* interrupts, but for historical reasons they are kept apart from these
* next interrupts.
*
* Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
* machine specific support files.
*/
/* Actually, #6 and #7 are missing in the EINT_GROUP1 */
#define IRQ_EINT_GROUP1_NR (15)
#define IRQ_EINT_GROUP2_NR (8)
#define IRQ_EINT_GROUP5_NR (7)
#define IRQ_EINT_GROUP6_NR (10)
/* Actually, #0, #1 and #2 are missing in the EINT_GROUP8 */
#define IRQ_EINT_GROUP8_NR (11)
#define IRQ_EINT_GROUP_BASE S5P_EINT(16)
#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0)
#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x))
#define IRQ_TIMER_BASE (11)
/* Set the default NR_IRQS */
#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
#endif /* __ASM_ARCH_IRQS_H */

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kernel/arch/arm/mach-s5p64x0/include/mach/map.h Normal file
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/* linux/arch/arm/mach-s5p64x0/include/mach/map.h
*
* Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 - Memory map definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H __FILE__
#include <plat/map-base.h>
#include <plat/map-s5p.h>
#define S5P64X0_PA_SDRAM 0x20000000
#define S5P64X0_PA_CHIPID 0xE0000000
#define S5P64X0_PA_SYSCON 0xE0100000
#define S5P64X0_PA_GPIO 0xE0308000
#define S5P64X0_PA_VIC0 0xE4000000
#define S5P64X0_PA_VIC1 0xE4100000
#define S5P64X0_PA_SROMC 0xE7000000
#define S5P64X0_PA_PDMA 0xE9000000
#define S5P64X0_PA_TIMER 0xEA000000
#define S5P64X0_PA_RTC 0xEA100000
#define S5P64X0_PA_WDT 0xEA200000
#define S5P6440_PA_IIC0 0xEC104000
#define S5P6440_PA_IIC1 0xEC20F000
#define S5P6450_PA_IIC0 0xEC100000
#define S5P6450_PA_IIC1 0xEC200000
#define S5P64X0_PA_SPI0 0xEC400000
#define S5P64X0_PA_SPI1 0xEC500000
#define S5P64X0_PA_HSOTG 0xED100000
#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
#define S5P64X0_PA_FB 0xEE000000
#define S5P64X0_PA_I2S 0xF2000000
#define S5P6450_PA_I2S1 0xF2800000
#define S5P6450_PA_I2S2 0xF2900000
#define S5P64X0_PA_PCM 0xF2100000
#define S5P64X0_PA_ADC 0xF3000000
/* Compatibiltiy Defines */
#define S3C_PA_HSMMC0 S5P64X0_PA_HSMMC(0)
#define S3C_PA_HSMMC1 S5P64X0_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5P64X0_PA_HSMMC(2)
#define S3C_PA_IIC S5P6440_PA_IIC0
#define S3C_PA_IIC1 S5P6440_PA_IIC1
#define S3C_PA_RTC S5P64X0_PA_RTC
#define S3C_PA_WDT S5P64X0_PA_WDT
#define S3C_PA_FB S5P64X0_PA_FB
#define S3C_PA_SPI0 S5P64X0_PA_SPI0
#define S3C_PA_SPI1 S5P64X0_PA_SPI1
#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
#define S5P_PA_SROMC S5P64X0_PA_SROMC
#define S5P_PA_SYSCON S5P64X0_PA_SYSCON
#define S5P_PA_TIMER S5P64X0_PA_TIMER
#define SAMSUNG_PA_ADC S5P64X0_PA_ADC
/* UART */
#define S5P6440_PA_UART(x) (0xEC000000 + ((x) * S3C_UART_OFFSET))
#define S5P6450_PA_UART(x) ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
#define S5P_PA_UART0 S5P6450_PA_UART(0)
#define S5P_PA_UART1 S5P6450_PA_UART(1)
#define S5P_PA_UART2 S5P6450_PA_UART(2)
#define S5P_PA_UART3 S5P6450_PA_UART(3)
#define S5P_PA_UART4 S5P6450_PA_UART(4)
#define S5P_PA_UART5 S5P6450_PA_UART(5)
#define S5P_SZ_UART SZ_256
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
#endif /* __ASM_ARCH_MAP_H */

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kernel/arch/arm/mach-s5p64x0/include/mach/pm-core.h Normal file
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/* linux/arch/arm/mach-s5p64x0/include/mach/pm-core.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 - PM core support for arch/arm/plat-samsung/pm.c
*
* Based on PM core support for S3C64XX by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <mach/regs-gpio.h>
static inline void s3c_pm_debug_init_uart(void)
{
u32 tmp = __raw_readl(S5P64X0_CLK_GATE_PCLK);
/*
* As a note, since the S5P64X0 UARTs generally have multiple
* clock sources, we simply enable PCLK at the moment and hope
* that the resume settings for the UART are suitable for the
* use with PCLK.
*/
tmp |= S5P64X0_CLK_GATE_PCLK_UART0;
tmp |= S5P64X0_CLK_GATE_PCLK_UART1;
tmp |= S5P64X0_CLK_GATE_PCLK_UART2;
tmp |= S5P64X0_CLK_GATE_PCLK_UART3;
__raw_writel(tmp, S5P64X0_CLK_GATE_PCLK);
udelay(10);
}
static inline void s3c_pm_arch_prepare_irqs(void)
{
/* VIC should have already been taken care of */
/* clear any pending EINT0 interrupts */
__raw_writel(__raw_readl(S5P64X0_EINT0PEND), S5P64X0_EINT0PEND);
}
static inline void s3c_pm_arch_stop_clocks(void) { }
static inline void s3c_pm_arch_show_resume_irqs(void) { }
/*
* make these defines, we currently do not have any need to change
* the IRQ wake controls depending on the CPU we are running on
*/
#define s3c_irqwake_eintallow ((1 << 16) - 1)
#define s3c_irqwake_intallow (~0)
static inline void s3c_pm_arch_update_uart(void __iomem *regs,
struct pm_uart_save *save)
{
u32 ucon = __raw_readl(regs + S3C2410_UCON);
u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
u32 new_ucon;
u32 delta;
/*
* S5P64X0 UART blocks only support level interrupts, so ensure that
* when we restore unused UART blocks we force the level interrupt
* settings.
*/
save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
/*
* We have a constraint on changing the clock type of the UART
* between UCLKx and PCLK, so ensure that when we restore UCON
* that the CLK field is correctly modified if the bootloader
* has changed anything.
*/
if (ucon_clk != save_clk) {
new_ucon = save->ucon;
delta = ucon_clk ^ save_clk;
/*
* change from UCLKx => wrong PCLK,
* either UCLK can be tested for by a bit-test
* with UCLK0
*/
if (ucon_clk & S3C6400_UCON_UCLK0 &&
!(save_clk & S3C6400_UCON_UCLK0) &&
delta & S3C6400_UCON_PCLK2) {
new_ucon &= ~S3C6400_UCON_UCLK0;
} else if (delta == S3C6400_UCON_PCLK2) {
/*
* as a precaution, don't change from
* PCLK2 => PCLK or vice-versa
*/
new_ucon ^= S3C6400_UCON_PCLK2;
}
S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
ucon, new_ucon, save->ucon);
save->ucon = new_ucon;
}
}
static inline void s3c_pm_restored_gpios(void)
{
/* ensure sleep mode has been cleared from the system */
__raw_writel(0, S5P64X0_SLPEN);
}
static inline void samsung_pm_saved_gpios(void)
{
/*
* turn on the sleep mode and keep it there, as it seems that during
* suspend the xCON registers get re-set and thus you can end up with
* problems between going to sleep and resuming.
*/
__raw_writel(S5P64X0_SLPEN_USE_xSLP, S5P64X0_SLPEN);
}

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/* linux/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 - Clock register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_CLOCK_H
#define __ASM_ARCH_REGS_CLOCK_H __FILE__
#include <mach/map.h>
#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
#define S5P64X0_APLL_CON S5P_CLKREG(0x0C)
#define S5P64X0_MPLL_CON S5P_CLKREG(0x10)
#define S5P64X0_EPLL_CON S5P_CLKREG(0x14)
#define S5P64X0_EPLL_CON_K S5P_CLKREG(0x18)
#define S5P64X0_CLK_SRC0 S5P_CLKREG(0x1C)
#define S5P64X0_CLK_DIV0 S5P_CLKREG(0x20)
#define S5P64X0_CLK_DIV1 S5P_CLKREG(0x24)
#define S5P64X0_CLK_DIV2 S5P_CLKREG(0x28)
#define S5P64X0_CLK_GATE_HCLK0 S5P_CLKREG(0x30)
#define S5P64X0_CLK_GATE_PCLK S5P_CLKREG(0x34)
#define S5P64X0_CLK_GATE_SCLK0 S5P_CLKREG(0x38)
#define S5P64X0_CLK_GATE_MEM0 S5P_CLKREG(0x3C)
#define S5P64X0_CLK_DIV3 S5P_CLKREG(0x40)
#define S5P64X0_CLK_GATE_HCLK1 S5P_CLKREG(0x44)
#define S5P64X0_CLK_GATE_SCLK1 S5P_CLKREG(0x48)
#define S5P6450_DPLL_CON S5P_CLKREG(0x50)
#define S5P6450_DPLL_CON_K S5P_CLKREG(0x54)
#define S5P64X0_AHB_CON0 S5P_CLKREG(0x100)
#define S5P64X0_CLK_SRC1 S5P_CLKREG(0x10C)
#define S5P64X0_SYS_ID S5P_CLKREG(0x118)
#define S5P64X0_SYS_OTHERS S5P_CLKREG(0x11C)
#define S5P64X0_PWR_CFG S5P_CLKREG(0x804)
#define S5P64X0_EINT_WAKEUP_MASK S5P_CLKREG(0x808)
#define S5P64X0_SLEEP_CFG S5P_CLKREG(0x818)
#define S5P64X0_PWR_STABLE S5P_CLKREG(0x828)
#define S5P64X0_OTHERS S5P_CLKREG(0x900)
#define S5P64X0_WAKEUP_STAT S5P_CLKREG(0x908)
#define S5P64X0_INFORM0 S5P_CLKREG(0xA00)
#define S5P64X0_CLKDIV0_HCLK_SHIFT (8)
#define S5P64X0_CLKDIV0_HCLK_MASK (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT)
/* HCLK GATE Registers */
#define S5P64X0_CLK_GATE_HCLK1_FIMGVG (1 << 2)
#define S5P64X0_CLK_GATE_SCLK1_FIMGVG (1 << 2)
/* PCLK GATE Registers */
#define S5P64X0_CLK_GATE_PCLK_UART3 (1 << 4)
#define S5P64X0_CLK_GATE_PCLK_UART2 (1 << 3)
#define S5P64X0_CLK_GATE_PCLK_UART1 (1 << 2)
#define S5P64X0_CLK_GATE_PCLK_UART0 (1 << 1)
#define S5P64X0_PWR_CFG_MMC1_DISABLE (1 << 15)
#define S5P64X0_PWR_CFG_MMC0_DISABLE (1 << 14)
#define S5P64X0_PWR_CFG_RTC_TICK_DISABLE (1 << 11)
#define S5P64X0_PWR_CFG_RTC_ALRM_DISABLE (1 << 10)
#define S5P64X0_PWR_CFG_WFI_MASK (3 << 5)
#define S5P64X0_PWR_CFG_WFI_SLEEP (3 << 5)
#define S5P64X0_SLEEP_CFG_OSC_EN (1 << 0)
#define S5P64X0_PWR_STABLE_PWR_CNT_VAL4 (4 << 0)
#define S5P6450_OTHERS_DISABLE_INT (1 << 31)
#define S5P64X0_OTHERS_RET_UART (1 << 26)
#define S5P64X0_OTHERS_RET_MMC1 (1 << 25)
#define S5P64X0_OTHERS_RET_MMC0 (1 << 24)
#define S5P64X0_OTHERS_USB_SIG_MASK (1 << 16)
/* Compatibility defines */
#define ARM_CLK_DIV S5P64X0_CLK_DIV0
#define ARM_DIV_RATIO_SHIFT 0
#define ARM_DIV_MASK (0xF << ARM_DIV_RATIO_SHIFT)
#define S5P_EPLL_CON S5P64X0_EPLL_CON
#endif /* __ASM_ARCH_REGS_CLOCK_H */

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/* linux/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 - GPIO register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_GPIO_H
#define __ASM_ARCH_REGS_GPIO_H __FILE__
#include <mach/map.h>
/* Base addresses for each of the banks */
#define S5P64X0_GPA_BASE (S5P_VA_GPIO + 0x0000)
#define S5P64X0_GPB_BASE (S5P_VA_GPIO + 0x0020)
#define S5P64X0_GPC_BASE (S5P_VA_GPIO + 0x0040)
#define S5P64X0_GPF_BASE (S5P_VA_GPIO + 0x00A0)
#define S5P64X0_GPG_BASE (S5P_VA_GPIO + 0x00C0)
#define S5P64X0_GPH_BASE (S5P_VA_GPIO + 0x00E0)
#define S5P64X0_GPI_BASE (S5P_VA_GPIO + 0x0100)
#define S5P64X0_GPJ_BASE (S5P_VA_GPIO + 0x0120)
#define S5P64X0_GPN_BASE (S5P_VA_GPIO + 0x0830)
#define S5P64X0_GPP_BASE (S5P_VA_GPIO + 0x0160)
#define S5P64X0_GPR_BASE (S5P_VA_GPIO + 0x0290)
#define S5P6450_GPD_BASE (S5P_VA_GPIO + 0x0060)
#define S5P6450_GPK_BASE (S5P_VA_GPIO + 0x0140)
#define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180)
#define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300)
#define S5P64X0_SPCON0 (S5P_VA_GPIO + 0x1A0)
#define S5P64X0_SPCON0_LCD_SEL_MASK (0x3 << 0)
#define S5P64X0_SPCON0_LCD_SEL_RGB (0x1 << 0)
#define S5P64X0_SPCON1 (S5P_VA_GPIO + 0x2B0)
#define S5P64X0_MEM0CONSLP0 (S5P_VA_GPIO + 0x1C0)
#define S5P64X0_MEM0CONSLP1 (S5P_VA_GPIO + 0x1C4)
#define S5P64X0_MEM0DRVCON (S5P_VA_GPIO + 0x1D0)
#define S5P64X0_MEM1DRVCON (S5P_VA_GPIO + 0x1D4)
#define S5P64X0_EINT12CON (S5P_VA_GPIO + 0x200)
#define S5P64X0_EINT12FLTCON (S5P_VA_GPIO + 0x220)
#define S5P64X0_EINT12MASK (S5P_VA_GPIO + 0x240)
/* External interrupt control registers for group0 */
#define EINT0CON0_OFFSET (0x900)
#define EINT0FLTCON0_OFFSET (0x910)
#define EINT0FLTCON1_OFFSET (0x914)
#define EINT0MASK_OFFSET (0x920)
#define EINT0PEND_OFFSET (0x924)
#define S5P64X0_EINT0CON0 (S5P_VA_GPIO + EINT0CON0_OFFSET)
#define S5P64X0_EINT0FLTCON0 (S5P_VA_GPIO + EINT0FLTCON0_OFFSET)
#define S5P64X0_EINT0FLTCON1 (S5P_VA_GPIO + EINT0FLTCON1_OFFSET)
#define S5P64X0_EINT0MASK (S5P_VA_GPIO + EINT0MASK_OFFSET)
#define S5P64X0_EINT0PEND (S5P_VA_GPIO + EINT0PEND_OFFSET)
#define S5P64X0_SLPEN (S5P_VA_GPIO + 0x930)
#define S5P64X0_SLPEN_USE_xSLP (1 << 0)
#endif /* __ASM_ARCH_REGS_GPIO_H */

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/* linux/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 - IRQ register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_IRQ_H
#define __ASM_ARCH_REGS_IRQ_H __FILE__
#include <asm/hardware/vic.h>
#include <mach/map.h>
#endif /* __ASM_ARCH_REGS_IRQ_H */

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/* linux/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Header file for s5p64x0 clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H __FILE__
#include <linux/clk.h>
extern struct clksrc_clk clk_mout_apll;
extern struct clksrc_clk clk_mout_mpll;
extern struct clksrc_clk clk_mout_epll;
extern int s5p64x0_epll_enable(struct clk *clk, int enable);
extern unsigned long s5p64x0_epll_get_rate(struct clk *clk);
extern struct clksrc_clk clk_armclk;
extern struct clksrc_clk clk_dout_mpll;
extern struct clksrc_sources clkset_hclk_low;
extern int s5p64x0_pclk_ctrl(struct clk *clk, int enable);
extern int s5p64x0_hclk0_ctrl(struct clk *clk, int enable);
extern int s5p64x0_hclk1_ctrl(struct clk *clk, int enable);
extern int s5p64x0_sclk_ctrl(struct clk *clk, int enable);
extern int s5p64x0_sclk1_ctrl(struct clk *clk, int enable);
extern int s5p64x0_mem_ctrl(struct clk *clk, int enable);
extern int s5p64x0_clk48m_ctrl(struct clk *clk, int enable);
#endif /* __ASM_ARCH_CLOCK_H */

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/* linux/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_SPI_CLKS_H
#define __ASM_ARCH_SPI_CLKS_H __FILE__
#define S5P64X0_SPI_SRCCLK_PCLK 0
#define S5P64X0_SPI_SRCCLK_SCLK 1
#endif /* __ASM_ARCH_SPI_CLKS_H */

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/* linux/arch/arm/mach-s5p64x0/include/mach/tick.h
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S5P64X0 - Timer tick support definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_TICK_H
#define __ASM_ARCH_TICK_H __FILE__
static inline u32 s3c24xx_ostimer_pending(void)
{
u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0)));
}
#define TICK_MAX (0xffffffff)
#endif /* __ASM_ARCH_TICK_H */

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/* linux/arch/arm/mach-s5p64x0/include/mach/timex.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Copyright (c) 2003-2005 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S5P64X0 - time parameters
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_TIMEX_H
#define __ASM_ARCH_TIMEX_H
/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
* a variable is useless. It seems as long as we make our timers an
* exact multiple of HZ, any value that makes a 1->1 correspondence
* for the time conversion functions to/from jiffies is acceptable.
*/
#define CLOCK_TICK_RATE 12000000
#endif /* __ASM_ARCH_TIMEX_H */

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/* linux/arch/arm/mach-s5p64x0/include/mach/uncompress.h
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 - uncompress code
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
#include <mach/map.h>
/*
* cannot use commonly <plat/uncompress.h>
* because uart base of S5P6440 and S5P6450 is different
*/
typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
/* uart setup */
unsigned int fifo_mask;
unsigned int fifo_max;
/* forward declerations */
static void arch_detect_cpu(void);
/* defines for UART registers */
#include <plat/regs-serial.h>
#include <plat/regs-watchdog.h>
/* working in physical space... */
#undef S3C2410_WDOGREG
#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
/* how many bytes we allow into the FIFO at a time in FIFO mode */
#define FIFO_MAX (14)
unsigned long uart_base;
static __inline__ void get_uart_base(void)
{
unsigned int chipid;
chipid = *(const volatile unsigned int __force *) 0xE0100118;
uart_base = S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT;
if ((chipid & 0xff000) == 0x50000)
uart_base += 0xEC800000;
else
uart_base += 0xEC000000;
}
static __inline__ void uart_wr(unsigned int reg, unsigned int val)
{
volatile unsigned int *ptr;
get_uart_base();
ptr = (volatile unsigned int *)(reg + uart_base);
*ptr = val;
}
static __inline__ unsigned int uart_rd(unsigned int reg)
{
volatile unsigned int *ptr;
get_uart_base();
ptr = (volatile unsigned int *)(reg + uart_base);
return *ptr;
}
/*
* we can deal with the case the UARTs are being run
* in FIFO mode, so that we don't hold up our execution
* waiting for tx to happen...
*/
static void putc(int ch)
{
if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
int level;
while (1) {
level = uart_rd(S3C2410_UFSTAT);
level &= fifo_mask;
if (level < fifo_max)
break;
}
} else {
/* not using fifos */
while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
barrier();
}
/* write byte to transmission register */
uart_wr(S3C2410_UTXH, ch);
}
static inline void flush(void)
{
}
#define __raw_writel(d, ad) \
do { \
*((volatile unsigned int __force *)(ad)) = (d); \
} while (0)
/*
* CONFIG_S3C_BOOT_WATCHDOG
*
* Simple boot-time watchdog setup, to reboot the system if there is
* any problem with the boot process
*/
#ifdef CONFIG_S3C_BOOT_WATCHDOG
#define WDOG_COUNT (0xff00)
static inline void arch_decomp_wdog(void)
{
__raw_writel(WDOG_COUNT, S3C2410_WTCNT);
}
static void arch_decomp_wdog_start(void)
{
__raw_writel(WDOG_COUNT, S3C2410_WTDAT);
__raw_writel(WDOG_COUNT, S3C2410_WTCNT);
__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
}
#else
#define arch_decomp_wdog_start()
#define arch_decomp_wdog()
#endif
#ifdef CONFIG_S3C_BOOT_ERROR_RESET
static void arch_decomp_error(const char *x)
{
putstr("\n\n");
putstr(x);
putstr("\n\n -- System resetting\n");
__raw_writel(0x4000, S3C2410_WTDAT);
__raw_writel(0x4000, S3C2410_WTCNT);
__raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
while(1);
}
#define arch_error arch_decomp_error
#endif
#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
static inline void arch_enable_uart_fifo(void)
{
u32 fifocon = uart_rd(S3C2410_UFCON);
if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
fifocon |= S3C2410_UFCON_RESETBOTH;
uart_wr(S3C2410_UFCON, fifocon);
/* wait for fifo reset to complete */
while (1) {
fifocon = uart_rd(S3C2410_UFCON);
if (!(fifocon & S3C2410_UFCON_RESETBOTH))
break;
}
}
}
#else
#define arch_enable_uart_fifo() do { } while(0)
#endif
static void arch_decomp_setup(void)
{
/*
* we may need to setup the uart(s) here if we are not running
* on an BAST... the BAST will have left the uarts configured
* after calling linux.
*/
arch_detect_cpu();
arch_decomp_wdog_start();
/*
* Enable the UART FIFOs if they where not enabled and our
* configuration says we should turn them on.
*/
arch_enable_uart_fifo();
}
static void arch_detect_cpu(void)
{
/* we do not need to do any cpu detection here at the moment. */
}
#endif /* __ASM_ARCH_UNCOMPRESS_H */