tobi/M7350
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

M7350v1_en_gpl

Browse Source
This commit is contained in:
T
2024-09-09 08:52:07 +00:00
commit f9cc65cfda
65988 changed files with 26357421 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
kernel/arch/arm/mach-iop33x/include/mach/adma.h Normal file
View File

@@ -0,0 +1,5 @@
#ifndef IOP33X_ADMA_H
#define IOP33X_ADMA_H
#include <asm/hardware/iop3xx-adma.h>
#endif

22
kernel/arch/arm/mach-iop33x/include/mach/debug-macro.S Normal file
View File

@@ -0,0 +1,22 @@
/*
* arch/arm/mach-iop33x/include/mach/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
.macro addruart, rp, rv, tmp
mov \rp, #0x00ff0000
orr \rp, \rp, #0x0000f700
orr \rv, #0xfe000000 @ virtual
orr \rp, #0xff000000 @ physical
.endm
#define UART_SHIFT 2
#include <asm/hardware/debug-8250.S>

34
kernel/arch/arm/mach-iop33x/include/mach/entry-macro.S Normal file
View File

@@ -0,0 +1,34 @@
/*
* arch/arm/mach-iop33x/include/mach/entry-macro.S
*
* Low-level IRQ helper macros for IOP33x-based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <mach/iop33x.h>
.macro get_irqnr_preamble, base, tmp
mrc p15, 0, \tmp, c15, c1, 0
orr \tmp, \tmp, #(1 << 6)
mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
mrc p15, 0, \tmp, c15, c1, 0
mov \tmp, \tmp
sub pc, pc, #4 @ cp_wait
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mrc p6, 0, \irqstat, c14, c0, 0 @ Read IINTVEC
cmp \irqstat, #0
mrceq p6, 0, \irqstat, c14, c0, 0 @ erratum 63 workaround
adds \irqnr, \irqstat, #1
movne \irqnr, \irqstat, lsr #2
.endm
.macro arch_ret_to_user, tmp1, tmp2
mrc p15, 0, \tmp1, c15, c1, 0
ands \tmp2, \tmp1, #(1 << 6)
bicne \tmp1, \tmp1, #(1 << 6)
mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
.endm

6
kernel/arch/arm/mach-iop33x/include/mach/gpio.h Normal file
View File

@@ -0,0 +1,6 @@
#ifndef __ASM_ARCH_IOP33X_GPIO_H
#define __ASM_ARCH_IOP33X_GPIO_H
#include <asm/hardware/iop3xx-gpio.h>
#endif

43
kernel/arch/arm/mach-iop33x/include/mach/hardware.h Normal file
View File

@@ -0,0 +1,43 @@
/*
* arch/arm/mach-iop33x/include/mach/hardware.h
*/
#ifndef __HARDWARE_H
#define __HARDWARE_H
#include <asm/types.h>
/*
* Note about PCI IO space mappings
*
* To make IO space accesses efficient, we store virtual addresses in
* the IO resources.
*
* The PCI IO space is located at virtual 0xfe000000 from physical
* 0x90000000. The PCI BARs must be programmed with physical addresses,
* but when we read them, we convert them to virtual addresses. See
* arch/arm/mach-iop3xx/iop3xx-pci.c
*/
#ifndef __ASSEMBLY__
void iop33x_init_irq(void);
extern struct platform_device iop33x_uart0_device;
extern struct platform_device iop33x_uart1_device;
#endif
/*
* Generic chipset bits
*
*/
#include "iop33x.h"
/*
* Board specific bits
*/
#include "iq80331.h"
#include "iq80332.h"
#endif

19
kernel/arch/arm/mach-iop33x/include/mach/io.h Normal file
View File

@@ -0,0 +1,19 @@
/*
* arch/arm/mach-iop33x/include/mach/io.h
*
* Copyright (C) 2001 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __IO_H
#define __IO_H
#include <asm/hardware/iop3xx.h>
#define IO_SPACE_LIMIT 0xffffffff
#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
#endif

41
kernel/arch/arm/mach-iop33x/include/mach/iop33x.h Normal file
View File

@@ -0,0 +1,41 @@
/*
* arch/arm/mach-iop33x/include/mach/iop33x.h
*
* Intel IOP33X Chip definitions
*
* Author: Dave Jiang (dave.jiang@intel.com)
* Copyright (C) 2003, 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __IOP33X_H
#define __IOP33X_H
/*
* Peripherals that are shared between the iop32x and iop33x but
* located at different addresses.
*/
#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1780 + (reg))
#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg))
#include <asm/hardware/iop3xx.h>
/* UARTs */
#define IOP33X_UART0_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1700)
#define IOP33X_UART0_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1700)
#define IOP33X_UART1_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740)
#define IOP33X_UART1_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740)
/* ATU Parameters
* set up a 1:1 bus to physical ram relationship
* w/ pci on top of physical ram in memory map
*/
#define IOP33X_MAX_RAM_SIZE 0x80000000UL
#define IOP3XX_MAX_RAM_SIZE IOP33X_MAX_RAM_SIZE
#define IOP3XX_PCI_LOWER_MEM_BA (PHYS_OFFSET + IOP33X_MAX_RAM_SIZE)
#endif

16
kernel/arch/arm/mach-iop33x/include/mach/iq80331.h Normal file
View File

@@ -0,0 +1,16 @@
/*
* arch/arm/mach-iop33x/include/mach/iq80331.h
*
* Intel IQ80331 evaluation board registers
*/
#ifndef __IQ80331_H
#define __IQ80331_H
#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */
#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
#define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */
#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */
#endif

16
kernel/arch/arm/mach-iop33x/include/mach/iq80332.h Normal file
View File

@@ -0,0 +1,16 @@
/*
* arch/arm/mach-iop33x/include/mach/iq80332.h
*
* Intel IQ80332 evaluation board registers
*/
#ifndef __IQ80332_H
#define __IQ80332_H
#define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */
#define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
#define IQ80332_ROTARY_SW 0xce8d0000 /* Rotary Switch */
#define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */
#endif

60
kernel/arch/arm/mach-iop33x/include/mach/irqs.h Normal file
View File

@@ -0,0 +1,60 @@
/*
* arch/arm/mach-iop33x/include/mach/irqs.h
*
* Author: Dave Jiang (dave.jiang@intel.com)
* Copyright: (C) 2003 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __IRQS_H
#define __IRQS_H
/*
* IOP80331 chipset interrupts
*/
#define IRQ_IOP33X_DMA0_EOT 0
#define IRQ_IOP33X_DMA0_EOC 1
#define IRQ_IOP33X_DMA1_EOT 2
#define IRQ_IOP33X_DMA1_EOC 3
#define IRQ_IOP33X_AA_EOT 6
#define IRQ_IOP33X_AA_EOC 7
#define IRQ_IOP33X_TIMER0 8
#define IRQ_IOP33X_TIMER1 9
#define IRQ_IOP33X_I2C_0 10
#define IRQ_IOP33X_I2C_1 11
#define IRQ_IOP33X_MSG 12
#define IRQ_IOP33X_MSGIBQ 13
#define IRQ_IOP33X_ATU_BIST 14
#define IRQ_IOP33X_PERFMON 15
#define IRQ_IOP33X_CORE_PMU 16
#define IRQ_IOP33X_XINT0 24
#define IRQ_IOP33X_XINT1 25
#define IRQ_IOP33X_XINT2 26
#define IRQ_IOP33X_XINT3 27
#define IRQ_IOP33X_XINT8 32
#define IRQ_IOP33X_XINT9 33
#define IRQ_IOP33X_XINT10 34
#define IRQ_IOP33X_XINT11 35
#define IRQ_IOP33X_XINT12 36
#define IRQ_IOP33X_XINT13 37
#define IRQ_IOP33X_XINT14 38
#define IRQ_IOP33X_XINT15 39
#define IRQ_IOP33X_UART0 51
#define IRQ_IOP33X_UART1 52
#define IRQ_IOP33X_PBIE 53
#define IRQ_IOP33X_ATU_CRW 54
#define IRQ_IOP33X_ATU_ERR 55
#define IRQ_IOP33X_MCU_ERR 56
#define IRQ_IOP33X_DMA0_ERR 57
#define IRQ_IOP33X_DMA1_ERR 58
#define IRQ_IOP33X_AA_ERR 60
#define IRQ_IOP33X_MSG_ERR 62
#define IRQ_IOP33X_HPI 63
#define NR_IRQS 64
#endif

4
kernel/arch/arm/mach-iop33x/include/mach/time.h Normal file
View File

@@ -0,0 +1,4 @@
#ifndef _IOP33X_TIME_H_
#define _IOP33X_TIME_H_
#define IRQ_IOP_TIMER0 IRQ_IOP33X_TIMER0
#endif

6
kernel/arch/arm/mach-iop33x/include/mach/timex.h Normal file
View File

@@ -0,0 +1,6 @@
/*
* arch/arm/mach-iop33x/include/mach/timex.h
*
* IOP3xx architecture timex specifications
*/
#define CLOCK_TICK_RATE (100 * HZ)

37
kernel/arch/arm/mach-iop33x/include/mach/uncompress.h Normal file
View File

@@ -0,0 +1,37 @@
/*
* arch/arm/mach-iop33x/include/mach/uncompress.h
*/
#include <asm/types.h>
#include <asm/mach-types.h>
#include <linux/serial_reg.h>
#include <mach/hardware.h>
volatile u32 *uart_base;
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
static inline void putc(char c)
{
while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
barrier();
uart_base[UART_TX] = c;
}
static inline void flush(void)
{
}
static __inline__ void __arch_decomp_setup(unsigned long arch_id)
{
if (machine_is_iq80331() || machine_is_iq80332())
uart_base = (volatile u32 *)IOP33X_UART0_PHYS;
else
uart_base = (volatile u32 *)0xfe800000;
}
/*
* nothing to do
*/
#define arch_decomp_setup() __arch_decomp_setup(arch_id)
#define arch_decomp_wdog()