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2024-09-09 08:52:07 +00:00
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26
kernel/arch/arm/mach-integrator/include/mach/clkdev.h Normal file
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#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#include <linux/module.h>
#include <plat/clock.h>
struct clk {
unsigned long rate;
const struct clk_ops *ops;
struct module *owner;
const struct icst_params *params;
void __iomem *vcoreg;
void *data;
};
static inline int __clk_get(struct clk *clk)
{
return try_module_get(clk->owner);
}
static inline void __clk_put(struct clk *clk)
{
module_put(clk->owner);
}
#endif

36
kernel/arch/arm/mach-integrator/include/mach/cm.h Normal file
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/*
* update the core module control register.
*/
void cm_control(u32, u32);
#define CM_CTRL_LED (1 << 0)
#define CM_CTRL_nMBDET (1 << 1)
#define CM_CTRL_REMAP (1 << 2)
#define CM_CTRL_RESET (1 << 3)
/*
* Integrator/AP,PP2 specific
*/
#define CM_CTRL_HIGHVECTORS (1 << 4)
#define CM_CTRL_BIGENDIAN (1 << 5)
#define CM_CTRL_FASTBUS (1 << 6)
#define CM_CTRL_SYNC (1 << 7)
/*
* ARM926/946/966 Integrator/CP specific
*/
#define CM_CTRL_LCDBIASEN (1 << 8)
#define CM_CTRL_LCDBIASUP (1 << 9)
#define CM_CTRL_LCDBIASDN (1 << 10)
#define CM_CTRL_LCDMUXSEL_MASK (7 << 11)
#define CM_CTRL_LCDMUXSEL_GENLCD (1 << 11)
#define CM_CTRL_LCDMUXSEL_VGA565_TFT555 (2 << 11)
#define CM_CTRL_LCDMUXSEL_SHARPLCD (3 << 11)
#define CM_CTRL_LCDMUXSEL_VGA555_TFT555 (4 << 11)
#define CM_CTRL_LCDEN0 (1 << 14)
#define CM_CTRL_LCDEN1 (1 << 15)
#define CM_CTRL_STATIC1 (1 << 16)
#define CM_CTRL_STATIC2 (1 << 17)
#define CM_CTRL_STATIC (1 << 18)
#define CM_CTRL_n24BITEN (1 << 19)
#define CM_CTRL_EBIWP (1 << 20)

20
kernel/arch/arm/mach-integrator/include/mach/debug-macro.S Normal file
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/* arch/arm/mach-integrator/include/mach/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
.macro addruart, rp, rv, tmp
mov \rp, #0x16000000 @ physical base address
mov \rv, #0xf0000000 @ virtual base
add \rv, \rv, #0x16000000 >> 4
.endm
#include <asm/hardware/debug-pl01x.S>

39
kernel/arch/arm/mach-integrator/include/mach/entry-macro.S Normal file
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/*
* arch/arm/mach-integrator/include/mach/entry-macro.S
*
* Low-level IRQ helper macros for Integrator platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <mach/hardware.h>
#include <mach/platform.h>
#include <mach/irqs.h>
.macro get_irqnr_preamble, base, tmp
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
/* FIXME: should not be using soo many LDRs here */
ldr \base, =IO_ADDRESS(INTEGRATOR_IC_BASE)
mov \irqnr, #IRQ_PIC_START
ldr \irqstat, [\base, #IRQ_STATUS] @ get masked status
ldr \base, =IO_ADDRESS(INTEGRATOR_HDR_BASE)
teq \irqstat, #0
ldreq \irqstat, [\base, #(INTEGRATOR_HDR_IC_OFFSET+IRQ_STATUS)]
moveq \irqnr, #IRQ_CIC_START
1001: tst \irqstat, #15
bne 1002f
add \irqnr, \irqnr, #4
movs \irqstat, \irqstat, lsr #4
bne 1001b
1002: tst \irqstat, #1
bne 1003f
add \irqnr, \irqnr, #1
movs \irqstat, \irqstat, lsr #1
bne 1002b
1003: /* EQ will be set if no irqs pending */
.endm

45
kernel/arch/arm/mach-integrator/include/mach/hardware.h Normal file
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/*
* arch/arm/mach-integrator/include/mach/hardware.h
*
* This file contains the hardware definitions of the Integrator.
*
* Copyright (C) 1999 ARM Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/sizes.h>
/*
* Where in virtual memory the IO devices (timers, system controllers
* and so on)
*/
#define IO_BASE 0xF0000000 // VA of IO
#define IO_SIZE 0x0B000000 // How much?
#define IO_START INTEGRATOR_HDR_BASE // PA of IO
/* macro to get at IO space when running virtually */
#ifdef CONFIG_MMU
#define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
#else
#define IO_ADDRESS(x) (x)
#endif
#define __io_address(n) ((void __iomem *)IO_ADDRESS(n))
#endif

18
kernel/arch/arm/mach-integrator/include/mach/impd1.h Normal file
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#define IMPD1_OSC1 0x00
#define IMPD1_OSC2 0x04
#define IMPD1_LOCK 0x08
#define IMPD1_LEDS 0x0c
#define IMPD1_INT 0x10
#define IMPD1_SW 0x14
#define IMPD1_CTRL 0x18
#define IMPD1_CTRL_DISP_LCD (0 << 0)
#define IMPD1_CTRL_DISP_VGA (1 << 0)
#define IMPD1_CTRL_DISP_LCD1 (2 << 0)
#define IMPD1_CTRL_DISP_ENABLE (1 << 2)
#define IMPD1_CTRL_DISP_MASK (7 << 0)
struct device;
void impd1_tweak_control(struct device *dev, u32 mask, u32 val);

33
kernel/arch/arm/mach-integrator/include/mach/io.h Normal file
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/*
* arch/arm/mach-integrator/include/mach/io.h
*
* Copyright (C) 1999 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
/*
* WARNING: this has to mirror definitions in platform.h
*/
#define PCI_MEMORY_VADDR 0xe8000000
#define PCI_CONFIG_VADDR 0xec000000
#define PCI_V3_VADDR 0xed000000
#define PCI_IO_VADDR 0xee000000
#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a)))
#endif

83
kernel/arch/arm/mach-integrator/include/mach/irqs.h Normal file
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/*
* arch/arm/mach-integrator/include/mach/irqs.h
*
* Copyright (C) 1999 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* Interrupt numbers
*/
#define IRQ_PIC_START 0
#define IRQ_SOFTINT 0
#define IRQ_UARTINT0 1
#define IRQ_UARTINT1 2
#define IRQ_KMIINT0 3
#define IRQ_KMIINT1 4
#define IRQ_TIMERINT0 5
#define IRQ_TIMERINT1 6
#define IRQ_TIMERINT2 7
#define IRQ_RTCINT 8
#define IRQ_AP_EXPINT0 9
#define IRQ_AP_EXPINT1 10
#define IRQ_AP_EXPINT2 11
#define IRQ_AP_EXPINT3 12
#define IRQ_AP_PCIINT0 13
#define IRQ_AP_PCIINT1 14
#define IRQ_AP_PCIINT2 15
#define IRQ_AP_PCIINT3 16
#define IRQ_AP_V3INT 17
#define IRQ_AP_CPINT0 18
#define IRQ_AP_CPINT1 19
#define IRQ_AP_LBUSTIMEOUT 20
#define IRQ_AP_APCINT 21
#define IRQ_CP_CLCDCINT 22
#define IRQ_CP_MMCIINT0 23
#define IRQ_CP_MMCIINT1 24
#define IRQ_CP_AACIINT 25
#define IRQ_CP_CPPLDINT 26
#define IRQ_CP_ETHINT 27
#define IRQ_CP_TSPENINT 28
#define IRQ_PIC_END 31
#define IRQ_CIC_START 32
#define IRQ_CM_SOFTINT 32
#define IRQ_CM_COMMRX 33
#define IRQ_CM_COMMTX 34
#define IRQ_CIC_END 34
/*
* IntegratorCP only
*/
#define IRQ_SIC_START 35
#define IRQ_SIC_CP_SOFTINT 35
#define IRQ_SIC_CP_RI0 36
#define IRQ_SIC_CP_RI1 37
#define IRQ_SIC_CP_CARDIN 38
#define IRQ_SIC_CP_LMINT0 39
#define IRQ_SIC_CP_LMINT1 40
#define IRQ_SIC_CP_LMINT2 41
#define IRQ_SIC_CP_LMINT3 42
#define IRQ_SIC_CP_LMINT4 43
#define IRQ_SIC_CP_LMINT5 44
#define IRQ_SIC_CP_LMINT6 45
#define IRQ_SIC_CP_LMINT7 46
#define IRQ_SIC_END 46
#define NR_IRQS_INTEGRATOR_AP 34
#define NR_IRQS_INTEGRATOR_CP 47

23
kernel/arch/arm/mach-integrator/include/mach/lm.h Normal file
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struct lm_device {
struct device dev;
struct resource resource;
unsigned int irq;
unsigned int id;
};
struct lm_driver {
struct device_driver drv;
int (*probe)(struct lm_device *);
void (*remove)(struct lm_device *);
int (*suspend)(struct lm_device *, pm_message_t);
int (*resume)(struct lm_device *);
};
int lm_driver_register(struct lm_driver *drv);
void lm_driver_unregister(struct lm_driver *drv);
int lm_device_register(struct lm_device *dev);
#define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev)
#define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d)

34
kernel/arch/arm/mach-integrator/include/mach/memory.h Normal file
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/*
* arch/arm/mach-integrator/include/mach/memory.h
*
* Copyright (C) 1999 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/*
* Physical DRAM offset.
*/
#define PLAT_PHYS_OFFSET UL(0x00000000)
#define BUS_OFFSET UL(0x80000000)
#define __virt_to_bus(x) ((x) - PAGE_OFFSET + BUS_OFFSET)
#define __bus_to_virt(x) ((x) - BUS_OFFSET + PAGE_OFFSET)
#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - PHYS_OFFSET))
#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - PHYS_OFFSET))
#endif

402
kernel/arch/arm/mach-integrator/include/mach/platform.h Normal file
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/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/**************************************************************************
* * Copyright © ARM Limited 1998. All rights reserved.
* ***********************************************************************/
/* ************************************************************************
*
* Integrator address map
*
* ***********************************************************************/
#ifndef __address_h
#define __address_h 1
/* ========================================================================
* Integrator definitions
* ========================================================================
* ------------------------------------------------------------------------
* Memory definitions
* ------------------------------------------------------------------------
* Integrator memory map
*
*/
#define INTEGRATOR_BOOT_ROM_LO 0x00000000
#define INTEGRATOR_BOOT_ROM_HI 0x20000000
#define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */
#define INTEGRATOR_BOOT_ROM_SIZE SZ_512K
/*
* New Core Modules have different amounts of SSRAM, the amount of SSRAM
* fitted can be found in HDR_STAT.
*
* The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
* the minimum amount of SSRAM fitted on any core module.
*
* New Core Modules also alias the SSRAM.
*
*/
#define INTEGRATOR_SSRAM_BASE 0x00000000
#define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
#define INTEGRATOR_SSRAM_SIZE SZ_256K
#define INTEGRATOR_FLASH_BASE 0x24000000
#define INTEGRATOR_FLASH_SIZE SZ_32M
#define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
#define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K
/*
* SDRAM is a SIMM therefore the size is not known.
*
*/
#define INTEGRATOR_SDRAM_BASE 0x00040000
#define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000
#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
#define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000
#define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000
#define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000
/*
* Logic expansion modules
*
*/
#define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000
#define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000
#define INTEGRATOR_LOGIC_MODULE1_BASE 0xD0000000
#define INTEGRATOR_LOGIC_MODULE2_BASE 0xE0000000
#define INTEGRATOR_LOGIC_MODULE3_BASE 0xF0000000
/* ------------------------------------------------------------------------
* Integrator header card registers
* ------------------------------------------------------------------------
*
*/
#define INTEGRATOR_HDR_ID_OFFSET 0x00
#define INTEGRATOR_HDR_PROC_OFFSET 0x04
#define INTEGRATOR_HDR_OSC_OFFSET 0x08
#define INTEGRATOR_HDR_CTRL_OFFSET 0x0C
#define INTEGRATOR_HDR_STAT_OFFSET 0x10
#define INTEGRATOR_HDR_LOCK_OFFSET 0x14
#define INTEGRATOR_HDR_SDRAM_OFFSET 0x20
#define INTEGRATOR_HDR_INIT_OFFSET 0x24 /* CM9x6 */
#define INTEGRATOR_HDR_IC_OFFSET 0x40
#define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100
#define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200
#define INTEGRATOR_HDR_BASE 0x10000000
#define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET)
#define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET)
#define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET)
#define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET)
#define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET)
#define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET)
#define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET)
#define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET)
#define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET)
#define INTEGRATOR_HDR_SPDBASE (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET)
#define INTEGRATOR_HDR_SPDTOP (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET)
#define INTEGRATOR_HDR_CTRL_LED 0x01
#define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02
#define INTEGRATOR_HDR_CTRL_REMAP 0x04
#define INTEGRATOR_HDR_CTRL_RESET 0x08
#define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10
#define INTEGRATOR_HDR_CTRL_BIG_ENDIAN 0x20
#define INTEGRATOR_HDR_CTRL_FASTBUS 0x40
#define INTEGRATOR_HDR_CTRL_SYNC 0x80
#define INTEGRATOR_HDR_OSC_CORE_10MHz 0x102
#define INTEGRATOR_HDR_OSC_CORE_15MHz 0x107
#define INTEGRATOR_HDR_OSC_CORE_20MHz 0x10C
#define INTEGRATOR_HDR_OSC_CORE_25MHz 0x111
#define INTEGRATOR_HDR_OSC_CORE_30MHz 0x116
#define INTEGRATOR_HDR_OSC_CORE_35MHz 0x11B
#define INTEGRATOR_HDR_OSC_CORE_40MHz 0x120
#define INTEGRATOR_HDR_OSC_CORE_45MHz 0x125
#define INTEGRATOR_HDR_OSC_CORE_50MHz 0x12A
#define INTEGRATOR_HDR_OSC_CORE_55MHz 0x12F
#define INTEGRATOR_HDR_OSC_CORE_60MHz 0x134
#define INTEGRATOR_HDR_OSC_CORE_65MHz 0x139
#define INTEGRATOR_HDR_OSC_CORE_70MHz 0x13E
#define INTEGRATOR_HDR_OSC_CORE_75MHz 0x143
#define INTEGRATOR_HDR_OSC_CORE_80MHz 0x148
#define INTEGRATOR_HDR_OSC_CORE_85MHz 0x14D
#define INTEGRATOR_HDR_OSC_CORE_90MHz 0x152
#define INTEGRATOR_HDR_OSC_CORE_95MHz 0x157
#define INTEGRATOR_HDR_OSC_CORE_100MHz 0x15C
#define INTEGRATOR_HDR_OSC_CORE_105MHz 0x161
#define INTEGRATOR_HDR_OSC_CORE_110MHz 0x166
#define INTEGRATOR_HDR_OSC_CORE_115MHz 0x16B
#define INTEGRATOR_HDR_OSC_CORE_120MHz 0x170
#define INTEGRATOR_HDR_OSC_CORE_125MHz 0x175
#define INTEGRATOR_HDR_OSC_CORE_130MHz 0x17A
#define INTEGRATOR_HDR_OSC_CORE_135MHz 0x17F
#define INTEGRATOR_HDR_OSC_CORE_140MHz 0x184
#define INTEGRATOR_HDR_OSC_CORE_145MHz 0x189
#define INTEGRATOR_HDR_OSC_CORE_150MHz 0x18E
#define INTEGRATOR_HDR_OSC_CORE_155MHz 0x193
#define INTEGRATOR_HDR_OSC_CORE_160MHz 0x198
#define INTEGRATOR_HDR_OSC_CORE_MASK 0x7FF
#define INTEGRATOR_HDR_OSC_MEM_10MHz 0x10C000
#define INTEGRATOR_HDR_OSC_MEM_15MHz 0x116000
#define INTEGRATOR_HDR_OSC_MEM_20MHz 0x120000
#define INTEGRATOR_HDR_OSC_MEM_25MHz 0x12A000
#define INTEGRATOR_HDR_OSC_MEM_30MHz 0x134000
#define INTEGRATOR_HDR_OSC_MEM_33MHz 0x13A000
#define INTEGRATOR_HDR_OSC_MEM_40MHz 0x148000
#define INTEGRATOR_HDR_OSC_MEM_50MHz 0x15C000
#define INTEGRATOR_HDR_OSC_MEM_60MHz 0x170000
#define INTEGRATOR_HDR_OSC_MEM_66MHz 0x17C000
#define INTEGRATOR_HDR_OSC_MEM_MASK 0x7FF000
#define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0 0x0
#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0 0x0800000
#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6 0x1000000
#define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00 0x1800000
#define INTEGRATOR_HDR_OSC_BUS_MODE_MASK 0x1800000
#define INTEGRATOR_HDR_SDRAM_SPD_OK (1 << 5)
/* ------------------------------------------------------------------------
* Integrator system registers
* ------------------------------------------------------------------------
*
*/
/*
* System Controller
*
*/
#define INTEGRATOR_SC_ID_OFFSET 0x00
#define INTEGRATOR_SC_OSC_OFFSET 0x04
#define INTEGRATOR_SC_CTRLS_OFFSET 0x08
#define INTEGRATOR_SC_CTRLC_OFFSET 0x0C
#define INTEGRATOR_SC_DEC_OFFSET 0x10
#define INTEGRATOR_SC_ARB_OFFSET 0x14
#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
#define INTEGRATOR_SC_LOCK_OFFSET 0x1C
#define INTEGRATOR_SC_BASE 0x11000000
#define INTEGRATOR_SC_ID (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)
#define INTEGRATOR_SC_OSC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)
#define INTEGRATOR_SC_CTRLS (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
#define INTEGRATOR_SC_CTRLC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
#define INTEGRATOR_SC_DEC (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)
#define INTEGRATOR_SC_ARB (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)
#define INTEGRATOR_SC_PCIENABLE (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
#define INTEGRATOR_SC_LOCK (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)
#define INTEGRATOR_SC_OSC_SYS_10MHz 0x20
#define INTEGRATOR_SC_OSC_SYS_15MHz 0x34
#define INTEGRATOR_SC_OSC_SYS_20MHz 0x48
#define INTEGRATOR_SC_OSC_SYS_25MHz 0x5C
#define INTEGRATOR_SC_OSC_SYS_33MHz 0x7C
#define INTEGRATOR_SC_OSC_SYS_MASK 0xFF
#define INTEGRATOR_SC_OSC_PCI_25MHz 0x100
#define INTEGRATOR_SC_OSC_PCI_33MHz 0x0
#define INTEGRATOR_SC_OSC_PCI_MASK 0x100
#define INTEGRATOR_SC_CTRL_SOFTRST (1 << 0)
#define INTEGRATOR_SC_CTRL_nFLVPPEN (1 << 1)
#define INTEGRATOR_SC_CTRL_nFLWP (1 << 2)
#define INTEGRATOR_SC_CTRL_URTS0 (1 << 4)
#define INTEGRATOR_SC_CTRL_UDTR0 (1 << 5)
#define INTEGRATOR_SC_CTRL_URTS1 (1 << 6)
#define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7)
/*
* External Bus Interface
*
*/
#define INTEGRATOR_EBI_BASE 0x12000000
#define INTEGRATOR_EBI_CSR0_OFFSET 0x00
#define INTEGRATOR_EBI_CSR1_OFFSET 0x04
#define INTEGRATOR_EBI_CSR2_OFFSET 0x08
#define INTEGRATOR_EBI_CSR3_OFFSET 0x0C
#define INTEGRATOR_EBI_LOCK_OFFSET 0x20
#define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET)
#define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
#define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET)
#define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET)
#define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
#define INTEGRATOR_EBI_8_BIT 0x00
#define INTEGRATOR_EBI_16_BIT 0x01
#define INTEGRATOR_EBI_32_BIT 0x02
#define INTEGRATOR_EBI_WRITE_ENABLE 0x04
#define INTEGRATOR_EBI_SYNC 0x08
#define INTEGRATOR_EBI_WS_2 0x00
#define INTEGRATOR_EBI_WS_3 0x10
#define INTEGRATOR_EBI_WS_4 0x20
#define INTEGRATOR_EBI_WS_5 0x30
#define INTEGRATOR_EBI_WS_6 0x40
#define INTEGRATOR_EBI_WS_7 0x50
#define INTEGRATOR_EBI_WS_8 0x60
#define INTEGRATOR_EBI_WS_9 0x70
#define INTEGRATOR_EBI_WS_10 0x80
#define INTEGRATOR_EBI_WS_11 0x90
#define INTEGRATOR_EBI_WS_12 0xA0
#define INTEGRATOR_EBI_WS_13 0xB0
#define INTEGRATOR_EBI_WS_14 0xC0
#define INTEGRATOR_EBI_WS_15 0xD0
#define INTEGRATOR_EBI_WS_16 0xE0
#define INTEGRATOR_EBI_WS_17 0xF0
#define INTEGRATOR_CT_BASE 0x13000000 /* Counter/Timers */
#define INTEGRATOR_IC_BASE 0x14000000 /* Interrupt Controller */
#define INTEGRATOR_RTC_BASE 0x15000000 /* Real Time Clock */
#define INTEGRATOR_UART0_BASE 0x16000000 /* UART 0 */
#define INTEGRATOR_UART1_BASE 0x17000000 /* UART 1 */
#define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */
#define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */
/*
* LED's & Switches
*
*/
#define INTEGRATOR_DBG_ALPHA_OFFSET 0x00
#define INTEGRATOR_DBG_LEDS_OFFSET 0x04
#define INTEGRATOR_DBG_SWITCH_OFFSET 0x08
#define INTEGRATOR_DBG_BASE 0x1A000000
#define INTEGRATOR_DBG_ALPHA (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET)
#define INTEGRATOR_DBG_LEDS (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET)
#define INTEGRATOR_DBG_SWITCH (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
#define INTEGRATOR_AP_GPIO_BASE 0x1B000000 /* GPIO */
#define INTEGRATOR_CP_MMC_BASE 0x1C000000 /* MMC */
#define INTEGRATOR_CP_AACI_BASE 0x1D000000 /* AACI */
#define INTEGRATOR_CP_ETH_BASE 0xC8000000 /* Ethernet */
#define INTEGRATOR_CP_GPIO_BASE 0xC9000000 /* GPIO */
#define INTEGRATOR_CP_SIC_BASE 0xCA000000 /* SIC */
#define INTEGRATOR_CP_CTL_BASE 0xCB000000 /* CP system control */
/* ------------------------------------------------------------------------
* KMI keyboard/mouse definitions
* ------------------------------------------------------------------------
*/
/* PS2 Keyboard interface */
#define KMI0_BASE INTEGRATOR_KBD_BASE
/* PS2 Mouse interface */
#define KMI1_BASE INTEGRATOR_MOUSE_BASE
/* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */
/* ------------------------------------------------------------------------
* Where in the memory map does PCI live?
* ------------------------------------------------------------------------
* This represents a fairly liberal usage of address space. Even though
* the V3 only has two windows (therefore we need to map stuff on the fly),
* we maintain the same addresses, even if they're not mapped.
*
*/
#define PHYS_PCI_MEM_BASE 0x40000000 /* 512M to xxx */
/* unused 256M from A0000000-AFFFFFFF might be used for I2O ???
*/
#define PHYS_PCI_IO_BASE 0x60000000 /* 16M to xxx */
/* unused (128-16)M from B1000000-B7FFFFFF
*/
#define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */
/* unused ((128-16)M - 64K) from XXX
*/
#define PHYS_PCI_V3_BASE 0x62000000
/* ------------------------------------------------------------------------
* Integrator Interrupt Controllers
* ------------------------------------------------------------------------
*
* Offsets from interrupt controller base
*
* System Controller interrupt controller base is
*
* INTEGRATOR_IC_BASE + (header_number << 6)
*
* Core Module interrupt controller base is
*
* INTEGRATOR_HDR_IC
*
*/
#define IRQ_STATUS 0
#define IRQ_RAW_STATUS 0x04
#define IRQ_ENABLE 0x08
#define IRQ_ENABLE_SET 0x08
#define IRQ_ENABLE_CLEAR 0x0C
#define INT_SOFT_SET 0x10
#define INT_SOFT_CLEAR 0x14
#define FIQ_STATUS 0x20
#define FIQ_RAW_STATUS 0x24
#define FIQ_ENABLE 0x28
#define FIQ_ENABLE_SET 0x28
#define FIQ_ENABLE_CLEAR 0x2C
/* ------------------------------------------------------------------------
* Interrupts
* ------------------------------------------------------------------------
*
*
* Each Core Module has two interrupts controllers, one on the core module
* itself and one in the system controller on the motherboard. The
* READ_INT macro in target.s reads both interrupt controllers and returns
* a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller
* and bits 24 to 31 are from the core module.
*
* The following definitions relate to the bitmask returned by READ_INT.
*
*/
/* ------------------------------------------------------------------------
* LED's
* ------------------------------------------------------------------------
*
*/
#define GREEN_LED 0x01
#define YELLOW_LED 0x02
#define RED_LED 0x04
#define GREEN_LED_2 0x08
#define ALL_LEDS 0x0F
#define LED_BANK INTEGRATOR_DBG_LEDS
/*
* Timer definitions
*
* Only use timer 1 & 2
* (both run at 24MHz and will need the clock divider set to 16).
*
* Timer 0 runs at bus frequency
*/
#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE
#define INTEGRATOR_TIMER1_BASE (INTEGRATOR_CT_BASE + 0x100)
#define INTEGRATOR_TIMER2_BASE (INTEGRATOR_CT_BASE + 0x200)
#define INTEGRATOR_CSR_BASE 0x10000000
#define INTEGRATOR_CSR_SIZE 0x10000000
#endif

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/*
* arch/arm/mach-integrator/include/mach/timex.h
*
* Integrator architecture timex specifications
*
* Copyright (C) 1999 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* ??
*/
#define CLOCK_TICK_RATE (50000000 / 16)

50
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/*
* arch/arm/mach-integrator/include/mach/uncompress.h
*
* Copyright (C) 1999 ARM Limited
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define AMBA_UART_DR (*(volatile unsigned char *)0x16000000)
#define AMBA_UART_LCRH (*(volatile unsigned char *)0x16000008)
#define AMBA_UART_LCRM (*(volatile unsigned char *)0x1600000c)
#define AMBA_UART_LCRL (*(volatile unsigned char *)0x16000010)
#define AMBA_UART_CR (*(volatile unsigned char *)0x16000014)
#define AMBA_UART_FR (*(volatile unsigned char *)0x16000018)
/*
* This does not append a newline
*/
static void putc(int c)
{
while (AMBA_UART_FR & (1 << 5))
barrier();
AMBA_UART_DR = c;
}
static inline void flush(void)
{
while (AMBA_UART_FR & (1 << 3))
barrier();
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()