M7350v1_en_gpl

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2024-09-09 08:52:07 +00:00
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OLPC XO-1 RTC
~~~~~~~~~~~~~
Required properties:
- compatible : "olpc,xo1-rtc"
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* msm-qpnp-rtc
msm-qpnp-rtc is a RTC driver that supports 32 bit RTC housed inside PMIC.
Driver utilizes MSM SPMI interface to communicate with the RTC module.
RTC device is divided into two sub-peripherals one which controls basic RTC
and other for controlling alarm.
[PMIC RTC Device Declarations]
-Root Node-
Required properties :
- compatible: Must be "qcom,qpnp-rtc"
- #address-cells: The number of cells dedicated to represent an address
This must be set to '1'.
- #size-cells: The number of cells dedicated to represent address
space range of a peripheral. This must be set to '1'.
- spmi-dev-container: This specifies that all the device nodes specified
within this node should have their resources
coalesced into a single spmi_device.
Optional properties:
- qcom,qpnp-rtc-write: This property enables/disables rtc write
operation. If not mentioned rtc driver keeps
rtc writes disabled.
0 = Disable rtc writes.
1 = Enable rtc writes.
- qcom,qpnp-rtc-alarm-pwrup: This property enables/disables feature of
powering up phone (from power down state)
through alarm interrupt.
If not mentioned rtc driver will disable
feature of powring-up phone through alarm.
0 = Disable powering up of phone through
alarm interrupt.
1 = Enable powering up of phone through
alarm interrupt.
-Child Nodes-
Required properties :
- reg : Specify the spmi offset and size for device.
- interrupts: Specifies alarm interrupt, only for rtc_alarm
sub-peripheral.
Example:
qcom,pm8941_rtc {
spmi-dev-container;
compatible = "qcom,qpnp-rtc";
#address-cells = <1>;
#size-cells = <1>;
qcom,qpnp-rtc-write = <0>;
qcom,qpnp-rtc-alarm-pwrup = <0>;
qcom,pm8941_rtc_rw@6000 {
reg = <0x6000 0x100>;
};
qcom,pm8941_rtc_alarm@6100 {
reg = <0x6100 0x100>;
interrupts = <0x0 0x61 0x1>;
};
};
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Motorola mc146818 compatible RTC
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Required properties:
- compatible : "motorola,mc146818"
- reg : should contain registers location and length.
Optional properties:
- interrupts : should contain interrupt.
- interrupt-parent : interrupt source phandle.
- ctrl-reg : Contains the initial value of the control register also
called "Register B".
- freq-reg : Contains the initial value of the frequency register also
called "Regsiter A".
"Register A" and "B" are usually initialized by the firmware (BIOS for
instance). If this is not done, it can be performed by the driver.
ISA Example:
rtc@70 {
compatible = "motorola,mc146818";
interrupts = <8 3>;
interrupt-parent = <&ioapic1>;
ctrl-reg = <2>;
freq-reg = <0x26>;
reg = <1 0x70 2>;
};
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* Samsung's S3C Real Time Clock controller
Required properties:
- compatible: should be one of the following.
* "samsung,s3c2410-rtc" - for controllers compatible with s3c2410 rtc.
* "samsung,s3c6410-rtc" - for controllers compatible with s3c6410 rtc.
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: Two interrupt numbers to the cpu should be specified. First
interrupt number is the rtc alarm interupt and second interrupt number
is the rtc tick interrupt. The number of cells representing a interrupt
depends on the parent interrupt controller.
Example:
rtc@10070000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x10070000 0x100>;
interrupts = <44 0 45 0>;
};
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* Marvell Real Time Clock controller
Required properties:
- compatible: should be "mrvl,sa1100-rtc"
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: Should be two. The first interrupt number is the rtc alarm
interrupt and the second interrupt number is the rtc hz interrupt.
- interrupt-names: Assign name of irq resource.
Example:
rtc: rtc@d4010000 {
compatible = "mrvl,mmp-rtc";
reg = <0xd4010000 0x1000>;
interrupts = <5>, <6>;
interrupt-name = "rtc 1Hz", "rtc alarm";
};
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* TI twl RTC
The TWL family (twl4030/6030) contains a RTC.
Required properties:
- compatible : Should be twl4030-rtc
Examples:
rtc@0 {
compatible = "ti,twl4030-rtc";
};