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87
kernel/Documentation/devicetree/bindings/platform/msm/ipa.txt Normal file
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Qualcomm Internet Packet Accelerator
Internet Packet Accelerator (IPA) is a programmable protocol
processor HW block. It is designed to support generic HW processing
of UL/DL IP packets for various use cases independent of radio technology.
Required properties:
IPA node:
- compatible : "qcom,ipa"
- reg: Specifies the base physical addresses and the sizes of the IPA
registers.
- reg-names: "ipa-base" - string to identify the IPA CORE base registers.
"bam-base" - string to identify the IPA BAM base registers.
"a2-bam-base" - string to identify the A2 BAM base registers.
- interrupts: Specifies the interrupt associated with IPA.
- interrupt-names: "ipa-irq" - string to identify the IPA core interrupt.
"bam-irq" - string to identify the IPA BAM interrupt.
"a2-bam-irq" - string to identify the A2 BAM interrupt.
- qcom,ipa-hw-ver: Specifies the IPA hardware version.
IPA pipe sub nodes (A2 static pipes configurations):
-label: two labels are supported, a2-to-ipa and ipa-to-a2 which
supply static configuration for A2-IPA connection.
-qcom,src-bam-physical-address: The physical address of the source BAM
-qcom,ipa-bam-mem-type:The memory type:
0(Pipe memory), 1(Private memory), 2(System memory)
-qcom,src-bam-pipe-index: Source pipe index
-qcom,dst-bam-physical-address: The physical address of the
destination BAM
-qcom,dst-bam-pipe-index: Destination pipe index
-qcom,data-fifo-offset: Data fifo base offset
-qcom,data-fifo-size: Data fifo size (bytes)
-qcom,descriptor-fifo-offset: Descriptor fifo base offset
-qcom,descriptor-fifo-size: Descriptor fifo size (bytes)
Optional properties:
-qcom,ipa-pipe-mem: Specifies the base physical address and the
size of the IPA pipe memory region.
Pipe memory is a feature which may be supported by the
target (HW platform). The Driver support using pipe
memory instead of system memory. In case this property
will not appear in the IPA DTS entry, the driver will
use system memory.
Example:
qcom,ipa@fd4c0000 {
compatible = "qcom,ipa";
reg = <0xfd4c0000 0x26000>,
<0xfd4c4000 0x14818>;
<0xfc834000 0x7000>;
reg-names = "ipa-base", "bam-base"; "a2-bam-base";
interrupts = <0 252 0>,
<0 253 0>;
<0 29 1>;
interrupt-names = "ipa-irq", "bam-irq"; "a2-bam-irq";
qcom,ipa-hw-ver = <1>;
qcom,pipe1 {
label = "a2-to-ipa";
qcom,src-bam-physical-address = <0xfc834000>;
qcom,ipa-bam-mem-type = <0>;
qcom,src-bam-pipe-index = <1>;
qcom,dst-bam-physical-address = <0xfd4c0000>;
qcom,dst-bam-pipe-index = <6>;
qcom,data-fifo-offset = <0x1000>;
qcom,data-fifo-size = <0xd00>;
qcom,descriptor-fifo-offset = <0x1d00>;
qcom,descriptor-fifo-size = <0x300>;
};
qcom,pipe2 {
label = "ipa-to-a2";
qcom,src-bam-physical-address = <0xfd4c0000>;
qcom,ipa-bam-mem-type = <0>;
qcom,src-bam-pipe-index = <7>;
qcom,dst-bam-physical-address = <0xfc834000>;
qcom,dst-bam-pipe-index = <0>;
qcom,data-fifo-offset = <0x00>;
qcom,data-fifo-size = <0xd00>;
qcom,descriptor-fifo-offset = <0xd00>;
qcom,descriptor-fifo-size = <0x300>;
};
};

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kernel/Documentation/devicetree/bindings/platform/msm/qpnp-clkdiv.txt Normal file
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* qpnp-clkdiv
clkdiv configures the clock frequency of a set of outputs on the PMIC.
These clocks are typically wired through alternate functions on
gpio pins.
Required properties :
- reg : The address and size of the peripheral. Size should be 0x1000, and the
address may vary.
- qcom,cxo-freq : The frequency of the cxo clock in Hz.
Optional properties :
- qcom,cxo-div : Integer to divide the CXO clock by when constructing the
output frequency. Please see the definitions in
include/linux/qpnp-clkdiv.h to choose the appropriate value.
- qcom,enable : 0 == disable clock output
1 == enable clock output.
Note: if an optional property is not specified, no device configuration will
occur at probe time.
Client required properties :
- <consumer name>-clk : A phandle to the corresponding divclk device. The
consumer name refers to the name that will be
passed to qpnp_clkdiv_get(), and allows for a
client specific name to be associated with each
divclk.
Clkdiv device example :
...
pm8941_clkdiv1: clkdiv@5b00 {
reg = <0x5b00 0x1000>;
qcom,cxo-freq = <19200000>;
qcom,cxo-div = <1>;
qcom,enable = <1>;
};
Client device example :
...
client {
my-clk = &pm8941_clkdiv1;
};

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kernel/Documentation/devicetree/bindings/platform/msm/qpnp-coincell.txt Normal file
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Qualcomm QPNP Coincell - coincell battery charger devices
Required properties:
- compatible: Must be "qcom,qpnp-coincell".
- reg: Specifies the SPMI address and size for this coincell device.
Required structure:
- A qcom,qpnp-coincell node must be a child of an SPMI node that has specified
the spmi-slave-container property.
Optional properties:
- qcom,rset-ohms: Specifies the resistance of the current limiting
resistor in ohms. Four values are supported:
800, 1200, 1700, and 2100.
- qcom,vset-millivolts: Specifies the coincell charging voltage in millivolts.
Four values are supported: 2500, 3000, 3100, and 3200.
- qcom,charge-enable: Specifies if coincell charging should be enabled or not.
0 = disable charging, 1 = enabled charging
If any of the optional properties are not specified, then the hardware default
values for the unspecified properties will be used instead.
Example:
qcom,spmi@fc4c0000 {
#address-cells = <1>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <3>;
qcom,pm8941@1 {
spmi-slave-container;
reg = <0x1>;
#address-cells = <1>;
#size-cells = <1>;
qcom,coincell@2800 {
compatible = "qcom,qpnp-coincell";
reg = <0x2800 0x100>;
qcom,rset-ohms = <800>;
qcom,vset-millivolts = <3100>;
qcom,charge-enable = <1>;
};
};
};

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kernel/Documentation/devicetree/bindings/platform/msm/qpnp-power-on.txt Normal file
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Qualcomm QPNP power-on
The qpnp-power-on is a driver which supports the power-on(PON)
peripheral on Qualcomm PMICs. The supported functionality includes
power on/off reason, key press/release detection, PMIC reset configurations
and other PON specifc features. The PON module supports multiple physical
power-on (KPDPWR_N, CBLPWR) and reset (KPDPWR_N, RESIN, KPDPWR+RESIN) sources.
This peripheral is connected to the host processor via the SPMI interface.
Required properties:
- compatible: Must be "qcom,qpnp-power-on"
- reg: Specifies the SPMI address and size for this PON (power-on) peripheral
- interrupts: Specifies the interrupt associated with PON.
- interrupt-names: Specify the interrupt names associated with interrupts. Must be
one of "kpdpwr", "kpdpwr-bark", "resin", "resin-bark", "cblpwr".
Bark interrupts are associated with system reset configuration
to allow default reset configuration to be activated. If system
reset configuration is not supported then bark interrupts are
nops.
Optional properties:
- qcom,pon-dbc-delay The debounce delay for the power-key interrupt
specified in us. The value ranges from 2 seconds
to 1/64 of a second. Possible values are -
- 2, 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64
- Intermediate value is rounded down to the
nearest valid value.
- qcom,pon_1 ...pon_n These represent the child nodes which describe
the properties (reset, key) for each of the pon
reset source. All the child nodes are optional.
If none of them is specified, the driver fails
to register.
- qcom,system-reset Specifies that this PON peripheral can be used
to reset the system. This property can only be
used by one device on the system. It is an error
to include it more than once.
All the below properties are in the sub-node section (properties of the child
node).
Sub-node required properties:
- qcom,pon-type The type of PON/RESET source. The driver
currently supports KPDPWR(0), RESIN(1) and
CBLPWR(2) pon/reset sources.
Sub-node optional properties:
- qcom,pull-up The initial state of the reset pin under
consideration.
0 = No pull-up
1 = pull-up enabled
This property is set to '0' if not specified.
- qcom,support-reset Indicates if this PON source supports
reset functionality.
0 = Not supported
1 = Supported
This property is set to '0' if not specified.
- qcom,s1-timer The debounce timer for the BARK interrupt for
that reset source. Value is specified in ms.
Supported values are -
- 0, 32, 56, 80, 128, 184, 272, 408, 608, 904
1352, 2048, 3072, 4480, 6720, 10256
This property must be specified only if
'support-reset' is set to 1.
- qcom,s2-timer The debounce timer for the S2 reset specified
in ms. On the expiry of this timer, the PMIC
executes the reset sequence. Supported values -
- 0, 10, 50, 100, 250, 500, 1000, 2000
This property is required only if
'support-reset' is set to 1.
- qcom,s2-type The type of reset associated with this source.
The supported resets are -
SOFT(0), WARM(1), SHUTDOWN(4), HARD(7)
This property is required only if
'support-reset' is set to 1.
- linux,code The input key-code associated with the reset source.
The reset source in its default configuration can be
used to support standard keys.
Example:
qcom,power-on@800 {
compatible = "qcom,qpnp-power-on";
reg = <0x800 0x100>;
interrupts = <0x0 0x8 0x0>,
<0x0 0x8 0x1>,
<0x0 0x8 0x4>;
interrupt-names = "kpdpwr", "resin", "resin-bark";
qcom,pon-dbc-delay = <15625>;
qcom,pon_1 {
qcom,pon-type = <0>;
qcom,pull-up = <1>;
linux,code = <116>;
};
qcom,pon_2 {
qcom,pon-type = <1>;
qcom,support-reset = <1>;
qcom,pull-up = <1>;
qcom,s1-timer = <3072>;
qcom,s2-timer = <2000>;
qcom,s2-type = <1>;
linux,code = <114>;
};
}

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kernel/Documentation/devicetree/bindings/platform/msm/qpnp-revid.txt Normal file
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QPNP-REVID
QPNP-REVID provides a way to read the PMIC part number and revision.
Required properties:
- compatible : should be "qcom,qpnp-revid"
- reg : offset and length of the PMIC peripheral register map.
Example:
qcom,revid@100 {
compatible = "qcom,qpnp-revid";
reg = <0x100 0x100>;
};

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kernel/Documentation/devicetree/bindings/platform/msm/qpnp-vibrator.txt Normal file
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QPNP Vibrator
QPNP (Qualcomm Plug N Play) vibrator is a peripheral on
Qualcomm PMICs. The PMIC is connected to Host processor
via SPMI bus.
Required Properties:
- status: default status is set to "disabled. Must be "okay"
- compatible: must be "qcom,qpnp-vibrator"
- label: name which describes the device
- reg: address of device
Optional Properties:
- qcom,vib-timeout-ms: timeout of vibrator, in ms. Default 15000 ms
- qcom,vib-vtg-level-mV: voltage level, in mV. Default 3100 mV
Example:
qcom,vib@c000 {
status = "okay";
compatible = "qcom,qpnp-vibrator";
reg = <0xc000 0x100>;
label = "vibrator";
qcom,vib-timeout-ms = <15000>;
qcom,vib-vtg-level-mV = <3100>;
};

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kernel/Documentation/devicetree/bindings/platform/msm/ssm.txt Normal file
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* Qualcomm Secure Service Module (SSM)
SSM provides an interface for OEM driver to communicate with Modem and
trustzone.
This module provides following features:
- Keyexchange between Modem and trustzone for encryption/Decryption
of mode information
- Interface to third party driver to send mode updates to modem
- Interface for loading the trustzone application
Required properties:
- compatible: Must be "qcom,ssm"
Optional properties:
- qcom,channel-name: Name of the SMD channel used for communication
between MODEM and SSM driver.
- qcom,need-keyexhg This property controls initial key exchange
between APPS(application processor) and MODEM.
If not mentioned the initial key exchange is
not required.
If this property is mentioned then it is mandatory
for modem to perform initial key exchange with APPS.
Example:
qcom,ssm {
compatible = "qcom,ssm";
qcom,channel-name = "SSM_RTR";
qcom,need-keyexhg;
}