M7350v1_en_gpl

kernel/Documentation/devicetree/bindings/mmc/fsl-esdhc.txt

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+* Freescale Enhanced Secure Digital Host Controller (eSDHC)
+
+The Enhanced Secure Digital Host Controller provides an interface
+for MMC, SD, and SDIO types of memory cards.
+
+Required properties:
+  - compatible : should be
+    "fsl,<chip>-esdhc", "fsl,esdhc"
+  - reg : should contain eSDHC registers location and length.
+  - interrupts : should contain eSDHC interrupt.
+  - interrupt-parent : interrupt source phandle.
+  - clock-frequency : specifies eSDHC base clock frequency.
+  - sdhci,wp-inverted : (optional) specifies that eSDHC controller
+    reports inverted write-protect state;
+  - sdhci,1-bit-only : (optional) specifies that a controller can
+    only handle 1-bit data transfers.
+  - sdhci,auto-cmd12: (optional) specifies that a controller can
+    only handle auto CMD12.
+
+Example:
+
+sdhci@2e000 {
+	compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
+	reg = <0x2e000 0x1000>;
+	interrupts = <42 0x8>;
+	interrupt-parent = <&ipic>;
+	/* Filled in by U-Boot */
+	clock-frequency = <0>;
+};

kernel/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt

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+* Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
+
+The Enhanced Secure Digital Host Controller on Freescale i.MX family
+provides an interface for MMC, SD, and SDIO types of memory cards.
+
+Required properties:
+- compatible : Should be "fsl,<chip>-esdhc"
+- reg : Should contain eSDHC registers location and length
+- interrupts : Should contain eSDHC interrupt
+
+Optional properties:
+- fsl,card-wired : Indicate the card is wired to host permanently
+- fsl,cd-internal : Indicate to use controller internal card detection
+- fsl,wp-internal : Indicate to use controller internal write protection
+- cd-gpios : Specify GPIOs for card detection
+- wp-gpios : Specify GPIOs for write protection
+
+Examples:
+
+esdhc@70004000 {
+	compatible = "fsl,imx51-esdhc";
+	reg = <0x70004000 0x4000>;
+	interrupts = <1>;
+	fsl,cd-internal;
+	fsl,wp-internal;
+};
+
+esdhc@70008000 {
+	compatible = "fsl,imx51-esdhc";
+	reg = <0x70008000 0x4000>;
+	interrupts = <2>;
+	cd-gpios = <&gpio0 6 0>; /* GPIO1_6 */
+	wp-gpios = <&gpio0 5 0>; /* GPIO1_5 */
+};

kernel/Documentation/devicetree/bindings/mmc/mmc-spi-slot.txt

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+MMC/SD/SDIO slot directly connected to a SPI bus
+
+Required properties:
+- compatible : should be "mmc-spi-slot".
+- reg : should specify SPI address (chip-select number).
+- spi-max-frequency : maximum frequency for this device (Hz).
+- voltage-ranges : two cells are required, first cell specifies minimum
+  slot voltage (mV), second cell specifies maximum slot voltage (mV).
+  Several ranges could be specified.
+
+Optional properties:
+- gpios : may specify GPIOs in this order: Card-Detect GPIO,
+  Write-Protect GPIO.
+- interrupts : the interrupt of a card detect interrupt.
+- interrupt-parent : the phandle for the interrupt controller that
+  services interrupts for this device.
+
+Example:
+
+	mmc-slot@0 {
+		compatible = "fsl,mpc8323rdb-mmc-slot",
+			     "mmc-spi-slot";
+		reg = <0>;
+		gpios = <&qe_pio_d 14 1
+			 &qe_pio_d 15 0>;
+		voltage-ranges = <3300 3300>;
+		spi-max-frequency = <50000000>;
+		interrupts = <42>;
+		interrupt-parent = <&PIC>;
+	};

kernel/Documentation/devicetree/bindings/mmc/msm_sdcc.txt

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+Qualcomm Secure Digital Card Controller (SDCC)
+
+Secure Digital Card Controller provides host interface to
+SD/MMC/SDIO cards.
+
+Required properties:
+  - compatible: should be "qcom,msm-sdcc"
+  - reg: should contain SDCC (mandatory), SDCC-DML (optional) and BAM
+    (optional) register maps.
+  - reg-names: indicates various resources passed to driver (via reg
+    property) by name. "reg-names" examples are "core_mem", "dml_mem"
+    and "bam_mem". "dml_mem" and "bam_mem" are optional, and the SDCC
+    driver will default to PIO mode when neither are present.
+  - interrupts: should contain SDCC core interrupt.
+  - interrupt-names: indicates interrupts passed to driver (via interrupts
+    property) by name. "core_irq" is mandatory, "bam_irq" is mandatory only
+    when BAM DMA engine is used. "status_irq" and "sdiowakeup_irq" are
+    optional.
+  - qcom,clk-rates: specifies supported SDCC clock frequencies, Units - Hz.
+  - qcom,sup-voltages: specifies supported voltage ranges for card. Should
+    always be specified in pairs (min, max), Units - mV.
+  - <supply-name>-supply: phandle to the regulator device tree node.
+    "supply-name" examples are "vdd", "vdd-io".
+
+Optional Properties:
+  - cell-index: defines slot ID.
+  - qcom,bus-width: defines the bus I/O width that controller supports.
+  - wp-gpios: specify GPIO for write protect switch detection.
+  - cd-gpios: specify GPIO for card detection.
+  - qcom,nonremovable: specifies whether the card in slot is hot pluggable
+    or hard wired.
+  - qcom,disable-cmd23: disable sending CMD23 to card when controller
+    can't support it.
+  - qcom,bus-speed-mode: specifies supported bus speed modes by host.
+  - qcom,current-limit: specifies max. current the host can drive.
+  - qcom,xpc: specifies if the host can supply more than 150mA for SDXC
+    cards.
+  - qcom,dat1-mpm-int: specifies MPM interrupt number corresponding to
+    DAT1 line of SDCC (used only if slot has dedicated DAT1 MSM pin
+    (not GPIO))
+
+In the following, <supply> can be vdd (flash core voltage) or vdd-io
+(I/O voltage).
+  - qcom,<supply>-always-on: specifies whether supply should be kept "on"
+    always.
+  - qcom,<supply>-lpm-sup: specifies whether supply can be kept in low
+    power mode (lpm).
+  - qcom,<supply>-voltage-level: specifies voltage levels for supply.
+    Should be specified in pairs (min, max), units uV.
+  - qcom,<supply>-current-level: specifies load levels for supply in
+    lpm or high power mode (hpm). Should be specified in pairs (lpm, hpm),
+    units uA.
+
+  - gpios: specifies gpios assigned for sdcc slot.
+  - qcom,gpio-names:  a list of strings that map in order to the list
+    of gpios. A slot has either gpios or dedicated tlmm pins as represented
+    below.
+  - qcom,pad-pull-on: Active pull configuration for sdc tlmm pins
+  - qcom,pad-pull-off: Suspend pull configuration for sdc tlmm pins.
+  - qcom,pad-drv-on: Active drive strength configuration for sdc tlmm pins.
+  - qcom,pad-drv-off: Suspend drive strength configuration for sdc tlmm pins.
+    Tlmm pins are specified as <clk cmd data>
+
+  - qcom,bus-bw-vectors-bps: specifies array of throughput values in
+    Bytes/sec. The values in the array are determined according to
+    supported bus speed modes. For example, if host supports SDR12 mode,
+    value is 13631488 Bytes/sec.
+  - Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for
+    below optional properties:
+	- qcom,msm-bus,name
+	- qcom,msm-bus,num-cases
+	- qcom,msm-bus,active-only
+	- qcom,msm-bus,num-paths
+	- qcom,msm-bus,vectors-KBps
+
+Example:
+
+	qcom,sdcc@f9600000 {
+	/* SDC1 used as eMMC slot */
+	cell-index = <1>;
+	compatible = "qcom,msm-sdcc";
+	reg = <0xf9600000 0x800   // SDCC register interface
+	/* To use PIO instead of BAM, skip DML and BAM regs */
+		0xf9600800 0x1800  // DML register interface
+		0xf9602000 0x2000> // BAM register interface
+
+	interrupts = <123>;
+	qcom,clk-rates = <400000 24000000 48000000>;
+	qcom,sup-voltages = <2700 3300>;
+	qcom,bus-width = <8>; //8-bit wide
+	qcom,nonremovable;
+
+	qcom,msm-bus,name = "sdcc2";
+	qcom,msm-bus,num-cases = <7>;
+	qcom,msm-bus,num-paths = <1>;
+	qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
+			<81 512 6656 13312>, /* 13 MB/s*/
+			<81 512 13312 26624>, /* 26 MB/s */
+			<81 512 26624 53248>, /* 52 MB/s */
+			<81 512 53248 106496>, /* 104 MB/s */
+			<81 512 106496 212992>, /* 208 MB/s */
+			<81 512 2147483647 4294967295>; /* Max. bandwidth */
+	qcom,bus-bw-vectors-bps = <0 13631488 27262976 54525952 109051904 218103808 4294967295>;
+};

kernel/Documentation/devicetree/bindings/mmc/nvidia-sdhci.txt

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+* NVIDIA Tegra Secure Digital Host Controller
+
+This controller on Tegra family SoCs provides an interface for MMC, SD,
+and SDIO types of memory cards.
+
+Required properties:
+- compatible : Should be "nvidia,<chip>-sdhci"
+- reg : Should contain SD/MMC registers location and length
+- interrupts : Should contain SD/MMC interrupt
+
+Optional properties:
+- cd-gpios : Specify GPIOs for card detection
+- wp-gpios : Specify GPIOs for write protection
+- power-gpios : Specify GPIOs for power control
+- support-8bit : Boolean, indicates if 8-bit mode should be used.
+
+Example:
+
+sdhci@c8000200 {
+	compatible = "nvidia,tegra20-sdhci";
+	reg = <0xc8000200 0x200>;
+	interrupts = <47>;
+	cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+	wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+	power-gpios = <&gpio 155 0>; /* gpio PT3 */
+	support-8bit;
+};

kernel/Documentation/devicetree/bindings/mmc/sdhci-msm.txt

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+Qualcomm Standard Secure Digital Host Controller (SDHC)
+
+Secure Digital Host Controller provides standard host interface to SD/MMC/SDIO cards.
+
+Required properties:
+  - compatible : should be "qcom,sdhci-msm"
+  - reg : should contain SDHC, SD Core register map.
+  - reg-names : indicates various resources passed to driver (via reg proptery) by name.
+		Required "reg-names" are "hc_mem" and "core_mem"
+  - interrupts : should contain SDHC interrupts.
+  - interrupt-names : indicates interrupts passed to driver (via interrupts property) by name.
+		      Required "interrupt-names" are "hc_irq" and "pwr_irq".
+  - <supply-name>-supply: phandle to the regulator device tree node
+			  Required "supply-name" are "vdd" and "vdd-io".
+  - qcom,clk-rates: this is an array that specifies supported SDHC clock
+		    frequencies for a slot, Units - Hz.
+
+Required alias:
+- The slot number is specified via an alias with the following format
+	'sdhc{n}' where n is the slot number.
+
+Optional Properties:
+	- interrupt-names - "status_irq". This status_irq will be used for card
+			     detection.
+	- cd-gpios: specify GPIO for card detection. If this property is
+		    defined, then it means SDHC device has more than one interrupt
+		    parent and hence, it is required to define the following properties
+		    to configure interrupts from multiple parents -
+
+		    interrupt-parent - This must provide reference to the current
+				       device node.
+		    #address-cells - Should provide a value of 0.
+		    interrupts - Should be <0 1 2> and it is an index to the
+				 interrupt-map.
+		    #interrupt-cells - should provide a value of 1.
+		    #interrupt-mask - should provide a value of 0xffffffff.
+		    interrupt-map - Must create mapping for the number of interrupts
+				    that are defined in above interrupts property.
+				    For SDHC device node, it must define 3 mappings for
+				    hc_irq, pwr_irq and status_irq in the format
+				    mentioned in below example node of sdhc_2.
+
+	- qcom,bus-width - defines the bus I/O width that controller supports.
+			   Units - number of bits. The valid bus-width values are
+			   1, 4 and 8.
+	- qcom,nonremovable - specifies whether the card in slot is
+			      hot pluggable or hard wired.
+	- qcom,bus-speed-mode - specifies supported bus speed modes by host.
+				The supported bus speed modes are :
+				"HS200_1p8v" - indicates that host can support HS200 at 1.8v.
+				"HS200_1p2v" - indicates that host can support HS200 at 1.2v.
+				"DDR_1p8v" - indicates that host can support DDR mode at 1.8v.
+				"DDR_1p2v" - indicates that host can support DDR mode at 1.2v.
+	- qcom,cpu-dma-latency-us: specifies acceptable DMA latency in microseconds. There is
+				   no default value that the driver assumes if this property
+				   is not specified. So if this property is not specified,
+				   then SDHC driver will not vote for PM QOS.
+
+In the following, <supply> can be vdd (flash core voltage) or vdd-io (I/O voltage).
+	- qcom,<supply>-always-on - specifies whether supply should be kept "on" always.
+	- qcom,<supply>-lpm_sup - specifies whether supply can be kept in low power mode (lpm).
+	- qcom,<supply>-voltage_level - specifies voltage levels for supply. Should be
+					specified in pairs (min, max), units uV.
+	- qcom,<supply>-current_level - specifies load levels for supply in lpm or
+					high power mode (hpm). Should be specified in
+					pairs (lpm, hpm), units uA.
+
+	- gpios - specifies gpios assigned for sdhc slot.
+	- qcom,gpio-names -  a list of strings that map in order to the list of gpios
+
+	A slot has either gpios or dedicated tlmm pins as represented below.
+	- qcom,pad-pull-on - Active pull configuration for sdc tlmm pins
+	- qcom,pad-pull-off - Suspend pull configuration for sdc tlmm pins.
+	- qcom,pad-drv-on - Active drive strength configuration for sdc tlmm pins.
+	- qcom,pad-drv-off - Suspend drive strength configuration for sdc tlmm pins.
+	Tlmm pins are specified as <clk cmd data>
+
+	- qcom,bus-bw-vectors-bps: specifies array of throughput values in
+	Bytes/sec. The values in the array are determined according to
+	supported bus speed modes. For example, if host supports SDR12 mode,
+	value is 13631488 Bytes/sec.
+	- Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for
+	below optional properties:
+	- qcom,msm-bus,name
+	- qcom,msm-bus,num-cases
+	- qcom,msm-bus,active-only
+	- qcom,msm-bus,num-paths
+	- qcom,msm-bus,vectors-KBps
+
+Example:
+
+	aliases {
+		sdhc1 = &sdhc_1;
+		sdhc2 = &sdhc_2;
+	};
+
+	sdhc_1: qcom,sdhc@f9824900 {
+		compatible = "qcom,sdhci-msm";
+                reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
+                reg-names = "hc_mem", "core_mem";
+                interrupts = <0 123 0>, <0 138 0>;
+                interrupt-names = "hc_irq", "pwr_irq";
+
+		vdd-supply = <&pm8941_l21>;
+		vdd-io-supply = <&pm8941_l13>;
+		qcom,vdd-voltage-level = <2950000 2950000>;
+		qcom,vdd-current-level = <9000 800000>;
+
+		qcom,vdd-io-always-on;
+		qcom,vdd-io-lpm-sup;
+		qcom,vdd-io-voltage-level = <1800000 2950000>;
+		qcom,vdd-io-current-level = <6 22000>;
+
+                qcom,bus-width = <4>;
+		qcom,nonremovable;
+		qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
+		qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>;
+
+		gpios = <&msmgpio 40 0>, /* CLK */
+			<&msmgpio 39 0>, /* CMD */
+			<&msmgpio 38 0>, /* DATA0 */
+			<&msmgpio 37 0>, /* DATA1 */
+			<&msmgpio 36 0>, /* DATA2 */
+			<&msmgpio 35 0>; /* DATA3 */
+		qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3";
+	};
+
+	sdhc_2: qcom,sdhc@f98a4900 {
+		compatible = "qcom,sdhci-msm";
+                reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
+                reg-names = "hc_mem", "core_mem";
+
+		#address-cells = <0>;
+		interrupt-parent = <&sdhc_2>;
+		interrupts = <0 1 2>;
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0xffffffff>;
+		interrupt-map = <0 &intc 0 125 0
+				1 &intc 0 221 0
+				2 &msmgpio 62 0x3>;
+                interrupt-names = "hc_irq", "pwr_irq", "status_irq";
+		cd-gpios = <&msmgpio 62 0x1>;
+
+		vdd-supply = <&pm8941_l21>;
+		vdd-io-supply = <&pm8941_l13>;
+
+                qcom,bus-width = <4>;
+		qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>;
+
+		qcom,pad-pull-on = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
+		qcom,pad-pull-off = <0x0 0x3 0x3>; /* no-pull, pull-up, pull-up */
+		qcom,pad-drv-on = <0x7 0x4 0x4>; /* 16mA, 10mA, 10mA */
+		qcom,pad-drv-off = <0x0 0x0 0x0>; /* 2mA, 2mA, 2mA */
+
+		qcom,cpu-dma-latency-us = <200>;
+		qcom,msm-bus,name = "sdhc2";
+		qcom,msm-bus,num-cases = <7>;
+		qcom,msm-bus,num-paths = <1>;
+		qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
+				<81 512 6656 13312>, /* 13 MB/s*/
+				<81 512 13312 26624>, /* 26 MB/s */
+				<81 512 26624 53248>, /* 52 MB/s */
+				<81 512 53248 106496>, /* 104 MB/s */
+				<81 512 106496 212992>, /* 208 MB/s */
+				<81 512 2147483647 4294967295>; /* Max. bandwidth */
+		qcom,bus-bw-vectors-bps = <0 13631488 27262976 54525952 109051904 218103808 4294967295>;
+	};

kernel/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt

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+* TI Highspeed MMC host controller for OMAP
+
+The Highspeed MMC Host Controller on TI OMAP family
+provides an interface for MMC, SD, and SDIO types of memory cards.
+
+Required properties:
+- compatible:
+ Should be "ti,omap2-hsmmc", for OMAP2 controllers
+ Should be "ti,omap3-hsmmc", for OMAP3 controllers
+ Should be "ti,omap4-hsmmc", for OMAP4 controllers
+- ti,hwmods: Must be "mmc<n>", n is controller instance starting 1
+- reg : should contain hsmmc registers location and length
+
+Optional properties:
+ti,dual-volt: boolean, supports dual voltage cards
+<supply-name>-supply: phandle to the regulator device tree node
+"supply-name" examples are "vmmc", "vmmc_aux" etc
+ti,bus-width: Number of data lines, default assumed is 1 if the property is missing.
+cd-gpios: GPIOs for card detection
+wp-gpios: GPIOs for write protection
+ti,non-removable: non-removable slot (like eMMC)
+ti,needs-special-reset: Requires a special softreset sequence
+
+Example:
+	mmc1: mmc@0x4809c000 {
+		compatible = "ti,omap4-hsmmc";
+		reg = <0x4809c000 0x400>;
+		ti,hwmods = "mmc1";
+		ti,dual-volt;
+		ti,bus-width = <4>;
+		vmmc-supply = <&vmmc>; /* phandle to regulator node */
+		ti,non-removable;
+	};