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60
kernel/Documentation/devicetree/bindings/gpio/8xxx_gpio.txt Normal file
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GPIO controllers on MPC8xxx SoCs
This is for the non-QE/CPM/GUTs GPIO controllers as found on
8349, 8572, 8610 and compatible.
Every GPIO controller node must have #gpio-cells property defined,
this information will be used to translate gpio-specifiers.
Required properties:
- compatible : "fsl,<CHIP>-gpio" followed by "fsl,mpc8349-gpio" for
83xx, "fsl,mpc8572-gpio" for 85xx and "fsl,mpc8610-gpio" for 86xx.
- #gpio-cells : Should be two. The first cell is the pin number and the
second cell is used to specify optional parameters (currently unused).
- interrupts : Interrupt mapping for GPIO IRQ.
- interrupt-parent : Phandle for the interrupt controller that
services interrupts for this device.
- gpio-controller : Marks the port as GPIO controller.
Example of gpio-controller nodes for a MPC8347 SoC:
gpio1: gpio-controller@c00 {
#gpio-cells = <2>;
compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
reg = <0xc00 0x100>;
interrupts = <74 0x8>;
interrupt-parent = <&ipic>;
gpio-controller;
};
gpio2: gpio-controller@d00 {
#gpio-cells = <2>;
compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio";
reg = <0xd00 0x100>;
interrupts = <75 0x8>;
interrupt-parent = <&ipic>;
gpio-controller;
};
See booting-without-of.txt for details of how to specify GPIO
information for devices.
To use GPIO pins as interrupt sources for peripherals, specify the
GPIO controller as the interrupt parent and define GPIO number +
trigger mode using the interrupts property, which is defined like
this:
interrupts = <number trigger>, where:
- number: GPIO pin (0..31)
- trigger: trigger mode:
2 = trigger on falling edge
3 = trigger on both edges
Example of device using this is:
funkyfpga@0 {
compatible = "funky-fpga";
...
interrupts = <4 3>;
interrupt-parent = <&gpio1>;
};

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kernel/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.txt Normal file
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* Freescale i.MX/MXC GPIO controller
Required properties:
- compatible : Should be "fsl,<soc>-gpio"
- reg : Address and length of the register set for the device
- interrupts : Should be the port interrupt shared by all 32 pins, if
one number. If two numbers, the first one is the interrupt shared
by low 16 pins and the second one is for high 16 pins.
- gpio-controller : Marks the device node as a gpio controller.
- #gpio-cells : Should be two. The first cell is the pin number and
the second cell is used to specify optional parameters (currently
unused).
Example:
gpio0: gpio@73f84000 {
compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
reg = <0x73f84000 0x4000>;
interrupts = <50 51>;
gpio-controller;
#gpio-cells = <2>;
};

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kernel/Documentation/devicetree/bindings/gpio/gpio-msm.txt Normal file
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MSM GPIO controller bindings
Required properties:
- compatible:
- "qcom,msm-gpio" for MSM controllers
- #gpio-cells : Should be two.
- first cell is the pin number
- second cell is used to specify optional parameters (unused)
- gpio-controller : Marks the device node as a GPIO controller.
- #interrupt-cells : Should be 2.
- interrupt-controller: Mark the device node as an interrupt controller
- interrupts : Specify the TLMM summary interrupt number
- ngpio : Specify the number of MSM GPIOs
- qcom,direct-connect-irqs : Specifies the number of GPIOs that can be used as
direct connect interrupts
Example:
msmgpio: gpio@fd510000 {
compatible = "qcom,msm-gpio";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0xfd510000 0x4000>;
interrupts = <0 208 0>;
ngpio = <150>;
qcom,direct-connect-irqs = <8>;
};
To specify gpios for a device:
device1@f991f000 {
compatible = "qcom,msm-device-v1";
reg = <0xf991f000 0x1000>;
gpios = <&msmgpio 45 0>;
cs-gpios = <&msmgpio 46 0>;
};
45, 46 - gpio numbers.
The driver for device1 can call of_get_gpio() to extract the
gpio45. In order to extract gpio46, the driver needs to call
of_get_named_gpio with "cs-gpios" as the name parameter.
Please refer to the file: include/linux/of_gpio.h for the
complete list of APIs the driver can use to extract gpio
information from the device tree.

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kernel/Documentation/devicetree/bindings/gpio/gpio-omap.txt Normal file
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OMAP GPIO controller bindings
Required properties:
- compatible:
- "ti,omap2-gpio" for OMAP2 controllers
- "ti,omap3-gpio" for OMAP3 controllers
- "ti,omap4-gpio" for OMAP4 controllers
- #gpio-cells : Should be two.
- first cell is the pin number
- second cell is used to specify optional parameters (unused)
- gpio-controller : Marks the device node as a GPIO controller.
- #interrupt-cells : Should be 2.
- interrupt-controller: Mark the device node as an interrupt controller
The first cell is the GPIO number.
The second cell is used to specify flags:
bits[3:0] trigger type and level flags:
1 = low-to-high edge triggered.
2 = high-to-low edge triggered.
4 = active high level-sensitive.
8 = active low level-sensitive.
OMAP specific properties:
- ti,hwmods: Name of the hwmod associated to the GPIO:
"gpio<X>", <X> being the 1-based instance number from the HW spec
Example:
gpio4: gpio4 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio4";
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};

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Samsung Exynos4 GPIO Controller
Required properties:
- compatible: Compatible property value should be "samsung,exynos4-gpio>".
- reg: Physical base address of the controller and length of memory mapped
region.
- #gpio-cells: Should be 4. The syntax of the gpio specifier used by client nodes
should be the following with values derived from the SoC user manual.
<[phandle of the gpio controller node]
[pin number within the gpio controller]
[mux function]
[pull up/down]
[drive strength]>
Values for gpio specifier:
- Pin number: is a value between 0 to 7.
- Pull Up/Down: 0 - Pull Up/Down Disabled.
1 - Pull Down Enabled.
3 - Pull Up Enabled.
- Drive Strength: 0 - 1x,
1 - 3x,
2 - 2x,
3 - 4x
- gpio-controller: Specifies that the node is a gpio controller.
- #address-cells: should be 1.
- #size-cells: should be 1.
Example:
gpa0: gpio-controller@11400000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "samsung,exynos4-gpio";
reg = <0x11400000 0x20>;
#gpio-cells = <4>;
gpio-controller;
};

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Qualcomm SMSM Point-to-Point (SMP2P) GPIO Driver
Used to map an SMP2P entry and remote processor ID to a virtual GPIO controller
and virtual interrupt controller.
Required properties:
-compatible : should be "qcom,smp2pgpio";
-qcom,entry-name : name of the SMP2P entry
-qcom,remote-pid : the SMP2P remote processor ID (see smp2p_private_api.h)
-gpio-controller : specifies that this is a GPIO controller
-#gpio-cells : number of GPIO cells (should always be <2>)
-interrupt-controller : specifies that this is an interrupt controller
-#interrupt-cells : number of interrupt cells (should always be <2>)
Optional properties:
-qcom,is-inbound : specifies that this is an inbound entry (default is outbound)
Comments:
All device tree entries must be unique. Therefore to prevent naming collisions
between clients, it is recommended that the DT nodes should be named using the
format:
smp2pgpio_<ENTRY_NAME>_<REMOTE PID>_<in|out>
Example:
/* Maps inbound "smp2p" entry on remote PID 7 to GPIO controller. */
smp2pgpio_smp2p_7_in: qcom,smp2pgpio-smp2p-7-in {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "smp2p";
qcom,remote-pid = <7>;
qcom,is-inbound;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
/*
* Maps inbound "smp2p" entry on remote PID 7 to client driver
* "qcom,smp2pgpio_test_smp2p_7_in".
*
* Note: If all 32-pins are used by this client, then you
* can just list pin 0 here as a shortcut.
*/
qcom,smp2pgpio_test_smp2p_7_in {
compatible = "qcom,smp2pgpio_test_smp2p_7_in";
gpios = <&smp2pgpio_smp2p_7_in 0 0>, /* pin 0 */
<&smp2pgpio_smp2p_7_in 1 0>,
. . .
<&smp2pgpio_smp2p_7_in 31 0>; /* pin 31 */
};
/* Maps outbound "smp2p" entry on remote PID 7 to GPIO controller. */
smp2pgpio_smp2p_7_out: qcom,smp2pgpio-smp2p-7-out {
compatible = "qcom,smp2pgpio";
qcom,entry-name = "smp2p";
qcom,remote-pid = <7>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
/*
* Maps outbound "smp2p" entry on remote PID 7 to client driver
* "qcom,smp2pgpio_test_smp2p_7_out".
*
* Note: If all 32-pins are used by this client, then you
* can just list pin 0 here as a shortcut.
*/
qcom,smp2pgpio_test_smp2p_7_out {
compatible = "qcom,smp2pgpio_test_smp2p_7_out";
gpios = <&smp2pgpio_smp2p_7_out 0 0>, /* pin 0 */
<&smp2pgpio_smp2p_7_out 1 0>,
. . .
<&smp2pgpio_smp2p_7_out 31 0>; /* pin 31 */
};

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twl4030 GPIO controller bindings
Required properties:
- compatible:
- "ti,twl4030-gpio" for twl4030 GPIO controller
- #gpio-cells : Should be two.
- first cell is the pin number
- second cell is used to specify optional parameters (unused)
- gpio-controller : Marks the device node as a GPIO controller.
- #interrupt-cells : Should be 2.
- interrupt-controller: Mark the device node as an interrupt controller
The first cell is the GPIO number.
The second cell is not used.
Example:
twl_gpio: gpio {
compatible = "ti,twl4030-gpio";
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};

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Specifying GPIO information for devices
============================================
1) gpios property
-----------------
Nodes that makes use of GPIOs should specify them using one or more
properties, each containing a 'gpio-list':
gpio-list ::= <single-gpio> [gpio-list]
single-gpio ::= <gpio-phandle> <gpio-specifier>
gpio-phandle : phandle to gpio controller node
gpio-specifier : Array of #gpio-cells specifying specific gpio
(controller specific)
GPIO properties should be named "[<name>-]gpios". Exact
meaning of each gpios property must be documented in the device tree
binding for each device.
For example, the following could be used to describe gpios pins to use
as chip select lines; with chip selects 0, 1 and 3 populated, and chip
select 2 left empty:
gpio1: gpio1 {
gpio-controller
#gpio-cells = <2>;
};
gpio2: gpio2 {
gpio-controller
#gpio-cells = <1>;
};
[...]
chipsel-gpios = <&gpio1 12 0>,
<&gpio1 13 0>,
<0>, /* holes are permitted, means no GPIO 2 */
<&gpio2 2>;
Note that gpio-specifier length is controller dependent. In the
above example, &gpio1 uses 2 cells to specify a gpio, while &gpio2
only uses one.
gpio-specifier may encode: bank, pin position inside the bank,
whether pin is open-drain and whether pin is logically inverted.
Exact meaning of each specifier cell is controller specific, and must
be documented in the device tree binding for the device.
Example of the node using GPIOs:
node {
gpios = <&qe_pio_e 18 0>;
};
In this example gpio-specifier is "18 0" and encodes GPIO pin number,
and empty GPIO flags as accepted by the "qe_pio_e" gpio-controller.
2) gpio-controller nodes
------------------------
Every GPIO controller node must both an empty "gpio-controller"
property, and have #gpio-cells contain the size of the gpio-specifier.
Example of two SOC GPIO banks defined as gpio-controller nodes:
qe_pio_a: gpio-controller@1400 {
#gpio-cells = <2>;
compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
reg = <0x1400 0x18>;
gpio-controller;
};
qe_pio_e: gpio-controller@1460 {
#gpio-cells = <2>;
compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
reg = <0x1460 0x18>;
gpio-controller;
};

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kernel/Documentation/devicetree/bindings/gpio/gpio_atmel.txt Normal file
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* Atmel GPIO controller (PIO)
Required properties:
- compatible: "atmel,<chip>-gpio", where <chip> is at91rm9200 or at91sam9x5.
- reg: Should contain GPIO controller registers location and length
- interrupts: Should be the port interrupt shared by all the pins.
- #gpio-cells: Should be two. The first cell is the pin number and
the second cell is used to specify optional parameters (currently
unused).
- gpio-controller: Marks the device node as a GPIO controller.
Example:
pioA: gpio@fffff200 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff200 0x100>;
interrupts = <2 4>;
#gpio-cells = <2>;
gpio-controller;
};

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Device-Tree bindings for i2c gpio driver
Required properties:
- compatible = "i2c-gpio";
- gpios: sda and scl gpio
Optional properties:
- i2c-gpio,sda-open-drain: sda as open drain
- i2c-gpio,scl-open-drain: scl as open drain
- i2c-gpio,scl-output-only: scl as output only
- i2c-gpio,delay-us: delay between GPIO operations (may depend on each platform)
- i2c-gpio,timeout-ms: timeout to get data
Example nodes:
i2c@0 {
compatible = "i2c-gpio";
gpios = <&pioA 23 0 /* sda */
&pioA 24 0 /* scl */
>;
i2c-gpio,sda-open-drain;
i2c-gpio,scl-open-drain;
i2c-gpio,delay-us = <2>; /* ~100 kHz */
#address-cells = <1>;
#size-cells = <0>;
rv3029c2@56 {
compatible = "rv3029c2";
reg = <0x56>;
};
};

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Device-Tree bindings for input/gpio_keys.c keyboard driver
Required properties:
- compatible = "gpio-keys";
Optional properties:
- input-name: input name of the device
- autorepeat: Boolean, Enable auto repeat feature of Linux input
subsystem.
Each button (key) is represented as a sub-node of "gpio-keys":
Subnode properties:
- gpios: OF device-tree gpio specification.
- label: Descriptive name of the key.
- linux,code: Keycode to emit.
Optional subnode-properties:
- linux,input-type: Specify event type this button/key generates.
If not specified defaults to <1> == EV_KEY.
- debounce-interval: Debouncing interval time in milliseconds.
If not specified defaults to 5.
- gpio-key,wakeup: Boolean, button can wake-up the system.
Example nodes:
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
input-name = "gpio-keys";
button@21 {
label = "GPIO Key UP";
linux,code = <103>;
gpios = <&gpio1 0 1>;
};
...

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kernel/Documentation/devicetree/bindings/gpio/gpio_nvidia.txt Normal file
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NVIDIA Tegra GPIO controller
Required properties:
- compatible : "nvidia,tegra<chip>-gpio"
- reg : Physical base address and length of the controller's registers.
- interrupts : The interrupt outputs from the controller. For Tegra20,
there should be 7 interrupts specified, and for Tegra30, there should
be 8 interrupts specified.
- #gpio-cells : Should be two. The first cell is the pin number and the
second cell is used to specify optional parameters:
- bit 0 specifies polarity (0 for normal, 1 for inverted)
- gpio-controller : Marks the device node as a GPIO controller.
- #interrupt-cells : Should be 2.
The first cell is the GPIO number.
The second cell is used to specify flags:
bits[3:0] trigger type and level flags:
1 = low-to-high edge triggered.
2 = high-to-low edge triggered.
4 = active high level-sensitive.
8 = active low level-sensitive.
Valid combinations are 1, 2, 3, 4, 8.
- interrupt-controller : Marks the device node as an interrupt controller.
Example:
gpio: gpio@6000d000 {
compatible = "nvidia,tegra20-gpio";
reg = < 0x6000d000 0x1000 >;
interrupts = < 0 32 0x04
0 33 0x04
0 34 0x04
0 35 0x04
0 55 0x04
0 87 0x04
0 89 0x04 >;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};

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LEDs connected to GPIO lines
Required properties:
- compatible : should be "gpio-leds".
Each LED is represented as a sub-node of the gpio-leds device. Each
node's name represents the name of the corresponding LED.
LED sub-node properties:
- gpios : Should specify the LED's GPIO, see "gpios property" in
Documentation/devicetree/gpio.txt. Active low LEDs should be
indicated using flags in the GPIO specifier.
- label : (optional) The label for this LED. If omitted, the label is
taken from the node name (excluding the unit address).
- linux,default-trigger : (optional) This parameter, if present, is a
string defining the trigger assigned to the LED. Current triggers are:
"backlight" - LED will act as a back-light, controlled by the framebuffer
system
"default-on" - LED will turn on, but see "default-state" below
"heartbeat" - LED "double" flashes at a load average based rate
"ide-disk" - LED indicates disk activity
"timer" - LED flashes at a fixed, configurable rate
- default-state: (optional) The initial state of the LED. Valid
values are "on", "off", and "keep". If the LED is already on or off
and the default-state property is set the to same value, then no
glitch should be produced where the LED momentarily turns off (or
on). The "keep" setting will keep the LED at whatever its current
state is, without producing a glitch. The default is off if this
property is not present.
Examples:
leds {
compatible = "gpio-leds";
hdd {
label = "IDE Activity";
gpios = <&mcu_pio 0 1>; /* Active low */
linux,default-trigger = "ide-disk";
};
fault {
gpios = <&mcu_pio 1 0>;
/* Keep LED on if BIOS detected hardware fault */
default-state = "keep";
};
};
run-control {
compatible = "gpio-leds";
red {
gpios = <&mpc8572 6 0>;
default-state = "off";
};
green {
gpios = <&mpc8572 7 0>;
default-state = "on";
};
}

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* Marvell PXA GPIO controller
Required properties:
- compatible : Should be "mrvl,pxa-gpio" or "mrvl,mmp-gpio"
- reg : Address and length of the register set for the device
- interrupts : Should be the port interrupt shared by all gpio pins, if
- interrupt-name : Should be the name of irq resource.
one number.
- gpio-controller : Marks the device node as a gpio controller.
- #gpio-cells : Should be one. It is the pin number.
Example:
gpio: gpio@d4019000 {
compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";
reg = <0xd4019000 0x1000>;
interrupts = <49>, <17>, <18>;
interrupt-name = "gpio_mux", "gpio0", "gpio1";
gpio-controller;
#gpio-cells = <1>;
interrupt-controller;
#interrupt-cells = <1>;
};

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ARM PL061 GPIO controller
Required properties:
- compatible : "arm,pl061", "arm,primecell"
- #gpio-cells : Should be two. The first cell is the pin number and the
second cell is used to specify optional parameters:
- bit 0 specifies polarity (0 for normal, 1 for inverted)
- gpio-controller : Marks the device node as a GPIO controller.
- interrupts : Interrupt mapping for GPIO IRQ.

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* msm-qpnp-pin
msm-qpnp-pin is a GPIO chip driver for the MSM SPMI implementation.
It creates a spmi_device for every spmi-dev-container block of device_nodes.
These device_nodes contained within specify the PMIC pin number associated
with each gpio chip. The driver will map these to Linux GPIO numbers.
[PMIC GPIO Device Declarations]
-Root Node-
Required properties :
- spmi-dev-container : Used to specify the following child nodes as part of the
same SPMI device.
- gpio-controller : Specify as gpio-contoller. All child nodes will belong to
this gpio_chip.
- #gpio-cells: We encode a PMIC pin number and a 32-bit flag field to
specify the gpio configuration. This must be set to '2'.
- #address-cells: Specify one address field. This must be set to '1'.
- #size-cells: Specify one size-cell. This must be set to '1'.
- compatible = "qcom,qpnp-pin" : Specify driver matching for this driver.
- label: String giving the name for the gpio_chip device. This name
should be unique on the system and portray the specifics of the device.
-Child Nodes-
Required properties :
- reg : Specify the spmi offset and size for this pin device.
- qcom,pin-num : Specify the PMIC pin number for this device.
Optional configuration properties :
- qcom,mode: indicates whether the pin should be input, output, or
both for gpios. mpp pins also support bidirectional,
analog in, analog out and current sink.
QPNP_PIN_MODE_DIG_IN = 0, (GPIO/MPP)
QPNP_PIN_MODE_DIG_OUT = 1, (GPIO/MPP)
QPNP_PIN_MODE_DIG_IN_OUT = 2, (GPIO/MPP)
QPNP_PIN_MODE_BIDIR = 3, (MPP)
QPNP_PIN_MODE_AIN = 4, (MPP)
QPNP_PIN_MODE_AOUT = 5, (MPP)
QPNP_PIN_MODE_SINK = 6 (MPP)
- qcom,output-type: indicates gpio should be configured as CMOS or open
drain.
QPNP_PIN_OUT_BUF_CMOS = 0, (GPIO)
QPNP_PIN_OUT_BUF_OPEN_DRAIN_NMOS = 1, (GPIO)
QPNP_PIN_OUT_BUF_OPEN_DRAIN_PMOS = 2 (GPIO)
- qcom,invert: Invert the signal of the gpio line -
QPNP_PIN_INVERT_DISABLE = 0 (GPIO/MPP)
QPNP_PIN_INVERT_ENABLE = 1 (GPIO/MPP)
- qcom,pull: This parameter should be programmed to different values
depending on whether it's GPIO or MPP.
For GPIO, it indicates whether a pull up or pull down
should be applied. If a pullup is required the
current strength needs to be specified.
Current values of 30uA, 1.5uA, 31.5uA, 1.5uA with 30uA
boost are supported. This value should be one of
the QPNP_PIN_GPIO_PULL_*. Note that the hardware ignores
this configuration if the GPIO is not set to input or
output open-drain mode.
QPNP_PIN_PULL_UP_30 = 0, (GPIO)
QPNP_PIN_PULL_UP_1P5 = 1, (GPIO)
QPNP_PIN_PULL_UP_31P5 = 2, (GPIO)
QPNP_PIN_PULL_UP_1P5_30 = 3, (GPIO)
QPNP_PIN_PULL_DN = 4, (GPIO)
QPNP_PIN_PULL_NO = 5 (GPIO)
For MPP, it indicates whether a pullup should be
applied for bidirectitional mode only. The hardware
ignores the configuration when operating in other modes.
This value should be one of the QPNP_PIN_MPP_PULL_*.
QPNP_PIN_MPP_PULL_UP_0P6KOHM = 0, (MPP)
QPNP_PIN_MPP_PULL_UP_OPEN = 1 (MPP)
QPNP_PIN_MPP_PULL_UP_10KOHM = 2, (MPP)
QPNP_PIN_MPP_PULL_UP_30KOHM = 3, (MPP)
- qcom,vin-sel: specifies the voltage level when the output is set to 1.
For an input gpio specifies the voltage level at which
the input is interpreted as a logical 1.
QPNP_PIN_VIN0 = 0, (GPIO/MPP)
QPNP_PIN_VIN1 = 1, (GPIO/MPP)
QPNP_PIN_VIN2 = 2, (GPIO/MPP)
QPNP_PIN_VIN3 = 3, (GPIO/MPP)
QPNP_PIN_VIN4 = 4, (GPIO/MPP)
QPNP_PIN_VIN5 = 5, (GPIO/MPP)
QPNP_PIN_VIN6 = 6, (GPIO/MPP)
QPNP_PIN_VIN7 = 7 (GPIO/MPP)
- qcom,out-strength: the amount of current supplied for an output gpio.
QPNP_PIN_OUT_STRENGTH_LOW = 1 (GPIO)
QPNP_PIN_OUT_STRENGTH_MED = 2, (GPIO)
QPNP_PIN_OUT_STRENGTH_HIGH = 3, (GPIO)
- qcom,src-sel: select a function for the pin. Certain pins
can be paired (shorted) with each other. Some gpio pins
can act as alternate functions.
In the context of gpio, this acts as a source select.
For mpps, this is an enable select.
QPNP_PIN_SEL_FUNC_CONSTANT = 0, (GPIO/MPP)
QPNP_PIN_SEL_FUNC_PAIRED = 1, (GPIO/MPP)
QPNP_PIN_SEL_FUNC_1 = 2, (GPIO/MPP)
QPNP_PIN_SEL_FUNC_2 = 3, (GPIO/MPP)
QPNP_PIN_SEL_DTEST1 = 4, (GPIO/MPP)
QPNP_PIN_SEL_DTEST2 = 5, (GPIO/MPP)
QPNP_PIN_SEL_DTEST3 = 6, (GPIO/MPP)
QPNP_PIN_SEL_DTEST4 = 7 (GPIO/MPP)
- qcom,master-en: 1 = Enable features within the
pin block based on configurations. (GPIO/MPP)
0 = Completely disable the block and
let the pin float with high impedance
regardless of other settings. (GPIO/MPP)
- qcom,aout-ref: set the analog output reference.
QPNP_PIN_AOUT_1V25 = 0, (MPP)
QPNP_PIN_AOUT_0V625 = 1, (MPP)
QPNP_PIN_AOUT_0V3125 = 2, (MPP)
QPNP_PIN_AOUT_MPP = 3, (MPP)
QPNP_PIN_AOUT_ABUS1 = 4, (MPP)
QPNP_PIN_AOUT_ABUS2 = 5, (MPP)
QPNP_PIN_AOUT_ABUS3 = 6, (MPP)
QPNP_PIN_AOUT_ABUS4 = 7 (MPP)
- qcom,ain-route: Set the destination for analog input.
QPNP_PIN_AIN_AMUX_CH5 = 0, (MPP)
QPNP_PIN_AIN_AMUX_CH6 = 1, (MPP)
QPNP_PIN_AIN_AMUX_CH7 = 2, (MPP)
QPNP_PIN_AIN_AMUX_CH8 = 3, (MPP)
QPNP_PIN_AIN_AMUX_ABUS1 = 4, (MPP)
QPNP_PIN_AIN_AMUX_ABUS2 = 5, (MPP)
QPNP_PIN_AIN_AMUX_ABUS3 = 6, (MPP)
QPNP_PIN_AIN_AMUX_ABUS4 = 7 (MPP)
- qcom,cs-out: Set the the amount of output to sync in mA.
QPNP_PIN_CS_OUT_5MA = 0, (MPP)
QPNP_PIN_CS_OUT_10MA = 1, (MPP)
QPNP_PIN_CS_OUT_15MA = 2, (MPP)
QPNP_PIN_CS_OUT_20MA = 3, (MPP)
QPNP_PIN_CS_OUT_25MA = 4, (MPP)
QPNP_PIN_CS_OUT_30MA = 5, (MPP)
QPNP_PIN_CS_OUT_35MA = 6, (MPP)
QPNP_PIN_CS_OUT_40MA = 7 (MPP)
*Note: If any of the configuration properties are not specified, then the
qpnp-pin driver will not modify that respective configuration in
hardware.
[PMIC GPIO clients]
Required properties :
- gpios : Contains 3 fields of the form <&gpio_controller pmic_pin_num flags>
[Example]
qpnp: qcom,spmi@fc4c0000 {
#address-cells = <1>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <3>;
qcom,pm8941@0 {
spmi-slave-container;
reg = <0x0>;
#address-cells = <1>;
#size-cells = <1>;
pm8941_gpios: gpios {
spmi-dev-container;
compatible = "qcom,qpnp-pin";
gpio-controller;
#gpio-cells = <2>;
#address-cells = <1>;
#size-cells = <1>;
gpio@c000 {
reg = <0xc000 0x100>;
qcom,pin-num = <62>;
};
gpio@c100 {
reg = <0xc100 0x100>;
qcom,pin-num = <20>;
qcom,source_sel = <2>;
qcom,pull = <5>;
};
};
qcom,testgpio@1000 {
compatible = "qcom,qpnp-testgpio";
reg = <0x1000 0x1000>;
gpios = <&pm8941_gpios 62 0x0 &pm8941_gpios 20 0x1>;
};
};
};
};

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GPIO controller on CE4100 / Sodaville SoCs
==========================================
The bindings for CE4100's GPIO controller match the generic description
which is covered by the gpio.txt file in this folder.
The only additional property is the intel,muxctl property which holds the
value which is written into the MUXCNTL register.
There is no compatible property for now because the driver is probed via
PCI id (vendor 0x8086 device 0x2e67).
The interrupt specifier consists of two cells encoded as follows:
- <1st cell>: The interrupt-number that identifies the interrupt source.
- <2nd cell>: The level-sense information, encoded as follows:
4 - active high level-sensitive
8 - active low level-sensitive
Example of the GPIO device and one user:
pcigpio: gpio@b,1 {
/* two cells for GPIO and interrupt */
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "pci8086,2e67.2",
"pci8086,2e67",
"pciclassff0000",
"pciclassff00";
reg = <0x15900 0x0 0x0 0x0 0x0>;
/* Interrupt line of the gpio device */
interrupts = <15 1>;
/* It is an interrupt and GPIO controller itself */
interrupt-controller;
gpio-controller;
intel,muxctl = <0>;
};
testuser@20 {
compatible = "example,testuser";
/* User the 11th GPIO line as an active high triggered
* level interrupt
*/
interrupts = <11 8>;
interrupt-parent = <&pcigpio>;
/* Use this GPIO also with the gpio functions */
gpios = <&pcigpio 11 0>;
};