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95
bootable/bootloader/lk/platform/qsd8k/acpuclock.c Normal file
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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
* Copyright (c) 2009, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <stdint.h>
#include <kernel/thread.h>
#include <platform/iomap.h>
#include <reg.h>
#define A11S_CLK_CNTL 0xAC100100
#define A11S_CLK_SEL 0xAC100104
#define SCPLL_CTL 0xA8800004
#define SCPLL_CTLE 0xA8800010
#define SCPLL_STAT 0xA8800018
void acpu_clock_init(void)
{
unsigned val;
/* Init Scorpion PLL */
writel(0x0, SCPLL_CTL);
writel(0x00400002, SCPLL_CTL);
writel(0x00600004, SCPLL_CTL);
thread_sleep(1);
while(readl(SCPLL_STAT) & 0x2);
writel(0x0, SCPLL_CTL);
/* Enable pll */
while(readl(SCPLL_STAT) & 0x1);
val = readl(SCPLL_CTL);
val &= ~(0x7);
val |= 0x2;
writel(val, SCPLL_CTL);
thread_sleep(1);
val = readl(SCPLL_CTL);
val |= 0x7;
writel(val, SCPLL_CTL);
thread_sleep(1);
/* For Scorpion PLL, must first SHOT to 384MHz then HOP to 768MHz */
/* Set pll to 384 MHz */
while(readl(SCPLL_STAT) & 0x3);
val = readl(SCPLL_CTLE);
val &= ~(0x3F << 3);
val |= (0xA << 3);
val &= ~(0x3 << 0);
val |= (4 << 0); // SHOT method
writel(val, SCPLL_CTLE);
writel(0x00600007, SCPLL_CTL);
thread_sleep(1);
/* HOP to 768MHz */
while(readl(SCPLL_STAT) & 0x3);
val = readl(SCPLL_CTLE);
val &= ~(0x3F << 3);
val |= (0x14 << 3); // Use 0x1A instead of 0x14 for 998MHz
val &= ~(0x3 << 0);
val |= (5 << 0); // HOP method
writel(val, SCPLL_CTLE);
writel(0x00600007, SCPLL_CTL);
thread_sleep(1);
val = readl(A11S_CLK_SEL);
val &= ~(0x3 << 1);
val |= (1 << 1);
writel(val, A11S_CLK_SEL);
}

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bootable/bootloader/lk/platform/qsd8k/arch_init.S Normal file
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/*
* Copyright (c) 2008-2009, The Linux Foundation. All rights reserved.
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Google, Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* TODO:
* - style cleanup
* - do we need to do *all* of this at boot?
*/
.text
.code 32
#define DSB .byte 0x4f, 0xf0, 0x7f, 0xf5
#define ISB .byte 0x6f, 0xf0, 0x7f, 0xf5
/*
; LVT Ring Osc counter
; used to determine sense amp settings
; Clobbers registers r0, r4, r5, r6, r7, r9, r10, r11
*/
.equ CLK_CTL_BASE, 0xA8600000
.equ A_GLBL_CLK_ENA, 0x0000
.equ A_PRPH_WEB_NS_REG,0x0080
.equ A_MSM_CLK_RINGOSC,0x00D0
.equ A_TCXO_CNT, 0x00D4
.equ A_TCXO_CNT_DONE, 0x00D8
.equ A_RINGOSC_CNT, 0x00DC
.equ A_MISC_CLK_CTL, 0x0108
.equ CLK_TEST, 0xA8600114
.equ SPSS_CSR_BASE, 0xAC100000
.equ A_SCRINGOSC, 0x0510
//;; Number of TCXO cycles to count ring oscillations
.equ TCXO_CNT_VAL, 0x100
//; Raptor addresses
.equ TCSR_SPARE2, 0xA8700060
.globl SET_SA
SET_SA:
//; no stack at this point and any registers we use will be 0'd
//; after we return
LDR r0, =TCSR_SPARE2
LDR r1, [r0]
LDR r0, = 0x010F
AND r2, r1, r0 //; concerned with bits [8, 3:0]
//;--------------------------------------------------------------------
//; Fuse bits used to determine sense amp settings
//;--------------------------------------------------------------------
LDR r0, = 0x0105
AND r4, r2, r0 //; mask off all but L1 ACC2, L1 ACC1 and L1 ACC0
//;set to default of FC00
LDR r5, =PVR0F0_6bits //; point to PVR0F0
LDR r3, =PVR2F0_6bits //; point to PVR2F0
ck_0:
//; if L1_[2:0] == 000 then ACC setting = FC00
LDR r1, = 0x0
CMP r4, r1
BNE ck_1
B WRITE_L1_SA_SETTINGS
ck_1:
//; if L1_[2:0] == 001 then ACC setting = FC00
LDR r1, = 0x01
CMP r4, r1
BNE ck_2
B WRITE_L1_SA_SETTINGS
ck_2:
//; if L1_[2:0] == 010 then ACC setting = 7C00
LDR r1, = 0x04
CMP r4, r1
BNE ck_3
LDR r5, =PVR0F0_5bits //; point to PVR0F0
LDR r3, =PVR2F0_5bits //; point to PVR2F0
B WRITE_L1_SA_SETTINGS
ck_3:
//; if L1_[2:0] == 011 then ACC setting = FC00
LDR r1, = 0x05
CMP r4, r1
BNE ck_4
LDR r5, =PVR0F0_6bits //; point to PVR0F0
LDR r3, =PVR2F0_6bits //; point to PVR2F0
B WRITE_L1_SA_SETTINGS
ck_4:
//; if L1_[2:0] == 0100 then ACC setting = 3C00
LDR r1, = 0x0100
CMP r4, r1
BNE ck_5
LDR r5, =PVR0F0_4bits //; point to PVR0F0
LDR r3, =PVR2F0_4bits //; point to PVR2F0
B WRITE_L1_SA_SETTINGS
ck_5:
//; if L1_[2:0] == 0101 then ACC setting = 0400
LDR r1, = 0x0101
CMP r4, r1
BNE ck_6
LDR r5, =PVR0F0_1bits //; point to PVR0F0
LDR r3, =PVR2F0_1bits //; point to PVR2F0
B WRITE_L1_SA_SETTINGS
ck_6:
//; if L1_[2:0] == 0110 then ACC setting = 0C00
LDR r1, = 0x0104
CMP r4, r1
BNE ck_7
LDR r5, =PVR0F0_2bits //; point to PVR0F0
LDR r3, =PVR2F0_2bits //; point to PVR2F0
B WRITE_L1_SA_SETTINGS
ck_7:
//; if L1_[2:0] == 0111 then ACC setting = 1C00
LDR r1, = 0x0105
CMP r4, r1
LDREQ r5, =PVR0F0_3bits //; point to PVR0F0
LDREQ r3, =PVR2F0_3bits //; point to PVR2F0
WRITE_L1_SA_SETTINGS:
LDR r5, [r5]
LDR r3, [r3]
//;WCP15_PVR0F0 r5
MCR p15,0x0,r5,c15,c15,0 //; write R5 to PVR0F0
//;WCP15_PVR2F0 r3
MCR p15,0x2,r3,c15,c15,0 //; write R3 to PVR2F0
AND r4, r2, #0x000A //; mask off all but L2 array SA settings
LDR r5, =HVT_010102 //; point to L2VR3F1 setting
//;it gets ovewritten if its one of the other two cases
//; if L2_1 and L2_0 == 0 ACC setting = 010102
LDR r1, = 0x0000
CMP r4, r1
BEQ WRITE_L2_SA_SETTINGS
//; if L2_1 = 0 & L2_0 = 1 ACC setting = 010102
LDR R1, = 0x0002
CMP r4, r1
BEQ WRITE_L2_SA_SETTINGS
//; if L2_1 = 1 & L2_0 = 0 ACC setting = 010101
LDR r5, =HVT_010101
LDR R1, = 0x0008
CMP r4, r1
BEQ WRITE_L2_SA_SETTINGS
//; else L2_1 = 1 & L2_0 = 1 ACC setting = 212102
LDR r5, =HVT_212102
WRITE_L2_SA_SETTINGS:
//;WCP15_L2VR3F1 r4
LDR r5, [r5]
MCR p15,0x3,r5,c15,c15,1 //;write r4 to L2VR3F1
LDR r0, =0 //;make sure the registers we touched
LDR r1, =0 //;are cleared when we return
LDR r2, =0
LDR r3, =0
LDR r4, =0
LDR r5, =0
//; routine complete
B _cpu_early_init_complete
//; L1 SA settings according to LVT speed
PVR0F0_0bits:
.word 0x38000000 //; PVR0F0
PVR2F0_0bits:
.word 0x00000000 //; PVR2F0 0 bits set
PVR0F0_1bits:
.word 0x38000400 //; PVR0F0
PVR2F0_1bits:
.word 0x04000000 //; PVR2F0 1 bits set
PVR0F0_2bits:
.word 0x38000C00 //; PVR0F0
PVR2F0_2bits:
.word 0x0C000000 //; PVR2F0 2 bits set
PVR0F0_3bits:
.word 0x38001C00 //; PVR0F0
PVR2F0_3bits:
.word 0x1C000000 //; PVR2F0 3 bits set
PVR0F0_4bits:
.word 0x38003C00 //; PVR0F0
PVR2F0_4bits:
.word 0x3C000000 //; PVR2F0 4 bits set
PVR0F0_5bits:
.word 0x38007C00 //; PVR0F0
PVR2F0_5bits:
.word 0x7C000000 //; PVR2F0 5 bits set
PVR0F0_6bits:
.word 0x3800FC00 //; PVR0F0
PVR2F0_6bits:
.word 0xFC000000 //; PVR2F0 6 bits set
//; L2 SA settings according to HVT speed
HVT_212102:
.word 0x00212102 //; L2VR3F1
HVT_010102:
.word 0x00010102 //; L2VR3F1
HVT_010101:
.word 0x00010101 //; L2VR3F1
.ltorg
.globl __cpu_early_init
__cpu_early_init:
//; Zero out r0 for use throughout this code. All other GPRs
//; (r1-r3) are set throughout this code to help establish
//; a consistent startup state for any code that follows.
//; Users should add code at the end of this routine to establish
//; their own stack address (r13), add translation page tables, enable
//; the caches, etc.
MOV r0, #0x0
//; Remove hardcoded cache settings. appsbl_handler.s calls Set_SA
//; API to dynamically configure cache for slow/nominal/fast parts
//; DCIALL to invalidate L2 cache bank (needs to be run 4 times, once per bank)
//; This must be done early in code (prior to enabling the caches)
MOV r1, #0x2
MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank D ([15:14] == 2'b00)
ORR r1, r1, #0x00004000
MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank C ([15:14] == 2'b01)
ADD r1, r1, #0x00004000
MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank B ([15:14] == 2'b10)
ADD r1, r1, #0x00004000
MCR p15, 0, r1, c9, c0, 6 //; DCIALL bank A ([15:14] == 2'b11)
//; Initialize the BPCR - setup Global History Mask (GHRM) to all 1's
//; and have all address bits (AM) participate.
//; Different settings can be used to improve performance
// MOVW r1, #0x01FF
.word 0xe30011ff // hardcoded MOVW instruction due to lack of compiler support
// MOVT r1, #0x01FF
.word 0xe34011ff // hardcoded MOVT instruction due to lack of compiler support
MCR p15, 7, r1, c15, c0, 2 //; WCP15_BPCR
//; Initialize all I$ Victim Registers to 0 for startup
MCR p15, 0, r0, c9, c1, 0 //; WCP15_ICVIC0 r0
MCR p15, 0, r0, c9, c1, 1 //; WCP15_ICVIC1 r0
MCR p15, 0, r0, c9, c1, 2 //; WCP15_ICVIC2 r0
MCR p15, 0, r0, c9, c1, 3 //; WCP15_ICVIC3 r0
MCR p15, 0, r0, c9, c1, 4 //; WCP15_ICVIC4 r0
MCR p15, 0, r0, c9, c1, 5 //; WCP15_ICVIC5 r0
MCR p15, 0, r0, c9, c1, 6 //; WCP15_ICVIC5 r0
MCR p15, 0, r0, c9, c1, 7 //; WCP15_ICVIC7 r0
//; Initialize all I$ Locked Victim Registers (Unlocked Floors) to 0
MCR p15, 1, r0, c9, c1, 0 //; WCP15_ICFLOOR0 r0
MCR p15, 1, r0, c9, c1, 1 //; WCP15_ICFLOOR1 r0
MCR p15, 1, r0, c9, c1, 2 //; WCP15_ICFLOOR2 r0
MCR p15, 1, r0, c9, c1, 3 //; WCP15_ICFLOOR3 r0
MCR p15, 1, r0, c9, c1, 4 //; WCP15_ICFLOOR4 r0
MCR p15, 1, r0, c9, c1, 5 //; WCP15_ICFLOOR5 r0
MCR p15, 1, r0, c9, c1, 6 //; WCP15_ICFLOOR6 r0
MCR p15, 1, r0, c9, c1, 7 //; WCP15_ICFLOOR7 r0
//; Initialize all D$ Victim Registers to 0
MCR p15, 2, r0, c9, c1, 0 //; WP15_DCVIC0 r0
MCR p15, 2, r0, c9, c1, 1 //; WP15_DCVIC1 r0
MCR p15, 2, r0, c9, c1, 2 //; WP15_DCVIC2 r0
MCR p15, 2, r0, c9, c1, 3 //; WP15_DCVIC3 r0
MCR p15, 2, r0, c9, c1, 4 //; WP15_DCVIC4 r0
MCR p15, 2, r0, c9, c1, 5 //; WP15_DCVIC5 r0
MCR p15, 2, r0, c9, c1, 6 //; WP15_DCVIC6 r0
MCR p15, 2, r0, c9, c1, 7 //; WP15_DCVIC7 r0
//; Initialize all D$ Locked VDCtim Registers (Unlocked Floors) to 0
MCR p15, 3, r0, c9, c1, 0 //; WCP15_DCFLOOR0 r0
MCR p15, 3, r0, c9, c1, 1 //; WCP15_DCFLOOR1 r0
MCR p15, 3, r0, c9, c1, 2 //; WCP15_DCFLOOR2 r0
MCR p15, 3, r0, c9, c1, 3 //; WCP15_DCFLOOR3 r0
MCR p15, 3, r0, c9, c1, 4 //; WCP15_DCFLOOR4 r0
MCR p15, 3, r0, c9, c1, 5 //; WCP15_DCFLOOR5 r0
MCR p15, 3, r0, c9, c1, 6 //; WCP15_DCFLOOR6 r0
MCR p15, 3, r0, c9, c1, 7 //; WCP15_DCFLOOR7 r0
//; Initialize ASID to zero
MCR p15, 0, r0, c13, c0, 1 //; WCP15_CONTEXTIDR r0
//; ICIALL to invalidate entire I-Cache
MCR p15, 0, r0, c7, c5, 0 //; ICIALLU
//; DCIALL to invalidate entire D-Cache
MCR p15, 0, r0, c9, c0, 6 //; DCIALL r0
//; Initialize ADFSR to zero
MCR p15, 0, r0, c5, c1, 0 //; ADFSR r0
//; Initialize EFSR to zero
MCR p15, 7, r0, c15, c0, 1 //; EFSR r0
//; The VBAR (Vector Base Address Register) should be initialized
//; early in your code. We are setting it to zero
MCR p15, 0, r0, c12, c0, 0 //; WCP15_VBAR r0
//; Ensure the MCR's above have completed their operation before continuing
DSB
ISB
//;-------------------------------------------------------------------
//; There are a number of registers that must be set prior to enabling
//; the MMU. The DCAR is one of these registers. We are setting
//; it to zero (no access) to easily detect improper setup in subsequent
//; code sequences
//;-------------------------------------------------------------------
//; Setup DACR (Domain Access Control Register) to zero
MCR p15, 0, r0, c3, c0, 0 //; WCP15_DACR r0
//; Setup DCLKCR to allow normal D-Cache line fills
MCR p15, 1, r0, c9, c0, 7 //; WCP15_DCLKCR r0
//; Setup the TLBLKCR
//; Victim = 6'b000000; Floor = 6'b000000;
//; IASIDCFG = 2'b00 (State-Machine); IALLCFG = 2'b01 (Flash); BNA = 1'b0;
MOV r1, #0x02
MCR p15, 0, r1, c10, c1, 3 //; WCP15_TLBLKCR r1
//;Make sure TLBLKCR is complete before continuing
ISB
//; Invalidate the UTLB
MCR p15, 0, r0, c8, c7, 0 //; UTLBIALL
//; Make sure UTLB request has been presented to macro before continuing
ISB
// Disable predecode repair cache on certain Scorpion revisions
// (Raptor V2 and earlier, or Halcyon V1)
MRC p15, 0, r1, c0, c0, 0 //; MIDR
BIC r2, r1, #0xf7 //; check for Raptor2 or below
LDR r3, =0x510f0000
CMP r2, r3
BEQ DPRC
BIC r2, r1, #0xf0 //; check for Halcyon V1
LDR r3, =0x511f0000
CMP r2, r3
BNE SYSI2
DPRC:
MRC p15, 0, r1, c15, c15, 2 //; PVR0F2
ORR r1, r1, #0x10 //; enable bit 4
MCR p15, 0, r1, c15, c15, 2 //; disable predecode repair cache
SYSI2:
//; setup L2CR1 to some default Instruction and data prefetching values
//; Users may want specific settings for various performance enhancements
MOV r2, #0x33
MCR p15, 3, r2, c15, c0, 3 //; WCP15_L2CR1 r0
//; Enable Z bit to enable branch prediction (default is off)
MRC p15, 0, r2, c1, c0, 0 //; RCP15_SCTLR r2
ORR r2, r2, #0x00000800
MCR p15, 0, r2, c1, c0, 0 //; WCP15_SCTLR r2
//; Make sure Link stack is initialized with branch and links to sequential addresses
//; This aids in creating a predictable startup environment
BL SEQ1
SEQ1: BL SEQ2
SEQ2: BL SEQ3
SEQ3: BL SEQ4
SEQ4: BL SEQ5
SEQ5: BL SEQ6
SEQ6: BL SEQ7
SEQ7: BL SEQ8
SEQ8:
//; REMOVE FOLLOWING THREE INSTRUCTIONS WHEN POWER COLLAPSE IS ENA
//;Make sure the DBGOSLSR[LOCK] bit is cleared to allow access to the debug registers
//; Writing anything but the "secret code" to the DBGOSLAR clears the DBGOSLSR[LOCK] bit
MCR p14, 0, r0, c1, c0, 4 //; WCP14_DBGOSLAR r0
//; Read the DBGPRSR to clear the DBGPRSR[STICKYPD]
//; Any read to DBGPRSR clear the STICKYPD bit
//; ISB guarantees the read completes before attempting to
//; execute a CP14 instruction.
MRC p14, 0, r3, c1, c5, 4 //; RCP14_DBGPRSR r3
ISB
//; Initialize the Watchpoint Control Registers to zero (optional)
//;;; MCR p14, 0, r0, c0, c0, 7 ; WCP14_DBGWCR0 r0
//;;; MCR p14, 0, r0, c0, c1, 7 ; WCP14_DBGWCR1 r0
//;----------------------------------------------------------------------
//; The saved Program Status Registers (SPSRs) should be setup
//; prior to any automatic mode switches. The following
//; code sets these registers up to a known state. Users will need to
//; customize these settings to meet their needs.
//;----------------------------------------------------------------------
MOV r2, #0x1f
MOV r1, #0xd7 //;ABT mode
msr cpsr_c, r1 //;ABT mode
msr spsr_cxfs, r2 //;clear the spsr
MOV r1, #0xdb //;UND mode
msr cpsr_c, r1 //;UND mode
msr spsr_cxfs, r2 //;clear the spsr
MOV r1, #0xd1 //;FIQ mode
msr cpsr_c, r1 //;FIQ mode
msr spsr_cxfs, r2 //;clear the spsr
MOV r1, #0xd2 //;IRQ mode
msr cpsr_c, r1 //;IRQ mode
msr spsr_cxfs, r2 //;clear the spsr
MOV r1, #0xd6 //;Monitor mode
msr cpsr_c, r1 //;Monitor mode
msr spsr_cxfs, r2 //;clear the spsr
MOV r1, #0xd3 //;SVC mode
msr cpsr_c, r1 //;SVC mode
msr spsr_cxfs, r2 //;clear the spsr
//;----------------------------------------------------------------------
//; Enabling Error reporting is something users may want to do at
//; some other point in time. We have chosen some default settings
//; that should be reviewed. Most of these registers come up in an
//; unpredictable state after reset.
//;----------------------------------------------------------------------
//;Start of error and control setting
//; setup L2CR0 with various L2/TCM control settings
//; enable out of order bus attributes and error reporting
//; this register comes up unpredictable after reset
// MOVW r1, #0x0F0F
.word 0xe3001f0f // hardcoded MOVW instruction due to lack of compiler support
// MOVT r1, #0xC005
.word 0xe34c1005 // hardcoded MOVW instruction due to lack of compiler support
MCR p15, 3, r1, c15, c0, 1 //; WCP15_L2CR0 r1
//; setup L2CPUCR
//; MOV r2, #0xFF
//; Enable I and D cache parity
//;L2CPUCR[7:5] = 3~Rh7 ~V enable parity error reporting for modified,
//;tag, and data parity errors
MOV r2, #0xe0
MCR p15, 3, r2, c15, c0, 2 //; WCP15_L2CPUCR r2
//; setup SPCR
//; enable all error reporting (reset value is unpredicatble for most bits)
MOV r3, #0x0F
MCR p15, 0, r3, c9, c7, 0 //; WCP15_SPCR r3
//; setup DMACHCRs (reset value unpredictable)
//; control setting and enable all error reporting
MOV r1, #0x0F
//; DMACHCR0 = 0000000F
MOV r2, #0x00 //; channel 0
MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
//; DMACHCR1 = 0000000F
MOV r2, #0x01 //; channel 1
MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
//; DMACHCR2 = 0000000F
MOV r2, #0x02 //; channel 2
MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
//; DMACHCR3 = 0000000F
MOV r2, #0x03 //; channel 3
MCR p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
MCR p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
//; Set ACTLR (reset unpredictable)
//; Set AVIVT control, error reporting, etc.
//; MOV r3, #0x07
//; Enable I and D cache parity
//;ACTLR[2:0] = 3'h7 - enable parity error reporting from L2/I$/D$)
//;ACTLR[5:4] = 2'h3 - enable parity
//;ACTLR[19:18] =2'h3 - always generate and check parity(when MMU disabled).
//;Value to be written #0xC0037
// MOVW r3, #0x0037
.word 0xe3003037 // hardcoded MOVW instruction due to lack of compiler support
// MOVT r3, #0x000C
.word 0xe340300c // hardcoded MOVW instruction due to lack of compiler support
//; read the version_id to determine if d-cache should be disabled
LDR r2, = 0xa8e00270 //;Read HW_REVISION_NUMBER, HWIO_HW_REVISION_NUMBER_ADDR
LDR r2,[r2]
AND r2,r2,#0xf0000000 //;hw_revision mask off bits 28-31
//;if HW_revision is 1.0 or older, (revision==0)
CMP r2,#0
//; Disable d-cache on older QSD8650 (Rev 1.0) silicon
//;orreq r3, r3, #0x4000 //;disable dcache
//;MCR p15, 0, r3, c1, c0, 1 //; WCP15_ACTLR r3
//;End of error and control setting
//;----------------------------------------------------------------------
//; Unlock ETM and read StickyPD to halt the ETM clocks from running.
//; This is required for power saving whether the ETM is used or not.
//;----------------------------------------------------------------------
//;Clear ETMOSLSR[LOCK] bit
MOV r1, #0x00000000
MCR p14, 1, r1, c1, c0, 4 //; WCP14_ETMOSLAR r1
//;Clear ETMPDSR[STICKYPD] bit
MRC p14, 1, r2, c1, c5, 4 //; RCP14_ETMPDSR r2
/*
#ifdef APPSBL_ETM_ENABLE
;----------------------------------------------------------------------
; Optionally Enable the ETM (Embedded Trace Macro) which is used for debug
;----------------------------------------------------------------------
; enable ETM clock if disabled
MRC p15, 7, r1, c15, c0, 5 ; RCP15_CPMR r1
ORR r1, r1, #0x00000008
MCR p15, 7, r1, c15, c0, 5 ; WCP15_CPMR r1
ISB
; set trigger event to counter1 being zero
MOV r3, #0x00000040
MCR p14, 1, r3, c0, c2, 0 ; WCP14_ETMTRIGGER r3
; clear ETMSR
MOV r2, #0x00000000
MCR p14, 1, r2, c0, c4, 0 ; WCP14_ETMSR r2
; clear trace enable single address comparator usage
MCR p14, 1, r2, c0, c7, 0 ; WCP14_ETMTECR2 r2
; set trace enable to always
MOV r2, #0x0000006F
MCR p14, 1, r2, c0, c8, 0 ; WCP14_ETMTEEVR r2
; clear trace enable address range comparator usage and exclude nothing
MOV r2, #0x01000000
MCR p14, 1, r2, c0, c9, 0 ; WCP14_ETMTECR1 r2
; set view data to always
MOV r2, #0x0000006F
MCR p14, 1, r2, c0, c12, 0 ; WCP14_ETMVDEVR r2
; clear view data single address comparator usage
MOV r2, #0x00000000
MCR p14, 1, r2, c0, c13, 0 ; WCP14_ETMVDCR1 r2
; clear view data address range comparator usage and exclude nothing
MOV r2, #0x00010000
MCR p14, 1, r2, c0, c15, 0 ; WCP14_ETMVDCR3 r2
; set counter1 to 194
MOV r2, #0x000000C2
MCR p14, 1, r2, c0, c0, 5 ; WCP14_ETMCNTRLDVR1 r2
; set counter1 to never reload
MOV r2, #0x0000406F
MCR p14, 1, r2, c0, c8, 5 ; WCP14_ETMCNTRLDEVR1 r2
; set counter1 to decrement every cycle
MOV r2, #0x0000006F
MCR p14, 1, r2, c0, c4, 5 ; WCP14_ETMCNTENR1 r2
; Set trace synchronization frequency 1024 bytes
MOV r2, #0x00000400
MCR p14, 1, r2, c0, c8, 7 ; WCP14_ETMSYNCFR r2
; Program etm control register
; - Set the CPU to ETM clock ratio to 1:1
; - Set the ETM to perform data address tracing
MOV r2, #0x00002008
MCR p14, 1, r2, c0, c0, 0 ; WCP14_ETMCR r2
ISB
#endif *//* APPSBL_ETM_ENABLE */
/*
#ifdef APPSBL_VFP_ENABLE
;----------------------------------------------------------------------
; Perform the following operations if you intend to make use of
; the VFP/Neon unit. Note that the FMXR instruction requires a CPU ID
; indicating the VFP unit is present (i.e.Cortex-A8). .
; Some tools will require full double precision floating point support
; which will become available in Scorpion pass 2
;----------------------------------------------------------------------
; allow full access to CP 10 and 11 space for VFP/NEON use
MRC p15, 0, r1, c1, c0, 2 ; Read CP Access Control Register
ORR r1, r1, #0x00F00000 ; enable full access for p10,11
MCR p15, 0, r1, c1, c0, 2 ; Write CPACR
;make sure the CPACR is complete before continuing
ISB
; Enable VFP itself (certain OSes may want to dynamically set/clear
; the enable bit based on the application being executed
MOV r1, #0x40000000
FMXR FPEXC, r1
#endif *//* APPSBL_VFP_ENABLE */
/* we have no stack, so just tail-call into the SET_SA routine... */
b SET_SA
.ltorg

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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <debug.h>
#include <reg.h>
#include <platform/iomap.h>
#include <dev/gpio.h>
#include "gpio_hw.h"
typedef struct gpioregs gpioregs;
struct gpioregs
{
unsigned out;
unsigned in;
unsigned int_status;
unsigned int_clear;
unsigned int_en;
unsigned int_edge;
unsigned int_pos;
unsigned oe;
};
static gpioregs GPIO_REGS[] = {
{
.out = GPIO_OUT_0,
.in = GPIO_IN_0,
.int_status = GPIO_INT_STATUS_0,
.int_clear = GPIO_INT_CLEAR_0,
.int_en = GPIO_INT_EN_0,
.int_edge = GPIO_INT_EDGE_0,
.int_pos = GPIO_INT_POS_0,
.oe = GPIO_OE_0,
},
{
.out = GPIO_OUT_1,
.in = GPIO_IN_1,
.int_status = GPIO_INT_STATUS_1,
.int_clear = GPIO_INT_CLEAR_1,
.int_en = GPIO_INT_EN_1,
.int_edge = GPIO_INT_EDGE_1,
.int_pos = GPIO_INT_POS_1,
.oe = GPIO_OE_1,
},
{
.out = GPIO_OUT_2,
.in = GPIO_IN_2,
.int_status = GPIO_INT_STATUS_2,
.int_clear = GPIO_INT_CLEAR_2,
.int_en = GPIO_INT_EN_2,
.int_edge = GPIO_INT_EDGE_2,
.int_pos = GPIO_INT_POS_2,
.oe = GPIO_OE_2,
},
{
.out = GPIO_OUT_3,
.in = GPIO_IN_3,
.int_status = GPIO_INT_STATUS_3,
.int_clear = GPIO_INT_CLEAR_3,
.int_en = GPIO_INT_EN_3,
.int_edge = GPIO_INT_EDGE_3,
.int_pos = GPIO_INT_POS_3,
.oe = GPIO_OE_3,
},
{
.out = GPIO_OUT_4,
.in = GPIO_IN_4,
.int_status = GPIO_INT_STATUS_4,
.int_clear = GPIO_INT_CLEAR_4,
.int_en = GPIO_INT_EN_4,
.int_edge = GPIO_INT_EDGE_4,
.int_pos = GPIO_INT_POS_4,
.oe = GPIO_OE_4,
},
{
.out = GPIO_OUT_5,
.in = GPIO_IN_5,
.int_status = GPIO_INT_STATUS_5,
.int_clear = GPIO_INT_CLEAR_5,
.int_en = GPIO_INT_EN_5,
.int_edge = GPIO_INT_EDGE_5,
.int_pos = GPIO_INT_POS_5,
.oe = GPIO_OE_5,
},
{
.out = GPIO_OUT_6,
.in = GPIO_IN_6,
.int_status = GPIO_INT_STATUS_6,
.int_clear = GPIO_INT_CLEAR_6,
.int_en = GPIO_INT_EN_6,
.int_edge = GPIO_INT_EDGE_6,
.int_pos = GPIO_INT_POS_6,
.oe = GPIO_OE_6,
},
{
.out = GPIO_OUT_7,
.in = GPIO_IN_7,
.int_status = GPIO_INT_STATUS_7,
.int_clear = GPIO_INT_CLEAR_7,
.int_en = GPIO_INT_EN_7,
.int_edge = GPIO_INT_EDGE_7,
.int_pos = GPIO_INT_POS_7,
.oe = GPIO_OE_7,
},
};
static gpioregs *find_gpio(unsigned n, unsigned *bit)
{
if(n > 164) return 0;
if(n > 152) {
*bit = 1 << (n - 153);
return GPIO_REGS + 7;
}
if(n > 121) {
*bit = 1 << (n - 122);
return GPIO_REGS + 6;
}
if(n > 103) {
*bit = 1 << (n - 104);
return GPIO_REGS + 5;
}
if(n > 94) {
*bit = 1 << (n - 95);
return GPIO_REGS + 4;
}
if(n > 67) {
*bit = 1 << (n - 68);
return GPIO_REGS + 3;
}
if(n > 42) {
*bit = 1 << (n - 43);
return GPIO_REGS + 2;
}
if(n > 15) {
*bit = 1 << (n - 16);
return GPIO_REGS + 1;
}
*bit = 1 << n;
return GPIO_REGS + 0;
}
int gpio_config(unsigned n, unsigned flags)
{
gpioregs *r;
unsigned b;
unsigned v;
if ((r = find_gpio(n, &b)) == 0)
return -1;
v = readl(r->oe);
if (flags & GPIO_OUTPUT) {
writel(v | b, r->oe);
} else {
writel(v & (~b), r->oe);
}
return 0;
}
void gpio_set(unsigned n, unsigned on)
{
gpioregs *r;
unsigned b;
unsigned v;
if((r = find_gpio(n, &b)) == 0) return;
v = readl(r->out);
if(on) {
writel(v | b, r->out);
} else {
writel(v & (~b), r->out);
}
}
int gpio_get(unsigned n)
{
gpioregs *r;
unsigned b;
if((r = find_gpio(n, &b)) == 0) return 0;
return (readl(r->in) & b) ? 1 : 0;
}

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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef __PLATFORM_QSD8K_GPIO_HW_H
#define __PLATFORM_QSD8K_GPIO_HW_H
#define MSM_GPIO1_BASE 0xA9000000
#define MSM_GPIO2_BASE 0xA9100000
#define GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
/* output value */
#define GPIO_OUT_0 GPIO1_REG(0x00) /* gpio 15-0 */
#define GPIO_OUT_1 GPIO2_REG(0x00) /* gpio 42-16 */
#define GPIO_OUT_2 GPIO1_REG(0x04) /* gpio 67-43 */
#define GPIO_OUT_3 GPIO1_REG(0x08) /* gpio 94-68 */
#define GPIO_OUT_4 GPIO1_REG(0x0C) /* gpio 103-95 */
#define GPIO_OUT_5 GPIO1_REG(0x10) /* gpio 121-104 */
#define GPIO_OUT_6 GPIO1_REG(0x14) /* gpio 152-122 */
#define GPIO_OUT_7 GPIO1_REG(0x18) /* gpio 164-153 */
/* same pin map as above, output enable */
#define GPIO_OE_0 GPIO1_REG(0x20)
#define GPIO_OE_1 GPIO2_REG(0x08)
#define GPIO_OE_2 GPIO1_REG(0x24)
#define GPIO_OE_3 GPIO1_REG(0x28)
#define GPIO_OE_4 GPIO1_REG(0x2C)
#define GPIO_OE_5 GPIO1_REG(0x30)
#define GPIO_OE_6 GPIO1_REG(0x34)
#define GPIO_OE_7 GPIO1_REG(0x38)
/* same pin map as above, input read */
#define GPIO_IN_0 GPIO1_REG(0x50)
#define GPIO_IN_1 GPIO2_REG(0x20)
#define GPIO_IN_2 GPIO1_REG(0x54)
#define GPIO_IN_3 GPIO1_REG(0x58)
#define GPIO_IN_4 GPIO1_REG(0x5C)
#define GPIO_IN_5 GPIO1_REG(0x60)
#define GPIO_IN_6 GPIO1_REG(0x64)
#define GPIO_IN_7 GPIO1_REG(0x68)
/* same pin map as above, 1=edge 0=level interrup */
#define GPIO_INT_EDGE_0 GPIO1_REG(0x70)
#define GPIO_INT_EDGE_1 GPIO2_REG(0x50)
#define GPIO_INT_EDGE_2 GPIO1_REG(0x74)
#define GPIO_INT_EDGE_3 GPIO1_REG(0x78)
#define GPIO_INT_EDGE_4 GPIO1_REG(0x7C)
#define GPIO_INT_EDGE_5 GPIO1_REG(0x80)
#define GPIO_INT_EDGE_6 GPIO1_REG(0x84)
#define GPIO_INT_EDGE_7 GPIO1_REG(0x88)
/* same pin map as above, 1=positive 0=negative */
#define GPIO_INT_POS_0 GPIO1_REG(0x90)
#define GPIO_INT_POS_1 GPIO2_REG(0x58)
#define GPIO_INT_POS_2 GPIO1_REG(0x94)
#define GPIO_INT_POS_3 GPIO1_REG(0x98)
#define GPIO_INT_POS_4 GPIO1_REG(0x9C)
#define GPIO_INT_POS_5 GPIO1_REG(0xA0)
#define GPIO_INT_POS_6 GPIO1_REG(0xA4)
#define GPIO_INT_POS_7 GPIO1_REG(0xA8)
/* same pin map as above, interrupt enable */
#define GPIO_INT_EN_0 GPIO1_REG(0xB0)
#define GPIO_INT_EN_1 GPIO2_REG(0x60)
#define GPIO_INT_EN_2 GPIO1_REG(0xB4)
#define GPIO_INT_EN_3 GPIO1_REG(0xB8)
#define GPIO_INT_EN_4 GPIO1_REG(0xBC)
#define GPIO_INT_EN_5 GPIO1_REG(0xC0)
#define GPIO_INT_EN_6 GPIO1_REG(0xC4)
#define GPIO_INT_EN_7 GPIO1_REG(0xC8)
/* same pin map as above, write 1 to clear interrupt */
#define GPIO_INT_CLEAR_0 GPIO1_REG(0xD0)
#define GPIO_INT_CLEAR_1 GPIO2_REG(0x68)
#define GPIO_INT_CLEAR_2 GPIO1_REG(0xD4)
#define GPIO_INT_CLEAR_3 GPIO1_REG(0xD8)
#define GPIO_INT_CLEAR_4 GPIO1_REG(0xDC)
#define GPIO_INT_CLEAR_5 GPIO1_REG(0xE0)
#define GPIO_INT_CLEAR_6 GPIO1_REG(0xE4)
#define GPIO_INT_CLEAR_7 GPIO1_REG(0xE8)
/* same pin map as above, 1=interrupt pending */
#define GPIO_INT_STATUS_0 GPIO1_REG(0xF0)
#define GPIO_INT_STATUS_1 GPIO2_REG(0x70)
#define GPIO_INT_STATUS_2 GPIO1_REG(0xF4)
#define GPIO_INT_STATUS_3 GPIO1_REG(0xF8)
#define GPIO_INT_STATUS_4 GPIO1_REG(0xFC)
#define GPIO_INT_STATUS_5 GPIO1_REG(0x100)
#define GPIO_INT_STATUS_6 GPIO1_REG(0x103)
#define GPIO_INT_STATUS_7 GPIO1_REG(0x108)
#endif

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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Google, Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _PLATFORM_MSM7K_IOMAP_H_
#define _PLATFORM_MSM7K_IOMAP_H_
#define MSM_UART1_BASE 0xA9A00000
#define MSM_UART2_BASE 0xA9B00000
#define MSM_UART3_BASE 0xA9C00000
#define MSM_VIC_BASE 0xAC000000
#define MSM_GPT_BASE 0xAC100000
#define MSM_CSR_BASE 0xAC100000
#if defined(PLATFORM_QSD8K)
#define MSM_SHARED_BASE 0x00100000
#else
#define MSM_SHARED_BASE 0x01F00000
#endif
#endif

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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Google, Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _PLATFORM_MSM7K_IRQS_H_
#define _PLATFORM_MSM7K_IRQS_H_
#define INT_A9_M2A_0 0
#define INT_A9_M2A_1 1
#define INT_A9_M2A_2 2
#define INT_A9_M2A_3 3
#define INT_A9_M2A_4 4
#define INT_A9_M2A_5 5
#define INT_A9_M2A_6 6
#define INT_GP_TIMER_EXP 7
#define INT_DEBUG_TIMER_EXP 8
#define INT_SIRC_0 9
#define INT_SDC3_0 10
#define INT_SDC3_1 11
#define INT_SDC4_0 12
#define INT_SDC4_1 13
#define INT_AD6_EXT_VFR 14
#define INT_USB_OTG 15
#define INT_MDDI_PRI 16
#define INT_MDDI_EXT 17
#define INT_MDDI_CLIENT 18
#define INT_MDP 19
#define INT_GRAPHICS 20
#define INT_ADM_AARM 21
#define INT_ADSP_A11 22
#define INT_ADSP_A9_A11 23
#define INT_SDC1_0 24
#define INT_SDC1_1 25
#define INT_SDC2_0 26
#define INT_SDC2_1 27
#define INT_KEYSENSE 28
#define INT_TCHSCRN_SSBI 29
#define INT_TCHSCRN1 30
#define INT_TCHSCRN2 31
#define INT_TCSR_MPRPH_SC1 (32 + 0)
#define INT_USB_FS2 (32 + 1)
#define INT_PWB_I2C (32 + 2)
#define INT_SOFTRESET (32 + 3)
#define INT_NAND_WR_ER_DONE (32 + 4)
#define INT_NAND_OP_DONE (32 + 5)
#define INT_TCSR_MPRPH_SC2 (32 + 6)
#define INT_OP_PEN (32 + 7)
#define INT_AD_HSSD (32 + 8)
#define INT_ARM11_PM (32 + 9)
#define INT_SDMA_NON_SECURE (32 + 10)
#define INT_TSIF_IRQ (32 + 11)
#define INT_UART1DM_IRQ (32 + 12)
#define INT_UART1DM_RX (32 + 13)
#define INT_SDMA_SECURE (32 + 14)
#define INT_SI2S_SLAVE (32 + 15)
#define INT_SC_I2CPU (32 + 16)
#define INT_SC_DBG_RDTRFULL (32 + 17)
#define INT_SC_DBG_WDTRFULL (32 + 18)
#define INT_SCPLL_CTL_DONE (32 + 19)
#define INT_UART2DM_IRQ (32 + 20)
#define INT_UART2DM_RX (32 + 21)
#define INT_VDC_MEC (32 + 22)
#define INT_VDC_DB (32 + 23)
#define INT_VDC_AXI (32 + 24)
#define INT_VFE (32 + 25)
#define INT_USB_HS (32 + 26)
#define INT_AUDIO_OUT0 (32 + 27)
#define INT_AUDIO_OUT1 (32 + 28)
#define INT_CRYPTO (32 + 29)
#define INT_AD6M_IDLE (32 + 30)
#define INT_SIRC_1 (32 + 31)
/* secondary interrupt controller */
#define INT_UART1_IRQ (64 + 0)
#define INT_UART2_IRQ (64 + 1)
#define INT_UART3_IRQ (64 + 2)
#define INT_UART1_RX (64 + 3)
#define INT_UART2_RX (64 + 4)
#define INT_UART3_RX (64 + 5)
#define INT_SPI_INPUT (64 + 6)
#define INT_SPI_OUTPUT (64 + 7)
#define INT_SPI_ERROR (64 + 8)
#define INT_GPIO1_SHADOW (64 + 9)
#define INT_GPIO2_SHADOW (64 + 10)
#define INT_GPIO1_SECURE (64 + 11)
#define INT_GPIO2_SECURE (64 + 12)
#define INT_SC_AVS_SVIC (64 + 13)
#define INT_SC_AVS_REQ_UP (64 + 14)
#define INT_SC_AVS_REQ_DOWN (64 + 15)
#define INT_PBUS_ERR (64 + 16)
#define INT_AXI (64 + 17)
#define INT_SMI (64 + 18)
#define INT_EBI (64 + 19)
#define INT_IMEM (64 + 20)
#define INT_SC_TEMP_SENSOR (64 + 21)
#define INT_TV_ENC (64 + 22)
#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31))
#define NR_IRQS 64
#endif

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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Google, Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <debug.h>
#include <arch/arm.h>
#include <reg.h>
#include <kernel/thread.h>
#include <platform/interrupts.h>
#include <platform/irqs.h>
#include <platform/iomap.h>
#define VIC_REG(off) (MSM_VIC_BASE + (off))
#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
#define VIC_INT_EN0 VIC_REG(0x0010)
#define VIC_INT_EN1 VIC_REG(0x0014)
#define VIC_INT_ENCLEAR0 VIC_REG(0x0020)
#define VIC_INT_ENCLEAR1 VIC_REG(0x0024)
#define VIC_INT_ENSET0 VIC_REG(0x0030)
#define VIC_INT_ENSET1 VIC_REG(0x0034)
#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
#define VIC_NO_PEND_VAL VIC_REG(0x0060)
#define VIC_INT_MASTEREN VIC_REG(0x0068) /* 1: IRQ, 2: FIQ */
#define VIC_CONFIG VIC_REG(0x006C) /* 1: USE ARM1136 VIC */
#define VIC_SECURITY0 VIC_REG(0x0070)
#define VIC_SECURITY1 VIC_REG(0x0074)
#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
#define VIC_IRQ_STATUS1 VIC_REG(0x0084)
#define VIC_FIQ_STATUS0 VIC_REG(0x0090)
#define VIC_FIQ_STATUS1 VIC_REG(0x0094)
#define VIC_RAW_STATUS0 VIC_REG(0x00A0)
#define VIC_RAW_STATUS1 VIC_REG(0x00A4)
#define VIC_INT_CLEAR0 VIC_REG(0x00B0)
#define VIC_INT_CLEAR1 VIC_REG(0x00B4)
#define VIC_SOFTINT0 VIC_REG(0x00C0)
#define VIC_SOFTINT1 VIC_REG(0x00C4)
#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
#define VIC_IRQ_VEC_WR VIC_REG(0x00D8)
#define VIC_FIQ_VEC_RD VIC_REG(0x00DC) /* pending int # */
#define VIC_FIQ_VEC_PEND_RD VIC_REG(0x00E0) /* pending vector addr */
#define VIC_FIQ_VEC_WR VIC_REG(0x00E4)
#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E8)
#define VIC_IRQ_IN_STACK VIC_REG(0x00EC)
#define VIC_FIQ_IN_SERVICE VIC_REG(0x00F0)
#define VIC_FIQ_IN_STACK VIC_REG(0x00F4)
#define VIC_TEST_BUS_SEL VIC_REG(0x00F8)
#define SIRC_REG(off) (MSM_SIRC_BASE + (off))
#define SIRC_INT_SELECT SIRC_REG(0x0000) /* 0: IRQ0 1: IRQ1 */
#define SIRC_INT_ENABLE SIRC_REG(0x0004)
#define SIRC_INT_ENCLEAR SIRC_REG(0x0008)
#define SIRC_INT_ENSET SIRC_REG(0x000C)
#define SIRC_INT_TYPE SIRC_REG(0x0010) /* 1: EDGE, 0: LEVEL */
#define SIRC_INT_POLARITY SIRC_REG(0x0014) /* 1: NEG, 0: POS */
#define SIRC_SECURITY SIRC_REG(0x0018) /* 0: SEC, 1: NSEC */
#define SIRC_IRQ0_STATUS SIRC_REG(0x001C)
#define SIRC_IRQ1_STATUS SIRC_REG(0x0020)
#define SIRC_RAW_STATUS SIRC_REG(0x0024)
struct ihandler {
int_handler func;
void *arg;
};
static struct ihandler handler[NR_IRQS];
void platform_init_interrupts(void)
{
writel(0xffffffff, VIC_INT_CLEAR0);
writel(0xffffffff, VIC_INT_CLEAR1);
writel(0, VIC_INT_SELECT0);
writel(0, VIC_INT_SELECT1);
writel(0xffffffff, VIC_INT_TYPE0);
writel(0xffffffff, VIC_INT_TYPE1);
writel(0, VIC_CONFIG);
writel(1, VIC_INT_MASTEREN);
}
enum handler_return platform_irq(struct arm_iframe *frame)
{
unsigned num;
enum handler_return ret;
num = readl(VIC_IRQ_VEC_RD);
num = readl(VIC_IRQ_VEC_PEND_RD);
if (num > NR_IRQS)
return 0;
writel(1 << (num & 31), (num > 31) ? VIC_INT_CLEAR1 : VIC_INT_CLEAR0);
ret = handler[num].func(handler[num].arg);
writel(0, VIC_IRQ_VEC_WR);
return ret;
}
void platform_fiq(struct arm_iframe *frame)
{
PANIC_UNIMPLEMENTED;
}
status_t mask_interrupt(unsigned int vector)
{
unsigned reg = (vector > 31) ? VIC_INT_ENCLEAR1 : VIC_INT_ENCLEAR0;
unsigned bit = 1 << (vector & 31);
writel(bit, reg);
return 0;
}
status_t unmask_interrupt(unsigned int vector)
{
unsigned reg = (vector > 31) ? VIC_INT_ENSET1 : VIC_INT_ENSET0;
unsigned bit = 1 << (vector & 31);
writel(bit, reg);
return 0;
}
void register_int_handler(unsigned int vector, int_handler func, void *arg)
{
if (vector >= NR_IRQS)
return;
enter_critical_section();
handler[vector].func = func;
handler[vector].arg = arg;
exit_critical_section();
}

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/* Copyright 2007, Google Inc. */
#include <debug.h>
#include <dev/gpio.h>
#include <kernel/thread.h>
#include <mddi.h>
#define MDDI_CLIENT_CORE_BASE 0x108000
#define LCD_CONTROL_BLOCK_BASE 0x110000
#define SPI_BLOCK_BASE 0x120000
#define I2C_BLOCK_BASE 0x130000
#define PWM_BLOCK_BASE 0x140000
#define GPIO_BLOCK_BASE 0x150000
#define SYSTEM_BLOCK1_BASE 0x160000
#define SYSTEM_BLOCK2_BASE 0x170000
#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)
#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)
#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)
#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)
#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)
#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)
#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)
#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)
#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)
#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)
#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)
#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)
#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)
#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)
#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)
#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)
#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
#define START (LCD_CONTROL_BLOCK_BASE|0x08)
#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)
#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)
#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)
#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)
#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)
#define PXL (LCD_CONTROL_BLOCK_BASE|0x30)
#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
#define HSW (LCD_CONTROL_BLOCK_BASE|0x38)
#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)
#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)
#define VSW (LCD_CONTROL_BLOCK_BASE|0x48)
#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)
#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)
#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)
#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)
#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)
#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)
#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)
#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)
#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)
#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)
#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)
#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)
#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)
#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)
#define MONI (LCD_CONTROL_BLOCK_BASE|0xB0)
#define Current (LCD_CONTROL_BLOCK_BASE|0xC0)
#define LCD (LCD_CONTROL_BLOCK_BASE|0xC4)
#define COMMAND (LCD_CONTROL_BLOCK_BASE|0xC8)
#define SSICTL (SPI_BLOCK_BASE|0x00)
#define SSITIME (SPI_BLOCK_BASE|0x04)
#define SSITX (SPI_BLOCK_BASE|0x08)
#define SSIRX (SPI_BLOCK_BASE|0x0C)
#define SSIINTC (SPI_BLOCK_BASE|0x10)
#define SSIINTS (SPI_BLOCK_BASE|0x14)
#define SSIDBG1 (SPI_BLOCK_BASE|0x18)
#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
#define SSIID (SPI_BLOCK_BASE|0x20)
#define I2CSETUP (I2C_BLOCK_BASE|0x00)
#define I2CCTRL (I2C_BLOCK_BASE|0x04)
#define TIMER0LOAD (PWM_BLOCK_BASE|0x00)
#define TIMER0VALUE (PWM_BLOCK_BASE|0x04)
#define TIMER0CONTROL (PWM_BLOCK_BASE|0x08)
#define TIMER0INTCLR (PWM_BLOCK_BASE|0x0C)
#define TIMER0RIS (PWM_BLOCK_BASE|0x10)
#define TIMER0MIS (PWM_BLOCK_BASE|0x14)
#define TIMER0BGLOAD (PWM_BLOCK_BASE|0x18)
#define PWM0OFF (PWM_BLOCK_BASE|0x1C)
#define TIMER1LOAD (PWM_BLOCK_BASE|0x20)
#define TIMER1VALUE (PWM_BLOCK_BASE|0x24)
#define TIMER1CONTROL (PWM_BLOCK_BASE|0x28)
#define TIMER1INTCLR (PWM_BLOCK_BASE|0x2C)
#define TIMER1RIS (PWM_BLOCK_BASE|0x30)
#define TIMER1MIS (PWM_BLOCK_BASE|0x34)
#define TIMER1BGLOAD (PWM_BLOCK_BASE|0x38)
#define PWM1OFF (PWM_BLOCK_BASE|0x3C)
#define TIMERITCR (PWM_BLOCK_BASE|0x60)
#define TIMERITOP (PWM_BLOCK_BASE|0x64)
#define PWMCR (PWM_BLOCK_BASE|0x68)
#define PWMID (PWM_BLOCK_BASE|0x6C)
#define PWMMON (PWM_BLOCK_BASE|0x70)
#define GPIODATA (GPIO_BLOCK_BASE|0x00)
#define GPIODIR (GPIO_BLOCK_BASE|0x04)
#define GPIOIS (GPIO_BLOCK_BASE|0x08)
#define GPIOIBE (GPIO_BLOCK_BASE|0x0C)
#define GPIOIEV (GPIO_BLOCK_BASE|0x10)
#define GPIOIE (GPIO_BLOCK_BASE|0x14)
#define GPIORIS (GPIO_BLOCK_BASE|0x18)
#define GPIOMIS (GPIO_BLOCK_BASE|0x1C)
#define GPIOIC (GPIO_BLOCK_BASE|0x20)
#define GPIOOMS (GPIO_BLOCK_BASE|0x24)
#define GPIOPC (GPIO_BLOCK_BASE|0x28)
#define GPIOID (GPIO_BLOCK_BASE|0x30)
#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
#define CNT_DIS (SYSTEM_BLOCK1_BASE|0x10)
#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
struct init_table {
unsigned int reg;
unsigned int val;
};
static struct init_table toshiba_480x800_init_table[] = {
{ DPSET0, 0x4BEC0066 }, // # MDC.DPSET0 # Setup DPLL parameters
{ DPSET1, 0x00000113 }, // # MDC.DPSET1
{ DPSUS, 0x00000000 }, // # MDC.DPSUS # Set DPLL oscillation enable
{ DPRUN, 0x00000001 }, // # MDC.DPRUN # Release reset signal for DPLL
{ 0, 15 }, // wait_ms(15);
{ SYSCKENA, 0x00000001 }, // # MDC.SYSCKENA # Enable system clock output
{ CLKENB, 0x000000E9 }, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK)
{ GPIO_BLOCK_BASE, 0x03FF0000 }, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0
{ GPIODIR, 0x0000024D }, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output)
{ SYSTEM_BLOCK2_BASE, 0x00000173 }, // # SYS.GPIOSEL # GPIO port multiplexing control
{ GPIOPC, 0x03C300C0 }, // # GPI .GPIOPC # GPIO2,3 PD cut
{ SYSTEM_BLOCK1_BASE, 0x00000000 }, // # SYS.WKREQ # Wake-up request event is VSYNC alignment
{ GPIOIS, 0x00000000 }, // # GPI .GPIOIS # Set interrupt sense of GPIO
{ GPIOIEV, 0x00000001 }, // # GPI .GPIOIEV # Set interrupt event of GPIO
{ GPIOIC, 0x000003FF }, // # GPI .GPIOIC # GPIO interrupt clear
{ GPIO_BLOCK_BASE, 0x00040004 }, // # GPI .GPIODATA # Release LCDD reset
{ GPIO_BLOCK_BASE, 0x00080008 }, // # GPI .GPIODATA # eDRAM VD supply
{ DRAMPWR, 0x00000001 }, // # SYS.DRAMPWR # eDRAM power up
{ CLKENB, 0x0000A0EB }, // # enable eDRAM clock
{ PWMCR, 0x00000000 }, // # PWM.PWMCR # PWM output enable
{ 0, 1 }, // wait_ms(1);
{ SPI_BLOCK_BASE, 0x00060399}, // # SPI .SSICTL # SPI operation mode setting
{ SSITIME, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting
{ CNT_DIS, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting
{ SPI_BLOCK_BASE, 0x0006039B }, // # SPI .SSICTL # Set SPI active mode
{ SSITX, 0x00000000 }, // # SPI.SSITX # Release from Deep Stanby mode
{ 0, 2 }, // wait_ms(2);
{ SSITX, 0x00000000 }, // # SPI.SSITX
{ 0, 2 }, // wait_ms(2);
{ SSITX, 0x00000000 }, // # SPI.SSITX
{ 0, 2 }, // wait_ms(2);
{ SSITX, 0x000800BA }, // # SPI.SSITX *NOTE 1 # Command setting of SPI block
{ SSITX, 0x00000111 }, // # Display mode setup(1) : Normaly Black
{ SSITX, 0x00080036 }, // # Command setting of SPI block
{ SSITX, 0x00000100 }, // # Memory access control
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x0008003A }, // # Command setting of SPI block
{ SSITX, 0x00000160 }, // # Display mode setup(2)
{ SSITX, 0x000800B1 }, // # Command setting of SPI block
{ SSITX, 0x0000015D }, // # RGB Interface data format
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800B2 }, // # Command setting of SPI block
{ SSITX, 0x00000133 }, // # Drivnig method
{ SSITX, 0x000800B3 }, // # Command setting of SPI block
{ SSITX, 0x00000122 }, // # Booster operation setup
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800B4 }, // # Command setting of SPI block
{ SSITX, 0x00000102 }, // # OP-amp capability/System clock freq. division setup
{ SSITX, 0x000800B5 }, // # Command setting of SPI block
{ SSITX, 0x0000011E }, // # VCS Voltage adjustment (1C->1F for Rev 2)
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800B6 }, // # Command setting of SPI block
{ SSITX, 0x00000127 }, // # VCOM Voltage adjustment
{ SSITX, 0x000800B7 }, // # Command setting of SPI block
{ SSITX, 0x00000103 }, // # Configure an external display signal
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800B9 }, // # Command setting of SPI block
{ SSITX, 0x00000124 }, // # DCCK/DCEV timing setup
{ SSITX, 0x000800BD }, // # Command setting of SPI block
{ SSITX, 0x000001A1 }, // # ASW signal control
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800BB }, // # Command setting of SPI block
{ SSITX, 0x00000100 }, // # Dummy display (white/black) count setup for QUAD Data operation
{ SSITX, 0x000800BF }, // # Command setting of SPI block
{ SSITX, 0x00000101 }, // # Dummy display (white/black) count setup for QUAD Data operation
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800BE }, // # Command setting of SPI block
{ SSITX, 0x00000100 }, // # wait_ms(-out FR count setup (A)
{ SSITX, 0x000800C0 }, // # Command setting of SPI block
{ SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (A)
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C1 }, // # Command setting of SPI block
{ SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (B)
{ SSITX, 0x000800C2 }, // # Command setting of SPI block
{ SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (C)
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C3 }, // # Command setting of SPI block
{ SSITX, 0x00080132 }, // # wait_ms(-in line clock count setup (D)
{ SSITX, 0x00000132 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C4 }, // # Command setting of SPI block
{ SSITX, 0x00080132 }, // # Seep-in line clock count setup (E)
{ SSITX, 0x00000132 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C5 }, // # Command setting of SPI block
{ SSITX, 0x00080132 }, // # wait_ms(-in line clock count setup (F)
{ SSITX, 0x00000132 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C6 }, // # Command setting of SPI block
{ SSITX, 0x00080132 }, // # wait_ms(-in line clock setup (G)
{ SSITX, 0x00000132 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C7 }, // # Command setting of SPI block
{ SSITX, 0x00080164 }, // # Gamma 1 fine tuning (1)
{ SSITX, 0x00000145 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C8 }, // # Command setting of SPI block
{ SSITX, 0x00000144 }, // # Gamma 1 fine tuning (2)
{ SSITX, 0x000800C9 }, // # Command setting of SPI block
{ SSITX, 0x00000152 }, // # Gamma 1 inclination adjustment
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800CA }, // # Command setting of SPI block
{ SSITX, 0x00000100 }, // # Gamma 1 blue offset adjustment
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800EC }, // # Command setting of SPI block
{ SSITX, 0x00080101 }, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]
{ SSITX, 0x000001FC }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800CF }, // # Command setting of SPI block
{ SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D0 }, // # Command setting of SPI block
{ SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]
{ SSITX, 0x00000104 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D1 }, // # Command setting of SPI block
{ SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D2 }, // # Command setting of SPI block
{ SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]
{ SSITX, 0x00000128 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D3 }, // # Command setting of SPI block
{ SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table1 for VGA]
{ SSITX, 0x00000128 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D4 }, // # Command setting of SPI block
{ SSITX, 0x00080126 }, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]
{ SSITX, 0x000001A4 }, //
{ 0, 1 }, // wait_ms(1); // # Wait SPI fifo empty
{ SSITX, 0x000800D5 }, // # Command setting of SPI block
{ SSITX, 0x00000120 }, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800EF }, // # Command setting of SPI block
{ SSITX, 0x00080132 }, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]
{ SSITX, 0x00000100 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ BITMAP0, 0x032001E0 }, // MDC.BITMAP0 ); // Setup of PITCH size to Frame buffer1
{ BITMAP1, 0x032001E0 }, // MDC.BITMAP1 ); // Setup of PITCH size to Frame buffer1
{ BITMAP2, 0x014000F0 }, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2
{ BITMAP3, 0x014000F0 }, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3
{ BITMAP4, 0x014000F0 }, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4
{ CLKENB, 0x0000A1EB }, // SYS.CLKENB ); // DCLK supply
{ PORT_ENB, 0x00000001 }, // LCD.PORT_ENB ); // Synchronous port enable
{ PORT, 0x00000004 }, // LCD.PORT ); // Polarity of DE is set to high active
{ PXL, 0x00000002 }, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output)
{ MPLFBUF, 0x00000000 }, // LCD.MPLFBUF ); // Select the reading buffer
{ HCYCLE, 0x000000FD }, // LCD.HCYCLE ); // Setup to VGA size
{ HSW, 0x00000003 }, // LCD.HSW
{ HDE_START, 0x00000007 }, // LCD.HDE_START
{ HDE_SIZE, 0x000000EF }, // LCD.HDE_SIZE
{ VCYCLE, 0x00000325 }, // LCD.VCYCLE
{ VSW, 0x00000001 }, // LCD.VSW
{ VDE_START, 0x00000003 }, // LCD.VDE_START
{ VDE_SIZE, 0x0000031F }, // LCD.VDE_SIZE
{ START, 0x00000001 }, // LCD.START ); // LCDC - Pixel data transfer start
{ 0, 10 }, // wait_ms( 10 );
{ SSITX, 0x000800BC }, // SPI.SSITX ); // Command setting of SPI block
{ SSITX, 0x00000180 }, // Display data setup
{ SSITX, 0x0008003B }, // Command setting of SPI block
{ SSITX, 0x00000100 }, // Quad Data configuration - VGA
{ 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
{ SSITX, 0x000800B0 }, // Command setting of SPI block
{ SSITX, 0x00000116 }, // Power supply ON/OFF control
{ 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
{ SSITX, 0x000800B8 }, // Command setting of SPI block
{ SSITX, 0x000801FF }, // Output control
{ SSITX, 0x000001F5 },
{ 0, 1 }, // wait_ms( 1); // Wait SPI fifo empty
{ SSITX, 0x00000011 }, // wait_ms(-out (Command only)
{ SSITX, 0x00000029 }, // Display on (Command only)
//{ SYSTEM_BLOCK1_BASE, 0x00000002 }, // # wakeREQ -> GPIO
{ 0, 0 }
};
static struct init_table toshiba_480x640_init_table[] = {
{ DPSET0, 0x4BEC0066 }, // # MDC.DPSET0 # Setup DPLL parameters
{ DPSET1, 0x00000113 }, // # MDC.DPSET1
{ DPSUS, 0x00000000 }, // # MDC.DPSUS # Set DPLL oscillation enable
{ DPRUN, 0x00000001 }, // # MDC.DPRUN # Release reset signal for DPLL
{ 0, 14 }, // wait_ms(14);
{ SYSCKENA, 0x00000001 }, // # MDC.SYSCKENA # Enable system clock output
{ CLKENB, 0x000000EF }, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK)
{ GPIO_BLOCK_BASE, 0x03FF0000 }, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0
{ GPIODIR, 0x0000024D }, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output)
{ SYSTEM_BLOCK2_BASE, 0x00000173 }, // # SYS.GPIOSEL # GPIO port multiplexing control
{ GPIOPC, 0x03C300C0 }, // # GPI .GPIOPC # GPIO2,3 PD cut
{ SYSTEM_BLOCK1_BASE, 0x00000000 }, // # SYS.WKREQ # Wake-up request event is VSYNC alignment
{ GPIOIS, 0x00000000 }, // # GPI .GPIOIS # Set interrupt sense of GPIO
{ GPIOIEV, 0x00000001 }, // # GPI .GPIOIEV # Set interrupt event of GPIO
{ GPIOIC, 0x000003FF }, // # GPI .GPIOIC # GPIO interrupt clear
{ GPIO_BLOCK_BASE, 0x00060006 }, // # GPI .GPIODATA # Release LCDD reset
{ GPIO_BLOCK_BASE, 0x00080008 }, // # GPI .GPIODATA # eDRAM VD supply
{ GPIO_BLOCK_BASE, 0x02000200 }, // # GPI .GPIODATA # TEST LED ON
{ DRAMPWR, 0x00000001 }, // # SYS.DRAMPWR # eDRAM power up
{ TIMER0CONTROL, 0x00000060 }, // # PWM.Timer0Control # PWM0 output stop
{ PWM_BLOCK_BASE, 0x00001388 }, // # PWM.Timer0Load # PWM0 10kHz , Duty 99 (BackLight OFF)
//{PWM0OFF, 0x00000001 }, // # PWM.PWM0OFF
#if 0
{ PWM0OFF, 0x00001387 }, // SURF 100% backlight
{ PWM0OFF, 0x00000000 }, // FFA 100% backlight
#endif
{ PWM0OFF, 0x000009C3 }, // 50% BL
{ TIMER1CONTROL, 0x00000060 }, // # PWM.Timer1Control # PWM1 output stop
{ TIMER1LOAD, 0x00001388 }, // # PWM.Timer1Load # PWM1 10kHz , Duty 99 (BackLight OFF)
//{PWM1OFF, 0x00000001 }, // # PWM.PWM1OFF
{ PWM1OFF, 0x00001387 },
{ TIMER0CONTROL, 0x000000E0 }, // # PWM.Timer0Control # PWM0 output start
{ TIMER1CONTROL, 0x000000E0 }, // # PWM.Timer1Control # PWM1 output start
{ PWMCR, 0x00000003 }, // # PWM.PWMCR # PWM output enable
{ 0, 1 }, // wait_ms(1);
{ SPI_BLOCK_BASE, 0x00000799 }, // # SPI .SSICTL # SPI operation mode setting
{ SSITIME, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting
{ SPI_BLOCK_BASE, 0x0000079b }, // # SPI .SSICTL # Set SPI active mode
{ SSITX, 0x00000000 }, // # SPI.SSITX # Release from Deep Stanby mode
{ 0, 1 }, // wait_ms(1);
{ SSITX, 0x00000000 }, // # SPI.SSITX
{ 0, 1 }, // wait_ms(1);
{ SSITX, 0x00000000 }, // # SPI.SSITX
{ 0, 1 }, // wait_ms(1);
{ SSITX, 0x000800BA }, // # SPI.SSITX *NOTE 1 # Command setting of SPI block
{ SSITX, 0x00000111 }, // # Display mode setup(1) : Normaly Black
{ SSITX, 0x00080036 }, // # Command setting of SPI block
{ SSITX, 0x00000100 }, // # Memory access control
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800BB }, // # Command setting of SPI block
{ SSITX, 0x00000100 }, // # Display mode setup(2)
{ SSITX, 0x0008003A }, // # Command setting of SPI block
{ SSITX, 0x00000160 }, // # RGB Interface data format
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800BF }, // # Command setting of SPI block
{ SSITX, 0x00000100 }, // # Drivnig method
{ SSITX, 0x000800B1 }, // # Command setting of SPI block
{ SSITX, 0x0000015D }, // # Booster operation setup
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800B2 }, // # Command setting of SPI block
{ SSITX, 0x00000133 }, // # Booster mode setup
{ SSITX, 0x000800B3 }, // # Command setting of SPI block
{ SSITX, 0x00000122 }, // # Booster frequencies setup
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800B4 }, // # Command setting of SPI block
{ SSITX, 0x00000102 }, // # OP-amp capability/System clock freq. division setup
{ SSITX, 0x000800B5 }, // # Command setting of SPI block
{ SSITX, 0x0000011F }, // # VCS Voltage adjustment (1C->1F for Rev 2)
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800B6 }, // # Command setting of SPI block
{ SSITX, 0x00000128 }, // # VCOM Voltage adjustment
{ SSITX, 0x000800B7 }, // # Command setting of SPI block
{ SSITX, 0x00000103 }, // # Configure an external display signal
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800B9 }, // # Command setting of SPI block
{ SSITX, 0x00000120 }, // # DCCK/DCEV timing setup
{ SSITX, 0x000800BD }, // # Command setting of SPI block
{ SSITX, 0x00000102 }, // # ASW signal control
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800BE }, // # Command setting of SPI block
{ SSITX, 0x00000100 }, // # Dummy display (white/black) count setup for QUAD Data operation
{ SSITX, 0x000800C0 }, // # Command setting of SPI block
{ SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (A)
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C1 }, // # Command setting of SPI block
{ SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (B)
{ SSITX, 0x000800C2 }, // # Command setting of SPI block
{ SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (C)
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C3 }, // # Command setting of SPI block
{ SSITX, 0x0008010A }, // # wait_ms(-in line clock count setup (D)
{ SSITX, 0x0000010A }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C4 }, // # Command setting of SPI block
{ SSITX, 0x00080160 }, // # Seep-in line clock count setup (E)
{ SSITX, 0x00000160 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C5 }, // # Command setting of SPI block
{ SSITX, 0x00080160 }, // # wait_ms(-in line clock count setup (F)
{ SSITX, 0x00000160 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C6 }, // # Command setting of SPI block
{ SSITX, 0x00080160 }, // # wait_ms(-in line clock setup (G)
{ SSITX, 0x00000160 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C7 }, // # Command setting of SPI block
{ SSITX, 0x00080133 }, // # Gamma 1 fine tuning (1)
{ SSITX, 0x00000143 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800C8 }, // # Command setting of SPI block
{ SSITX, 0x00000144 }, // # Gamma 1 fine tuning (2)
{ SSITX, 0x000800C9 }, // # Command setting of SPI block
{ SSITX, 0x00000133 }, // # Gamma 1 inclination adjustment
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800CA }, // # Command setting of SPI block
{ SSITX, 0x00000100 }, // # Gamma 1 blue offset adjustment
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800EC }, // # Command setting of SPI block
{ SSITX, 0x00080102 }, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]
{ SSITX, 0x00000118 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800CF }, // # Command setting of SPI block
{ SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D0 }, // # Command setting of SPI block
{ SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]
{ SSITX, 0x00000104 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D1 }, // # Command setting of SPI block
{ SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D2 }, // # Command setting of SPI block
{ SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]
{ SSITX, 0x0000013A }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D3 }, // # Command setting of SPI block
{ SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table1 for VGA]
{ SSITX, 0x0000013A }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D4 }, // # Command setting of SPI block
{ SSITX, 0x00080124 }, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]
{ SSITX, 0x0000016E }, //
{ 0, 1 }, // wait_ms(1); // # Wait SPI fifo empty
{ SSITX, 0x000800D5 }, // # Command setting of SPI block
{ SSITX, 0x00000124 }, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800ED }, // # Command setting of SPI block
{ SSITX, 0x00080101 }, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]
{ SSITX, 0x0000010A }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D6 }, // # Command setting of SPI block
{ SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table2 for QVGA]
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D7 }, // # Command setting of SPI block
{ SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table2 for QVGA]
{ SSITX, 0x0000010A }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D8 }, // # Command setting of SPI block
{ SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table2 for QVGA]
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800D9 }, // # Command setting of SPI block
{ SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table2 for QVGA]
{ SSITX, 0x00000114 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800DE }, // # Command setting of SPI block
{ SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table2 for QVGA]
{ SSITX, 0x00000114 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800DF }, // # Command setting of SPI block
{ SSITX, 0x00080112 }, // # ASW timing control (1) [PCLK Sync. Table2 for QVGA]
{ SSITX, 0x0000013F }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800E0 }, // # Command setting of SPI block
{ SSITX, 0x0000010B }, // # ASW timing control (2) [PCLK Sync. Table2 for QVGA]
{ SSITX, 0x000800E2 }, // # Command setting of SPI block
{ SSITX, 0x00000101 }, // # Built-in oscillator frequency division setup [Frequency division ratio : 2 (60Hq)
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800E3 }, // # Command setting of SPI block
{ SSITX, 0x00000136 }, // # Built-in oscillator clock count setup
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800E4 }, // # Command setting of SPI block
{ SSITX, 0x00080100 }, // # CKV timing control for using build-in osc
{ SSITX, 0x00000103 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800E5 }, // # Command setting of SPI block
{ SSITX, 0x00080102 }, // # OEV timing control for using build-in osc
{ SSITX, 0x00000104 }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800E6 }, // # Command setting of SPI block
{ SSITX, 0x00000103 }, // # DCEV timing control for using build-in osc
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800E7 }, // # Command setting of SPI block
{ SSITX, 0x00080104 }, // # ASW timing setup for using build-in osc(1)
{ SSITX, 0x0000010A }, //
{ 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
{ SSITX, 0x000800E8 }, // # Command setting of SPI block
{ SSITX, 0x00000104 }, // # ASW timing setup for using build-in osc(2)
{ CLKENB, 0x000001EF }, // # SYS.CLKENB # DCLK enable
{ START, 0x00000000 }, // # LCD.START # LCDC wait_ms( mode
{ WRSTB, 0x0000003F }, // # LCD.WRSTB # write_client_reg( strobe
{ RDSTB, 0x00000432 }, // # LCD.RDSTB # Read strobe
{ PORT_ENB, 0x00000002 }, // # LCD.PORT_ENB # Asynchronous port enable
{ VSYNIF, 0x00000000 }, // # LCD.VSYNCIF # VSYNC I/F mode set
{ ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
{ ASY_DATB, 0x00000001 }, // # Oscillator start
{ ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
{ ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
{ 0, 10 }, // wait_ms(10);
{ ASY_DATA, 0x80000000 }, // # LCD.ASY_DATx # DUMMY write_client_reg(<28>@*NOTE2
{ ASY_DATB, 0x80000000 }, //
{ ASY_DATC, 0x80000000 }, //
{ ASY_DATD, 0x80000000 }, //
{ ASY_CMDSET, 0x00000009 }, // # LCD.ASY_CMDSET
{ ASY_CMDSET, 0x00000008 }, // # LCD.ASY_CMDSET
{ ASY_DATA, 0x80000007 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
{ ASY_DATB, 0x00004005 }, // # LCD driver control
{ ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
{ ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
{ 0, 20 }, // wait_ms(20);
{ ASY_DATA, 0x80000059 }, // # LCD.ASY_DATx # Index setting of SUB LCDD
{ ASY_DATB, 0x00000000 }, // # LTPS I/F control
{ ASY_CMDSET, 0x00000005 }, // # LCD.ASY_CMDSET # Direct command transfer enable
{ ASY_CMDSET, 0x00000004 }, // # LCD.ASY_CMDSET # Direct command transfer disable
{ VSYNIF, 0x00000001 }, // # LCD.VSYNCIF # VSYNC I/F mode OFF
{ PORT_ENB, 0x00000001 }, // # LCD.PORT_ENB # SYNC I/F output select
/******************************/
{ VSYNIF, 0x00000001 }, // VSYNC I/F mode OFF
{ PORT_ENB, 0x00000001 }, // SYNC I/F mode ON
{ BITMAP1, 0x01E000F0 }, // MDC.BITMAP2 ); // Setup of PITCH size to Frame buffer1
{ BITMAP2, 0x01E000F0 }, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2
{ BITMAP3, 0x01E000F0 }, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3
{ BITMAP4, 0x00DC00B0 }, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4
{ CLKENB, 0x000001EF }, // SYS.CLKENB ); // DCLK supply
{ PORT_ENB, 0x00000001 }, // LCD.PORT_ENB ); // Synchronous port enable
{ PORT, 0x00000004 }, // LCD.PORT ); // Polarity of DE is set to high active
{ PXL, 0x00000002 }, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output)
{ MPLFBUF, 0x00000000 }, // LCD.MPLFBUF ); // Select the reading buffer
{ HCYCLE, 0x0000010b }, // LCD.HCYCLE ); // Setup to VGA size
{ HSW, 0x00000003 }, // LCD.HSW
{ HDE_START, 0x00000007 }, // LCD.HDE_START
{ HDE_SIZE, 0x000000EF }, // LCD.HDE_SIZE
{ VCYCLE, 0x00000285 }, // LCD.VCYCLE
{ VSW, 0x00000001 }, // LCD.VSW
{ VDE_START, 0x00000003 }, // LCD.VDE_START
{ VDE_SIZE, 0x0000027F }, // LCD.VDE_SIZE
{ START, 0x00000001 }, // LCD.START ); // LCDC - Pixel data transfer start
{ 0, 10 }, // wait_ms( 10 );
{ SSITX, 0x000800BC }, // SPI.SSITX ); // Command setting of SPI block
{ SSITX, 0x00000180 }, // Display data setup
{ SSITX, 0x0008003B }, // Command setting of SPI block
{ SSITX, 0x00000100 }, // Quad Data configuration - VGA
{ 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
{ SSITX, 0x000800B0 }, // Command setting of SPI block
{ SSITX, 0x00000116 }, // Power supply ON/OFF control
{ 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
{ SSITX, 0x000800B8 }, // Command setting of SPI block
{ SSITX, 0x000801FF }, // Output control
{ SSITX, 0x000001F5 },
{ 0, 1 }, // wait_ms( 1); // Wait SPI fifo empty
{ SSITX, 0x00000011 }, // wait_ms(-out (Command only)
{ SSITX, 0x00000029 }, // Display on (Command only)
{ SYSTEM_BLOCK1_BASE, 0x00000002 }, // # wakeREQ -> GPIO
{ 0, 0 }
};
static void _panel_init(struct init_table *init_table)
{
unsigned n;
dprintf(INFO, "panel_init()\n");
n = 0;
while (init_table[n].reg != 0 || init_table[n].val != 0) {
if (init_table[n].reg != 0)
mddi_remote_write(init_table[n].val, init_table[n].reg);
else
mdelay(init_table[n].val);
n++;
}
dprintf(INFO, "panel_init() done\n");
}
void panel_init(struct mddi_client_caps *client_caps)
{
switch(client_caps->manufacturer_name) {
case 0xd263: // Toshiba
dprintf(INFO, "Found Toshiba panel\n");
_panel_init(toshiba_480x800_init_table);
break;
case 0x4474: //??
if (client_caps->product_code == 0xc065)
dprintf(INFO, "Found WVGA panel\n");
break;
}
}
void panel_poweron(void)
{
gpio_set(88, 0);
gpio_config(88, GPIO_OUTPUT);
udelay(10);
gpio_set(88, 1);
mdelay(10);
//mdelay(1000); // uncomment for second stage boot
}
void panel_backlight(int on)
{}

83
bootable/bootloader/lk/platform/qsd8k/platform.c Normal file
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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Google, Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <debug.h>
#include <dev/fbcon.h>
#include <kernel/thread.h>
#include <platform/debug.h>
#include <mddi.h>
static struct fbcon_config *fb_config;
void platform_init_interrupts(void);
void platform_init_timer();
void uart3_clock_init(void);
void uart_init(void);
struct fbcon_config *lcdc_init(void);
void platform_early_init(void)
{
//uart3_clock_init();
//uart_init();
platform_init_interrupts();
platform_init_timer();
}
void platform_init(void)
{
dprintf(INFO, "platform_init()\n");
#if (!ENABLE_NANDWRITE)
acpu_clock_init();
#endif
}
void display_init(void)
{
struct fbcon_config *fb_cfg;
#if DISPLAY_TYPE_MDDI
fb_config = mddi_init();
ASSERT(fb_config);
fbcon_setup(fb_config);
#endif
#if DISPLAY_TYPE_LCDC
fb_config = lcdc_init();
ASSERT(fb_config);
fbcon_setup(fb_config);
#endif
}

26
bootable/bootloader/lk/platform/qsd8k/rules.mk Normal file
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LOCAL_DIR := $(GET_LOCAL_DIR)
ARCH := arm
ARM_CPU := cortex-a8
#arm1136j-s
CPU := generic
DEFINES += WITH_CPU_EARLY_INIT=1 WITH_CPU_WARM_BOOT=1 MEMBASE=0
INCLUDES += -I$(LOCAL_DIR)/include
DEVS += fbcon
MODULES += dev/fbcon
OBJS += \
$(LOCAL_DIR)/arch_init.o \
$(LOCAL_DIR)/platform.o \
$(LOCAL_DIR)/interrupts.o \
$(LOCAL_DIR)/gpio.o \
$(LOCAL_DIR)/panel.o \
$(LOCAL_DIR)/acpuclock.o
LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
include platform/msm_shared/rules.mk