M7350v1_en_gpl

bootable/bootloader/lk/platform/omap5912/debug.c

@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2008 Travis Geiselbrecht
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <stdarg.h>
+#include <reg.h>
+#include <debug.h>
+#include <printf.h>
+#include <kernel/thread.h>
+#include <kernel/timer.h>
+#include <platform/debug.h>
+#include <arch/ops.h>
+#include <platform/omap5912.h>
+#include <lib/cbuf.h>
+
+static cbuf_t debug_buf;
+static timer_t debug_timer;
+
+static void write_uart_reg(int uart, int reg, unsigned char data)
+{
+	unsigned long base;
+	int mul = 4;
+
+	switch(uart) {
+		case 0: base = UART0_BASE; break;
+		case 1: base = UART1_BASE; break;
+		case 2: base = UART2_BASE; break;
+		default: return;
+	}
+
+	*(volatile unsigned char *)(base + reg * mul) = data;
+}
+
+static unsigned char read_uart_reg(int uart, int reg)
+{
+	unsigned long base;
+	int mul = 4;
+
+	switch(uart) {
+		case 0: base = UART0_BASE; break;
+		case 1: base = UART1_BASE; break;
+		case 2: base = UART2_BASE; break;
+		default: return 0;
+	}
+
+	return *(volatile unsigned char *)(base + reg * mul);
+}
+
+static int uart_init(void)
+{
+	/* clear the tx & rx fifo and disable */
+	write_uart_reg(0, UART_FCR, 0x6);
+
+	return 0;
+}
+
+static int uart_putc(int port, char c )
+{
+	while (!(read_uart_reg(port, UART_LSR) & (1<<6))) // wait for the shift register to empty
+		;
+  	write_uart_reg(port, UART_THR, c);
+	return 0;
+}
+
+static int uart_getc(int port, bool wait)  /* returns -1 if no data available */
+{
+	if (wait) {
+		while (!(read_uart_reg(port, UART_LSR) & (1<<0))) // wait for data to show up in the rx fifo
+			;
+	} else {
+		if (!(read_uart_reg(port, UART_LSR) & (1<<0)))
+			return -1;
+	}
+	return read_uart_reg(port, UART_RHR);
+}
+
+void _dputc(char c)
+{
+	if (c == '\n')
+		uart_putc(0, '\r');
+	uart_putc(0, c);
+}
+
+static enum handler_return debug_timer_callback(timer_t *t, time_t now, void *arg)
+{
+	signed char c;
+	c = uart_getc(0, false);
+	if (c > 0) {
+		cbuf_write(&debug_buf, &c, 1, false);
+		return INT_RESCHEDULE;
+	} else {
+		return INT_NO_RESCHEDULE;
+	}
+}
+
+int dgetc(char *c, bool wait)
+{
+	ssize_t len;
+
+	len = cbuf_read(&debug_buf, c, 1, wait);
+	return len;
+}
+
+void debug_dump_regs(void)
+{
+	PANIC_UNIMPLEMENTED;
+}
+
+void platform_halt(void)
+{
+	dprintf(ALWAYS, "HALT: spinning forever...\n");
+	for(;;);
+}
+
+void debug_dump_memory_bytes(void *mem, int len)
+{
+	PANIC_UNIMPLEMENTED;
+}
+
+void debug_dump_memory_halfwords(void *mem, int len)
+{
+	PANIC_UNIMPLEMENTED;
+}
+
+void debug_dump_memory_words(void *mem, int len)
+{
+	PANIC_UNIMPLEMENTED;
+}
+
+void debug_set_trace_level(int trace_type, int level)
+{
+	PANIC_UNIMPLEMENTED;
+}
+
+void platform_init_debug(void)
+{
+	cbuf_initialize(&debug_buf, 512);
+	timer_set_periodic(&debug_timer, 10, &debug_timer_callback, NULL);
+}

bootable/bootloader/lk/platform/omap5912/include/platform/omap5912.h

@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2008 Travis Geiselbrecht
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __OMAP5912_H
+#define __OMAP5912_H
+
+/* memory map */
+#define SDRAM_BASE	0x10000000
+
+/* clocks */
+#define DPLL_CTRL	(*(volatile unsigned short *)0xfffecf00)
+#define ARM_CKCTL	(*(volatile unsigned int *)0xfffece00)
+#define ARM_SYSST	(*(volatile unsigned int *)0xfffece18)
+
+/* uart */
+#define UART0_BASE 0xfffb0000
+#define UART1_BASE 0xfffb0800
+#define UART2_BASE 0xfffb9800
+
+#define UART_RHR	0
+#define UART_THR	0
+#define UART_DLL	0
+#define UART_IER	1
+#define UART_DLH	1
+#define UART_IIR	2
+#define UART_FCR	2
+#define UART_EFR	2
+#define UART_LCR	3
+#define UART_MCR	4
+#define UART_LSR	5
+#define UART_MSR	6
+#define UART_TCR	6
+#define UART_SPR	7
+#define UART_TLR	7
+#define UART_MDR1	8
+#define UART_MDR2	9
+#define UART_SFLSR	10
+#define UART_RESUME	11
+#define UART_TXFLL	10
+#define UART_TXFLH	11
+#define UART_SFREGL	12
+#define UART_SFREGH	13
+#define UART_RXFLL	12
+#define UART_RXFLH	13
+#define UART_BLR	14
+#define UART_UASR	14
+#define UART_ACREG	15
+#define UART_SCR	16
+#define UART_SSR	17
+#define UART_EBLR	18
+#define UART_MVR	19
+#define UART_SYSC	20
+
+/* timers */
+#define MPU_TIMER0_BASE      0xfffec500
+#define MPU_TIMER1_BASE      0xfffec600
+#define MPU_TIMER2_BASE      0xfffec700
+#define WATCHDOG_TIMER_BASE  0xfffec800
+#define OS_TIMER_BASE        0xfffb9000
+#define GP_TIMER1_BASE       0xfffb1400
+#define GP_TIMER2_BASE       0xfffb1c00
+#define GP_TIMER3_BASE       0xfffb2400
+#define GP_TIMER4_BASE       0xfffb2c00
+#define GP_TIMER5_BASE       0xfffb3400
+#define GP_TIMER6_BASE       0xfffb3c00
+#define GP_TIMER7_BASE       0xfffb4400
+#define GP_TIMER8_BASE       0xfffb5c00
+
+#define MPU_CNTL_TIMER1		(*(volatile unsigned int *)(MPU_TIMER1_BASE + 0x00))
+#define MPU_LOAD_TIMER1		(*(volatile unsigned int *)(MPU_TIMER1_BASE + 0x04))
+#define MPU_READ_TIMER1		(*(volatile unsigned int *)(MPU_TIMER1_BASE + 0x08))
+#define MPU_CNTL_TIMER2		(*(volatile unsigned int *)(MPU_TIMER2_BASE + 0x00))
+#define MPU_LOAD_TIMER2		(*(volatile unsigned int *)(MPU_TIMER2_BASE + 0x04))
+#define MPU_READ_TIMER2		(*(volatile unsigned int *)(MPU_TIMER2_BASE + 0x08))
+#define MPU_CNTL_TIMER3		(*(volatile unsigned int *)(MPU_TIMER3_BASE + 0x00))
+#define MPU_LOAD_TIMER3		(*(volatile unsigned int *)(MPU_TIMER3_BASE + 0x04))
+#define MPU_READ_TIMER3		(*(volatile unsigned int *)(MPU_TIMER3_BASE + 0x08))
+
+#define OS_TIMER_TICK_VALUE_REG 	(*(volatile unsigned int *)(OS_TIMER_BASE + 0x00))
+#define OS_TIMER_TICK_COUNTER_REG 	(*(volatile unsigned int *)(OS_TIMER_BASE + 0x04))
+#define OS_TIMER_CTRL_REG		(*(volatile unsigned int *)(OS_TIMER_BASE + 0x08))
+
+
+/* interrupt controller */
+#define INT_VECTORS			(32 + 128)
+#define INTCON0_BASE		0xfffecb00	
+#define INTCON1_BASE		0xfffe0000
+#define INTCON2_BASE		0xfffe0100
+#define INTCON3_BASE		0xfffe0200
+#define INTCON4_BASE		0xfffe0300
+
+#define INTCON_ITR			0x00
+#define INTCON_MIR			0x04
+#define INTCON_SIR_IRQ		0x10
+#define INTCON_SIR_FIQ		0x14
+#define INTCON_CONTROL		0x18
+#define INTCON_ILR_BASE		0x1c
+#define INTCON_SISR			0x9c
+#define INTCON_GMR			0xa0	/* only on first level controller */
+#define INTCON_STATUS		0xa0	/* only on second level controllers */
+#define INTCON_OCP_CFG		0xa4
+#define INTCON_INTH_REV		0xa8
+
+/* interrupts */
+#define IRQ_TIMER3			16
+#define IRQ_GPTIMER1		17
+#define IRQ_GPTIMER2		18
+#define IRQ_TIMER1			26
+#define IRQ_WD_TIMER		27
+#define IRQ_TIMER2			30
+#define IRQ_OS_TIMER		(32 + 22)
+#define IRQ_GPTIMER3		(32 + 34)
+#define IRQ_GPTIMER4		(32 + 35)
+#define IRQ_GPTIMER5		(32 + 36)
+#define IRQ_GPTIMER6		(32 + 37)
+#define IRQ_GPTIMER7		(32 + 38)
+#define IRQ_GPTIMER8		(32 + 39)
+
+#endif
+

bootable/bootloader/lk/platform/omap5912/interrupts.c

@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2008 Travis Geiselbrecht
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <err.h>
+#include <sys/types.h>
+#include <debug.h>
+#include <reg.h>
+#include <kernel/thread.h>
+#include <platform/interrupts.h>
+#include <arch/ops.h>
+#include <arch/arm.h>
+#include "platform_p.h"
+#include <platform/omap5912.h>
+
+struct int_handler_struct {
+	int_handler handler;
+	void *arg;
+};
+
+static struct int_handler_struct int_handler_table[INT_VECTORS];
+
+static const uint32_t icBase[5] = {
+	INTCON0_BASE, INTCON1_BASE, INTCON2_BASE, INTCON3_BASE, INTCON4_BASE };
+
+/* a bitmap of the level triggered interrupt vectors */
+static uint32_t level_trigger[5] = {
+	0xb3fefe8f,	// level 1 0-31
+	0xfdb3c1fd,	// level 2 0-31
+	0xfffff7ff, // level 2 32-63
+	0xbfffffff, // level 2 64-95
+	0xffffffff // level 2 96-128
+};
+
+static inline volatile uint32_t *ICReg(uint controller, uint reg)
+{
+	return (volatile uint32_t *)(icBase[controller] + reg);
+}
+
+static inline uint32_t readICReg(uint controller, uint reg)
+{
+	return *ICReg(controller, reg);
+}
+static inline void writeICReg(uint controller, uint reg, uint val)
+{
+	*ICReg(controller, reg) = val;
+}
+
+static inline uint vectorToController(uint vector)
+{
+	return vector / 32;
+}
+
+void platform_init_interrupts(void)
+{
+	unsigned int i;
+
+	// mask all interrupts
+	*ICReg(0, INTCON_MIR) = 0xfffffffa;
+	*ICReg(1, INTCON_MIR) = 0xffffffff;
+	*ICReg(2, INTCON_MIR) = 0xffffffff;
+	*ICReg(3, INTCON_MIR) = 0xffffffff;
+	*ICReg(4, INTCON_MIR) = 0xffffffff;
+
+	// set up each of the interrupts
+	for (i = 0; i < INT_VECTORS; i++) {
+		// set each vector up as high priority, IRQ, and default edge/level sensitivity
+		*ICReg(i / 32, INTCON_ILR_BASE + 4*(i%32)) = ((level_trigger[i/32] & (1<<(i%32))) ? (1<<1) : (0<<1)) | 0;
+	}
+
+	// clear any pending interrupts
+	*ICReg(0, INTCON_ITR) = 0;
+	*ICReg(1, INTCON_ITR) = 0;
+	*ICReg(2, INTCON_ITR) = 0;
+	*ICReg(3, INTCON_ITR) = 0;
+	*ICReg(4, INTCON_ITR) = 0;
+
+	// globally unmask interrupts
+	*ICReg(1, INTCON_CONTROL) = 3;
+	*ICReg(0, INTCON_CONTROL) = 3;
+	*ICReg(0, INTCON_GMR) = 0;
+}
+
+status_t mask_interrupt(unsigned int vector)
+{
+	if (vector >= INT_VECTORS)
+		return ERR_INVALID_ARGS;
+
+//	dprintf("%s: vector %d\n", __PRETTY_FUNCTION__, vector);
+
+	enter_critical_section();
+
+	volatile uint32_t *mir = ICReg(vectorToController(vector), INTCON_MIR);
+	*mir = *mir | (1<<(vector % 32));
+
+	exit_critical_section();
+
+	return NO_ERROR;
+}
+
+status_t unmask_interrupt(unsigned int vector)
+{
+	if (vector >= INT_VECTORS)
+		return ERR_INVALID_ARGS;
+
+//	dprintf("%s: vector %d\n", __PRETTY_FUNCTION__, vector);
+
+	enter_critical_section();
+
+	volatile uint32_t *mir = ICReg(vectorToController(vector), INTCON_MIR);
+	*mir = *mir & ~(1<<(vector % 32));
+
+	exit_critical_section();
+
+	return NO_ERROR;
+}
+
+enum handler_return platform_irq(struct arm_iframe *frame)
+{
+	// get the current vector
+	unsigned int vector;
+   
+#if THREAD_STATS
+	thread_stats.interrupts++;
+#endif
+
+	// read from the first level int handler
+	vector = *ICReg(0, INTCON_SIR_IRQ);
+	
+	// see if it's coming from the second level handler
+	if (vector == 0) {
+		vector = *ICReg(1, INTCON_SIR_IRQ) + 32;
+	}
+
+//	dprintf("platform_irq: spsr 0x%x, pc 0x%x, currthread %p, vector %d\n", frame->spsr, frame->pc, current_thread, vector);
+
+	// deliver the interrupt
+	enum handler_return ret; 
+
+	ret = INT_NO_RESCHEDULE;
+	if (int_handler_table[vector].handler)
+		ret = int_handler_table[vector].handler(int_handler_table[vector].arg);
+
+	// ack the interrupt
+	if (vector >= 32) {
+		// interrupt is chained, so ack the second level first, and then the first
+		*ICReg(vector / 32, INTCON_ITR) = ~(1 << (vector % 32));
+		*ICReg(1, INTCON_CONTROL) |= 1;
+		vector = 0; // force the following code to ack the chained first level vector
+	} 
+
+	*ICReg(0, INTCON_ITR) = ~(1 << vector);
+	*ICReg(0, INTCON_CONTROL) = 1;
+
+	return ret;
+}
+
+void platform_fiq(struct arm_iframe *frame)
+{
+	PANIC_UNIMPLEMENTED;
+}
+
+void register_int_handler(unsigned int vector, int_handler handler, void *arg)
+{
+	if (vector >= INT_VECTORS)
+		panic("register_int_handler: vector out of range %d\n", vector);
+
+	enter_critical_section();
+
+	int_handler_table[vector].handler = handler;
+	int_handler_table[vector].arg = arg;
+
+	exit_critical_section();
+}
+

bootable/bootloader/lk/platform/omap5912/platform.c

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2008-2009 Travis Geiselbrecht
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <err.h>
+#include <debug.h>
+#include <platform.h>
+#include "platform_p.h"
+#include <platform/omap5912.h>
+#include <arch/arm/mmu.h>
+
+void platform_init_mmu_mappings(void)
+{
+	/* do some memory map initialization */
+	addr_t addr;
+	arm_mmu_map_section(SDRAM_BASE, 0, MMU_FLAG_CACHED|MMU_FLAG_BUFFERED);
+	for (addr = SDRAM_BASE; addr < SDRAM_BASE + SDRAM_SIZE; addr += (1024*1024)) {
+		arm_mmu_map_section(addr, addr, MMU_FLAG_CACHED|MMU_FLAG_BUFFERED|MMU_FLAG_READWRITE);
+	}
+}
+
+void platform_early_init(void)
+{
+	/* initialize the interrupt controller */
+	platform_init_interrupts();
+
+	/* initialize the timer block */
+	platform_init_timer();
+}
+
+void platform_init(void)
+{
+	platform_init_debug();
+}
+

bootable/bootloader/lk/platform/omap5912/platform_p.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2008-2009 Travis Geiselbrecht
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __PLATFORM_P_H
+#define __PLATFORM_P_H
+
+void platform_init_interrupts(void);
+void platform_init_timer(void);
+void platform_init_debug(void);
+
+#endif
+

bootable/bootloader/lk/platform/omap5912/rules.mk

@@ -0,0 +1,27 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+ARCH := arm
+ARM_CPU := arm926ej-s
+CPU := generic
+
+MODULES += \
+	lib/cbuf
+
+INCLUDES += \
+	-I$(LOCAL_DIR)/include
+
+OBJS += \
+	$(LOCAL_DIR)/debug.o \
+	$(LOCAL_DIR)/interrupts.o \
+	$(LOCAL_DIR)/platform.o \
+	$(LOCAL_DIR)/timer.o
+
+
+#	$(LOCAL_DIR)/console.o \
+
+MEMBASE := 0x10000000
+#MEMSIZE := 0x02000000	# 32MB
+
+LINKER_SCRIPT += \
+	$(BUILDDIR)/system-onesegment.ld
+

bootable/bootloader/lk/platform/omap5912/timer.c

@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2008 Travis Geiselbrecht
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <sys/types.h>
+#include <err.h>
+#include <kernel/thread.h>
+#include <debug.h>
+#include <platform.h>
+#include <platform/interrupts.h>
+#include <platform/timer.h>
+#include <platform/omap5912.h>
+#include "platform_p.h"
+
+static time_t system_time = 0;
+
+static time_t tick_interval;
+static uint32_t ticks_per_interval;
+static platform_timer_callback t_callback;
+static void *callback_arg;
+
+status_t platform_set_periodic_timer(platform_timer_callback callback, void *arg, time_t interval)
+{
+	enter_critical_section();
+
+	t_callback = callback;
+	callback_arg = arg;
+	tick_interval = interval;
+	ticks_per_interval = interval * 32768 / 1000; // interval is in ms
+
+	OS_TIMER_CTRL_REG = 0; // stop it
+	OS_TIMER_TICK_VALUE_REG = ticks_per_interval;
+	OS_TIMER_CTRL_REG = (1<<3) | (1<<2) | (1<<1) | (1<<0);
+
+	exit_critical_section();
+
+	return NO_ERROR;
+}
+
+time_t current_time(void)
+{
+	time_t t;
+	uint32_t delta_ticks;
+	uint32_t delta_ticks2;
+
+retry:
+	delta_ticks = OS_TIMER_TICK_COUNTER_REG;
+	t = system_time;
+	delta_ticks2 = OS_TIMER_TICK_COUNTER_REG;
+	if (delta_ticks2 > delta_ticks)
+		goto retry;
+
+	t += ((ticks_per_interval - delta_ticks2) * tick_interval) / ticks_per_interval;
+
+	return t;
+}
+
+bigtime_t current_time_hires(void)
+{
+	time_t t;
+	uint32_t delta_ticks;
+	uint32_t delta_ticks2;
+
+retry:
+	delta_ticks = OS_TIMER_TICK_COUNTER_REG;
+	t = system_time;
+	delta_ticks2 = OS_TIMER_TICK_COUNTER_REG;
+	if (delta_ticks2 > delta_ticks)
+		goto retry;
+
+	t += ((ticks_per_interval - delta_ticks2) * tick_interval) / ticks_per_interval;
+
+	return t * 1000ULL;
+}
+
+
+static enum handler_return os_timer_tick(void *arg)
+{
+	system_time += tick_interval;
+//	dprintf("os_timer_tick %d\n", system_time);
+
+	return t_callback(callback_arg, system_time);
+}
+
+void platform_init_timer(void)
+{
+	OS_TIMER_CTRL_REG = 0; // stop the timer if it's already running
+
+	register_int_handler(IRQ_OS_TIMER, &os_timer_tick, NULL);
+	unmask_interrupt(IRQ_OS_TIMER);
+}
+