tobi/M7350
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

M7350v1_en_gpl

Browse Source
This commit is contained in:
T
2024-09-09 08:52:07 +00:00
commit f9cc65cfda
65988 changed files with 26357421 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bootable/bootloader/lk/platform/msm_shared/include/bam.h
+264
View File
@@ -0,0 +1,264 @@
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLATFORM_MSM_SHARED_BAM_H
#define __PLATFORM_MSM_SHARED_BAM_H
#include <stdint.h>
#include <compiler.h>
#define BAM_DESC_SIZE 8
#define BAM_CE_SIZE 16
#define BAM_MAX_DESC_DATA_LEN 0xFFFF
#define BAM_NDP_MAX_DESC_DATA_LEN 0x7FFF
#define BAM_DATA_READ 0
#define BAM_DATA_WRITE 1
#define BAM_CTRL_REG(x) (0x0000 + (x))
#define BAM_SW_RST_BIT_MASK 1
#define BAM_ENABLE_BIT_MASK (1 << 1)
#define BAM_DESC_CNT_TRSHLD_REG(x) (0x0008 + (x))
#define COUNT_TRESHOLD_MASK 0xFF
#define BAM_IRQ_SRCS(x, n) (0x00000800 + (0x80 * (n)) + (x))
#define BAM_IRQ_SRCS_MSK(x, n) (0x00000804 + (0x80 * (n)) + (x))
#define BAM_IRQ_MASK (1 << 31)
#define P_IRQ_MASK (1)
/* Pipe Interrupt masks */
enum p_int_type
{
P_PRCSD_DESC_EN_MASK = 1,
P_OUT_OF_DESC_EN_MASK = (1 << 3),
P_ERR_EN_MASK = (1 << 4),
P_TRNSFR_END_EN_MASK = (1 << 5)
};
#define BAM_IRQ_STTS(x) (0x00000014 + (x))
#define BAM_IRQ_SRCS_UNMASKED(x) (0x00000030 + (x))
#define BAM_IRQ_EN_REG(x) (0x001C + (x))
#define BAM_TIMER_EN_MASK (1 << 4)
/* Available only in BAM-Lite */
#define BAM_EMPTY_EN_MASK (1 << 3)
#define BAM_ERROR_EN_MASK (1 << 2)
/* Available only in BAM */
#define BAM_HRESP_ERR_EN_MASK (1 << 1)
#define BAM_TRUST_REG(x) (0x00000070 + (x))
#define BAM_EE_MASK (7 << 0)
#define BAM_RESET_BLK_MASK (1 << 7)
#define BAM_LOCK_EE_CTRL_MASK (1 << 13)
#define BAM_CNFG_BITS(x) (0x0000007C + (x))
#define BAM_P_CTRLn(n, x) (0x00001000 + 0x1000 * (n) + (x))
#define P_SYS_MODE_MASK (1 << 5)
/* 1: Producer mode 0: Consumer mode */
#define P_DIRECTION_SHIFT 3
#define P_LOCK_GRP_SHIFT 16
#define P_ENABLE (1 << 1)
#define BAM_P_RSTn(n, x) (0x00001000 + 0x4 + 0x1000 * (n) + (x))
#define BAM_P_IRQ_STTSn(n, x) (0x00001000 + 0x10 + 0x1000 * (n) + (x))
#define BAM_P_IRQ_CLRn(n, x) (0x00001000 + 0x14 + 0x1000 * (n) + (x))
#define BAM_P_IRQ_ENn(n, x) (0x00001000 + 0x18 + 0x1000 * (n) + (x))
#define BAM_P_TRUST_REGn(n, x) (0x00001000 + 0x30 + 0x1000 * (n) + (x))
#define BAM_P_SW_OFSTSn(n, x) (0x00001800 + 0x1000 * (n) + (x))
#define BAM_P_EVNT_REGn(n, x) (0x00001818 + 0x1000 * (n) + (x))
#define P_DESC_FIFO_PEER_OFST_MASK 0xFF
#define BAM_P_DESC_FIFO_ADDRn(n, x) (0x0000181C + 0x1000 * (n) + (x))
#define BAM_P_FIFO_SIZESn(n, x) (0x00001820 + 0x1000 * (n) + (x))
/* Flags for descriptors */
#define BAM_DESC_INT_FLAG (1 << 7)
#define BAM_DESC_EOT_FLAG (1 << 6)
#define BAM_DESC_EOB_FLAG (1 << 5)
#define BAM_DESC_NWD_FLAG (1 << 4)
#define BAM_DESC_CMD_FLAG (1 << 3)
#define BAM_DESC_LOCK_FLAG (1 << 2)
#define BAM_DESC_UNLOCK_FLAG (1 << 1)
enum bam_ce_cmd_t{
CE_WRITE_TYPE = 0,
CE_READ_TYPE = 1
};
/* result type */
typedef enum {
BAM_RESULT_SUCCESS = 0,
BAM_RESULT_FAILURE = 1,
BAM_RESULT_TIMEOUT = 2
} bam_result_t;
/* Enum to define the BAM type:
* BAM2BAM:Producer BAM to Consumer BAM.
* SYS2BAM:Producer System to Consumer BAM.
* BAM2SYS:Producer BAM to Consumer System.
*/
enum bam_transaction_type {
SYS2BAM,
BAM2SYS,
BAM2BAM,
};
/* Enum to define BAM mode:
* SPS:Use BAM pipes.
* DIRECT:Pipes are disabled.
* LEGACY:BAM is not used.
*/
enum bam_mode {
SPS,
DIRECT,
LEGACY,
};
/* Enum to define BAM pipe states:
* ENABLED:Producer and Consumer pipes are enabled.
* HALT:Consumer pipe is halted. (Preferred type)
* FULL_HALT:Both Producer and Consumer pipes are halted.
*/
enum bam_pipe_state {
ENABLED,
HALT,
FULL_HALT,
};
enum bam_type {
BAM_LITE,
BAM,
};
/* Structure to define BAM descriptors that describe the data
* descriptors written to the data FIFO.
* addr:Descriptor address.
* size:Each descriptor is 8 bytes. Size of the descriptor fifo must
* contain an integer number of Descriptors.
*/
struct bam_desc {
uint32_t addr;
uint16_t size;
uint8_t reserved;
uint8_t flags;
} __PACKED;
struct bam_desc_fifo {
struct bam_desc *head;
struct bam_desc *current;
uint16_t size;
uint16_t offset;
};
/* Structure to define BAM pipes
* pipe_state: BAM pipe states.
* trans_type: BAM tranaction type.
* evt_gen_threshold: This register configures the threshold value for
* Read/Write event generation by the BAM
* towards another BAM.
* fifo: Circular fifo associated with this pipe.
* num_pipe: Number of pipes used in this bam.
* pipe: Pipe number for this pipe.
* spi_num: SPI number for the BAM interrupt.
* int_mode: Specifies the pipe mode.
* 1: Interrupt mode
* 0: Polling mode
*/
struct bam_pipe {
enum bam_pipe_state state;
enum bam_transaction_type trans_type;
struct bam_desc_fifo fifo;
uint16_t evt_gen_threshold;
uint8_t pipe_num;
uint8_t spi_num;
uint8_t int_mode;
uint8_t initialized;
uint8_t lock_grp;
};
/* Structure to define a BAM instance being used
* base:Base address for the BAM.
* type:BAM type.
* mode:BAM mode.
* pipe_pair:The pipe pairs to be used to access the BAM.
* threshold:This Register holds a threshold value for the
* counter summing the Size of the Descriptors Provided.
* ee:Execution Environment for the BAM.
* desc_len: Max desc length for the current BAM.
*/
struct bam_instance {
uint32_t base;
enum bam_type type;
enum bam_mode mode;
uint8_t num_of_pipes;
struct bam_pipe pipe[3];
uint16_t threshold;
uint32_t ee;
uint16_t max_desc_len;
void (*callback)(int);
};
/* Command element(CE) structure*/
struct cmd_element {
uint32_t addr_n_cmd;
uint32_t reg_data;
uint32_t reg_mask;
uint32_t reserve;
} __PACKED;
void bam_init(struct bam_instance *bam);
void bam_sys_pipe_init(struct bam_instance *bam,
uint8_t pipe_num);
int bam_pipe_fifo_init(struct bam_instance *bam,
uint8_t pipe_num);
struct cmd_element* bam_add_cmd_element(struct cmd_element *ptr,
uint32_t addr,
uint32_t data,
enum bam_ce_cmd_t cmd_type);
int bam_add_desc(struct bam_instance *bam,
unsigned int pipe_num,
unsigned char *data_ptr,
unsigned int data_len,
unsigned flags);
int bam_add_one_desc(struct bam_instance *bam,
unsigned int pipe_num,
unsigned char*,
uint32_t len,
uint8_t flags);
void bam_sys_gen_event(struct bam_instance *bam,
uint8_t pipe_num,
unsigned int num_desc);
int bam_wait_for_interrupt(struct bam_instance *bam,
uint8_t pipe_num,
enum p_int_type interrupt);
void bam_read_offset_update(struct bam_instance *bam, unsigned int pipe_num);
void bam_pipe_reset(struct bam_instance *bam,
uint8_t pipe_num);
#endif
bootable/bootloader/lk/platform/msm_shared/include/baseband.h
+46
View File
@@ -0,0 +1,46 @@
/* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __BASEBAND_H__
#define __BASEBAND_H__
enum baseband {
BASEBAND_MSM = 0,
BASEBAND_APQ = 1,
BASEBAND_CSFB = 2,
BASEBAND_SVLTE1 = 3,
BASEBAND_SVLTE2A = 4,
BASEBAND_MDM = 5,
BASEBAND_SGLTE = 6,
BASEBAND_DSDA = 7,
BASEBAND_DSDA2 = 8,
BASEBAND_SGLTE2 = 9,
BASEBAND_32BITS = 0x7FFFFFFF
};
#endif
bootable/bootloader/lk/platform/msm_shared/include/blsp_qup.h
+45
View File
@@ -0,0 +1,45 @@
/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __BLSP_QUP_H_
#define __BLSP_QUP_H_
enum {
QUP_ID_0 = 0,
QUP_ID_1,
QUP_ID_2,
QUP_ID_3,
QUP_ID_4,
QUP_ID_5,
} qup_instance;
enum {
BLSP_ID_1 = 1,
BLSP_ID_2,
} blsp_instance;
#endif /* __BLSP_QUP_H_ */
bootable/bootloader/lk/platform/msm_shared/include/board.h
+64
View File
@@ -0,0 +1,64 @@
/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Fundation, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __BOARD_H
#define __BOARD_H
#include <smem.h>
#define LINUX_MACHTYPE_UNKNOWN 0
#define BOARD_SOC_VERSION2 0x20000
#define MAX_PMIC_DEVICES SMEM_MAX_PMIC_DEVICES
struct board_pmic_data {
uint32_t pmic_type;
uint32_t pmic_version;
};
struct board_data {
uint32_t platform;
uint32_t platform_version;
uint32_t platform_hw;
uint32_t platform_subtype;
uint32_t target;
uint32_t baseband;
struct board_pmic_data pmic_info[MAX_PMIC_DEVICES];
};
void board_init();
void target_detect(struct board_data *);
void target_baseband_detect(struct board_data *);
uint32_t board_platform_id();
uint32_t board_target_id();
uint32_t board_baseband();
uint32_t board_hardware_id();
uint8_t board_pmic_info(struct board_pmic_data *, uint8_t num_ent);
uint32_t board_soc_version();
#endif
bootable/bootloader/lk/platform/msm_shared/include/certificate.h
+31
View File
@@ -0,0 +1,31 @@
/* Copyright (c) 2011, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#define CERTIFICATE_SIZE 724
extern const char certBuffer[CERTIFICATE_SIZE];
bootable/bootloader/lk/platform/msm_shared/include/clock-local.h
+234
View File
@@ -0,0 +1,234 @@
/*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of The Linux Foundation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef CLOCK_LOCAL_H
#define CLOCK_LOCAL_H
struct clk;
struct clk_ops;
#define FREQ_END (UINT_MAX-1)
#define F_END \
{ \
.freq_hz = FREQ_END, \
}
#define container_of(ptr, type, member) \
((type *)((addr_t)(ptr) - offsetof(type, member)))
/*
* Bit manipulation macros
*/
#define BM(msb, lsb) (((((uint32_t)-1) << (31-msb)) >> (31-msb+lsb)) << lsb)
#define BVAL(msb, lsb, val) (((val) << lsb) & BM(msb, lsb))
/*
* Halt/Status Checking Mode Macros
*/
#define HALT 0 /* Bit pol: 1 = halted */
#define NOCHECK 1 /* No bit to check, do nothing */
#define HALT_VOTED 2 /* Bit pol: 1 = halted; delay on disable */
#define ENABLE 3 /* Bit pol: 1 = running */
#define ENABLE_VOTED 4 /* Bit pol: 1 = running; delay on disable */
#define DELAY 5 /* No bit to check, just delay */
/*
* Variables from clock-local driver
*/
extern struct fixed_clk gnd_clk;
/*
* Generic frequency-definition structs and macros
*/
struct clk_freq_tbl {
const uint32_t freq_hz;
struct clk *src_clk;
const uint32_t md_val;
const uint32_t ns_val;
const uint32_t ctl_val;
uint32_t mnd_en_mask;
void *const extra_freq_data;
};
extern struct clk_freq_tbl local_dummy_freq;
/* Some clocks have two banks to avoid glitches when switching frequencies.
* The unused bank is programmed while running on the other bank, and
* switched to afterwards. The following two structs describe the banks. */
struct bank_mask_info {
void *const md_reg;
const uint32_t ns_mask;
const uint32_t rst_mask;
const uint32_t mnd_en_mask;
const uint32_t mode_mask;
};
struct bank_masks {
const uint32_t bank_sel_mask;
const struct bank_mask_info bank0_mask;
const struct bank_mask_info bank1_mask;
};
/**
* struct branch - branch on/off
* @ctl_reg: clock control register
* @en_mask: ORed with @ctl_reg to enable the clock
* @halt_reg: halt register
* @halt_check: type of halt check to perform
* @halt_bit: ANDed with @halt_reg to test for clock halted
* @reset_reg: reset register
* @reset_mask: ORed with @reset_reg to reset the clock domain
*/
struct branch {
void *const ctl_reg;
const uint32_t en_mask;
void *const halt_reg;
const uint16_t halt_check;
const uint16_t halt_bit;
void *const reset_reg;
const uint32_t reset_mask;
};
/*
* Generic clock-definition struct and macros
*/
struct rcg_clk {
bool enabled;
void *const ns_reg;
void *const md_reg;
const uint32_t root_en_mask;
uint32_t ns_mask;
const uint32_t ctl_mask;
struct bank_masks *const bank_masks;
void (*set_rate)(struct rcg_clk *, struct clk_freq_tbl *);
struct clk_freq_tbl *const freq_tbl;
struct clk_freq_tbl *current_freq;
struct clk *depends;
struct branch b;
struct clk c;
};
static inline struct rcg_clk *to_rcg_clk(struct clk *clk)
{
return container_of(clk, struct rcg_clk, c);
}
/**
* struct fixed_clk - fixed rate clock (used for crystal oscillators)
* @rate: output rate
* @c: clk
*/
struct fixed_clk {
unsigned long rate;
struct clk c;
};
static inline struct fixed_clk *to_fixed_clk(struct clk *clk)
{
return container_of(clk, struct fixed_clk, c);
}
static inline unsigned fixed_clk_get_rate(struct clk *clk)
{
struct fixed_clk *f = to_fixed_clk(clk);
return f->rate;
}
/**
* struct branch_clk - branch
* @enabled: true if clock is on, false otherwise
* @b: branch
* @parent: clock source
* @c: clk
*
* An on/off switch with a rate derived from the parent.
*/
struct branch_clk {
bool enabled;
struct branch b;
struct clk *parent;
struct clk c;
};
static inline struct branch_clk *to_branch_clk(struct clk *clk)
{
return container_of(clk, struct branch_clk, c);
}
int branch_clk_enable(struct clk *clk);
void branch_clk_disable(struct clk *clk);
struct clk *branch_clk_get_parent(struct clk *clk);
int branch_clk_set_parent(struct clk *clk, struct clk *parent);
int branch_clk_is_enabled(struct clk *clk);
void branch_clk_auto_off(struct clk *clk);
int branch_clk_reset(struct clk *c, enum clk_reset_action action);
/**
* struct measure_clk - for rate measurement debug use
* @sample_ticks: sample period in reference clock ticks
* @multiplier: measurement scale-up factor
* @divider: measurement scale-down factor
* @c: clk
*/
struct measure_clk {
uint64_t sample_ticks;
uint32_t multiplier;
uint32_t divider;
struct clk c;
};
extern struct clk_ops clk_ops_measure;
static inline struct measure_clk *to_measure_clk(struct clk *clk)
{
return container_of(clk, struct measure_clk, c);
}
/*
* clk_ops APIs
*/
int local_clk_enable(struct clk *c);
void local_clk_disable(struct clk *c);
int local_clk_set_rate(struct clk *c, unsigned rate);
unsigned local_clk_get_rate(struct clk *c);
int local_clk_is_enabled(struct clk *clk);
long local_clk_round_rate(struct clk *c, unsigned rate);
struct clk *local_clk_get_parent(struct clk *clk);
/*
* Generic set-rate implementations
*/
void set_rate_mnd(struct rcg_clk *clk, struct clk_freq_tbl *nf);
void set_rate_mnd_banked(struct rcg_clk *clk, struct clk_freq_tbl *nf);
void set_rate_nop(struct rcg_clk *clk, struct clk_freq_tbl *nf);
#endif
bootable/bootloader/lk/platform/msm_shared/include/clock.h
+190
View File
@@ -0,0 +1,190 @@
/*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of The Linux Foundation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef CLOCK_H
#define CLOCK_H
#undef readl_relaxed
#undef writel_relaxed
#ifdef MSM_SECURE_IO
#define readl_relaxed secure_readl
#define writel_relaxed secure_writel
#else
#define readl_relaxed readl
#define writel_relaxed writel
#endif
enum clk_reset_action {
CLK_RESET_DEASSERT = 0,
CLK_RESET_ASSERT = 1
};
struct clk;
struct clk_ops {
int (*enable)(struct clk *clk);
void (*disable)(struct clk *clk);
void (*auto_off)(struct clk *clk);
int (*reset)(struct clk *clk, enum clk_reset_action action);
int (*set_rate)(struct clk *clk, unsigned rate);
int (*set_min_rate)(struct clk *clk, unsigned rate);
int (*set_max_rate)(struct clk *clk, unsigned rate);
int (*set_flags)(struct clk *clk, unsigned flags);
unsigned (*get_rate)(struct clk *clk);
int (*list_rate)(struct clk *clk, unsigned n);
int (*is_enabled)(struct clk *clk);
long (*round_rate)(struct clk *clk, unsigned rate);
int (*set_parent)(struct clk *clk, struct clk *parent);
struct clk *(*get_parent)(struct clk *clk);
bool (*is_local)(struct clk *clk);
};
/**
* struct clk
* @count: enable refcount
* @lock: protects clk_enable()/clk_disable() path and @count
*/
struct clk {
uint32_t flags;
uint32_t rate;
struct clk_ops *ops;
const char *dbg_name;
unsigned count;
};
/**
* clk_get - lookup and obtain a reference to a clock producer.
* @dev: device for clock "consumer"
* @id: clock comsumer ID
*
* Returns a struct clk corresponding to the clock producer, or
* valid IS_ERR() condition containing errno. The implementation
* uses @dev and @id to determine the clock consumer, and thereby
* the clock producer. (IOW, @id may be identical strings, but
* clk_get may return different clock producers depending on @dev.)
*
* Drivers must assume that the clock source is not enabled.
*
* clk_get should not be called from within interrupt context.
*/
struct clk *clk_get(const char *id);
/**
* clk_enable - inform the system when the clock source should be running.
* @clk: clock source
*
* If the clock can not be enabled/disabled, this should return success.
*
* Returns success (0) or negative errno.
*/
int clk_enable(struct clk *clk);
/**
* clk_disable - inform the system when the clock source is no longer required.
* @clk: clock source
*
* Inform the system that a clock source is no longer required by
* a driver and may be shut down.
*
* Implementation detail: if the clock source is shared between
* multiple drivers, clk_enable() calls must be balanced by the
* same number of clk_disable() calls for the clock source to be
* disabled.
*/
void clk_disable(struct clk *clk);
/**
* clk_get_rate - obtain the current clock rate (in Hz) for a clock source.
* This is only valid once the clock source has been enabled.
* @clk: clock source
*/
unsigned long clk_get_rate(struct clk *clk);
/**
* clk_set_rate - set the clock rate for a clock source
* @clk: clock source
* @rate: desired clock rate in Hz
*
* Returns success (0) or negative errno.
*/
int clk_set_rate(struct clk *clk, unsigned long rate);
/**
* clk_set_parent - set the parent clock source for this clock
* @clk: clock source
* @parent: parent clock source
*
* Returns success (0) or negative errno.
*/
int clk_set_parent(struct clk *clk, struct clk *parent);
/**
* clk_get_parent - get the parent clock source for this clock
* @clk: clock source
*
* Returns struct clk corresponding to parent clock source, or
* valid IS_ERR() condition containing errno.
*/
struct clk *clk_get_parent(struct clk *clk);
/**
* clk_get_set_enable -
* -- get the clock.
* -- set the rate to @rate if @rate is non-zero
* -- enable the clock if @enable = ture;
* @id: clock identifier (char *)
* @rate: desired clock rate in Hz
*
* Returns success (0) or negative errno.
*/
int clk_get_set_enable(char *id, unsigned long rate, bool enable);
struct clk_lookup {
const char *con_id;
struct clk *clk;
};
struct clk_list {
struct clk_lookup *clist;
unsigned num;
};
#define CLK_LOOKUP(con, c) { .con_id = con, .clk = &c }
#ifdef DEBUG_CLOCK
struct clk_list *clk_get_list(void);
#endif
/**
* clk_init - register all the clocks in the system.
* @clist: pointer to clock list
* @num: number of clocks in the list
*/
void clk_init(struct clk_lookup *clist, unsigned num);
#endif
bootable/bootloader/lk/platform/msm_shared/include/clock_lib2.h
+198
View File
@@ -0,0 +1,198 @@
/*
* Copyright (c) 2012-2013, Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Linux Foundation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __CLOCK_LIB2_H
#define __CLOCK_LIB2_H
/*
* Bit manipulation macros
*/
#define BIT(n) (1 << (n))
#define BM(msb, lsb) (((((uint32_t)-1) << (31-msb)) >> (31-msb+lsb)) << lsb)
#define BVAL(msb, lsb, val) (((val) << lsb) & BM(msb, lsb))
#define container_of(ptr, type, member) \
((type *)((addr_t)(ptr) - offsetof(type, member)))
/* Frequency Macros */
#define FREQ_END (UINT_MAX-1)
#define F_END \
{ \
.freq_hz = FREQ_END, \
}
/* F(frequency, source, div, m, n) */
#define F(f, s, div, m, n) \
{ \
.freq_hz = (f), \
.src_clk = &s##_clk_src.c, \
.m_val = (m), \
.n_val = ~((n)-(m)) * !!(n), \
.d_val = ~(n),\
.div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \
| BVAL(10, 8, s##_source_val), \
}
/* F_MM(frequency, source, div, m, n) */
#define F_MM(f, s, div, m, n) \
{ \
.freq_hz = (f), \
.src_clk = &s##_clk_src.c, \
.m_val = (m), \
.n_val = ~((n)-(m)) * !!(n), \
.d_val = ~(n),\
.div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \
| BVAL(10, 8, s##_mm_source_val), \
}
/* Branch Clock Bits */
#define CBCR_BRANCH_ENABLE_BIT BIT(0)
#define CBCR_BRANCH_OFF_BIT BIT(31)
#define BRANCH_CHECK_MASK BM(31, 28)
#define BRANCH_ON_VAL BVAL(31, 28, 0x0)
#define BRANCH_NOC_FSM_ON_VAL BVAL(31, 28, 0x2)
/* Root Clock Bits */
#define CMD_UPDATE_BIT BIT(0)
#define CMD_UPDATE_MASK 1
#define CFG_SRC_DIV_OFFSET 0
#define CFG_SRC_DIV_MASK (0x1F << CFG_SRC_DIV_OFFSET)
#define CFG_SRC_SEL_OFFSET 8
#define CFG_SRC_SEL_MASK (0x3 << CFG_SRC_SEL_OFFSET)
#define CFG_MODE_DUAL_EDGE 0x2
#define CFG_MODE_OFFSET 12
#define CFG_MODE_MASK (0x3 << CFG_MODE_OFFSET)
/*
* Generic frequency-definition structs and macros
*/
struct clk_freq_tbl {
const uint32_t freq_hz;
struct clk *src_clk;
const uint32_t div_src_val;
/* TODO: find out if sys_vdd is needed. */
const uint32_t m_val;
const uint32_t n_val; /* not_n_minus_m_val */
const uint32_t d_val; /* not_2d_val */
};
/* Fixed clock */
struct fixed_clk {
struct clk c;
};
/* Branch clock */
struct branch_clk {
uint32_t *const bcr_reg;
uint32_t *const cbcr_reg;
void (*set_rate)(struct branch_clk *, struct clk_freq_tbl *);
struct clk *parent;
struct clk c;
int has_sibling;
uint32_t cur_div;
uint32_t max_div;
uint32_t halt_check;
};
/* Root Clock */
struct rcg_clk {
/* RCG registers for this clock */
uint32_t *const cmd_reg; /* Command reg */
uint32_t *const cfg_reg; /* Config reg */
uint32_t *const m_reg; /* m */
uint32_t *const n_reg; /* not (n-m) */
uint32_t *const d_reg; /* not (2d) */
/* set rate function for this clock */
void (*set_rate)(struct rcg_clk *, struct clk_freq_tbl *);
/* freq table */
struct clk_freq_tbl *const freq_tbl;
struct clk_freq_tbl *current_freq;
struct clk c;
};
/* Vote Clock */
struct vote_clk {
uint32_t *const cbcr_reg;
uint32_t *const vote_reg;
uint32_t en_mask;
struct clk c;
};
static inline struct rcg_clk *to_rcg_clk(struct clk *clk)
{
return container_of(clk, struct rcg_clk, c);
}
static inline struct branch_clk *to_branch_clk(struct clk *clk)
{
return container_of(clk, struct branch_clk, c);
}
static inline struct vote_clk *to_local_vote_clk(struct clk *clk)
{
return container_of(clk, struct vote_clk, c);
}
/* RCG clock functions */
int clock_lib2_rcg_enable(struct clk *c);
int clock_lib2_rcg_set_rate(struct clk *c, unsigned rate);
void clock_lib2_rcg_set_rate_mnd(struct rcg_clk *rclk, struct clk_freq_tbl *freq);
void clock_lib2_rcg_set_rate_hid(struct rcg_clk *rclk, struct clk_freq_tbl *freq);
/* CXO clock functions */
int cxo_clk_enable(struct clk *clk);
void cxo_clk_disable(struct clk *clk);
/* Branch clock functions */
int clock_lib2_branch_clk_enable(struct clk *clk);
void clock_lib2_branch_clk_disable(struct clk *clk);
int clock_lib2_branch_set_rate(struct clk *c, unsigned rate);
/* Vote clock functions*/
int clock_lib2_vote_clk_enable(struct clk *c);
void clock_lib2_vote_clk_disable(struct clk *c);
#endif
bootable/bootloader/lk/platform/msm_shared/include/clock_pll.h
+104
View File
@@ -0,0 +1,104 @@
/*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of The Linux Foundation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef CLOCK_PLL_H
#define CLOCK_PLL_H
/*
* Bit manipulation macros
*/
#define BM(msb, lsb) (((((uint32_t)-1) << (31-msb)) >> (31-msb+lsb)) << lsb)
#define BVAL(msb, lsb, val) (((val) << lsb) & BM(msb, lsb))
struct clk;
struct clk_ops;
#define container_of(ptr, type, member) \
((type *)((addr_t)(ptr) - offsetof(type, member)))
/**
* struct pll_vote_clk - phase locked loop (HW voteable)
* @rate: output rate
* @en_reg: enable register
* @en_mask: ORed with @en_reg to enable the clock
* @status_reg: status register
* @parent: clock source
* @c: clk
*/
struct pll_vote_clk {
unsigned long rate;
void *const en_reg;
const uint32_t en_mask;
void *const status_reg;
const uint32_t status_mask;
struct clk *parent;
struct clk c;
};
static inline struct pll_vote_clk *to_pll_vote_clk(struct clk *clk)
{
return container_of(clk, struct pll_vote_clk, c);
}
/**
* struct pll_clk - phase locked loop
* @rate: output rate
* @mode_reg: enable register
* @parent: clock source
* @c: clk
*/
struct pll_clk {
unsigned long rate;
void *const mode_reg;
struct clk *parent;
struct clk c;
};
static inline struct pll_clk *to_pll_clk(struct clk *clk)
{
return container_of(clk, struct pll_clk, c);
}
int pll_vote_clk_enable(struct clk *clk);
void pll_vote_clk_disable(struct clk *clk);
unsigned pll_vote_clk_get_rate(struct clk *clk);
struct clk *pll_vote_clk_get_parent(struct clk *clk);
int pll_vote_clk_is_enabled(struct clk *clk);
int pll_clk_enable(struct clk *clk);
void pll_clk_disable(struct clk *clk);
unsigned pll_clk_get_rate(struct clk *clk);
struct clk *pll_clk_get_parent(struct clk *clk);
#endif
bootable/bootloader/lk/platform/msm_shared/include/crypto4_eng.h
+76
View File
@@ -0,0 +1,76 @@
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __CRYPTO4_ENG_H__
#define __CRYPYO4_ENG_H__
#define CRYPTO_ENG_REG(base, offset) ((base) + offset)
#define IS_ALIGNED(ptr) (!(((unsigned int)ptr) & 0x03))
/* CRYPTO4 registers */
#define CRYPTO_DATA_IN 0x0008
#define CRYPTO_DATA_OUT 0x0010
#define CRYPTO_STATUS 0x0100
#define CRYPTO_CONFIG 0x0500
#define CRYPTO_DEBUG 0x0508
#define CRYPTO_ENCR_SEG_CFG 0x0300
#define CRYPTO_SEG_SIZE 0x0200
#define CRYPTO_GOPROC 0x0204
#define CRYPTO_ENGINES_AVAIL 0x0104
#define CRYPTO_AUTH_SEG_CFG 0x0400
#define CRYPTO_AUTH_SEG_SIZE 0x0404
#define CRYPTO_AUTH_SEG_START 0x0408
#define CRYPTO_AUTH_BYTECNTn(n) (0x04A0 + 4*(n))
#define CRYPTO_AUTH_IVn(n) (0x0450 + 4*(n))
/* Register bit definitions */
#define SW_ERR BIT(0)
#define OPERATION_DONE BIT(1)
#define DIN_RDY BIT(2)
#define DIN_SIZE_AVAIL 0x00380000
/* CRYPTO_CONFIG register bit definitions */
#define AUTO_SHUTDOWN_EN BIT(2)
#define MASK_ERR_INTR BIT(3)
#define MASK_OP_DONE_INTR BIT(4)
#define MASK_DIN_INTR BIT(5)
#define MASK_DOUT_INTR BIT(6)
#define HIGH_SPD_IN_EN_N BIT(13)
#define HIGH_SPD_OUT_EN_N BIT(14)
/* CRYPTO_AUTH_SEG_CFG register bit definitions */
#define SEG_CFG_AUTH_ALG_SHA (1<<0)
#define SEG_CFG_AUTH_SIZE_SHA1 (0<<9)
#define SEG_CFG_AUTH_SIZE_SHA256 (1<<9)
#define SEG_CFG_LAST (1<<14)
#define GOPROC_GO 1
#endif
bootable/bootloader/lk/platform/msm_shared/include/crypto5_eng.h
+179
View File
@@ -0,0 +1,179 @@
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __CRYPTO5_ENG_H__
#define __CRYPYO5_ENG_H__
#include <bits.h>
#include <bam.h>
#include <crypto_hash.h>
/* CRYPTO registers */
#define CRYPTO_VERSION(x) (x + 0x0000)
#define CRYPTO_DATA_IN(x) (x + 0x0010)
#define CRYPTO_DATA_OUT(x) (x + 0x0020)
#define CRYPTO_STATUS(x) (x + 0x0100)
#define CRYPTO_STATUS2(x) (x + 0x0104)
#define CRYPTO_SEG_SIZE(x) (x + 0x0110)
#define CRYPTO_GOPROC(x) (x + 0x0120)
#define CRYPTO_ENGINES_AVAIL(x) (x + 0x0108)
#define CRYPTO_ENCR_SEG_CFG(x) (x + 0x0200)
#define CRYPTO_AUTH_SEG_CFG(x) (x + 0x0300)
#define CRYPTO_AUTH_SEG_SIZE(x) (x + 0x0304)
#define CRYPTO_AUTH_SEG_START(x) (x + 0x0308)
#define CRYPTO_AUTH_IVn(x, n) (x + 0x0310 + 4*(n))
#define CRYPTO_AUTH_BYTECNTn(x, n) (x + 0x0390 + 4*(n))
#define CRYPTO_CONFIG(x) (x + 0x0400)
#define CRYPTO_DEBUG(x) (x + 0x5004)
/* Status register errors. */
#define SW_ERR BIT(0)
#define AXI_ERR BIT(14)
#define HSD_ERR BIT(20)
#define AUTH_BUSY BIT(8)
/* Status2 register errors. */
#define AXI_EXTRA BIT(1)
/* CRYPTO_CONFIG register bit definitions */
#define MASK_ERR_INTR BIT(0)
#define MASK_OP_DONE_INTR BIT(1)
#define MASK_DIN_INTR BIT(2)
#define MASK_DOUT_INTR BIT(3)
#define HIGH_SPD_IN_EN_N (0 << 4)
#define PIPE_SET_SELECT_SHIFT 5
#define LITTLE_ENDIAN_MODE BIT(9)
#define MAX_QUEUED_REQS (0 << 14) /* 1 Max queued request. */
#define REQ_SIZE (7 << 17) /* 8 beats */
/* CRYPTO_AUTH_SEG_CFG register bit definitions */
#define SEG_CFG_AUTH_ALG_SHA (1 << 0)
#define SEG_CFG_AUTH_SIZE_SHA1 (0 << 9)
#define SEG_CFG_AUTH_SIZE_SHA256 (1 << 9)
#define SEG_CFG_LAST (1 << 16)
/* The value to be written to the GOPROC register.
* Enable result dump option along with GO bit.
*/
#define GOPROC_GO (1 | 1 << 2)
#define CRYPTO_READ_PIPE_INDEX 0
#define CRYPTO_WRITE_PIPE_INDEX 1
/* Burst length recommended by HPG for maximum throughput. */
#define CRYPTO_BURST_LEN 64
/* This value determines how much descriptor data can be advertised on
* the pipe sideband interface at a time.
* The recommendation is to make it the size of your largest descriptor.
* The max setting is 32KB.
*/
#define CRYPTO_MAX_THRESHOLD (32 * 1024)
/* Basic CE setting to put the CE in HS mode. */
#define CRYPTO_RESET_CONFIG 0xE000F
struct crypto_bam_pipes
{
uint8_t read_pipe;
uint8_t write_pipe;
};
struct output_dump
{
uint32_t auth_iv[16];
uint32_t auth_bytcnt[4];
uint32_t encr_cntr_iv[4];
uint32_t status;
uint32_t status2;
uint8_t burst_align_buf[24];
}__PACKED;
/* Struct to save the CE device info.
* base : Base addr of CE.
* instance : CE instance used.
* ce_array : ptr to the cmd elements array.
* ce_array_index : index within ce_array where the next cmd element needs to be added.
* cd_start : index within the ce_array to keep track of the num of
* cmd elements that need to be added in the next desc.
* dump : ptr to the result dump memory.
* bam : bam instance used with this CE.
* do_bam_init : Flag to determine if bam should be initalized.
*/
struct crypto_dev
{
uint32_t base;
uint32_t instance;
struct cmd_element *ce_array;
uint32_t ce_array_index;
uint32_t cd_start;
struct output_dump *dump;
struct bam_instance bam;
uint8_t do_bam_init;
};
/* Struct to pass the initial params to CE.
* crypto_base : Base addr of the CE.
* crypto_instance : CE instance used.
* bam_base : Base addr of CE BAM.
* bam_ee : EE used for CE BAM.
* num_ce : Number of cmd elements to be allocated.
* read_fifo_size : Size of the BAM desc read fifo.
* write_fifo_size : Size of the BAM desc write fifo.
* do_bam_init : Flag to determine if bam should be initalized.
*/
struct crypto_init_params
{
uint32_t crypto_base;
uint32_t crypto_instance;
uint32_t bam_base;
uint32_t bam_ee;
uint32_t num_ce;
uint32_t read_fifo_size;
uint32_t write_fifo_size;
uint8_t do_bam_init;
struct crypto_bam_pipes pipes;
};
void crypto5_init_params(struct crypto_dev *dev, struct crypto_init_params *params);
void crypto5_init(struct crypto_dev *dev);
void crypto5_set_ctx(struct crypto_dev *dev,
void *ctx_ptr,
crypto_auth_alg_type auth_alg);
uint32_t crypto5_send_data(struct crypto_dev *dev,
void *ctx_ptr,
uint8_t *data_ptr);
void crypto5_cleanup(struct crypto_dev *dev);
uint32_t crypto5_get_digest(struct crypto_dev *dev,
uint8_t *digest_ptr,
crypto_auth_alg_type auth_alg);
void crypto5_get_ctx(struct crypto_dev *dev, void *ctx_ptr);
uint32_t crypto5_get_max_auth_blk_size(struct crypto_dev *dev);
#endif
bootable/bootloader/lk/platform/msm_shared/include/crypto5_wrapper.h
+37
View File
@@ -0,0 +1,37 @@
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __CRYPTO5_WRAPPER_H__
#define __CRYPYO5_WRAPPER_H__
#include <crypto5_eng.h>
void crypto_init_params(struct crypto_init_params * params);
uint32_t crypto_get_max_auth_blk_size();
#endif
bootable/bootloader/lk/platform/msm_shared/include/crypto_eng.h
+92
View File
@@ -0,0 +1,92 @@
/* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __CRYPTO_ENG_H__
#define __CRYPYO_ENG_H__
#define CRYPTO_ENG_REG(offset) (MSM_CRYPTO_BASE + offset)
#define wr_ce(val,reg) writel(val,CRYPTO_ENG_REG(reg))
#define rd_ce(reg) readl(CRYPTO_ENG_REG(reg))
#define IS_ALIGNED(ptr) (!(((unsigned int)ptr) & 0x03))
#define CRYPTO_ERR_NONE 0x01
#define CRYPTO_ERR_FAIL 0x02
/* CRYPTO3 registers */
#define CRYPTO3_DATA_IN 0x0000
#define CRYPTO3_DATA_OUT 0x0010
#define CRYPTO3_STATUS 0x0020
#define CRYPTO3_CONFIG 0x0024
#define CRYPTO3_DEBUG 0x0028
#define CRYPTO3_REGISTER_LOCK 0x002C
#define CRYPTO3_SEG_CFG 0x0030
#define CRYPTO3_ENCR_SEG_CFG 0x0034
#define CRYPTO3_AUTH_SEG_CFG 0x0038
#define CRYPTO3_SEG_SIZE 0x003C
#define CRYPTO3_GOPROC 0x0040
#define CRYPTO3_ENGINES_AVAIL 0x0044
#define CRYPTO3_DES_KEYn(n) (0x0050 + 4*(n))
#define CRYPTO3_CNTRn_KEYn(n) (0x0070 + 4*(n))
#define CRYPTO3_CNTR_MASK 0x0080
#define CRYPTO3_AUTH_BYTECNTn(n) (0x0090 + 4*(n))
#define CRYPTO3_AUTH_IVn(n) (0x0100 + 4*(n))
#define CRYPTO3_AES_RNDKEYn(n) (0x0200 + 4*(n))
#define CRYPTO3_DATA_SHADOW0 0x8000
#define CRYPTO3_DATA_SHADOW8191 0xFFFC
/* Register bit definitions */
#define SW_ERR 0x00000001
#define AUTH_DONE 0x00000002
#define DIN_RDY 0x00000004
#define DIN_SIZE_AVAIL 0x00380000
#define SW_RST 0x00000001
#define AUTO_SHUTDOWN_EN 0x00000004
#define MASK_ERR_INTR 0x00000008
#define MASK_AUTH_DONE_INTR 0x00000010
#define MASK_DIN_INTR 0x00000020
#define MASK_DOUT_INTR 0x00000040
#define HIGH_SPD_IN_EN_N 0x00002000
#define HIGH_SPD_OUT_EN_N 0x00004000
#define HIGH_SPD_HASH_EN_N 0x00008000
#define SEG_CFG_AUTH_ALG_SHA (1<<9)
#define SEG_CFG_AUTH_SIZE_SHA1 (0<<11)
#define SEG_CFG_AUTH_SIZE_SHA256 (1<<11)
#define SEG_CFG_FIRST (1<<17)
#define SEG_CFG_LAST (1<<18)
#define AUTH_SEG_CFG_AUTH_SIZE 16
#define GOPROC_GO 1
#endif
bootable/bootloader/lk/platform/msm_shared/include/crypto_hash.h
+132
View File
@@ -0,0 +1,132 @@
/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __CRYPTO_HASH_H__
#define __CRYPYO_HASH_H__
#ifndef NULL
#define NULL 0
#endif
#define TRUE 1
#define FALSE 0
#define SHA256_INIT_VECTOR_SIZE 8
#define SHA1_INIT_VECTOR_SIZE 5
#define CRYPTO_SHA_BLOCK_SIZE 64
#define CRYPTO_ERR_NONE 0x01
#define CRYPTO_ERR_FAIL 0x02
typedef enum {
CRYPTO_FIRST_CHUNK = 1,
CRYPTO_LAST_CHUNK = 2,
} crypto_flag_type;
typedef enum {
CRYPTO_SHA_ERR_NONE,
CRYPTO_SHA_ERR_BUSY,
CRYPTO_SHA_ERR_FAIL,
CRYPTO_SHA_ERR_INVALID_PARAM,
} crypto_result_type;
typedef enum {
CRYPTO_ENGINE_TYPE_NONE,
CRYPTO_ENGINE_TYPE_SW,
CRYPTO_ENGINE_TYPE_HW,
}crypto_engine_type;
typedef enum {
CRYPTO_AUTH_ALG_SHA1 = 1,
CRYPTO_AUTH_ALG_SHA256
} crypto_auth_alg_type;
typedef struct {
unsigned int auth_bytecnt[2];
unsigned char saved_buff[64];
unsigned char saved_buff_indx;
unsigned int auth_iv[5];
uint32_t flags;
} crypto_SHA1_ctx;
typedef struct {
unsigned int auth_bytecnt[2];
unsigned char saved_buff[64];
unsigned char saved_buff_indx;
unsigned int auth_iv[8];
uint32_t bytes_to_write;
uint32_t flags;
} crypto_SHA256_ctx;
extern void crypto_eng_reset(void);
extern void crypto_eng_init(void);
extern void crypto_set_sha_ctx(void *ctx_ptr,
unsigned int bytes_to_write,
crypto_auth_alg_type auth_alg,
bool first, bool last);
extern void crypto_send_data(void *ctx_ptr,
unsigned char *data_ptr, unsigned int buff_size,
unsigned int bytes_to_write,
unsigned int *ret_status);
extern void crypto_get_digest(unsigned char *digest_ptr,
unsigned int *ret_status,
crypto_auth_alg_type auth_alg, bool last);
extern void crypto_get_ctx(void *ctx_ptr);
extern uint32_t crypto_get_max_auth_blk_size();
static void crypto_init(void);
static crypto_result_type do_sha(unsigned char *buff_ptr,
unsigned int buff_size,
unsigned char *digest_ptr,
crypto_auth_alg_type auth_alg);
static crypto_result_type do_sha_update(void *ctx_ptr,
unsigned char *buff_ptr,
unsigned int buff_size,
crypto_auth_alg_type auth_alg,
bool first, bool last);
static unsigned int calc_num_bytes_to_send(void *ctx_ptr,
unsigned int buff_size, bool last);
static crypto_result_type crypto_sha256(unsigned char *buff_ptr,
unsigned int buff_size,
unsigned char *digest_ptr);
static crypto_result_type crypto_sha1(unsigned char *buff_ptr,
unsigned int buff_size,
unsigned char *digest_ptr);
#endif
bootable/bootloader/lk/platform/msm_shared/include/dev_tree.h
+71
View File
@@ -0,0 +1,71 @@
/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <debug.h>
#ifndef __DEVICE_TREE__
#define __DEVICE_TREE__
#define DEV_TREE_SUCCESS 0
#define DEV_TREE_MAGIC 0x54444351 /* "QCDT" */
#define DEV_TREE_MAGIC_LEN 4
#define DEV_TREE_VERSION 1
#define DEV_TREE_HEADER_SIZE 12
#define DTB_MAGIC 0xedfe0dd0
#define DTB_OFFSET 0x2C
#define DTB_PAD_SIZE 1024
struct dt_entry
{
uint32_t platform_id;
uint32_t variant_id;
uint32_t soc_rev;
uint32_t offset;
uint32_t size;
};
struct dt_table
{
uint32_t magic;
uint32_t version;
uint32_t num_entries;
};
enum dt_err_codes
{
DT_OP_SUCCESS,
DT_OP_FAILURE = -1,
};
struct dt_entry * dev_tree_get_entry_ptr(struct dt_table *);
int update_device_tree(void *, const char *, void *, unsigned);
int dev_tree_add_mem_info(void *fdt, uint32_t offset, uint32_t size, uint32_t addr);
void *dev_tree_appended(void *kernel, void *tags, uint32_t kernel_size);
#endif
bootable/bootloader/lk/platform/msm_shared/include/dload_util.h
+36
View File
@@ -0,0 +1,36 @@
/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __DLOAD_UTIL_H
#define __DLOAD_UTIL_H
#include <sys/types.h>
void dload_util_write_cookie(uint32_t target_dload_mode_addr);
#endif
bootable/bootloader/lk/platform/msm_shared/include/gpio.h
+68
View File
@@ -0,0 +1,68 @@
/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _GPIO_H_
#define _GPIO_H_
#define TLMM_PULL_MASK 0x3
#define TLMM_HDRV_MASK 0x7
/* Current values for tlmm pins */
enum {
TLMM_CUR_VAL_16MA = 0x7,
TLMM_CUR_VAL_10MA = 0x4,
} tlmm_drive_config;
enum {
TLMM_PULL_UP = 0x3,
TLMM_NO_PULL = 0x0,
} tlmm_pull_values;
/* Bit offsets in the TLMM register */
enum {
SDC1_DATA_HDRV_CTL_OFF = 0,
SDC1_CMD_HDRV_CTL_OFF = 3,
SDC1_CLK_HDRV_CTL_OFF = 6,
SDC1_DATA_PULL_CTL_OFF = 9,
SDC1_CMD_PULL_CTL_OFF = 11,
SDC1_CLK_PULL_CTL_OFF = 13,
} tlmm_drv_ctrl;
/* Input for the tlmm config function */
struct tlmm_cfgs {
uint32_t off; /* Bit offeset in the register */
uint8_t val; /* Current value */
uint8_t mask; /* Mask for the clk/dat/cmd control */
};
/* APIs: exposed for other drivers */
/* API: Hdrive control for tlmm pins */
void tlmm_set_hdrive_ctrl(struct tlmm_cfgs *, uint8_t);
/* API: Pull control for tlmm pins */
void tlmm_set_pull_ctrl(struct tlmm_cfgs *, uint8_t);
#endif
bootable/bootloader/lk/platform/msm_shared/include/gsbi.h
+60
View File
@@ -0,0 +1,60 @@
/* Copyright (c) 2011, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __GSBI_H_
#define __GSBI_H_
#include <platform/iomap.h>
/* GSBI Registers */
#define GSBI_CTRL_REG(base) ((base) + 0x0)
#define GSBI_CTRL_REG_PROTOCOL_CODE_S 4
#define GSBI_PROTOCOL_CODE_I2C 0x2
#define GSBI_PROTOCOL_CODE_SPI 0x3
#define GSBI_PROTOCOL_CODE_UART_FLOW 0x4
#define GSBI_PROTOCOL_CODE_I2C_UART 0x6
#define GSBI_HCLK_CTL_S 4
#define GSBI_HCLK_CTL_CLK_ENA 0x1
enum {
GSBI_ID_1 = 1,
GSBI_ID_2,
GSBI_ID_3,
GSBI_ID_4,
GSBI_ID_5,
GSBI_ID_6,
GSBI_ID_7,
GSBI_ID_8,
GSBI_ID_9,
GSBI_ID_10,
GSBI_ID_11,
GSBI_ID_12,
};
#endif
bootable/bootloader/lk/platform/msm_shared/include/hdmi.h
+84
View File
@@ -0,0 +1,84 @@
/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __PLATFORM_MSM_SHARED_HDMI_H
#define __PLATFORM_MSM_SHARED_HDMI_H
#include <reg.h>
#include <debug.h>
#include <bits.h>
#include <dev/fbcon.h>
#include <target/display.h>
#define MDP_GET_PACK_PATTERN(a,x,y,z,bit) (((a)<<(bit*3))|((x)<<(bit*2))|((y)<<bit)|(z))
#define DMA_PACK_ALIGN_LSB 0
#define DMA_PACK_PATTERN_RGB \
(MDP_GET_PACK_PATTERN(0,CLR_R,CLR_G,CLR_B,2)<<8)
#define CLR_G 0x0
#define CLR_B 0x1
#define CLR_R 0x2
#define DMA_DSTC0G_8BITS (BIT(1)|BIT(0))
#define DMA_DSTC1B_8BITS (BIT(3)|BIT(2))
#define DMA_DSTC2R_8BITS (BIT(5)|BIT(4))
#define BM(m, l) (((((uint32_t)-1) << (31-m)) >> (31-m+l)) << l)
#define BVAL(m, l, val) (((val) << l) & BM(m, l))
#define CC(m, n) (BVAL((m+1), m, 0x2) * !!(n))
#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \
(BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \
| BVAL(s_msb, s_lsb, s))
extern int pm8901_mpp_enable();
extern int pm8901_vs_enable();
extern int pm8058_ldo_set_voltage();
extern int pm8058_vreg_enable();
void gpio_tlmm_config(uint32_t gpio, uint8_t func,
uint8_t dir, uint8_t pull,
uint8_t drvstr, uint32_t enable);
int hdmi_dtv_on(void);
void hdmi_msm_set_mode(int on);
void hdmi_msm_init_phy(void);
void hdmi_display_shutdown(void);
void hdmi_msm_reset_core(void);
void hdmi_set_fb_addr(void *addr);
struct hdmi_disp_mode_timing_type {
uint32_t height;
uint32_t hsync_porch_fp;
uint32_t hsync_width;
uint32_t hsync_porch_bp;
uint32_t width;
uint32_t vsync_porch_fp;
uint32_t vsync_width;
uint32_t vsync_porch_bp;
uint32_t refresh_rate;
uint32_t bpp;
void *base;
};
#endif /* __PLATFORM_MSM_SHARED_HDMI_H */
bootable/bootloader/lk/platform/msm_shared/include/i2c_qup.h
+249
View File
@@ -0,0 +1,249 @@
/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __I2C_QUP__
#define __I2C_QUP__
#include <stdint.h>
/**
* struct i2c_msg - an I2C transaction segment beginning with START
* @addr: Slave address, either seven or ten bits. When this is a ten
* bit address, I2C_M_TEN must be set in @flags and the adapter
* must support I2C_FUNC_10BIT_ADDR.
* @flags: I2C_M_RD is handled by all adapters. No other flags may be
* provided unless the adapter exported the relevant I2C_FUNC_*
* flags through i2c_check_functionality().
* @len: Number of data bytes in @buf being read from or written to the
* I2C slave address. For read transactions where I2C_M_RECV_LEN
* is set, the caller guarantees that this buffer can hold up to
* 32 bytes in addition to the initial length byte sent by the
* slave (plus, if used, the SMBus PEC); and this value will be
* incremented by the number of block data bytes received.
* @buf: The buffer into which data is read, or from which it's written.
*
* An i2c_msg is the low level representation of one segment of an I2C
* transaction. It is visible to drivers in the @i2c_transfer() procedure,
* to userspace from i2c-dev, and to I2C adapter drivers through the
* @i2c_adapter.@master_xfer() method.
*
* Except when I2C "protocol mangling" is used, all I2C adapters implement
* the standard rules for I2C transactions. Each transaction begins with a
* START. That is followed by the slave address, and a bit encoding read
* versus write. Then follow all the data bytes, possibly including a byte
* with SMBus PEC. The transfer terminates with a NAK, or when all those
* bytes have been transferred and ACKed. If this is the last message in a
* group, it is followed by a STOP. Otherwise it is followed by the next
* @i2c_msg transaction segment, beginning with a (repeated) START.
*
* Alternatively, when the adapter supports I2C_FUNC_PROTOCOL_MANGLING then
* passing certain @flags may have changed those standard protocol behaviors.
* Those flags are only for use with broken/nonconforming slaves, and with
* adapters which are known to support the specific mangling options they
* need (one or more of IGNORE_NAK, NO_RD_ACK, NOSTART, and REV_DIR_ADDR).
*/
struct i2c_msg {
unsigned short addr; /* slave address */
unsigned short flags;
#define I2C_M_TEN 0x0010 /* this is a ten bit chip address */
#define I2C_M_WR 0x0000 /* write data, from master to slave */
#define I2C_M_RD 0x0001 /* read data, from slave to master */
#define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_PROTOCOL_MANGLING */
#define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */
#define I2C_M_IGNORE_NAK 0x1000 /* if I2C_FUNC_PROTOCOL_MANGLING */
#define I2C_M_NO_RD_ACK 0x0800 /* if I2C_FUNC_PROTOCOL_MANGLING */
#define I2C_M_RECV_LEN 0x0400 /* length will be first received byte */
unsigned short len; /* msg length */
unsigned char *buf; /* pointer to msg data */
};
struct qup_i2c_dev {
unsigned int gsbi_base;
unsigned int qup_base;
unsigned int gsbi_number;
int qup_irq;
int num_irqs;
struct i2c_msg *msg;
int pos;
int cnt;
int err;
int mode;
int clk_ctl;
int clk_freq;
int src_clk_freq;
int one_bit_t;
int out_fifo_sz;
int in_fifo_sz;
int out_blk_sz;
int in_blk_sz;
int wr_sz;
int suspended;
int clk_state;
};
/* Function Definitions */
struct qup_i2c_dev *qup_i2c_init(uint8_t gsbi_id,
unsigned clk_freq, unsigned src_clk_freq);
struct qup_i2c_dev *qup_blsp_i2c_init(uint8_t blsp_id, uint8_t qup_id,
uint32_t clk_freq, uint32_t src_clk_freq);
int qup_i2c_deinit(struct qup_i2c_dev *dev);
int qup_i2c_xfer(struct qup_i2c_dev *dev, struct i2c_msg msgs[], int num);
struct device {
struct device *parent;
const char *init_name; /* initial name of the device */
void (*release) (struct device * dev);
};
/**
* enum irqreturn
* @IRQ_NONE interrupt was not from this device
* @IRQ_HANDLED interrupt was handled by this device
* @IRQ_WAKE_THREAD handler requests to wake the handler thread
*/
enum irqreturn {
IRQ_NONE,
IRQ_HANDLED,
IRQ_WAKE_THREAD,
IRQ_FAIL,
};
typedef enum irqreturn irqreturn_t;
#define I2C_SMBUS_BLOCK_MAX 32
union i2c_smbus_data {
unsigned char byte;
unsigned short word;
unsigned char block[I2C_SMBUS_BLOCK_MAX + 2];
};
/*
* i2c_adapter is the structure used to identify a physical i2c bus along
* with the access algorithms necessary to access it.
*/
struct i2c_adapter {
struct module *owner;
unsigned int id;
unsigned int class; /* classes to allow probing for */
const struct i2c_algorithm *algo; /* the algorithm to access the bus */
void *algo_data;
/* data fields that are valid for all devices */
unsigned int level; /* nesting level for lockdep */
int timeout; /* in jiffies */
int retries;
struct device dev; /* the adapter device */
int nr;
char name[48];
};
/*
* The following structs are for those who like to implement new bus drivers:
* i2c_algorithm is the interface to a class of hardware solutions which can
* be addressed using the same bus algorithms - i.e. bit-banging or the PCF8584
* to name two of the most common.
*/
struct i2c_algorithm {
/* If an adapter algorithm can't do I2C-level access, set master_xfer to
NULL. If an adapter algorithm can do SMBus access, set smbus_xfer. If
set to NULL, the SMBus protocol is simulated using common I2C messages */
/* master_xfer should return the number of messages successfully processed,
or a negative value on error */
int (*master_xfer) (struct i2c_adapter * adap, struct i2c_msg * msgs,
int num);
int (*smbus_xfer) (struct i2c_adapter * adap, unsigned short addr,
unsigned short flags, char read_write,
unsigned char command, int size,
union i2c_smbus_data * data);
/* To determine what the adapter supports */
unsigned int (*functionality) (struct i2c_adapter *);
};
#define EIO 5
#define ENOMEM 12
#define EBUSY 16
#define ENODEV 19
#define ENOSYS 38
#define EPROTONOSUPPORT 93
#define ETIMEDOUT 110
#define FALSE 0
#define TRUE 1
#define USEC_PER_SEC 1000000L
#define IRQF_TRIGGER_NONE 0x00000000
#define IRQF_TRIGGER_RISING 0x00000001
#define IRQF_TRIGGER_FALLING 0x00000002
#define IRQF_TRIGGER_HIGH 0x00000004
#define IRQF_TRIGGER_LOW 0x00000008
#define IRQF_TRIGGER_MASK (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW | \
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)
#define IRQF_TRIGGER_PROBE 0x00000010
/* To determine what functionality is present */
#define I2C_FUNC_I2C 0x00000001
#define I2C_FUNC_10BIT_ADDR 0x00000002
#define I2C_FUNC_PROTOCOL_MANGLING 0x00000004 /* I2C_M_NOSTART etc. */
#define I2C_FUNC_SMBUS_PEC 0x00000008
#define I2C_FUNC_SMBUS_BLOCK_PROC_CALL 0x00008000 /* SMBus 2.0 */
#define I2C_FUNC_SMBUS_QUICK 0x00010000
#define I2C_FUNC_SMBUS_READ_BYTE 0x00020000
#define I2C_FUNC_SMBUS_WRITE_BYTE 0x00040000
#define I2C_FUNC_SMBUS_READ_BYTE_DATA 0x00080000
#define I2C_FUNC_SMBUS_WRITE_BYTE_DATA 0x00100000
#define I2C_FUNC_SMBUS_READ_WORD_DATA 0x00200000
#define I2C_FUNC_SMBUS_WRITE_WORD_DATA 0x00400000
#define I2C_FUNC_SMBUS_PROC_CALL 0x00800000
#define I2C_FUNC_SMBUS_READ_BLOCK_DATA 0x01000000
#define I2C_FUNC_SMBUS_WRITE_BLOCK_DATA 0x02000000
#define I2C_FUNC_SMBUS_READ_I2C_BLOCK 0x04000000 /* I2C-like block xfer */
#define I2C_FUNC_SMBUS_WRITE_I2C_BLOCK 0x08000000 /* w/ 1-byte reg. addr. */
#define I2C_FUNC_SMBUS_BYTE (I2C_FUNC_SMBUS_READ_BYTE | \
I2C_FUNC_SMBUS_WRITE_BYTE)
#define I2C_FUNC_SMBUS_BYTE_DATA (I2C_FUNC_SMBUS_READ_BYTE_DATA | \
I2C_FUNC_SMBUS_WRITE_BYTE_DATA)
#define I2C_FUNC_SMBUS_WORD_DATA (I2C_FUNC_SMBUS_READ_WORD_DATA | \
I2C_FUNC_SMBUS_WRITE_WORD_DATA)
#define I2C_FUNC_SMBUS_BLOCK_DATA (I2C_FUNC_SMBUS_READ_BLOCK_DATA | \
I2C_FUNC_SMBUS_WRITE_BLOCK_DATA)
#define I2C_FUNC_SMBUS_I2C_BLOCK (I2C_FUNC_SMBUS_READ_I2C_BLOCK | \
I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)
#define I2C_FUNC_SMBUS_EMUL (I2C_FUNC_SMBUS_QUICK | \
I2C_FUNC_SMBUS_BYTE | \
I2C_FUNC_SMBUS_BYTE_DATA | \
I2C_FUNC_SMBUS_WORD_DATA | \
I2C_FUNC_SMBUS_PROC_CALL | \
I2C_FUNC_SMBUS_WRITE_BLOCK_DATA | \
I2C_FUNC_SMBUS_I2C_BLOCK | \
I2C_FUNC_SMBUS_PEC)
#endif /* __I2C_QUP__ */
bootable/bootloader/lk/platform/msm_shared/include/image_verify.h
+40
View File
@@ -0,0 +1,40 @@
/*
* Copyright (c) 2011, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef __IMAGE_VERIFY_H
#define __IMAGE_VERIFY_H
#define SHA1_SIZE 16
#define SHA256_SIZE 32
/* For keys of length 2048 bits */
#define SIGNATURE_SIZE 256
static int image_decrypt_signature(unsigned char *signature_ptr,
unsigned char *plain_text);
int image_verify(unsigned char *image_ptr,
unsigned char *signature_ptr,
unsigned int image_size, unsigned hash_type);
#endif
bootable/bootloader/lk/platform/msm_shared/include/jtag.h
+37
View File
@@ -0,0 +1,37 @@
/*
* Copyright (C) 2008 The Android Open Source Project
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _JTAG_H_
#define _JTAG_H_
void jtag_okay(const char *msg);
void jtag_fail(const char *msg);
void jtag_dputc(unsigned ch);
void jtag_cmd_loop(void (*do_cmd) (const char *, unsigned, unsigned, unsigned));
#endif /*__JTAG_H_ */
bootable/bootloader/lk/platform/msm_shared/include/mddi.h
+83
View File
@@ -0,0 +1,83 @@
/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef __PLATFORM_MDDI_H
#define __PLATFORM_MDDI_H
struct fbcon_config;
struct __attribute__ ((packed)) mddi_client_caps {
unsigned short length;
unsigned short type;
unsigned short client_id;
unsigned short protocol_ver;
unsigned short min_protocol_ver;
unsigned short data_rate_cap;
unsigned char interface_type_cap;
unsigned char num_alt_displays;
unsigned short postcal_data_rate;
unsigned short bitmap_width;
unsigned short bitmap_height;
unsigned short display_window_width;
unsigned short display_window_height;
unsigned cmap_size;
unsigned short cmap_rgb_width;
unsigned short rgb_cap;
unsigned char mono_cap;
unsigned char reserved1;
unsigned short ycbcr_cap;
unsigned short bayer_cap;
unsigned short alpha_cursor_planes;
unsigned client_feature_cap;
unsigned char max_video_frame_rate_cap;
unsigned char min_video_frame_rate_cap;
unsigned short min_sub_frame_rate;
unsigned short audio_buf_depth;
unsigned short audio_channel_cap;
unsigned short audio_sampe_rate_rap;
unsigned char audio_sample_res;
unsigned char mic_audio_sample_res;
unsigned short mic_sample_rate_cap;
unsigned char keyboard_data_fmt;
unsigned char pointing_device_data_fmt;
unsigned short content_protection_type;
unsigned short manufacturer_name;
unsigned short product_code;
unsigned short reserved3;
unsigned serial_no;
unsigned char week_of_manufacture;
unsigned char year_of_manufacture;
unsigned short crc;
};
void mddi_remote_write(unsigned val, unsigned reg);
struct fbcon_config *mddi_init(void);
#endif /* __PLATFORM_MDDI_H */
bootable/bootloader/lk/platform/msm_shared/include/mdp3.h
+53
View File
@@ -0,0 +1,53 @@
/* Copyright (c) 2011, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <dev/fbcon.h>
//TODO: Make a global PASS / FAIL define
#define PASS 0
#define FAIL 1
int mdp_setup_dma_p_video_mode(unsigned short disp_width,
unsigned short disp_height,
unsigned short img_width,
unsigned short img_height,
unsigned short hsync_porch0_fp,
unsigned short hsync_porch0_bp,
unsigned short vsync_porch0_fp,
unsigned short vsync_porch0_bp,
unsigned short hsync_width,
unsigned short vsync_width,
unsigned long input_img_addr,
unsigned short img_width_full_size,
unsigned short pack_pattern,
unsigned char ystride);
void mdp_disable(void);
void mdp_shutdown(void);
void mdp_set_revision(int rev);
int mdp_get_revision();
bootable/bootloader/lk/platform/msm_shared/include/mdp4.h
+114
View File
@@ -0,0 +1,114 @@
/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _PLATFORM_MSM_SHARED_MDP_4_H_
#define _PLATFORM_MSM_SHARED_MDP_4_H_
#include <dev/fbcon.h>
#include <msm_panel.h>
//TODO: Make a global PASS / FAIL define
#define PASS 0
#define FAIL 1
#define MDP_OVERLAYPROC0_START REG_MDP(0x00004)
#define MDP_DMA_P_START REG_MDP(0x0000C)
#define MDP_DMA_S_START REG_MDP(0x00010)
#define MDP_AXI_RDMASTER_CONFIG REG_MDP(0x00028)
#define MDP_AXI_WRMASTER_CONFIG REG_MDP(0x00030)
#define MDP_DISP_INTF_SEL REG_MDP(0x00038)
#define MDP_MAX_RD_PENDING_CMD_CONFIG REG_MDP(0x0004C)
#define MDP_INTR_ENABLE REG_MDP(0x00050)
#define MDP_DSI_CMD_MODE_ID_MAP REG_MDP(0x000A0)
#define MDP_DSI_CMD_MODE_TRIGGER_EN REG_MDP(0x000A4)
#define MDP_OVERLAYPROC0_CFG REG_MDP(0x10004)
#define MDP_OVERLAYPROC0_OPMODE REG_MDP(0x10014)
#define MDP_LAYERMIXER_IN_CFG REG_MDP(0x10100)
#define MDP_OVERLAY_REG_FLUSH REG_MDP(0x18000)
#define MDP_RGB1_SRC_SIZE REG_MDP(0x40000)
#define MDP_RGB1_SRC_XY REG_MDP(0x40004)
#define MDP_RGB1_OUT_SIZE REG_MDP(0x40008)
#define MDP_RGB1_OUT_XY REG_MDP(0x4000C)
#define MDP_RGB1_SRCP0_ADDR REG_MDP(0x40010)
#define MDP_RGB1_SRCP0_ADDR_1 REG_MDP(0x40014)
#define MDP_RGB1_SRCP0_ADDR_2 REG_MDP(0x40018)
#define MDP_RGB1_SRC_YSTRIDE1 REG_MDP(0x40040)
#define MDP_RGB1_SRC_FORMAT REG_MDP(0x40050)
#define MDP_RGB1_CONSTANT_COLOR REG_MDP(0x41008)
#define MDP_DSI_VIDEO_EN REG_MDP(0xE0000)
#define MDP_DSI_VIDEO_HSYNC_CTL REG_MDP(0xE0004)
#define MDP_DSI_VIDEO_VSYNC_PERIOD REG_MDP(0xE0008)
#define MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH REG_MDP(0xE000C)
#define MDP_DSI_VIDEO_DISPLAY_HCTL REG_MDP(0xE0010)
#define MDP_DSI_VIDEO_DISPLAY_V_START REG_MDP(0xE0014)
#define MDP_DSI_VIDEO_DISPLAY_V_END REG_MDP(0xE0018)
#define MDP_DSI_VIDEO_ACTIVE_HCTL REG_MDP(0xE001C)
#define MDP_DSI_VIDEO_BORDER_CLR REG_MDP(0xE0028)
#define MDP_DSI_VIDEO_HSYNC_SKEW REG_MDP(0xE0030)
#define MDP_DSI_VIDEO_CTL_POLARITY REG_MDP(0xE0038)
#define MDP_DSI_VIDEO_TEST_CTL REG_MDP(0xE0034)
#define MDP_TEST_MODE_CLK REG_MDP(0xF0000)
#define MDP_INTR_STATUS REG_MDP(0x00054)
void mdp_setup_dma_p_video_config(unsigned short pack_pattern,
unsigned short img_width,
unsigned short img_height,
unsigned long input_img_addr,
unsigned short img_width_full_size,
unsigned char ystride);
int mdp_setup_dma_p_video_mode(unsigned short disp_width,
unsigned short disp_height,
unsigned short img_width,
unsigned short img_height,
unsigned short hsync_porch0_fp,
unsigned short hsync_porch0_bp,
unsigned short vsync_porch0_fp,
unsigned short vsync_porch0_bp,
unsigned short hsync_width,
unsigned short vsync_width,
unsigned long input_img_addr,
unsigned short img_width_full_size,
unsigned short pack_pattern,
unsigned char ystride);
int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg,
unsigned short num_of_lanes);
void mdp_shutdown(void);
void mdp_disable(void);
void mdp_start_dma(void);
int mdp_dsi_video_off();
int mdp_dsi_video_on();
int mdp_dsi_video_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
int mdp_lcdc_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
int mdp_lcdc_on();
int mdp_lcdc_off();
void mdp_set_revision(int rev);
int mdp_get_revision();
#endif
bootable/bootloader/lk/platform/msm_shared/include/mdp5.h
+127
View File
@@ -0,0 +1,127 @@
/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _PLATFORM_MSM_SHARED_MDP_5_H_
#define _PLATFORM_MSM_SHARED_MDP_5_H_
#include <msm_panel.h>
#define MDP_VP_0_RGB_0_SSPP_SRC0_ADDR REG_MDP(0x1E14)
#define MDP_VP_0_RGB_0_SSPP_SRC_YSTRIDE REG_MDP(0x1E24)
#define MDP_VP_0_RGB_0_SSPP_SRC_IMG_SIZE REG_MDP(0x1E04)
#define MDP_VP_0_RGB_0_SSPP_SRC_SIZE REG_MDP(0x1E00)
#define MDP_VP_0_RGB_0_SSPP_SRC_OUT_SIZE REG_MDP(0x1E0C)
#define MDP_VP_0_RGB_0_SSPP_SRC_XY REG_MDP(0x1E08)
#define MDP_VP_0_RGB_0_SSPP_OUT_XY REG_MDP(0x1E10)
#define MDP_VP_0_RGB_0_SSPP_SRC_FORMAT REG_MDP(0x1E30)
#define MDP_VP_0_RGB_0_SSPP_SRC_UNPACK_PATTERN REG_MDP(0x1E34)
#define MDP_VP_0_RGB_0_SSPP_SRC_OP_MODE REG_MDP(0x1E38)
#define MDP_VP_0_LAYER_0_OUT_SIZE REG_MDP(0x3204)
#define MDP_VP_0_LAYER_0_OP_MODE REG_MDP(0x3200)
#define MDP_VP_0_LAYER_0_BORDER_COLOR_0 REG_MDP(0x3208)
#define MDP_VP_0_LAYER_0_BLEND_OP REG_MDP(0x3220)
#define MDP_VP_0_LAYER_0_BLEND0_FG_ALPHA REG_MDP(0x3224)
#define MDP_VP_0_LAYER_1_BLEND_OP REG_MDP(0x3250)
#define MDP_VP_0_LAYER_1_BLEND0_FG_ALPHA REG_MDP(0x3254)
#define MDP_VP_0_LAYER_2_BLEND_OP REG_MDP(0x3280)
#define MDP_VP_0_LAYER_2_BLEND0_FG_ALPHA REG_MDP(0x3284)
#define MDP_VP_0_LAYER_3_BLEND_OP REG_MDP(0x32B0)
#define MDP_VP_0_LAYER_3_BLEND0_FG_ALPHA REG_MDP(0x32B4)
#define MDSS_MDP_HW_REV_100 0x10000000
#define MDSS_MDP_HW_REV_102 0x10020000
#define MDP_HW_REV REG_MDP(0x0100)
#define MDP_INTR_EN REG_MDP(0x0110)
#define MDP_INTR_CLEAR REG_MDP(0x0118)
#define MDP_HIST_INTR_EN REG_MDP(0x011C)
#define MDP_DISP_INTF_SEL REG_MDP(0x0104)
#define MDP_VIDEO_INTF_UNDERFLOW_CTL REG_MDP(0x03E0)
#define MDP_UPPER_NEW_ROI_PRIOR_RO_START REG_MDP(0x02EC)
#define MDP_LOWER_NEW_ROI_PRIOR_TO_START REG_MDP(0x04F8)
#define MDP_INTF_1_TIMING_ENGINE_EN REG_MDP(0x12700)
#define MDP_CTL_0_LAYER_0 REG_MDP(0x600)
#define MDP_CTL_0_TOP REG_MDP(0x614)
#define MDP_CTL_0_FLUSH REG_MDP(0x618)
#define MDP_CTL_0_START REG_MDP(0x61C)
#define MDP_INTF_1_HSYNC_CTL REG_MDP(0x12708)
#define MDP_INTF_1_VSYNC_PERIOD_F0 REG_MDP(0x1270C)
#define MDP_INTF_1_VSYNC_PERIOD_F1 REG_MDP(0x12710)
#define MDP_INTF_1_VSYNC_PULSE_WIDTH_F0 REG_MDP(0x12714)
#define MDP_INTF_1_VSYNC_PULSE_WIDTH_F1 REG_MDP(0x12718)
#define MDP_INTF_1_DISPLAY_HCTL REG_MDP(0x1273C)
#define MDP_INTF_1_DISPLAY_V_START_F0 REG_MDP(0x1271C)
#define MDP_INTF_1_DISPLAY_V_START_F1 REG_MDP(0x12720)
#define MDP_INTF_1_DISPLAY_V_END_F0 REG_MDP(0x12724)
#define MDP_INTF_1_DISPLAY_V_END_F1 REG_MDP(0x12728)
#define MDP_INTF_1_ACTIVE_HCTL REG_MDP(0x12740)
#define MDP_INTF_1_ACTIVE_V_START_F0 REG_MDP(0x1272C)
#define MDP_INTF_1_ACTIVE_V_START_F1 REG_MDP(0x12730)
#define MDP_INTF_1_ACTIVE_V_END_F0 REG_MDP(0x12734)
#define MDP_INTF_1_ACTIVE_V_END_F1 REG_MDP(0x12738)
#define MDP_INTF_1_UNDERFFLOW_COLOR REG_MDP(0x12748)
#define MDP_INTF_1_PANEL_FORMAT REG_MDP(0x12790)
#define MDP_CLK_CTRL0 REG_MDP(0x03AC)
#define MDP_CLK_CTRL1 REG_MDP(0x03B4)
#define MDP_CLK_CTRL2 REG_MDP(0x03BC)
#define MDP_CLK_CTRL3 REG_MDP(0x04A8)
#define MDP_CLK_CTRL4 REG_MDP(0x04B0)
#define MDP_CLK_CTRL5 REG_MDP(0x04B8)
#define MMSS_MDP_SMP_ALLOC_W_0 REG_MDP(0x0180)
#define MMSS_MDP_SMP_ALLOC_W_1 REG_MDP(0x0184)
#define MMSS_MDP_SMP_ALLOC_R_0 REG_MDP(0x0230)
#define MMSS_MDP_SMP_ALLOC_R_1 REG_MDP(0x0234)
#define VBIF_VBIF_DDR_FORCE_CLK_ON REG_MDP(0x24004)
#define VBIF_VBIF_DDR_OUT_MAX_BURST REG_MDP(0x240D8)
#define VBIF_VBIF_DDR_ARB_CTRL REG_MDP(0x240F0)
#define VBIF_VBIF_DDR_RND_RBN_QOS_ARB REG_MDP(0x24124)
#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0 REG_MDP(0x24160)
#define VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1 REG_MDP(0x24164)
#define VBIF_VBIF_DDR_OUT_AOOO_AXI_EN REG_MDP(0x24178)
#define VBIF_VBIF_DDR_OUT_AX_AOOO REG_MDP(0x2417C)
void mdp_set_revision(int rev);
int mdp_get_revision();
int mdp_dsi_video_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg,
unsigned short num_of_lanes);
int mdp_dsi_video_on(void);
int mdp_dma_on(void);
void mdp_disable(void);
#endif
bootable/bootloader/lk/platform/msm_shared/include/mipi_dsi.h
+962
View File
@@ -0,0 +1,962 @@
/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _PLATFORM_MSM_SHARED_MIPI_DSI_H_
#define _PLATFORM_MSM_SHARED_MIPI_DSI_H_
#include <msm_panel.h>
#define PASS 0
#define FAIL 1
#define DSI_CLKOUT_TIMING_CTRL REG_DSI(0x0C0)
#define DSI_SOFT_RESET REG_DSI(0x114)
#define DSI_CAL_CTRL REG_DSI(0x0F4)
#define DSIPHY_SW_RESET REG_DSI(0x128)
#define DSIPHY_PLL_RDY REG_DSI(0x280)
#define DSIPHY_REGULATOR_CAL_PWR_CFG REG_DSI(0x518)
#define DSI_CLK_CTRL REG_DSI(0x118)
#define DSI_TRIG_CTRL REG_DSI(0x080)
#define DSI_CTRL REG_DSI(0x000)
#define DSI_COMMAND_MODE_DMA_CTRL REG_DSI(0x038)
#define DSI_COMMAND_MODE_MDP_CTRL REG_DSI(0x03C)
#define DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL REG_DSI(0x040)
#define DSI_DMA_CMD_OFFSET REG_DSI(0x044)
#define DSI_DMA_CMD_LENGTH REG_DSI(0x048)
#define DSI_COMMAND_MODE_MDP_STREAM0_CTRL REG_DSI(0x054)
#define DSI_COMMAND_MODE_MDP_STREAM0_TOTAL REG_DSI(0x058)
#define DSI_COMMAND_MODE_MDP_STREAM1_CTRL REG_DSI(0x05C)
#define DSI_COMMAND_MODE_MDP_STREAM1_TOTAL REG_DSI(0x060)
#define DSI_ERR_INT_MASK0 REG_DSI(0x108)
#define DSI_INT_CTRL REG_DSI(0x10C)
#define DSI_VIDEO_MODE_ACTIVE_H REG_DSI(0x020)
#define DSI_VIDEO_MODE_ACTIVE_V REG_DSI(0x024)
#define DSI_VIDEO_MODE_TOTAL REG_DSI(0x028)
#define DSI_VIDEO_MODE_HSYNC REG_DSI(0x02C)
#define DSI_VIDEO_MODE_VSYNC REG_DSI(0x030)
#define DSI_VIDEO_MODE_VSYNC_VPOS REG_DSI(0x034)
#define DSI_MISR_CMD_CTRL REG_DSI(0x09C)
#define DSI_MISR_VIDEO_CTRL REG_DSI(0x0A0)
#define DSI_EOT_PACKET_CTRL REG_DSI(0x0C8)
#define DSI_VIDEO_MODE_CTRL REG_DSI(0x00C)
#define DSI_CAL_STRENGTH_CTRL REG_DSI(0x100)
#define DSI_CMD_MODE_DMA_SW_TRIGGER REG_DSI(0x08C)
#define DSI_CMD_MODE_MDP_SW_TRIGGER REG_DSI(0x090)
#define DSI_HS_TIMER_CTRL REG_DSI(0x0B8)
#define DSI_LANE_CTRL REG_DSI(0x0A8)
#define MIPI_DSI_MRPS 0x04 /* Maximum Return Packet Size */
#define MIPI_DSI_REG_LEN 16 /* 4 x 4 bytes register */
#define DTYPE_GEN_WRITE2 0x23 /* 4th Byte is 0x80 */
#define DTYPE_GEN_LWRITE 0x29 /* 4th Byte is 0xc0 */
#define DTYPE_DCS_WRITE1 0x15 /* 4th Byte is 0x80 */
//BEGINNING OF Tochiba Config- video mode
static const unsigned char toshiba_panel_mcap_off[8] = {
0x02, 0x00, 0x29, 0xc0,
0xb2, 0x00, 0xff, 0xff
};
static const unsigned char toshiba_panel_ena_test_reg[8] = {
0x03, 0x00, 0x29, 0xc0,
0xEF, 0x01, 0x01, 0xff
};
static const unsigned char toshiba_panel_ena_test_reg_wvga[8] = {
0x03, 0x00, 0x29, 0xc0,
0xEF, 0x01, 0x01, 0xff
};
static const unsigned char toshiba_panel_num_of_2lane[8] = {
0x03, 0x00, 0x29, 0xc0, // 63:2lane
0xEF, 0x60, 0x63, 0xff
};
static const unsigned char toshiba_panel_num_of_1lane[8] = {
0x03, 0x00, 0x29, 0xc0, // 62:1lane
0xEF, 0x60, 0x62, 0xff
};
static const unsigned char toshiba_panel_non_burst_sync_pulse[8] = {
0x03, 0x00, 0x29, 0xc0,
0xef, 0x61, 0x09, 0xff
};
static const unsigned char toshiba_panel_set_DMODE_WQVGA[8] = {
0x02, 0x00, 0x29, 0xc0,
0xB3, 0x01, 0xFF, 0xff
};
static const unsigned char toshiba_panel_set_DMODE_WVGA[8] = {
0x02, 0x00, 0x29, 0xc0,
0xB3, 0x00, 0xFF, 0xff
};
static const unsigned char toshiba_panel_set_intern_WR_clk1_wvga[8]
= {
0x03, 0x00, 0x29, 0xC0, // 1 last packet
0xef, 0x2f, 0xcc, 0xff,
};
static const unsigned char toshiba_panel_set_intern_WR_clk2_wvga[8]
= {
0x03, 0x00, 0x29, 0xC0, // 1 last packet
0xef, 0x6e, 0xdd, 0xff,
};
static const unsigned char
toshiba_panel_set_intern_WR_clk1_wqvga[8] = {
0x03, 0x00, 0x29, 0xC0, // 1 last packet
0xef, 0x2f, 0x22, 0xff,
};
static const unsigned char
toshiba_panel_set_intern_WR_clk2_wqvga[8] = {
0x03, 0x00, 0x29, 0xC0, // 1 last packet
0xef, 0x6e, 0x33, 0xff,
};
static const unsigned char toshiba_panel_set_hor_addr_2A_wvga[12] = {
0x05, 0x00, 0x39, 0xC0, // 1 last packet
// 0x2A, 0x00, 0x08, 0x00,//100 = 64h
// 0x6b, 0xFF, 0xFF, 0xFF,
0x2A, 0x00, 0x00, 0x01, // 0X1DF = 480-1 0X13F = 320-1
0xdf, 0xFF, 0xFF, 0xFF,
};
static const unsigned char toshiba_panel_set_hor_addr_2B_wvga[12] = {
0x05, 0x00, 0x39, 0xC0, // 1 last packet
// 0x2B, 0x00, 0x08, 0x00,//0X355 = 854-1; 0X1DF = 480-1
// 0x6b, 0xFF, 0xFF, 0xFF,
0x2B, 0x00, 0x00, 0x03, // 0X355 = 854-1; 0X1DF = 480-1
0x55, 0xFF, 0xFF, 0xFF,
};
static const unsigned char toshiba_panel_set_hor_addr_2A_wqvga[12]
= {
0x05, 0x00, 0x39, 0xC0, // 1 last packet
0x2A, 0x00, 0x00, 0x00, // 0XEF = 240-1
0xef, 0xFF, 0xFF, 0xFF,
};
static const unsigned char toshiba_panel_set_hor_addr_2B_wqvga[12]
= {
0x05, 0x00, 0x39, 0xC0, // 1 last packet
0x2B, 0x00, 0x00, 0x01, // 0X1aa = 427-1;
0xaa, 0xFF, 0xFF, 0xFF,
};
static const unsigned char toshiba_panel_IFSEL[8] = {
0x02, 0x00, 0x29, 0xc0,
0x53, 0x01, 0xff, 0xff
};
static const unsigned char toshiba_panel_IFSEL_cmd_mode[8] = {
0x02, 0x00, 0x29, 0xc0,
0x53, 0x00, 0xff, 0xff
};
static const unsigned char toshiba_panel_exit_sleep[4] = {
0x11, 0x00, 0x05, 0x80, // 25 Reg 0x29 < Display On>; generic write 1
// params
};
static const unsigned char toshiba_panel_display_on[4] = {
// 0x29, 0x00, 0x05, 0x80,//25 Reg 0x29 < Display On>; generic write 1
// params
0x29, 0x00, 0x05, 0x80, // 25 Reg 0x29 < Display On>; generic write 1
// params
};
//color mode off
static const unsigned char dsi_display_config_color_mode_off[4] = {
0x00, 0x00, 0x02, 0x80,
};
//color mode on
static const unsigned char dsi_display_config_color_mode_on[4] = {
0x00, 0x00, 0x12, 0x80,
};
//the end OF Tochiba Config- video mode
/* NOVATEK BLUE panel */
static char novatek_panel_sw_reset[4] = { 0x01, 0x00, 0x05, 0x00 }; /* DTYPE_DCS_WRITE */
static char novatek_panel_enter_sleep[4] = { 0x10, 0x00, 0x05, 0x80 }; /* DTYPE_DCS_WRITE */
static char novatek_panel_exit_sleep[4] = { 0x11, 0x00, 0x05, 0x80 }; /* DTYPE_DCS_WRITE */
static char novatek_panel_display_off[4] = { 0x28, 0x00, 0x05, 0x80 }; /* DTYPE_DCS_WRITE */
static char novatek_panel_display_on[4] = { 0x29, 0x00, 0x05, 0x80 }; /* DTYPE_DCS_WRITE */
static char novatek_panel_max_packet[4] = { 0x04, 0x00, 0x37, 0x80 }; /* DTYPE_SET_MAX_PACKET */
static char novatek_panel_set_onelane[4] = { 0xae, 0x01, 0x15, 0x80 }; /* DTYPE_DCS_WRITE1 */
static char novatek_panel_rgb_888[4] = { 0x3A, 0x77, 0x15, 0x80 }; /* DTYPE_DCS_WRITE1 */
static char novatek_panel_set_twolane[4] = { 0xae, 0x03, 0x15, 0x80 }; /* DTYPE_DCS_WRITE1 */
static char novatek_panel_manufacture_id[4] = { 0x04, 0x00, 0x06, 0xA0 }; /* DTYPE_DCS_READ */
/* commands by Novatke */
static char novatek_panel_f4[4] = { 0xf4, 0x55, 0x15, 0x80 }; /* DTYPE_DCS_WRITE1 */
static char novatek_panel_8c[20] = { /* DTYPE_DCS_LWRITE */
0x10, 0x00, 0x39, 0xC0, 0x8C, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x08, 0x08, 0x00, 0x30, 0xC0, 0xB7, 0x37
};
static char novatek_panel_ff[4] = { 0xff, 0x55, 0x15, 0x80 }; /* DTYPE_DCS_WRITE1 */
static char novatek_panel_set_width[12] = { /* DTYPE_DCS_LWRITE */
0x05, 0x00, 0x39, 0xC0, //1 last packet
0x2A, 0x00, 0x00, 0x02, //clmn:0 - 0x21B=539
0x1B, 0xFF, 0xFF, 0xFF
}; /* 540 - 1 */
static char novatek_panel_set_height[12] = { /* DTYPE_DCS_LWRITE */
0x05, 0x00, 0x39, 0xC0, //1 last packet
0x2B, 0x00, 0x00, 0x03, //row:0 - 0x3BF=959
0xBF, 0xFF, 0xFF, 0xFF,
}; /* 960 - 1 */
/* Commands to control Backlight */
static char novatek_panel_set_led_pwm1[8] = { /* DTYPE_DCS_LWRITE */
0x02, 0x00, 0x39, 0xC0, //1 last packet
0x51, 0xFA, 0xFF, 0xFF, // Brightness level set to 0xFA -> 250
};
static char novatek_panel_set_led_pwm2[8] = { /* DTYPE_DCS_LWRITE */
0x02, 0x00, 0x39, 0xC0,
0x53, 0x24, 0xFF, 0xFF,
};
static char novatek_panel_set_led_pwm3[8] = { /* DTYPE_DCS_LWRITE */
0x02, 0x00, 0x39, 0xC0,
0x55, 0x00, 0xFF, 0xFF,
};
/* End of Novatek Blue panel commands */
/* Toshiba mdt61 panel cmds */
static const unsigned char toshiba_mdt61_mcap_start[4] = {
0xB0, 0x04, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdt61_num_out_pixelform[8] = {
0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xB3, 0x00, 0x87, 0xFF
};
static const unsigned char toshiba_mdt61_dsi_ctrl[8] = {
0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xB6, 0x30, 0x83, 0xFF
};
static const unsigned char toshiba_mdt61_panel_driving[12] = {
0x07, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xC0, 0x01, 0x00, 0x85,
0x00, 0x00, 0x00, 0xFF
};
static const unsigned char toshiba_mdt61_dispV_timing[12] = {
0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xC1, 0x00, 0x10, 0x00,
0x01, 0xFF, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_dispCtrl[8] = {
0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xC3, 0x00, 0x19, 0xFF
};
static const unsigned char toshiba_mdt61_test_mode_c4[4] = {
0xC4, 0x03, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdt61_dispH_timing[20] = {
0x0F, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xC5, 0x00, 0x01, 0x05,
0x04, 0x5E, 0x00, 0x00,
0x00, 0x00, 0x0B, 0x17,
0x05, 0x00, 0x00, 0xFF
};
static const unsigned char toshiba_mdt61_test_mode_c6[4] = {
0xC6, 0x00, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdt61_gamma_setA[20] = {
0x0D, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xC8, 0x0A, 0x15, 0x18,
0x1B, 0x1C, 0x0D, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0xFF, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_gamma_setB[20] = {
0x0D, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xC9, 0x0D, 0x1D, 0x1F,
0x1F, 0x1F, 0x10, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0xFF, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_gamma_setC[20] = {
0x0D, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xCA, 0x1E, 0x1F, 0x1E,
0x1D, 0x1D, 0x10, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0xFF, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_powerSet_ChrgPmp[12] = {
0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xD0, 0x02, 0x00, 0xA3,
0xB8, 0xFF, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_testMode_d1[12] = {
0x06, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xD1, 0x10, 0x14, 0x53,
0x64, 0x00, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_powerSet_SrcAmp[8] = {
0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xD2, 0xB3, 0x00, 0xFF
};
static const unsigned char toshiba_mdt61_powerInt_PS[8] = {
0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xD3, 0x33, 0x03, 0xFF
};
static const unsigned char toshiba_mdt61_vreg[4] = {
0xD5, 0x00, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdt61_test_mode_d6[4] = {
0xD6, 0x01, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdt61_timingCtrl_d7[16] = {
0x09, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xD7, 0x09, 0x00, 0x84,
0x81, 0x61, 0xBC, 0xB5,
0x05, 0xFF, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_timingCtrl_d8[12] = {
0x07, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xD8, 0x04, 0x25, 0x90,
0x4C, 0x92, 0x00, 0xFF
};
static const unsigned char toshiba_mdt61_timingCtrl_d9[8] = {
0x04, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xD9, 0x5B, 0x7F, 0x05
};
static const unsigned char toshiba_mdt61_white_balance[12] = {
0x06, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xCB, 0x00, 0x00, 0x00,
0x1C, 0x00, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_vcs_settings[4] = {
0xDD, 0x53, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdt61_vcom_dc_settings[4] = {
0xDE, 0x43, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdt61_testMode_e3[12] = {
0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xE3, 0x00, 0x00, 0x00,
0x00, 0xFF, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_testMode_e4[12] = {
0x06, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xE4, 0x00, 0x00, 0x22,
0xAA, 0x00, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_testMode_e5[4] = {
0xE5, 0x00, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdt61_testMode_fa[8] = {
0x04, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xFA, 0x00, 0x00, 0x00
};
static const unsigned char toshiba_mdt61_testMode_fd[12] = {
0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xFD, 0x00, 0x00, 0x00,
0x00, 0xFF, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_testMode_fe[12] = {
0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xFE, 0x00, 0x00, 0x00,
0x00, 0xFF, 0xFF, 0xFF
};
static const unsigned char toshiba_mdt61_mcap_end[4] = {
0xB0, 0x03, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdt61_set_add_mode[4] = {
0x36, 0x00, DTYPE_DCS_WRITE1, 0x80,
};
static const unsigned char toshiba_mdt61_set_pixel_format[4] = {
0x3A, 0x70, DTYPE_DCS_WRITE1, 0x80,
};
/* Done Toshiba MDT61 Panel Commands */
/* Toshiba MDT61 (R69320) End */
/* Toshiba MDV24 panel commands */
static const unsigned char toshiba_mdv24_mcap[4] = {
0xB0, 0x00, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdv24_acr[4] = {
0xB2, 0x00, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdv24_intf[4] = {
0xB3, 0x0c, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdv24_pixel[4] = {
0xB4, 0x02, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdv24_drive_setting[12] = {
0x06, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xC0, 0x40, 0x02, 0x7F,
0xC8, 0x08, 0xFF, 0xFF
};
static const unsigned char toshiba_mdv24_display_h_timing[20] = {
0x10, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xC1, 0x00, 0xA8, 0x00,
0x00, 0x00, 0x00, 0x00,
0x9D, 0x08, 0x27, 0x00,
0x00, 0x00, 0x00, 0x00
};
static const unsigned char toshiba_mdv24_source_output[12] = {
0x06, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xC2, 0x00, 0x00, 0x09,
0x00, 0x00, 0xFF, 0xFF
};
static const unsigned char toshiba_mdv24_gate_control[4] = {
0xC3, 0x04, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdv24_ltps_control_c4[8] = {
0x04, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xC4, 0x4d, 0x83, 0x00
};
static const unsigned char toshiba_mdv24_source_output_mode[16] = {
0x0B, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xC6, 0x12, 0x00, 0x08,
0x71, 0x00, 0x00, 0x00,
0x80, 0x00, 0x04, 0xFF
};
static const unsigned char toshiba_mdv24_ltps_control_c7[4] = {
0xC7, 0x22, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdv24_gamma_ctrl[12] = {
0x05, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xC8, 0x4C, 0x0C, 0x0C,
0x0C, 0xFF, 0xFF, 0xFF
};
static const unsigned char toshiba_mdv24_gamma_ctrl_a_pos[20] = {
0x0E, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xC9, 0x00, 0x40, 0x00,
0x16, 0x32, 0x2E, 0x3A,
0x43, 0x3E, 0x3C, 0x45,
0x79, 0x3F, 0xFF, 0xFF
};
static const unsigned char toshiba_mdv24_gamma_ctrl_a_neg[20] = {
0x0E, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xCA, 0x00, 0x46, 0x1A,
0x23, 0x21, 0x1C, 0x25,
0x31, 0x2D, 0x49, 0x5F,
0x7F, 0x3F, 0xFF, 0xFF
};
static const unsigned char toshiba_mdv24_gamma_ctrl_b_pos[20] = {
0x0E, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xCb, 0x00, 0x4c, 0x20,
0x3A, 0x42, 0x40, 0x47,
0x4B, 0x42, 0x3E, 0x46,
0x7E, 0x3F, 0xFF, 0xFF
};
static const unsigned char toshiba_mdv24_gamma_ctrl_b_neg[20] = {
0x0E, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xCC, 0x00, 0x41, 0x19,
0x21, 0x1D, 0x14, 0x18,
0x1F, 0x1D, 0x25, 0x3F,
0x73, 0x3F, 0xFF, 0xFF
};
static const unsigned char toshiba_mdv24_gamma_ctrl_c_pos[20] = {
0x0E, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xCD, 0x23, 0x79, 0x5A,
0x5F, 0x57, 0x4C, 0x51,
0x51, 0x45, 0x3F, 0x4B,
0x7F, 0x3F, 0xFF, 0xFF
};
static const unsigned char toshiba_mdv24_gamma_ctrl_c_neg[20] = {
0x0E, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xCE, 0x00, 0x40, 0x14,
0x20, 0x1A, 0x0E, 0x0E,
0x13, 0x08, 0x00, 0x05,
0x46, 0x1C, 0xFF, 0xFF
};
static const unsigned char toshiba_mdv24_pwr_setting1[8] = {
0x04, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xD0, 0x6A, 0x64, 0x01
};
static const unsigned char toshiba_mdv24_pwr_setting2[8] = {
0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xD1, 0x77, 0xd4, 0xFF
};
static const unsigned char toshiba_mdv24_pwr_setting_internal[4] = {
0xD3, 0x33, DTYPE_GEN_WRITE2, 0x80,
};
static const unsigned char toshiba_mdv24_lvl_setting[8] = {
0x03, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xD5, 0x0F, 0x0F, 0xFF
};
static const unsigned char toshiba_mdv24_vcomdc_setting1[12] = {
0x07, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xD8, 0x34, 0x64, 0x23,
0x25, 0x62, 0x32, 0xFF
};
static const unsigned char toshiba_mdv24_vcomdc_setting2[16] = {
0x0C, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xDE, 0x10, 0x7B, 0x11,
0x0A, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00
};
static const unsigned char toshiba_mdv24_init_fd[16] = {
0x09, 0x00, DTYPE_GEN_LWRITE, 0xC0,
0xFD, 0x04, 0x55, 0x53,
0x00, 0x70, 0xFF, 0x10,
0x73, 0xFF, 0xFF, 0xFF
};
static const unsigned char toshiba_mdv24_nvm_load_ctrl[4] = {
0xE2, 0x00, DTYPE_GEN_WRITE2, 0x80,
};
/* End of Toshiba MDV24 commands */
static const unsigned char dsi_display_exit_sleep[4] = {
0x11, 0x00, 0x15, 0x80,
};
static const unsigned char dsi_display_display_on[4] = {
0x29, 0x00, 0x15, 0x80,
};
#define MIPI_VIDEO_MODE 1
#define MIPI_CMD_MODE 2
struct mipi_dsi_phy_ctrl {
uint32_t regulator[5];
uint32_t timing[12];
uint32_t ctrl[4];
uint32_t strength[4];
uint32_t pll[21];
};
struct mdss_dsi_phy_ctrl {
uint32_t regulator[7];
uint32_t timing[12];
uint32_t ctrl[4];
uint32_t strength[2];
char bistCtrl[6];
char laneCfg[45];
};
struct mipi_dsi_cmd {
int size;
char *payload;
};
struct mipi_dsi_panel_config {
char mode;
char num_of_lanes;
char lane_swap;
char pack;
struct mipi_dsi_phy_ctrl *dsi_phy_config;
struct mdss_dsi_phy_ctrl *mdss_dsi_phy_config;
struct mipi_dsi_cmd *panel_cmds;
int num_of_panel_cmds;
};
static struct mipi_dsi_cmd toshiba_panel_video_mode_cmds[] = {
{sizeof(toshiba_panel_mcap_off), (char *)toshiba_panel_mcap_off},
{sizeof(toshiba_panel_ena_test_reg),
(char *)toshiba_panel_ena_test_reg},
{sizeof(toshiba_panel_num_of_1lane),
(char *)toshiba_panel_num_of_1lane},
{sizeof(toshiba_panel_non_burst_sync_pulse),
(char *)toshiba_panel_non_burst_sync_pulse},
{sizeof(toshiba_panel_set_DMODE_WVGA),
(char *)toshiba_panel_set_DMODE_WVGA},
{sizeof(toshiba_panel_set_intern_WR_clk1_wvga),
(char *)toshiba_panel_set_intern_WR_clk1_wvga},
{sizeof(toshiba_panel_set_intern_WR_clk2_wvga),
(char *)toshiba_panel_set_intern_WR_clk2_wvga},
{sizeof(toshiba_panel_set_hor_addr_2A_wvga),
(char *)toshiba_panel_set_hor_addr_2A_wvga},
{sizeof(toshiba_panel_set_hor_addr_2B_wvga),
(char *)toshiba_panel_set_hor_addr_2B_wvga},
{sizeof(toshiba_panel_IFSEL), (char *)toshiba_panel_IFSEL},
{sizeof(toshiba_panel_exit_sleep), (char *)toshiba_panel_exit_sleep},
{sizeof(toshiba_panel_display_on), (char *)toshiba_panel_display_on},
{sizeof(dsi_display_config_color_mode_on),
(char *)dsi_display_config_color_mode_on},
{sizeof(dsi_display_config_color_mode_off),
(char *)dsi_display_config_color_mode_off},
};
static struct mipi_dsi_phy_ctrl mipi_dsi_toshiba_panel_phy_ctrl = {
/* 480*854, RGB888, 1 Lane 60 fps video mode */
{0x03, 0x01, 0x01, 0x00}, /* regulator */
/* timing */
{0x50, 0x0f, 0x14, 0x19, 0x23, 0x0e, 0x12, 0x16,
0x1b, 0x1c, 0x04},
{0x7f, 0x00, 0x00, 0x00}, /* phy ctrl */
{0xee, 0x03, 0x86, 0x03}, /* strength */
/* pll control */
#if defined(DSI_BIT_CLK_366MHZ)
{0x41, 0xdb, 0xb2, 0xf5, 0x00, 0x50, 0x48, 0x63,
0x31, 0x0f, 0x07,
0x05, 0x14, 0x03, 0x03, 0x03, 0x54, 0x06, 0x10, 0x04, 0x03},
#elif defined(DSI_BIT_CLK_380MHZ)
{0x41, 0xf7, 0xb2, 0xf5, 0x00, 0x50, 0x48, 0x63,
0x31, 0x0f, 0x07,
0x05, 0x14, 0x03, 0x03, 0x03, 0x54, 0x06, 0x10, 0x04, 0x03},
#elif defined(DSI_BIT_CLK_400MHZ)
{0x41, 0x8f, 0xb1, 0xda, 0x00, 0x50, 0x48, 0x63,
0x31, 0x0f, 0x07,
0x05, 0x14, 0x03, 0x03, 0x03, 0x54, 0x06, 0x10, 0x04, 0x03},
#else /* 200 mhz */
{0x41, 0x8f, 0xb1, 0xda, 0x00, 0x50, 0x48, 0x63,
0x33, 0x1f, 0x1f /* for 1 lane ; 0x0f for 2 lanes */ ,
0x05, 0x14, 0x03, 0x03, 0x03, 0x54, 0x06, 0x10, 0x04, 0x03},
#endif
};
static struct mipi_dsi_cmd toshiba_mdt61_video_mode_cmds[] = {
{sizeof(toshiba_mdt61_mcap_start), (char *)toshiba_mdt61_mcap_start},
{sizeof(toshiba_mdt61_num_out_pixelform),
(char *)toshiba_mdt61_num_out_pixelform},
{sizeof(toshiba_mdt61_dsi_ctrl), (char *)toshiba_mdt61_dsi_ctrl},
{sizeof(toshiba_mdt61_panel_driving),
(char *)toshiba_mdt61_panel_driving},
{sizeof(toshiba_mdt61_dispV_timing),
(char *)toshiba_mdt61_dispV_timing},
{sizeof(toshiba_mdt61_dispCtrl), (char *)toshiba_mdt61_dispCtrl},
{sizeof(toshiba_mdt61_test_mode_c4),
(char *)toshiba_mdt61_test_mode_c4},
{sizeof(toshiba_mdt61_dispH_timing),
(char *)toshiba_mdt61_dispH_timing},
{sizeof(toshiba_mdt61_test_mode_c6),
(char *)toshiba_mdt61_test_mode_c6},
{sizeof(toshiba_mdt61_gamma_setA), (char *)toshiba_mdt61_gamma_setA},
{sizeof(toshiba_mdt61_gamma_setB), (char *)toshiba_mdt61_gamma_setB},
{sizeof(toshiba_mdt61_gamma_setC), (char *)toshiba_mdt61_gamma_setC},
{sizeof(toshiba_mdt61_powerSet_ChrgPmp),
(char *)toshiba_mdt61_powerSet_ChrgPmp},
{sizeof(toshiba_mdt61_testMode_d1), (char *)toshiba_mdt61_testMode_d1},
{sizeof(toshiba_mdt61_powerSet_SrcAmp),
(char *)toshiba_mdt61_powerSet_SrcAmp},
{sizeof(toshiba_mdt61_powerInt_PS), (char *)toshiba_mdt61_powerInt_PS},
{sizeof(toshiba_mdt61_vreg), (char *)toshiba_mdt61_vreg},
{sizeof(toshiba_mdt61_test_mode_d6),
(char *)toshiba_mdt61_test_mode_d6},
{sizeof(toshiba_mdt61_timingCtrl_d7),
(char *)toshiba_mdt61_timingCtrl_d7},
{sizeof(toshiba_mdt61_timingCtrl_d8),
(char *)toshiba_mdt61_timingCtrl_d8},
{sizeof(toshiba_mdt61_timingCtrl_d9),
(char *)toshiba_mdt61_timingCtrl_d9},
{sizeof(toshiba_mdt61_white_balance),
(char *)toshiba_mdt61_white_balance},
{sizeof(toshiba_mdt61_vcs_settings),
(char *)toshiba_mdt61_vcs_settings},
{sizeof(toshiba_mdt61_vcom_dc_settings),
(char *)toshiba_mdt61_vcom_dc_settings},
{sizeof(toshiba_mdt61_testMode_e3), (char *)toshiba_mdt61_testMode_e3},
{sizeof(toshiba_mdt61_testMode_e4), (char *)toshiba_mdt61_testMode_e4},
{sizeof(toshiba_mdt61_testMode_e5), (char *)toshiba_mdt61_testMode_e5},
{sizeof(toshiba_mdt61_testMode_fa), (char *)toshiba_mdt61_testMode_fa},
{sizeof(toshiba_mdt61_testMode_fd), (char *)toshiba_mdt61_testMode_fd},
{sizeof(toshiba_mdt61_testMode_fe), (char *)toshiba_mdt61_testMode_fe},
{sizeof(toshiba_mdt61_mcap_end), (char *)toshiba_mdt61_mcap_end},
{sizeof(toshiba_mdt61_set_add_mode),
(char *)toshiba_mdt61_set_add_mode},
{sizeof(toshiba_mdt61_set_pixel_format),
(char *)toshiba_mdt61_set_pixel_format},
{sizeof(dsi_display_exit_sleep), (char *)dsi_display_exit_sleep},
{sizeof(dsi_display_display_on), (char *)dsi_display_display_on},
};
static struct mipi_dsi_cmd toshiba_mdv24_video_mode_cmds[] = {
{sizeof(toshiba_mdv24_mcap), (char *)toshiba_mdv24_mcap},
{sizeof(toshiba_mdv24_acr),
(char *)toshiba_mdv24_acr},
{sizeof(toshiba_mdv24_intf), (char *)toshiba_mdv24_intf},
{sizeof(toshiba_mdv24_pixel), (char *)toshiba_mdv24_pixel},
{sizeof(toshiba_mdv24_drive_setting),
(char *)toshiba_mdv24_drive_setting},
{sizeof(toshiba_mdv24_display_h_timing),
(char *)toshiba_mdv24_display_h_timing},
{sizeof(toshiba_mdv24_source_output),
(char *)toshiba_mdv24_source_output},
{sizeof(toshiba_mdv24_gate_control),
(char *)toshiba_mdv24_gate_control},
{sizeof(toshiba_mdv24_ltps_control_c4),
(char *)toshiba_mdv24_ltps_control_c4},
{sizeof(toshiba_mdv24_source_output_mode),
(char *)toshiba_mdv24_source_output_mode},
{sizeof(toshiba_mdv24_ltps_control_c7),
(char *)toshiba_mdv24_ltps_control_c7},
{sizeof(toshiba_mdv24_gamma_ctrl),
(char *)toshiba_mdv24_gamma_ctrl},
{sizeof(toshiba_mdv24_gamma_ctrl_a_pos),
(char *)toshiba_mdv24_gamma_ctrl_a_pos},
{sizeof(toshiba_mdv24_gamma_ctrl_a_neg),
(char *)toshiba_mdv24_gamma_ctrl_a_neg},
{sizeof(toshiba_mdv24_gamma_ctrl_b_pos),
(char *)toshiba_mdv24_gamma_ctrl_b_pos},
{sizeof(toshiba_mdv24_gamma_ctrl_b_neg),
(char *)toshiba_mdv24_gamma_ctrl_b_neg},
{sizeof(toshiba_mdv24_gamma_ctrl_c_pos),
(char *)toshiba_mdv24_gamma_ctrl_c_pos},
{sizeof(toshiba_mdv24_gamma_ctrl_c_neg),
(char *)toshiba_mdv24_gamma_ctrl_c_neg},
{sizeof(toshiba_mdv24_pwr_setting1),
(char *)toshiba_mdv24_pwr_setting1},
{sizeof(toshiba_mdv24_pwr_setting2),
(char *)toshiba_mdv24_pwr_setting2},
{sizeof(toshiba_mdv24_pwr_setting_internal),
(char *)toshiba_mdv24_pwr_setting_internal},
{sizeof(toshiba_mdv24_lvl_setting),
(char *)toshiba_mdv24_lvl_setting},
{sizeof(toshiba_mdv24_vcomdc_setting1),
(char *)toshiba_mdv24_vcomdc_setting1},
{sizeof(toshiba_mdv24_vcomdc_setting2),
(char *)toshiba_mdv24_vcomdc_setting2},
{sizeof(toshiba_mdv24_init_fd),
(char *)toshiba_mdv24_init_fd},
{sizeof(toshiba_mdv24_nvm_load_ctrl),
(char *)toshiba_mdv24_nvm_load_ctrl},
{sizeof(dsi_display_exit_sleep), (char *)dsi_display_exit_sleep},
{sizeof(dsi_display_display_on), (char *)dsi_display_display_on},
};
static struct mipi_dsi_phy_ctrl mipi_dsi_toshiba_mdt61_panel_phy_ctrl = {
/* 600*1024, RGB888, 3 Lane 55 fps video mode */
{0x03, 0x0a, 0x04, 0x00, 0x20},
/* timing */
{0xab, 0x8a, 0x18, 0x00, 0x92, 0x97, 0x1b, 0x8c,
0x0c, 0x03, 0x04, 0xa0},
{0x5f, 0x00, 0x00, 0x10}, /* phy ctrl */
{0xff, 0x00, 0x06, 0x00}, /* strength */
/* pll control 1- 19 */
{0x01, 0x7f, 0x31, 0xda, 0x00, 0x40, 0x03, 0x62,
0x41, 0x0f, 0x01,
0x00, 0x1a, 0x00, 0x00, 0x02, 0x00, 0x20, 0x00, 0x01, 0x00},
};
static struct mipi_dsi_cmd novatek_panel_manufacture_id_cmd =
{ sizeof(novatek_panel_manufacture_id), novatek_panel_manufacture_id };
static struct mipi_dsi_cmd novatek_panel_cmd_mode_cmds[] = {
{sizeof(novatek_panel_sw_reset), novatek_panel_sw_reset}
,
{sizeof(novatek_panel_exit_sleep), novatek_panel_exit_sleep}
,
{sizeof(novatek_panel_display_on), novatek_panel_display_on}
,
{sizeof(novatek_panel_max_packet), novatek_panel_max_packet}
,
{sizeof(novatek_panel_f4), novatek_panel_f4}
,
{sizeof(novatek_panel_8c), novatek_panel_8c}
,
{sizeof(novatek_panel_ff), novatek_panel_ff}
,
{sizeof(novatek_panel_set_twolane), novatek_panel_set_twolane}
,
{sizeof(novatek_panel_set_width), novatek_panel_set_width}
,
{sizeof(novatek_panel_set_height), novatek_panel_set_height}
,
{sizeof(novatek_panel_rgb_888), novatek_panel_rgb_888}
,
{sizeof(novatek_panel_set_led_pwm1), novatek_panel_set_led_pwm1}
,
{sizeof(novatek_panel_set_led_pwm2), novatek_panel_set_led_pwm2}
,
{sizeof(novatek_panel_set_led_pwm3), novatek_panel_set_led_pwm3}
};
static struct mipi_dsi_cmd sharp_qhd_video_mode_cmds[] = {
{sizeof(novatek_panel_sw_reset), novatek_panel_sw_reset}
,
{sizeof(novatek_panel_exit_sleep), novatek_panel_exit_sleep}
,
{sizeof(novatek_panel_display_on), novatek_panel_display_on}
,
{sizeof(novatek_panel_set_twolane), novatek_panel_set_twolane}
,
{sizeof(novatek_panel_rgb_888), novatek_panel_rgb_888}
,
{sizeof(novatek_panel_set_led_pwm1), novatek_panel_set_led_pwm1}
,
{sizeof(novatek_panel_set_led_pwm2), novatek_panel_set_led_pwm2}
,
{sizeof(novatek_panel_set_led_pwm3), novatek_panel_set_led_pwm3}
};
static struct mipi_dsi_phy_ctrl mipi_dsi_novatek_panel_phy_ctrl = {
/* DSI_BIT_CLK at 500MHz, 2 lane, RGB888 */
{0x03, 0x01, 0x01, 0x00}, /* regulator */
/* timing */
{0x96, 0x26, 0x23, 0x00, 0x50, 0x4B, 0x1e,
0x28, 0x28, 0x03, 0x04},
{0x7f, 0x00, 0x00, 0x00}, /* phy ctrl */
{0xee, 0x02, 0x86, 0x00}, /* strength */
/* pll control */
{0x40, 0xf9, 0xb0, 0xda, 0x00, 0x50, 0x48, 0x63,
/* 0x30, 0x07, 0x07, --> One lane configuration */
0x30, 0x07, 0x03, /* --> Two lane configuration */
0x05, 0x14, 0x03, 0x0, 0x0, 0x54, 0x06, 0x10, 0x04, 0x0},
};
enum { /* mipi dsi panel */
DSI_VIDEO_MODE,
DSI_CMD_MODE,
};
#define DSI_NON_BURST_SYNCH_PULSE 0
#define DSI_NON_BURST_SYNCH_EVENT 1
#define DSI_BURST_MODE 2
#define DSI_RGB_SWAP_RGB 0
#define DSI_RGB_SWAP_RBG 1
#define DSI_RGB_SWAP_BGR 2
#define DSI_RGB_SWAP_BRG 3
#define DSI_RGB_SWAP_GRB 4
#define DSI_RGB_SWAP_GBR 5
#define DSI_VIDEO_DST_FORMAT_RGB565 0
#define DSI_VIDEO_DST_FORMAT_RGB666 1
#define DSI_VIDEO_DST_FORMAT_RGB666_LOOSE 2
#define DSI_VIDEO_DST_FORMAT_RGB888 3
#define DSI_CMD_DST_FORMAT_RGB111 0
#define DSI_CMD_DST_FORMAT_RGB332 3
#define DSI_CMD_DST_FORMAT_RGB444 4
#define DSI_CMD_DST_FORMAT_RGB565 6
#define DSI_CMD_DST_FORMAT_RGB666 7
#define DSI_CMD_DST_FORMAT_RGB888 8
#define DSI_CMD_TRIGGER_NONE 0x0 /* mdp trigger */
#define DSI_CMD_TRIGGER_TE 0x02
#define DSI_CMD_TRIGGER_SW 0x04
#define DSI_CMD_TRIGGER_SW_SEOF 0x05 /* cmd dma only */
#define DSI_CMD_TRIGGER_SW_TE 0x06
int mipi_config(struct msm_fb_panel_data *panel);
int mdss_dsi_config(struct msm_fb_panel_data *panel);
int mipi_dsi_video_mode_config(unsigned short disp_width,
unsigned short disp_height,
unsigned short img_width,
unsigned short img_height,
unsigned short hsync_porch0_fp,
unsigned short hsync_porch0_bp,
unsigned short vsync_porch0_fp,
unsigned short vsync_porch0_bp,
unsigned short hsync_width,
unsigned short vsync_width,
unsigned short dst_format,
unsigned short traffic_mode,
unsigned char lane_en,
unsigned low_pwr_stop_mode,
unsigned char eof_bllp_pwr,
unsigned char interleav);
int mipi_dsi_on();
int mipi_dsi_off();
int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count);
int mipi_dsi_cmds_rx(char **rp, int len);
#endif
bootable/bootloader/lk/platform/msm_shared/include/mmc.h
+622
View File
@@ -0,0 +1,622 @@
/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MMC_H__
#define __MMC_H__
#if MMC_SDHCI_SUPPORT
#include "mmc_sdhci.h"
#include "mmc_wrapper.h"
#else
#ifndef MMC_SLOT
#define MMC_SLOT 0
#endif
extern unsigned int mmc_boot_mci_base;
#define MMC_BOOT_MCI_REG(offset) ((mmc_boot_mci_base) + offset)
/*
* Define Macros for SDCC Registers
*/
#define MMC_BOOT_MCI_POWER MMC_BOOT_MCI_REG(0x000) /* 8 bit */
/* MCICMD output control - 6th bit */
#ifdef PLATFORM_MSM7X30
#define MMC_BOOT_MCI_OPEN_DRAIN (1 << 6)
#define MMC_BOOT_MCI_PWR_OFF 0x00
#define MMC_BOOT_MCI_PWR_UP 0x01
#define MMC_BOOT_MCI_PWR_ON 0x01
#else
#define MMC_BOOT_MCI_OPEN_DRAIN (1 << 6)
#define MMC_BOOT_MCI_PWR_OFF 0x00
#define MMC_BOOT_MCI_PWR_UP 0x02
#define MMC_BOOT_MCI_PWR_ON 0x03
#endif
#define MMC_BOOT_MCI_CLK MMC_BOOT_MCI_REG(0x004) /* 16 bits */
/* Enable MCI bus clock - 0: clock disabled 1: enabled */
#define MMC_BOOT_MCI_CLK_ENABLE (1 << 8)
#define MMC_BOOT_MCI_CLK_DISABLE (0 << 8)
/* Disable clk o/p when bus idle- 0:always enabled 1:enabled when bus active */
#define MMC_BOOT_MCI_CLK_PWRSAVE (1 << 9)
/* Enable Widebus mode - 00: 1 bit mode 10:4 bit mode 01/11: 8 bit mode */
#define MMC_BOOT_MCI_CLK_WIDEBUS_MODE (3 << 10)
#define MMC_BOOT_MCI_CLK_WIDEBUS_1_BIT 0
#define MMC_BOOT_MCI_CLK_WIDEBUS_4_BIT (2 << 10)
#define MMC_BOOT_MCI_CLK_WIDEBUS_8_BIT (1 << 10)
/* Enable flow control- 0: disable 1: enable */
#define MMC_BOOT_MCI_CLK_ENA_FLOW (1 << 12)
/* Set/clear to select rising/falling edge for data/cmd output */
#define MMC_BOOT_MCI_CLK_INVERT_OUT (1 << 13)
/* Select to lach data/cmd coming in falling/rising/feedbk/loopbk of MCIclk */
#define MMC_BOOT_MCI_CLK_IN_FALLING 0x0
#define MMC_BOOT_MCI_CLK_IN_RISING (1 << 14)
#define MMC_BOOT_MCI_CLK_IN_FEEDBACK (2 << 14)
#define MMC_BOOT_MCI_CLK_IN_LOOPBACK (3 << 14)
/* Bus Width */
#define MMC_BOOT_BUS_WIDTH_1_BIT 0
#define MMC_BOOT_BUS_WIDTH_4_BIT 2
#define MMC_BOOT_BUS_WIDTH_8_BIT 3
/* Bus width support for DDR mode */
#define MMC_DDR_BUS_WIDTH_4_BIT 6
#define MMC_DDR_BUS_WIDTH_8_BIT 7
/* DDR mode select */
#define MMC_MCI_MODE_SELECT 14
#define MMC_MCI_DDR_MODE_EN 0x3
#define MMC_DEVICE_TYPE 196
#define MMC_BOOT_MCI_ARGUMENT MMC_BOOT_MCI_REG(0x008) /* 32 bits */
#define MMC_BOOT_MCI_CMD MMC_BOOT_MCI_REG(0x00C) /* 16 bits */
/* Command Index: 0 -5 */
/* Waits for response if set */
#define MMC_BOOT_MCI_CMD_RESPONSE (1 << 6)
/* Receives a 136-bit long response if set */
#define MMC_BOOT_MCI_CMD_LONGRSP (1 << 7)
/* If set, CPSM disables command timer and waits for interrupt */
#define MMC_BOOT_MCI_CMD_INTERRUPT (1 << 8)
/* If set waits for CmdPend before starting to send a command */
#define MMC_BOOT_MCI_CMD_PENDING (1 << 9)
/* CPSM is enabled if set */
#define MMC_BOOT_MCI_CMD_ENABLE (1 << 10)
/* If set PROG_DONE status bit asserted when busy is de-asserted */
#define MMC_BOOT_MCI_CMD_PROG_ENA (1 << 11)
/* To indicate that this is a Command with Data (for SDIO interrupts) */
#define MMC_BOOT_MCI_CMD_DAT_CMD (1 << 12)
/* Signals the next command to be an abort (stop) command. Always read 0 */
#define MMC_BOOT_MCI_CMD_MCIABORT (1 << 13)
/* Waits for Command Completion Signal if set */
#define MMC_BOOT_MCI_CMD_CCS_ENABLE (1 << 14)
/* If set sends CCS disable sequence */
#define MMC_BOOT_MCI_CMD_CCS_DISABLE (1 << 15)
#define MMC_BOOT_MCI_RESP_CMD MMC_BOOT_MCI_REG(0x010)
#define MMC_BOOT_MCI_RESP_0 MMC_BOOT_MCI_REG(0x014)
#define MMC_BOOT_MCI_RESP_1 MMC_BOOT_MCI_REG(0x018)
#define MMC_BOOT_MCI_RESP_2 MMC_BOOT_MCI_REG(0x01C)
#define MMC_BOOT_MCI_RESP_3 MMC_BOOT_MCI_REG(0x020)
#define MMC_BOOT_MCI_DATA_TIMER MMC_BOOT_MCI_REG(0x024)
#define MMC_BOOT_MCI_DATA_LENGTH MMC_BOOT_MCI_REG(0x028)
#define MMC_BOOT_MCI_DATA_CTL MMC_BOOT_MCI_REG(0x02C) /* 16 bits */
/* Data transfer enabled */
#define MMC_BOOT_MCI_DATA_ENABLE (1 << 0)
/* Data transfer direction - 0: controller to card 1:card to controller */
#define MMC_BOOT_MCI_DATA_DIR (1 << 1)
/* Data transfer mode - 0: block data transfer 1: stream data transfer */
#define MMC_BOOT_MCI_DATA_MODE (1 << 2)
/* Enable DM interface - 0: DM disabled 1: DM enabled */
#define MMC_BOOT_MCI_DATA_DM_ENABLE (1 << 3)
/* Data block length in bytes (1-4096) */
#define MMC_BOOT_MCI_BLKSIZE_POS 4
#define MMC_BOOT_MCI_DATA_COUNT MMC_BOOT_MCI_REG(0x030)
#define MMC_BOOT_MCI_STATUS MMC_BOOT_MCI_REG(0x034)
/* Command response received - CRC check failed */
#define MMC_BOOT_MCI_STAT_CMD_CRC_FAIL (1 << 0)
/* Data block sent/received - CRC check failed */
#define MMC_BOOT_MCI_STAT_DATA_CRC_FAIL (1 << 1)
/* Command resonse timeout */
#define MMC_BOOT_MCI_STAT_CMD_TIMEOUT (1 << 2)
/* Data timeout */
#define MMC_BOOT_MCI_STAT_DATA_TIMEOUT (1 << 3)
/* Transmit FIFO underrun error */
#define MMC_BOOT_MCI_STAT_TX_UNDRUN (1 << 4)
/* Receive FIFO overrun error */
#define MMC_BOOT_MCI_STAT_RX_OVRRUN (1 << 5)
/* Command response received - CRC check passed */
#define MMC_BOOT_MCI_STAT_CMD_RESP_END (1 << 6)
/* Command sent - no response required */
#define MMC_BOOT_MCI_STAT_CMD_SENT (1 << 7)
/* Data end - data counter zero */
#define MMC_BOOT_MCI_STAT_DATA_END (1 << 8)
/* Start bit not detected on all data signals in wide bus mode */
#define MMC_BOOT_MCI_STAT_START_BIT_ERR (1 << 9)
/* Data block sent/received - CRC check passed */
#define MMC_BOOT_MCI_STAT_DATA_BLK_END (1 << 10)
/* Command transfer in progress */
#define MMC_BOOT_MCI_STAT_CMD_ACTIVE (1 << 11)
/* Data transmit in progress */
#define MMC_BOOT_MCI_STAT_TX_ACTIVE (1 << 12)
/* Data receive in progress */
#define MMC_BOOT_MCI_STAT_RX_ACTIVE (1 << 13)
/* Transmit FIFO half full */
#define MMC_BOOT_MCI_STAT_TX_FIFO_HFULL (1 << 14)
/* Receive FIFO half full */
#define MMC_BOOT_MCI_STAT_RX_FIFO_HFULL (1 << 15)
/* Transmit FIFO full */
#define MMC_BOOT_MCI_STAT_TX_FIFO_FULL (1 << 16)
/* Receive FIFO full */
#define MMC_BOOT_MCI_STAT_RX_FIFO_FULL (1 << 17)
/* Transmit FIFO empty */
#define MMC_BOOT_MCI_STAT_TX_FIFO_EMPTY (1 << 18)
/* Receive FIFO empty */
#define MMC_BOOT_MCI_STAT_RX_FIFO_EMPTY (1 << 19)
/* Data available in transmit FIFO */
#define MMC_BOOT_MCI_STAT_TX_DATA_AVLBL (1 << 20)
/* Data available in receive FIFO */
#define MMC_BOOT_MCI_STAT_RX_DATA_AVLBL (1 << 21)
/* SDIO interrupt indicator for wake-up */
#define MMC_BOOT_MCI_STAT_SDIO_INTR (1 << 22)
/* Programming done */
#define MMC_BOOT_MCI_STAT_PROG_DONE (1 << 23)
/* CE-ATA command completion signal detected */
#define MMC_BOOT_MCI_STAT_ATA_CMD_CMPL (1 << 24)
/* SDIO interrupt indicator for normal operation */
#define MMC_BOOT_MCI_STAT_SDIO_INTR_OP (1 << 25)
/* Commpand completion signal timeout */
#define MMC_BOOT_MCI_STAT_CCS_TIMEOUT (1 << 26)
#define MMC_BOOT_MCI_STATIC_STATUS (MMC_BOOT_MCI_STAT_CMD_CRC_FAIL| \
MMC_BOOT_MCI_STAT_DATA_CRC_FAIL| \
MMC_BOOT_MCI_STAT_CMD_TIMEOUT| \
MMC_BOOT_MCI_STAT_DATA_TIMEOUT| \
MMC_BOOT_MCI_STAT_TX_UNDRUN| \
MMC_BOOT_MCI_STAT_RX_OVRRUN| \
MMC_BOOT_MCI_STAT_CMD_RESP_END| \
MMC_BOOT_MCI_STAT_CMD_SENT| \
MMC_BOOT_MCI_STAT_DATA_END| \
MMC_BOOT_MCI_STAT_START_BIT_ERR| \
MMC_BOOT_MCI_STAT_DATA_BLK_END| \
MMC_BOOT_MCI_SDIO_INTR_CLR| \
MMC_BOOT_MCI_STAT_PROG_DONE| \
MMC_BOOT_MCI_STAT_ATA_CMD_CMPL |\
MMC_BOOT_MCI_STAT_CCS_TIMEOUT)
#define MMC_BOOT_MCI_CLEAR MMC_BOOT_MCI_REG(0x038)
#define MMC_BOOT_MCI_CMD_CRC_FAIL_CLR (1 << 0)
#define MMC_BOOT_MCI_DATA_CRC_FAIL_CLR (1 << 1)
#define MMC_BOOT_MCI_CMD_TIMEOUT_CLR (1 << 2)
#define MMC_BOOT_MCI_DATA_TIMEOUT_CLR (1 << 3)
#define MMC_BOOT_MCI_TX_UNDERRUN_CLR (1 << 4)
#define MMC_BOOT_MCI_RX_OVERRUN_CLR (1 << 5)
#define MMC_BOOT_MCI_CMD_RESP_END_CLR (1 << 6)
#define MMC_BOOT_MCI_CMD_SENT_CLR (1 << 7)
#define MMC_BOOT_MCI_DATA_END_CLR (1 << 8)
#define MMC_BOOT_MCI_START_BIT_ERR_CLR (1 << 9)
#define MMC_BOOT_MCI_DATA_BLK_END_CLR (1 << 10)
#define MMC_BOOT_MCI_SDIO_INTR_CLR (1 << 22)
#define MMC_BOOT_MCI_PROG_DONE_CLR (1 << 23)
#define MMC_BOOT_MCI_ATA_CMD_COMPLR_CLR (1 << 24)
#define MMC_BOOT_MCI_CCS_TIMEOUT_CLR (1 << 25)
#define MMC_BOOT_MCI_INT_MASK0 MMC_BOOT_MCI_REG(0x03C)
#define MMC_BOOT_MCI_CMD_CRC_FAIL_MASK (1 << 0)
#define MMC_BOOT_MCI_DATA_CRC_FAIL_MASK (1 << 1)
#define MMC_BOOT_MCI_CMD_TIMEOUT_MASK (1 << 2)
#define MMC_BOOT_MCI_DATA_TIMEOUT_MASK (1 << 3)
#define MMC_BOOT_MCI_TX_OVERRUN_MASK (1 << 4)
#define MMC_BOOT_MCI_RX_OVERRUN_MASK (1 << 5)
#define MMC_BOOT_MCI_CMD_RESP_END_MASK (1 << 6)
#define MMC_BOOT_MCI_CMD_SENT_MASK (1 << 7)
#define MMC_BOOT_MCI_DATA_END_MASK (1 << 8)
#define MMC_BOOT_MCI_START_BIT_ERR_MASK (1 << 9)
#define MMC_BOOT_MCI_DATA_BLK_END_MASK (1 << 10)
#define MMC_BOOT_MCI_CMD_ACTIVE_MASK (1 << 11)
#define MMC_BOOT_MCI_TX_ACTIVE_MASK (1 << 12)
#define MMC_BOOT_MCI_RX_ACTIVE_MASK (1 << 13)
#define MMC_BOOT_MCI_TX_FIFO_HFULL_MASK (1 << 14)
#define MMC_BOOT_MCI_RX_FIFO_HFULL_MASK (1 << 15)
#define MMC_BOOT_MCI_TX_FIFO_FULL_MASK (1 << 16)
#define MMC_BOOT_MCI_RX_FIFO_FULL_MASK (1 << 17)
#define MMC_BOOT_MCI_TX_FIFO_EMPTY_MASK (1 << 18)
#define MMC_BOOT_MCI_RX_FIFO_EMPTY_MASK (1 << 19)
#define MMC_BOOT_MCI_TX_DATA_AVLBL_MASK (1 << 20)
#define MMC_BOOT_MCI_RX_DATA_AVLBL_MASK (1 << 21)
#define MMC_BOOT_MCI_SDIO_INT_MASK (1 << 22)
#define MMC_BOOT_MCI_PROG_DONE_MASK (1 << 23)
#define MMC_BOOT_MCI_ATA_CMD_COMPL_MASK (1 << 24)
#define MMC_BOOT_MCI_SDIO_INT_OPER_MASK (1 << 25)
#define MMC_BOOT_MCI_CCS_TIME_OUT_MASK (1 << 26)
#define MMC_BOOT_MCI_INT_MASK1 MMC_BOOT_MCI_REG(0x040)
#define MMC_BOOT_MCI_FIFO_COUNT MMC_BOOT_MCI_REG(0x044)
#define MMC_BOOT_MCI_VERSION MMC_BOOT_MCI_REG(0x050)
#define MMC_BOOT_MCI_CCS_TIMER MMC_BOOT_MCI_REG(0x0058)
#define MMC_BOOT_MCI_STATUS2 MMC_BOOT_MCI_REG(0x06C)
#define MMC_BOOT_MCI_MCLK_REG_WR_ACTIVE (1 << 0)
#define MMC_BOOT_MCI_FIFO MMC_BOOT_MCI_REG(0x080)
/* Card status */
#define MMC_BOOT_CARD_STATUS(x) ((x>>9) & 0x0F)
#define MMC_BOOT_TRAN_STATE 4
#define MMC_BOOT_PROG_STATE 7
#define MMC_BOOT_SWITCH_FUNC_ERR_FLAG (1 << 7)
/* SD Memory Card bus commands */
#define CMD0_GO_IDLE_STATE 0
#define CMD1_SEND_OP_COND 1
#define CMD2_ALL_SEND_CID 2
#define CMD3_SEND_RELATIVE_ADDR 3
#define CMD4_SET_DSR 4
#define CMD6_SWITCH_FUNC 6
#define ACMD6_SET_BUS_WIDTH 6 /* SD card */
#define CMD7_SELECT_DESELECT_CARD 7
#define CMD8_SEND_EXT_CSD 8
#define CMD8_SEND_IF_COND 8 /* SD card */
#define CMD9_SEND_CSD 9
#define CMD10_SEND_CID 10
#define CMD12_STOP_TRANSMISSION 12
#define CMD13_SEND_STATUS 13
#define CMD15_GO_INACTIVE_STATUS 15
#define CMD16_SET_BLOCKLEN 16
#define CMD17_READ_SINGLE_BLOCK 17
#define CMD18_READ_MULTIPLE_BLOCK 18
#define CMD23_SET_BLOCK_COUNT 23
#define CMD24_WRITE_SINGLE_BLOCK 24
#define CMD25_WRITE_MULTIPLE_BLOCK 25
#define CMD28_SET_WRITE_PROTECT 28
#define CMD29_CLEAR_WRITE_PROTECT 29
#define CMD31_SEND_WRITE_PROT_TYPE 31
#define CMD32_ERASE_WR_BLK_START 32
#define CMD33_ERASE_WR_BLK_END 33
#define CMD35_ERASE_GROUP_START 35
#define CMD36_ERASE_GROUP_END 36
#define CMD38_ERASE 38
#define ACMD41_SEND_OP_COND 41 /* SD card */
#define ACMD51_SEND_SCR 51 /* SD card */
#define CMD55_APP_CMD 55 /* SD card */
/* Switch Function Modes */
#define MMC_BOOT_SWITCH_FUNC_CHECK 0
#define MMC_BOOT_SWITCH_FUNC_SET 1
/* OCR Register */
#define MMC_BOOT_OCR_17_19 (1 << 7)
#define MMC_BOOT_OCR_27_36 (0x1FF << 15)
#define MMC_BOOT_OCR_SEC_MODE (2 << 29)
#define MMC_BOOT_OCR_BUSY (1 << 31)
/* Commands type */
#define MMC_BOOT_CMD_BCAST (1 << 0)
#define MMC_BOOT_CMD_BCAST_W_RESP (1 << 1)
#define MMC_BOOT_CMD_ADDRESS (1 << 2)
#define MMC_BOOT_CMD_ADDR_DATA_XFER (1 << 3)
/* Response types */
#define MMC_BOOT_RESP_NONE 0
#define MMC_BOOT_RESP_R1 (1 << 0)
#define MMC_BOOT_RESP_R1B (1 << 1)
#define MMC_BOOT_RESP_R2 (1 << 2)
#define MMC_BOOT_RESP_R3 (1 << 3)
#define MMC_BOOT_RESP_R6 (1 << 6)
#define MMC_BOOT_RESP_R7 (1 << 7)
#define IS_RESP_136_BITS(x) (x & MMC_BOOT_RESP_R2)
#define CHECK_FOR_BUSY_AT_RESP(x)
/* Card Status bits (R1 register) */
#define MMC_BOOT_R1_AKE_SEQ_ERROR (1 << 3)
#define MMC_BOOT_R1_APP_CMD (1 << 5)
#define MMC_BOOT_R1_RDY_FOR_DATA (1 << 6)
#define MMC_BOOT_R1_CURR_STATE_IDLE (0 << 9)
#define MMC_BOOT_R1_CURR_STATE_RDY (1 << 9)
#define MMC_BOOT_R1_CURR_STATE_IDENT (2 << 9)
#define MMC_BOOT_R1_CURR_STATE_STBY (3 << 9)
#define MMC_BOOT_R1_CURR_STATE_TRAN (4 << 9)
#define MMC_BOOT_R1_CURR_STATE_DATA (5 << 9)
#define MMC_BOOT_R1_CURR_STATE_RCV (6 << 9)
#define MMC_BOOT_R1_CURR_STATE_PRG (7 << 9)
#define MMC_BOOT_R1_CURR_STATE_DIS (8 << 9)
#define MMC_BOOT_R1_ERASE_RESET (1 << 13)
#define MMC_BOOT_R1_CARD_ECC_DISABLED (1 << 14)
#define MMC_BOOT_R1_WP_ERASE_SKIP (1 << 15)
#define MMC_BOOT_R1_ERROR (1 << 19)
#define MMC_BOOT_R1_CC_ERROR (1 << 20)
#define MMC_BOOT_R1_CARD_ECC_FAILED (1 << 21)
#define MMC_BOOT_R1_ILLEGAL_CMD (1 << 22)
#define MMC_BOOT_R1_COM_CRC_ERR (1 << 23)
#define MMC_BOOT_R1_LOCK_UNLOCK_FAIL (1 << 24)
#define MMC_BOOT_R1_CARD_IS_LOCKED (1 << 25)
#define MMC_BOOT_R1_WP_VIOLATION (1 << 26)
#define MMC_BOOT_R1_ERASE_PARAM (1 << 27)
#define MMC_BOOT_R1_ERASE_SEQ_ERR (1 << 28)
#define MMC_BOOT_R1_BLOCK_LEN_ERR (1 << 29)
#define MMC_BOOT_R1_ADDR_ERR (1 << 30)
#define MMC_BOOT_R1_OUT_OF_RANGE (1 << 31)
/* Macros for Common Errors */
#define MMC_BOOT_E_SUCCESS 0
#define MMC_BOOT_E_FAILURE 1
#define MMC_BOOT_E_TIMEOUT 2
#define MMC_BOOT_E_INVAL 3
#define MMC_BOOT_E_CRC_FAIL 4
#define MMC_BOOT_E_INIT_FAIL 5
#define MMC_BOOT_E_CMD_INDX_MISMATCH 6
#define MMC_BOOT_E_RESP_VERIFY_FAIL 7
#define MMC_BOOT_E_NOT_SUPPORTED 8
#define MMC_BOOT_E_CARD_BUSY 9
#define MMC_BOOT_E_MEM_ALLOC_FAIL 10
#define MMC_BOOT_E_CLK_ENABLE_FAIL 11
#define MMC_BOOT_E_CMMC_DECODE_FAIL 12
#define MMC_BOOT_E_CID_DECODE_FAIL 13
#define MMC_BOOT_E_BLOCKLEN_ERR 14
#define MMC_BOOT_E_ADDRESS_ERR 15
#define MMC_BOOT_E_DATA_CRC_FAIL 16
#define MMC_BOOT_E_DATA_TIMEOUT 17
#define MMC_BOOT_E_RX_OVRRUN 18
#define MMC_BOOT_E_VREG_SET_FAILED 19
#define MMC_BOOT_E_GPIO_CFG_FAIL 20
#define MMC_BOOT_E_DATA_ADM_ERR 21
/* EXT_CSD */
#define MMC_BOOT_ACCESS_WRITE 0x3
#define MMC_BOOT_EXT_USER_WP 171
#define MMC_BOOT_EXT_ERASE_GROUP_DEF 175
#define MMC_BOOT_EXT_ERASE_MEM_CONT 181
#define MMC_BOOT_EXT_CMMC_BUS_WIDTH 183
#define MMC_BOOT_EXT_CMMC_HS_TIMING 185
#define MMC_BOOT_EXT_HC_WP_GRP_SIZE 221
#define MMC_BOOT_EXT_ERASE_TIMEOUT_MULT 223
#define MMC_BOOT_EXT_HC_ERASE_GRP_SIZE 224
#define IS_BIT_SET_EXT_CSD(val, bit) ((ext_csd_buf[val]) & (1<<(bit)))
#define IS_ADDR_OUT_OF_RANGE(resp) ((resp >> 31) & 0x01)
#define MMC_BOOT_US_PERM_WP_EN 2
#define MMC_BOOT_US_PWR_WP_DIS 3
#define MMC_BOOT_US_PERM_WP_DIS (1<<4)
#define MMC_BOOT_US_PWR_WP_EN 1
/* For SD */
#define MMC_BOOT_SD_HC_VOLT_SUPPLIED 0x000001AA
#define MMC_BOOT_SD_NEG_OCR 0x00FF8000
#define MMC_BOOT_SD_HC_HCS 0x40000000
#define MMC_BOOT_SD_DEV_READY 0x80000000
#define MMC_BOOT_SD_SWITCH_HS 0x80FFFFF1
/* Data structure definitions */
struct mmc_boot_command {
unsigned int cmd_index;
unsigned int argument;
unsigned int cmd_type;
unsigned int resp[4];
unsigned int resp_type;
unsigned int prg_enabled;
unsigned int xfer_mode;
};
#define MMC_BOOT_XFER_MODE_BLOCK 0
#define MMC_BOOT_XFER_MODE_STREAM 1
/* CSD Register.
* Note: not all the fields have been defined here
*/
struct mmc_csd {
unsigned int cmmc_structure;
unsigned int spec_vers;
unsigned int card_cmd_class;
unsigned int write_blk_len;
unsigned int read_blk_len;
unsigned int r2w_factor;
unsigned int sector_size;
unsigned int c_size_mult;
unsigned int c_size;
unsigned int nsac_clk_cycle;
unsigned int taac_ns;
unsigned int tran_speed;
unsigned int erase_grp_size;
unsigned int erase_grp_mult;
unsigned int wp_grp_size;
unsigned int wp_grp_enable:1;
unsigned int perm_wp:1;
unsigned int temp_wp:1;
unsigned int erase_blk_len:1;
unsigned int read_blk_misalign:1;
unsigned int write_blk_misalign:1;
unsigned int read_blk_partial:1;
unsigned int write_blk_partial:1;
};
/* CID Register */
struct mmc_cid {
unsigned int mid; /* 8 bit manufacturer id */
unsigned int oid; /* 16 bits 2 character ASCII - OEM ID */
unsigned char pnm[7]; /* 6 character ASCII - product name */
unsigned int prv; /* 8 bits - product revision */
unsigned int psn; /* 32 bits - product serial number */
unsigned int month; /* 4 bits manufacturing month */
unsigned int year; /* 4 bits manufacturing year */
};
/* SCR Register */
struct mmc_boot_scr {
unsigned int scr_structure;
unsigned int mmc_spec;
#define MMC_BOOT_SCR_MMC_SPEC_V1_01 0
#define MMC_BOOT_SCR_MMC_SPEC_V1_10 1
#define MMC_BOOT_SCR_MMC_SPEC_V2_00 2
unsigned int data_stat_after_erase;
unsigned int mmc_security;
#define MMC_BOOT_SCR_NO_SECURITY 0
#define MMC_BOOT_SCR_SECURITY_UNUSED 1
#define MMC_BOOT_SCR_SECURITY_V1_01 2
#define MMC_BOOT_SCR_SECURITY_V2_00 3
unsigned int mmc_bus_width;
#define MMC_BOOT_SCR_BUS_WIDTH_1_BIT (1<<0)
#define MMC_BOOT_SCR_BUS_WIDTH_4_BIT (1<<2)
};
struct mmc_card {
unsigned int rca;
unsigned int ocr;
unsigned long long capacity;
unsigned int type;
#define MMC_BOOT_TYPE_STD_SD 0
#define MMC_BOOT_TYPE_SDHC 1
#define MMC_BOOT_TYPE_SDIO 2
#define MMC_BOOT_TYPE_MMCHC 3
#define MMC_BOOT_TYPE_STD_MMC 4
unsigned int status;
#define MMC_BOOT_STATUS_INACTIVE 0
#define MMC_BOOT_STATUS_ACTIVE 1
unsigned int rd_timeout_ns;
unsigned int wr_timeout_ns;
unsigned int rd_block_len;
unsigned int wr_block_len;
//unsigned int data_xfer_len;
struct mmc_cid cid;
struct mmc_csd csd;
struct mmc_boot_scr scr;
};
#define MMC_BOOT_XFER_MULTI_BLOCK 0
#define MMC_BOOT_XFER_SINGLE_BLOCK 1
/* Capabilities for the mmc host */
struct mmc_caps {
uint8_t ddr_mode; /* DDR mode support */
uint8_t hs200_mode; /* HS200 mode support */
uint8_t bus_width; /* bus width */
uint32_t hs_clk_rate; /* Clock rate for high speed mode */
};
struct mmc_host {
unsigned int mclk_rate;
unsigned int ocr;
unsigned int cmd_retry;
uint32_t mmc_cont_version;
struct mmc_caps caps;
};
/* MACRO used to evoke regcomp */
#define REGCOMP_CKRTN(regx, str, errhandle) \
do { \
if(regcomp(regx, str, REG_EXTENDED) != 0) { \
printf("Error building regex: %s\n", str); \
goto errhandle; \
} \
} while(0);
#define PUT_LWORD_TO_BYTE(x, y) do{*(x) = y & 0xff; \
*(x+1) = (y >> 8) & 0xff; \
*(x+2) = (y >> 16) & 0xff; \
*(x+3) = (y >> 24) & 0xff; }while(0)
#define GET_PAR_NUM_FROM_POS(x) (((x & 0x0000FF00) >> 8) + (x & 0x000000FF))
#define OFFSET_STATUS 0x00
#define OFFSET_TYPE 0x04
#define OFFSET_FIRST_SEC 0x08
#define OFFSET_SIZE 0x0C
#define COPYBUFF_SIZE (1024 * 16)
#define BINARY_IN_TABLE_SIZE (16 * 512)
#define MAX_FILE_ENTRIES 20
#define MMC_RCA 2
/* Can be used to unpack array of upto 32 bits data */
#define UNPACK_BITS(array, start, len, size_of) \
({ \
unsigned int indx = (start) / (size_of); \
unsigned int offset = (start) % (size_of); \
unsigned int mask = (((len)<(size_of))? 1<<(len):0) - 1; \
unsigned int unpck = array[indx] >> offset; \
unsigned int indx2 = ((start) + (len) - 1) / (size_of); \
if(indx2 > indx) \
unpck |= array[indx2] << ((size_of) - offset); \
unpck & mask; \
})
#define MMC_BOOT_MAX_COMMAND_RETRY 1000
#define MMC_BOOT_RD_BLOCK_LEN 512
#define MMC_BOOT_WR_BLOCK_LEN 512
/* We have 16 32-bits FIFO registers */
#define MMC_BOOT_MCI_FIFO_DEPTH 16
#define MMC_BOOT_MCI_HFIFO_COUNT ( MMC_BOOT_MCI_FIFO_DEPTH / 2 )
#define MMC_BOOT_MCI_FIFO_SIZE ( MMC_BOOT_MCI_FIFO_DEPTH * 4 )
#define MAX_PARTITIONS 64
#define MMC_BOOT_CHECK_PATTERN 0xAA /* 10101010b */
#define MMC_CLK_400KHZ 400000
#define MMC_CLK_144KHZ 144000
#define MMC_CLK_20MHZ 20000000
#define MMC_CLK_25MHZ 25000000
#define MMC_CLK_48MHZ 48000000
#define MMC_CLK_50MHZ 49152000
#define MMC_CLK_96MHZ 96000000
#define MMC_CLK_200MHZ 200000000
#define MMC_CLK_ENABLE 1
#define MMC_CLK_DISABLE 0
unsigned int mmc_boot_main(unsigned char slot, unsigned int base);
unsigned int mmc_write(unsigned long long data_addr,
unsigned int data_len, unsigned int *in);
unsigned int mmc_read(unsigned long long data_addr, unsigned int *out,
unsigned int data_len);
unsigned mmc_get_psn(void);
unsigned int mmc_erase_card(unsigned long long data_addr,
unsigned long long data_len);
void mmc_mclk_reg_wr_delay();
void mmc_boot_mci_clk_enable();
void mmc_boot_mci_clk_disable();
uint8_t card_supports_ddr_mode();
uint8_t card_supports_hs200_mode();
uint64_t mmc_get_device_capacity();
#endif
#endif
bootable/bootloader/lk/platform/msm_shared/include/mmc_dml.h
+59
View File
@@ -0,0 +1,59 @@
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MMC_DML_H__
#define __MMC_DML_H__
#include <platform/iomap.h>
#define SDCC_DML_CONFIG(base) (0x00 + base)
#define SDCC_CONSUMER_CRCI_SEL_SHIFT 2
#define SDCC_PRODUCER_CRCI_SEL_SHIFT 0
#define SDCC_PRODUCER_TRANS_END_EN_SHIFT 4
#define SDCC_BYPASS_SHIFT 16
#define SDCC_DIRECT_MODE_SHIFT 17
#define SDCC_INFINITE_CONS_TRANS_SHIFT 18
#define SDCC_DML_STATUS(base) (0x04 + base)
#define SDCC_DML_PRODUCER_IDLE_SHIFT 0
#define SDCC_DML_CONSUMER_IDLE_SHIFT 16
#define SDCC_DML_SW_RESET(base) (0x08 + base)
#define SDCC_DML_PRODUCER_START(base) (0x0C + base)
#define SDCC_DML_CONSUMER_START(base) (0x10 + base)
#define SDCC_DML_PRODUCER_PIPE_LOGICAL_SIZE(base) (0x14 + base)
#define SDCC_DML_CONSUMER_PIPE_LOGICAL_SIZE(base) (0x18 + base)
#define SDCC_DML_PIPE_ID(base) (0x1C + base)
#define SDCC_CONSUMER_PIPE_ID_SHIFT 16
#define SDCC_PRODUCER_PIPE_ID_SHIFT 0
#define SDCC_DML_PRODUCER_BAM_BLOCK_SIZE(base) (0x24 + base)
#define SDCC_DML_PRODUCER_BAM_TRANS_SIZE(base) (0x28 + base)
#endif
bootable/bootloader/lk/platform/msm_shared/include/mmc_sdhci.h
+221
View File
@@ -0,0 +1,221 @@
/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MMC_SDHCI_H__
#define __MMC_SDHCI_H__
#include <sdhci.h>
/* Emmc Card bus commands */
#define CMD0_GO_IDLE_STATE 0
#define CMD1_SEND_OP_COND 1
#define CMD2_ALL_SEND_CID 2
#define CMD3_SEND_RELATIVE_ADDR 3
#define CMD4_SET_DSR 4
#define CMD6_SWITCH_FUNC 6
#define CMD7_SELECT_DESELECT_CARD 7
#define CMD8_SEND_EXT_CSD 8
#define CMD9_SEND_CSD 9
#define CMD10_SEND_CID 10
#define CMD12_STOP_TRANSMISSION 12
#define CMD13_SEND_STATUS 13
#define CMD15_GO_INACTIVE_STATUS 15
#define CMD16_SET_BLOCKLEN 16
#define CMD17_READ_SINGLE_BLOCK 17
#define CMD18_READ_MULTIPLE_BLOCK 18
#define CMD23_SET_BLOCK_COUNT 23
#define CMD24_WRITE_SINGLE_BLOCK 24
#define CMD25_WRITE_MULTIPLE_BLOCK 25
#define CMD28_SET_WRITE_PROTECT 28
#define CMD29_CLEAR_WRITE_PROTECT 29
#define CMD31_SEND_WRITE_PROT_TYPE 31
#define CMD32_ERASE_WR_BLK_START 32
#define CMD33_ERASE_WR_BLK_END 33
#define CMD35_ERASE_GROUP_START 35
#define CMD36_ERASE_GROUP_END 36
#define CMD38_ERASE 38
/* Card type */
#define MMC_TYPE_STD_SD 0
#define MMC_TYPE_SDHC 1
#define MMC_TYPE_SDIO 2
#define MMC_TYPE_MMCHC 3
#define MMC_TYPE_STD_MMC 4
/* OCR Register */
#define MMC_OCR_17_19 (1 << 7)
#define MMC_OCR_27_36 (0x1FF << 15)
#define MMC_OCR_SEC_MODE (2 << 29)
#define MMC_OCR_BUSY (1 << 31)
/* Card status */
#define MMC_CARD_STATUS(x) ((x >> 9) & 0x0F)
#define MMC_TRAN_STATE 4
#define MMC_PROG_STATE 7
#define MMC_SWITCH_FUNC_ERR_FLAG (1 << 7)
#define MMC_STATUS_INACTIVE 0
#define MMC_STATUS_ACTIVE 1
/* EXT_CSD */
/* Offsets in the ext csd */
#define MMC_EXT_MMC_BUS_WIDTH 183
#define MMC_EXT_MMC_HS_TIMING 185
#define MMC_DEVICE_TYPE 196
#define MMC_EXT_HC_WP_GRP_SIZE 221
#define MMC_SEC_COUNT4 215
#define MMC_SEC_COUNT3 214
#define MMC_SEC_COUNT2 213
#define MMC_SEC_COUNT1 212
#define MMC_PART_CONFIG 179
#define MMC_ERASE_GRP_DEF 175
#define MMC_USR_WP 171
/* Values for ext csd fields */
#define MMC_HS_TIMING 0x1
#define MMC_HS200_TIMING 0x2
#define MMC_ACCESS_WRITE 0x3
#define MMC_HS_DDR_MODE (BIT(2) | BIT(3))
#define MMC_HS_HS200_MODE (BIT(4) | BIT(5))
#define MMC_SEC_COUNT4_SHIFT 24
#define MMC_SEC_COUNT3_SHIFT 16
#define MMC_SEC_COUNT2_SHIFT 8
/* Command related */
#define MMC_MAX_COMMAND_RETRY 1000
#define MMC_RD_BLOCK_LEN 512
#define MMC_WR_BLOCK_LEN 512
#define MMC_R1_BLOCK_LEN_ERR (1 << 29)
#define MMC_R1_ADDR_ERR (1 << 30)
/* RCA of the card */
#define MMC_RCA 2
/* Misc card macros */
#define MMC_BLK_SZ 512
/* Clock rates */
#define MMC_CLK_400KHZ 400000
#define MMC_CLK_144KHZ 144000
#define MMC_CLK_20MHZ 20000000
#define MMC_CLK_25MHZ 25000000
#define MMC_CLK_48MHZ 48000000
#define MMC_CLK_50MHZ 49152000
#define MMC_CLK_96MHZ 96000000
#define MMC_CLK_200MHZ 200000000
/* Can be used to unpack array of upto 32 bits data */
#define UNPACK_BITS(array, start, len, size_of) \
({ \
uint32_t indx = (start) / (size_of); \
uint32_t offset = (start) % (size_of); \
uint32_t mask = (((len)<(size_of))? 1<<(len):0) - 1; \
uint32_t unpck = array[indx] >> offset; \
uint32_t indx2 = ((start) + (len) - 1) / (size_of); \
if(indx2 > indx) \
unpck |= array[indx2] << ((size_of) - offset); \
unpck & mask; \
})
/* CSD Register.
* Note: not all the fields have been defined here
*/
struct mmc_csd {
uint32_t cmmc_structure;
uint32_t spec_vers;
uint32_t card_cmd_class;
uint32_t write_blk_len;
uint32_t read_blk_len;
uint32_t r2w_factor;
uint32_t sector_size;
uint32_t c_size_mult;
uint32_t c_size;
uint32_t nsac_clk_cycle;
uint32_t taac_ns;
uint32_t tran_speed;
uint32_t erase_grp_size;
uint32_t erase_grp_mult;
uint32_t wp_grp_size;
uint32_t wp_grp_enable:1;
uint32_t perm_wp:1;
uint32_t temp_wp:1;
uint32_t erase_blk_len:1;
uint32_t read_blk_misalign:1;
uint32_t write_blk_misalign:1;
uint32_t read_blk_partial:1;
uint32_t write_blk_partial:1;
};
/* CID Register */
struct mmc_cid {
uint32_t mid; /* 8 bit manufacturer id */
uint32_t oid; /* 16 bits 2 character ASCII - OEM ID */
uint8_t pnm[7]; /* 6 character ASCII - product name */
uint32_t prv; /* 8 bits - product revision */
uint32_t psn; /* 32 bits - product serial number */
uint32_t month; /* 4 bits manufacturing month */
uint32_t year; /* 4 bits manufacturing year */
};
/* mmc card register */
struct mmc_card {
uint32_t rca; /* Relative addres of the card*/
uint32_t ocr; /* Operating range of the card*/
uint64_t capacity; /* card capacity */
uint32_t type; /* Type of the card */
uint32_t status; /* Card status */
uint8_t *ext_csd; /* Ext CSD for the card info */
uint32_t raw_csd[4]; /* Raw CSD for the card */
struct mmc_cid cid; /* CID structure */
struct mmc_csd csd; /* CSD structure */
};
/* mmc device config data */
struct mmc_config_data {
uint8_t slot; /* Sdcc slot used */
uint32_t base; /* Based address for the sdcc */
uint16_t bus_width; /* Bus width used */
uint32_t max_clk_rate; /* Max clock rate supported */
};
/* mmc device structure */
struct mmc_device {
struct sdhci_host host; /* Handle to host controller */
struct mmc_card card; /* Handle to mmc card */
struct mmc_config_data config; /* Handle for the mmc config data */
};
/*
* APIS exposed to block level driver
*/
/* API: Initialize the mmc card */
struct mmc_device *mmc_init(struct mmc_config_data *);
/* API: Read required number of blocks from card into destination */
uint32_t mmc_sdhci_read(struct mmc_device *dev, void *dest, uint64_t blk_addr, uint32_t num_blocks);
/* API: Write requried number of blocks from source to card */
uint32_t mmc_sdhci_write(struct mmc_device *dev, void *src, uint64_t blk_addr, uint32_t num_blocks);
#endif
bootable/bootloader/lk/platform/msm_shared/include/mmc_wrapper.h
+44
View File
@@ -0,0 +1,44 @@
/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MMC_WRAPPER_H__
#define __MMC_WRAPPER_H__
#include <mmc_sdhci.h>
/* Wrapper APIs */
struct mmc_device *get_mmc_device();
uint32_t mmc_get_psn(void);
uint32_t mmc_read(uint64_t data_addr, uint32_t *out, uint32_t data_len);
uint32_t mmc_write(uint64_t data_addr, uint32_t data_len, void *in);
uint32_t mmc_erase_card(uint64_t, uint64_t);
uint64_t mmc_get_device_capacity(void);
uint32_t mmc_erase_card(uint64_t addr, uint64_t len);
#endif
bootable/bootloader/lk/platform/msm_shared/include/mmu.h
+41
View File
@@ -0,0 +1,41 @@
/* Copyright (c) 2011, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MSM_SHARED_MMU_H__
#define __MSM_SHARED_MMU_H__
#include <sys/types.h>
typedef struct {
addr_t paddress;
addr_t vaddress;
uint32_t num_of_sections;
uint32_t flags;
} mmu_section_t;
#endif
bootable/bootloader/lk/platform/msm_shared/include/msm_panel.h
+200
View File
@@ -0,0 +1,200 @@
/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _PLATFORM_MSM_SHARED_MSM_PANEL_H_
#define _PLATFORM_MSM_SHARED_MSM_PANEL_H_
#include <stdint.h>
#include <dev/fbcon.h>
#define TRUE 1
#define FALSE 0
/* panel type list */
#define NO_PANEL 0xffff /* No Panel */
#define MDDI_PANEL 1 /* MDDI */
#define EBI2_PANEL 2 /* EBI2 */
#define LCDC_PANEL 3 /* internal LCDC type */
#define EXT_MDDI_PANEL 4 /* Ext.MDDI */
#define TV_PANEL 5 /* TV */
#define HDMI_PANEL 6 /* HDMI TV */
#define DTV_PANEL 7 /* DTV */
#define MIPI_VIDEO_PANEL 8 /* MIPI */
#define MIPI_CMD_PANEL 9 /* MIPI */
#define WRITEBACK_PANEL 10 /* Wifi display */
#define LVDS_PANEL 11 /* LVDS */
enum msm_mdp_hw_revision {
MDP_REV_20 = 1,
MDP_REV_22,
MDP_REV_30,
MDP_REV_303,
MDP_REV_31,
MDP_REV_40,
MDP_REV_41,
MDP_REV_42,
MDP_REV_43,
MDP_REV_44,
MDP_REV_50,
};
/* panel info type */
struct lcd_panel_info {
uint32_t vsync_enable;
uint32_t refx100;
uint32_t v_back_porch;
uint32_t v_front_porch;
uint32_t v_pulse_width;
uint32_t hw_vsync_mode;
uint32_t vsync_notifier_period;
uint32_t rev;
};
struct hdmi_panel_info {
uint32_t h_back_porch;
uint32_t h_front_porch;
uint32_t h_pulse_width;
uint32_t v_back_porch;
uint32_t v_front_porch;
uint32_t v_pulse_width;
};
struct lcdc_panel_info {
uint32_t h_back_porch;
uint32_t h_front_porch;
uint32_t h_pulse_width;
uint32_t v_back_porch;
uint32_t v_front_porch;
uint32_t v_pulse_width;
uint32_t border_clr;
uint32_t underflow_clr;
uint32_t hsync_skew;
/* Pad width */
uint32_t xres_pad;
/* Pad height */
uint32_t yres_pad;
};
struct mipi_panel_info {
char mode; /* video/cmd */
char interleave_mode;
char crc_check;
char ecc_check;
char dst_format; /* shared by video and command */
char num_of_lanes;
char data_lane0;
char data_lane1;
char data_lane2;
char data_lane3;
char dlane_swap; /* data lane swap */
char rgb_swap;
char b_sel;
char g_sel;
char r_sel;
char rx_eot_ignore;
char tx_eot_append;
char t_clk_post; /* 0xc0, DSI_CLKOUT_TIMING_CTRL */
char t_clk_pre; /* 0xc0, DSI_CLKOUT_TIMING_CTRL */
char vc; /* virtual channel */
struct mipi_dsi_phy_ctrl *dsi_phy_db;
struct mdss_dsi_phy_ctrl *mdss_dsi_phy_db;
struct mipi_dsi_cmd *panel_cmds;
int num_of_panel_cmds;
/* video mode */
char pulse_mode_hsa_he;
char hfp_power_stop;
char hbp_power_stop;
char hsa_power_stop;
char eof_bllp_power_stop;
char bllp_power_stop;
char traffic_mode;
char frame_rate;
/* command mode */
char interleave_max;
char insert_dcs_cmd;
char wr_mem_continue;
char wr_mem_start;
char te_sel;
char stream; /* 0 or 1 */
char mdp_trigger;
char dma_trigger;
uint32_t dsi_pclk_rate;
/* The packet-size should not bet changed */
char no_max_pkt_size;
/* Clock required during LP commands */
char force_clk_lane_hs;
char lane_swap;
};
enum lvds_mode {
LVDS_SINGLE_CHANNEL_MODE,
LVDS_DUAL_CHANNEL_MODE,
};
struct lvds_panel_info {
enum lvds_mode channel_mode;
/* Channel swap in dual mode */
char channel_swap;
};
struct msm_panel_info {
uint32_t xres;
uint32_t yres;
uint32_t bpp;
uint32_t type;
uint32_t wait_cycle;
uint32_t clk_rate;
struct lcd_panel_info lcd;
struct lcdc_panel_info lcdc;
struct mipi_panel_info mipi;
struct lvds_panel_info lvds;
struct hdmi_panel_info hdmi;
int (*on) (void);
int (*off) (void);
int (*early_config) (void *pdata);
int (*config) (void *pdata);
int (*rotate) (void);
};
struct msm_fb_panel_data {
struct msm_panel_info panel_info;
struct fbcon_config fb;
int mdp_rev;
int rotate;
/* function entry chain */
int (*power_func) (int enable);
int (*clk_func) (int enable);
};
int msm_display_init(struct msm_fb_panel_data *pdata);
#endif
bootable/bootloader/lk/platform/msm_shared/include/nand.h
+204
View File
@@ -0,0 +1,204 @@
/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef __PLATFORM_MSM_SHARED_NAND_H
#define __PLATFORM_MSM_SHARED_NAND_H
#ifdef PLATFORM_MSM7X30
#define MSM_NAND_BASE 0xA0200000
#elif PLATFORM_MDM9X15
#define MSM_NAND_BASE 0x1B400000
#else
#define MSM_NAND_BASE 0xA0A00000
#endif
#define MSM_NAND_NC01_BASE 0xA0240000
#define MSM_NAND_NC10_BASE 0xA0280000
#define MSM_NAND_NC11_BASE 0xA02C0000
#define EBI2_REG_BASE 0xA0000000
#define NC01(off) (MSM_NAND_NC01_BASE + (off))
#define NC10(off) (MSM_NAND_NC10_BASE + (off))
#define NC11(off) (MSM_NAND_NC11_BASE + (off))
#define EBI2_REG(off) (EBI2_REG_BASE + (off))
#define NAND_REG(off) (MSM_NAND_BASE + (off))
#define NAND_FLASH_CMD NAND_REG(0x0000)
#define NAND_ADDR0 NAND_REG(0x0004)
#define NAND_ADDR1 NAND_REG(0x0008)
#define NAND_FLASH_CHIP_SELECT NAND_REG(0x000C)
#define NAND_EXEC_CMD NAND_REG(0x0010)
#define NAND_FLASH_STATUS NAND_REG(0x0014)
#define NAND_BUFFER_STATUS NAND_REG(0x0018)
#define NAND_DEV0_CFG0 NAND_REG(0x0020)
#define NAND_DEV0_CFG1 NAND_REG(0x0024)
#define NAND_DEV1_CFG0 NAND_REG(0x0030)
#define NAND_DEV1_CFG1 NAND_REG(0x0034)
#define NAND_SFLASHC_CMD NAND_REG(0x0038)
#define NAND_SFLASHC_EXEC_CMD NAND_REG(0x003C)
#define NAND_READ_ID NAND_REG(0x0040)
#define NAND_READ_STATUS NAND_REG(0x0044)
#define NAND_CONFIG_DATA NAND_REG(0x0050)
#define NAND_CONFIG NAND_REG(0x0054)
#define NAND_CONFIG_MODE NAND_REG(0x0058)
#define NAND_CONFIG_STATUS NAND_REG(0x0060)
#define NAND_MACRO1_REG NAND_REG(0x0064)
#define NAND_XFR_STEP1 NAND_REG(0x0070)
#define NAND_XFR_STEP2 NAND_REG(0x0074)
#define NAND_XFR_STEP3 NAND_REG(0x0078)
#define NAND_XFR_STEP4 NAND_REG(0x007C)
#define NAND_XFR_STEP5 NAND_REG(0x0080)
#define NAND_XFR_STEP6 NAND_REG(0x0084)
#define NAND_XFR_STEP7 NAND_REG(0x0088)
#define NAND_GENP_REG0 NAND_REG(0x0090)
#define NAND_GENP_REG1 NAND_REG(0x0094)
#define NAND_GENP_REG2 NAND_REG(0x0098)
#define NAND_GENP_REG3 NAND_REG(0x009C)
#define NAND_SFLASHC_STATUS NAND_REG(0x001C)
#define NAND_DEV_CMD0 NAND_REG(0x00A0)
#define NAND_DEV_CMD1 NAND_REG(0x00A4)
#define NAND_DEV_CMD2 NAND_REG(0x00A8)
#define NAND_DEV_CMD_VLD NAND_REG(0x00AC)
#define NAND_EBI2_MISR_SIG_REG NAND_REG(0x00B0)
#define NAND_ADDR2 NAND_REG(0x00C0)
#define NAND_ADDR3 NAND_REG(0x00C4)
#define NAND_ADDR4 NAND_REG(0x00C8)
#define NAND_ADDR5 NAND_REG(0x00CC)
#define NAND_DEV_CMD3 NAND_REG(0x00D0)
#define NAND_DEV_CMD4 NAND_REG(0x00D4)
#define NAND_DEV_CMD5 NAND_REG(0x00D8)
#define NAND_DEV_CMD6 NAND_REG(0x00DC)
#define NAND_SFLASHC_BURST_CFG NAND_REG(0x00E0)
#define NAND_ADDR6 NAND_REG(0x00E4)
#define NAND_EBI2_ECC_BUF_CFG NAND_REG(0x00F0)
#define NAND_FLASH_BUFFER NAND_REG(0x0100)
#define NAND_HW_INFO NAND_REG(0x00FC)
/* device commands */
#define NAND_CMD_SOFT_RESET 0x01
#define NAND_CMD_PAGE_READ 0x32
#define NAND_CMD_PAGE_READ_ECC 0x33
#define NAND_CMD_PAGE_READ_ALL 0x34
#define NAND_CMD_SEQ_PAGE_READ 0x15
#define NAND_CMD_PRG_PAGE 0x36
#define NAND_CMD_PRG_PAGE_ECC 0x37
#define NAND_CMD_PRG_PAGE_ALL 0x39
#define NAND_CMD_BLOCK_ERASE 0x3A
#define NAND_CMD_FETCH_ID 0x0B
#define NAND_CMD_STATUS 0x0C
#define NAND_CMD_RESET 0x0D
/* Sflash Commands */
#define NAND_SFCMD_DATXS 0x0
#define NAND_SFCMD_CMDXS 0x1
#define NAND_SFCMD_BURST 0x0
#define NAND_SFCMD_ASYNC 0x1
#define NAND_SFCMD_ABORT 0x1
#define NAND_SFCMD_REGRD 0x2
#define NAND_SFCMD_REGWR 0x3
#define NAND_SFCMD_INTLO 0x4
#define NAND_SFCMD_INTHI 0x5
#define NAND_SFCMD_DATRD 0x6
#define NAND_SFCMD_DATWR 0x7
#define SFLASH_PREPCMD(numxfr, offval, delval, trnstp, mode, opcode) \
((numxfr<<20)|(offval<<12)|(delval<<6)|(trnstp<<5)|(mode<<4)|opcode)
#define SFLASH_BCFG 0x20100327
#define CLEAN_DATA_32 0xFFFFFFFF
#define CLEAN_DATA_16 0xFFFF
/* Onenand addresses */
#define ONENAND_MANUFACTURER_ID 0xF000
#define ONENAND_DEVICE_ID 0xF001
#define ONENAND_VERSION_ID 0xF002
#define ONENAND_DATA_BUFFER_SIZE 0xF003
#define ONENAND_BOOT_BUFFER_SIZE 0xF004
#define ONENAND_AMOUNT_OF_BUFFERS 0xF005
#define ONENAND_TECHNOLOGY 0xF006
#define ONENAND_START_ADDRESS_1 0xF100
#define ONENAND_START_ADDRESS_2 0xF101
#define ONENAND_START_ADDRESS_3 0xF102
#define ONENAND_START_ADDRESS_4 0xF103
#define ONENAND_START_ADDRESS_5 0xF104
#define ONENAND_START_ADDRESS_6 0xF105
#define ONENAND_START_ADDRESS_7 0xF106
#define ONENAND_START_ADDRESS_8 0xF107
#define ONENAND_START_BUFFER 0xF200
#define ONENAND_COMMAND 0xF220
#define ONENAND_SYSTEM_CONFIG_1 0xF221
#define ONENAND_SYSTEM_CONFIG_2 0xF222
#define ONENAND_CONTROLLER_STATUS 0xF240
#define ONENAND_INTERRUPT_STATUS 0xF241
#define ONENAND_START_BLOCK_ADDRESS 0xF24C
#define ONENAND_WRITE_PROT_STATUS 0xF24E
#define ONENAND_ECC_STATUS 0xFF00
#define ONENAND_ECC_ERRPOS_MAIN0 0xFF01
#define ONENAND_ECC_ERRPOS_SPARE0 0xFF02
#define ONENAND_ECC_ERRPOS_MAIN1 0xFF03
#define ONENAND_ECC_ERRPOS_SPARE1 0xFF04
#define ONENAND_ECC_ERRPOS_MAIN2 0xFF05
#define ONENAND_ECC_ERRPOS_SPARE2 0xFF06
#define ONENAND_ECC_ERRPOS_MAIN3 0xFF07
#define ONENAND_ECC_ERRPOS_SPARE3 0xFF08
/* Onenand commands */
#define ONENAND_CMDLOAD 0x0000
#define ONENAND_CMDLOADSPARE 0x0013
#define ONENAND_CMDPROG 0x0080
#define ONENAND_CMDPROGSPARE 0x001A
#define ONENAND_CMDERAS 0x0094
#define ONENAND_SYSCFG1_ECCENA 0x40E0
#define ONENAND_SYSCFG1_ECCDIS 0x41E0
#define ONENAND_CLRINTR 0x0000
#define ONENAND_STARTADDR1_RES 0x07FF
#define ONENAND_STARTADDR3_RES 0x07FF
#define DEVICE_FLASHCORE_0 0
#define DEVICE_BUFFERRAM_0 0
#define DATARAM0_0 0x8
/* Flash type */
#define FLASH_UNKNOWN_DEVICE 0x00
#define FLASH_NAND_DEVICE 0x01
#define FLASH_8BIT_NAND_DEVICE 0x01
#define FLASH_16BIT_NAND_DEVICE 0x02
#define FLASH_ONENAND_DEVICE 0x03
#define EBI2_CFG_REG EBI2_REG(0x0004)
#define EBI2_NAND_ADM_MUX EBI2_REG(0x005C)
#define EBI2_CHIP_SELECT_CFG0 EBI2_REG(0x0000)
#endif /* __PLATFORM_MSM_SHARED_NAND_H */
bootable/bootloader/lk/platform/msm_shared/include/partition_parser.h
+169
View File
@@ -0,0 +1,169 @@
/* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PARTITION_PARSER_H
#define __PARTITION_PARSER_H
#include <mmc.h>
#define INVALID_PTN -1
#define PARTITION_TYPE_MBR 0
#define PARTITION_TYPE_GPT 1
#define PARTITION_TYPE_GPT_BACKUP 2
/* GPT Signature should be 0x5452415020494645 */
#define GPT_SIGNATURE_1 0x54524150
#define GPT_SIGNATURE_2 0x20494645
#define MMC_MBR_SIGNATURE_BYTE_0 0x55
#define MMC_MBR_SIGNATURE_BYTE_1 0xAA
/* GPT Offsets */
#define PROTECTIVE_MBR_SIZE BLOCK_SIZE
#define HEADER_SIZE_OFFSET 12
#define HEADER_CRC_OFFSET 16
#define PRIMARY_HEADER_OFFSET 24
#define BACKUP_HEADER_OFFSET 32
#define FIRST_USABLE_LBA_OFFSET 40
#define LAST_USABLE_LBA_OFFSET 48
#define PARTITION_ENTRIES_OFFSET 72
#define PARTITION_COUNT_OFFSET 80
#define PENTRY_SIZE_OFFSET 84
#define PARTITION_CRC_OFFSET 88
#define MIN_PARTITION_ARRAY_SIZE 0x4000
#define PARTITION_ENTRY_LAST_LBA 40
#define ENTRY_SIZE 0x080
#define UNIQUE_GUID_OFFSET 16
#define FIRST_LBA_OFFSET 32
#define LAST_LBA_OFFSET 40
#define ATTRIBUTE_FLAG_OFFSET 48
#define PARTITION_NAME_OFFSET 56
#define MAX_GPT_NAME_SIZE 72
#define PARTITION_TYPE_GUID_SIZE 16
#define UNIQUE_PARTITION_GUID_SIZE 16
#define NUM_PARTITIONS 32
/* Some useful define used to access the MBR/EBR table */
#define BLOCK_SIZE 0x200
#define TABLE_ENTRY_0 0x1BE
#define TABLE_ENTRY_1 0x1CE
#define TABLE_ENTRY_2 0x1DE
#define TABLE_ENTRY_3 0x1EE
#define TABLE_SIGNATURE 0x1FE
#define TABLE_ENTRY_SIZE 0x010
#define OFFSET_STATUS 0x00
#define OFFSET_TYPE 0x04
#define OFFSET_FIRST_SEC 0x08
#define OFFSET_SIZE 0x0C
#define COPYBUFF_SIZE (1024 * 16)
#define BINARY_IN_TABLE_SIZE (16 * 512)
#define MAX_FILE_ENTRIES 20
#define MBR_EBR_TYPE 0x05
#define MBR_MODEM_TYPE 0x06
#define MBR_MODEM_TYPE2 0x0C
#define MBR_SBL1_TYPE 0x4D
#define MBR_SBL2_TYPE 0x51
#define MBR_SBL3_TYPE 0x45
#define MBR_RPM_TYPE 0x47
#define MBR_TZ_TYPE 0x46
#define MBR_MODEM_ST1_TYPE 0x4A
#define MBR_MODEM_ST2_TYPE 0x4B
#define MBR_EFS2_TYPE 0x4E
#define MBR_ABOOT_TYPE 0x4C
#define MBR_BOOT_TYPE 0x48
#define MBR_SYSTEM_TYPE 0x82
#define MBR_USERDATA_TYPE 0x83
#define MBR_RECOVERY_TYPE 0x60
#define MBR_MISC_TYPE 0x63
#define MBR_PROTECTED_TYPE 0xEE
#define MBR_SSD_TYPE 0x5D
#define GET_LWORD_FROM_BYTE(x) ((unsigned)*(x) | \
((unsigned)*(x+1) << 8) | \
((unsigned)*(x+2) << 16) | \
((unsigned)*(x+3) << 24))
#define GET_LLWORD_FROM_BYTE(x) ((unsigned long long)*(x) | \
((unsigned long long)*(x+1) << 8) | \
((unsigned long long)*(x+2) << 16) | \
((unsigned long long)*(x+3) << 24) | \
((unsigned long long)*(x+4) << 32) | \
((unsigned long long)*(x+5) << 40) | \
((unsigned long long)*(x+6) << 48) | \
((unsigned long long)*(x+7) << 56))
#define GET_LONG(x) ((uint32_t)*(x) | \
((uint32_t)*(x+1) << 8) | \
((uint32_t)*(x+2) << 16) | \
((uint32_t)*(x+3) << 24))
#define PUT_LONG(x, y) *(x) = y & 0xff; \
*(x+1) = (y >> 8) & 0xff; \
*(x+2) = (y >> 16) & 0xff; \
*(x+3) = (y >> 24) & 0xff;
#define PUT_LONG_LONG(x,y) *(x) =(y) & 0xff; \
*((x)+1) = (((y) >> 8) & 0xff); \
*((x)+2) = (((y) >> 16) & 0xff); \
*((x)+3) = (((y) >> 24) & 0xff); \
*((x)+4) = (((y) >> 32) & 0xff); \
*((x)+5) = (((y) >> 40) & 0xff); \
*((x)+6) = (((y) >> 48) & 0xff); \
*((x)+7) = (((y) >> 56) & 0xff);
/* Unified mbr and gpt entry types */
struct partition_entry {
unsigned char type_guid[PARTITION_TYPE_GUID_SIZE];
unsigned dtype;
unsigned char unique_partition_guid[UNIQUE_PARTITION_GUID_SIZE];
unsigned long long first_lba;
unsigned long long last_lba;
unsigned long long size;
unsigned long long attribute_flag;
unsigned char name[MAX_GPT_NAME_SIZE];
};
int partition_get_index(const char *name);
unsigned long long partition_get_size(int index);
unsigned long long partition_get_offset(int index);
unsigned int partition_read_table();
unsigned int write_partition(unsigned size, unsigned char *partition);
/* For Debugging */
void partition_dump(void);
#endif
bootable/bootloader/lk/platform/msm_shared/include/qgic.h
+66
View File
@@ -0,0 +1,66 @@
/*
* Copyright (c) 2011, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLATFORM_MSM_SHARED_QGIC_H
#define __PLATFORM_MSM_SHARED_QGIC_H
#include <platform/iomap.h>
#include <platform/interrupts.h>
#define GIC_CPU_REG(off) (MSM_GIC_CPU_BASE + (off))
#define GIC_DIST_REG(off) (MSM_GIC_DIST_BASE + (off))
#define GIC_CPU_CTRL GIC_CPU_REG(0x00)
#define GIC_CPU_PRIMASK GIC_CPU_REG(0x04)
#define GIC_CPU_BINPOINT GIC_CPU_REG(0x08)
#define GIC_CPU_INTACK GIC_CPU_REG(0x0c)
#define GIC_CPU_EOI GIC_CPU_REG(0x10)
#define GIC_CPU_RUNNINGPRI GIC_CPU_REG(0x14)
#define GIC_CPU_HIGHPRI GIC_CPU_REG(0x18)
#define GIC_DIST_CTRL GIC_DIST_REG(0x000)
#define GIC_DIST_CTR GIC_DIST_REG(0x004)
#define GIC_DIST_ENABLE_SET GIC_DIST_REG(0x100)
#define GIC_DIST_ENABLE_CLEAR GIC_DIST_REG(0x180)
#define GIC_DIST_PENDING_SET GIC_DIST_REG(0x200)
#define GIC_DIST_PENDING_CLEAR GIC_DIST_REG(0x280)
#define GIC_DIST_ACTIVE_BIT GIC_DIST_REG(0x300)
#define GIC_DIST_PRI GIC_DIST_REG(0x400)
#define GIC_DIST_TARGET GIC_DIST_REG(0x800)
#define GIC_DIST_CONFIG GIC_DIST_REG(0xc00)
#define GIC_DIST_SOFTINT GIC_DIST_REG(0xf00)
struct ihandler {
int_handler func;
void *arg;
};
void qgic_init(void);
#endif
bootable/bootloader/lk/platform/msm_shared/include/qpic_nand.h
+350
View File
@@ -0,0 +1,350 @@
/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef __QPIC_NAND_H
#define __QPIC_NAND_H
#include <debug.h>
#include <dev/flash.h>
#include <platform/iomap.h>
#define NAND_REG(off) (nand_base + (off))
#define NAND_FLASH_CMD NAND_REG(0x0000)
#define NAND_ADDR0 NAND_REG(0x0004)
#define NAND_ADDR1 NAND_REG(0x0008)
#define NAND_FLASH_CHIP_SELECT NAND_REG(0x000C)
#define NAND_EXEC_CMD NAND_REG(0x0010)
#define NAND_FLASH_STATUS NAND_REG(0x0014)
#define NAND_BUFFER_STATUS NAND_REG(0x0018)
#define NAND_DEV0_CFG0 NAND_REG(0x0020)
#define NAND_DEV0_CFG1 NAND_REG(0x0024)
#define NAND_DEV0_ECC_CFG NAND_REG(0x0028)
#define NAND_DEV1_CFG0 NAND_REG(0x0030)
#define NAND_DEV1_CFG1 NAND_REG(0x0034)
#define NAND_SFLASHC_CMD NAND_REG(0x0038)
#define NAND_SFLASHC_EXEC_CMD NAND_REG(0x003C)
#define NAND_READ_ID NAND_REG(0x0040)
#define NAND_READ_STATUS NAND_REG(0x0044)
#define NAND_CONFIG_DATA NAND_REG(0x0050)
#define NAND_CONFIG NAND_REG(0x0054)
#define NAND_CONFIG_MODE NAND_REG(0x0058)
#define NAND_CONFIG_STATUS NAND_REG(0x0060)
#define NAND_MACRO1_REG NAND_REG(0x0064)
#define NAND_XFR_STEP1 NAND_REG(0x0070)
#define NAND_XFR_STEP2 NAND_REG(0x0074)
#define NAND_XFR_STEP3 NAND_REG(0x0078)
#define NAND_XFR_STEP4 NAND_REG(0x007C)
#define NAND_XFR_STEP5 NAND_REG(0x0080)
#define NAND_XFR_STEP6 NAND_REG(0x0084)
#define NAND_XFR_STEP7 NAND_REG(0x0088)
#define NAND_GENP_REG0 NAND_REG(0x0090)
#define NAND_GENP_REG1 NAND_REG(0x0094)
#define NAND_GENP_REG2 NAND_REG(0x0098)
#define NAND_GENP_REG3 NAND_REG(0x009C)
#define NAND_SFLASHC_STATUS NAND_REG(0x001C)
#define NAND_DEV_CMD0 NAND_REG(0x00A0)
#define NAND_DEV_CMD1 NAND_REG(0x00A4)
#define NAND_DEV_CMD2 NAND_REG(0x00A8)
#define NAND_DEV_CMD_VLD NAND_REG(0x00AC)
#define NAND_EBI2_MISR_SIG_REG NAND_REG(0x00B0)
#define NAND_ADDR2 NAND_REG(0x00C0)
#define NAND_ADDR3 NAND_REG(0x00C4)
#define NAND_ADDR4 NAND_REG(0x00C8)
#define NAND_ADDR5 NAND_REG(0x00CC)
#define NAND_DEV_CMD3 NAND_REG(0x00D0)
#define NAND_DEV_CMD4 NAND_REG(0x00D4)
#define NAND_DEV_CMD5 NAND_REG(0x00D8)
#define NAND_DEV_CMD6 NAND_REG(0x00DC)
#define NAND_SFLASHC_BURST_CFG NAND_REG(0x00E0)
#define NAND_ADDR6 NAND_REG(0x00E4)
#define NAND_ERASED_CW_DETECT_CFG NAND_REG(0x00E8)
#define NAND_ERASED_CW_DETECT_STATUS NAND_REG(0x00EC)
#define NAND_EBI2_ECC_BUF_CFG NAND_REG(0x00F0)
#define NAND_HW_INFO NAND_REG(0x00FC)
#define NAND_FLASH_BUFFER NAND_REG(0x0100)
/* NANDc registers used during BAM transfer */
#define NAND_READ_LOCATION_n(n) (NAND_REG(0xF20) + 4 * (n))
#define NAND_RD_LOC_LAST_BIT(x) ((x) << 31)
#define NAND_RD_LOC_SIZE(x) ((x) << 16)
#define NAND_RD_LOC_OFFSET(x) ((x) << 0)
/* Shift Values */
#define NAND_DEV0_CFG1_WIDE_BUS_SHIFT 1
#define NAND_DEV0_CFG0_DIS_STS_AFTER_WR_SHIFT 4
#define NAND_DEV0_CFG0_CW_PER_PAGE_SHIFT 6
#define NAND_DEV0_CFG0_UD_SIZE_BYTES_SHIFT 9
#define NAND_DEV0_CFG0_ADDR_CYCLE_SHIFT 27
#define NAND_DEV0_CFG0_SPARE_SZ_BYTES_SHIFT 23
#define NAND_DEV0_CFG1_RECOVERY_CYCLES_SHIFT 2
#define NAND_DEV0_CFG1_CS_ACTIVE_BSY_SHIFT 5
#define NAND_DEV0_CFG1_BAD_BLK_BYTE_NUM_SHIFT 6
#define NAND_DEV0_CFG1_BAD_BLK_IN_SPARE_SHIFT 16
#define NAND_DEV0_CFG1_WR_RD_BSY_GAP_SHIFT 17
#define NAND_DEV0_ECC_DISABLE_SHIFT 0
#define NAND_DEV0_ECC_SW_RESET_SHIFT 1
#define NAND_DEV0_ECC_MODE_SHIFT 4
#define NAND_DEV0_ECC_DISABLE_SHIFT 0
#define NAND_DEV0_ECC_PARITY_SZ_BYTES_SHIFT 8
#define NAND_DEV0_ECC_NUM_DATA_BYTES 16
#define NAND_DEV0_ECC_FORCE_CLK_OPEN_SHIFT 30
#define NAND_ERASED_CW_DETECT_STATUS_PAGE_ALL_ERASED 7
#define NAND_ERASED_CW_DETECT_STATUS_CODEWORD_ALL_ERASED 6
#define NAND_ERASED_CW_DETECT_STATUS_CODEWORD_ERASED 4
#define NAND_ERASED_CW_DETECT_CFG_RESET_CTRL 1
#define NAND_ERASED_CW_DETECT_CFG_ACTIVATE_CTRL 0
#define NAND_ERASED_CW_DETECT_ERASED_CW_ECC_MASK (1 << 1)
#define NAND_ERASED_CW_DETECT_ERASED_CW_ECC_NO_MASK (0 << 1)
/* device commands */
#define NAND_CMD_SOFT_RESET 0x01
#define NAND_CMD_PAGE_READ 0x32
#define NAND_CMD_PAGE_READ_ECC 0x33
#define NAND_CMD_PAGE_READ_ALL 0x34
#define NAND_CMD_SEQ_PAGE_READ 0x15
#define NAND_CMD_PRG_PAGE 0x36
#define NAND_CMD_PRG_PAGE_ECC 0x37
#define NAND_CMD_PRG_PAGE_ALL 0x39
#define NAND_CMD_BLOCK_ERASE 0x3A
#define NAND_CMD_FETCH_ID 0x0B
#define NAND_CMD_STATUS 0x0C
#define NAND_CMD_RESET 0x0D
/* NAND Status errors */
#define NAND_FLASH_MPU_ERR (1 << 8)
#define NAND_FLASH_TIMEOUT_ERR (1 << 6)
#define NAND_FLASH_OP_ERR (1 << 4)
#define NAND_FLASH_ERR (NAND_FLASH_MPU_ERR | \
NAND_FLASH_TIMEOUT_ERR | \
NAND_FLASH_OP_ERR)
#define PROG_ERASE_OP_RESULT (1 << 7)
#define DATA_CONSUMER_PIPE_INDEX 0
#define DATA_PRODUCER_PIPE_INDEX 1
#define CMD_PIPE_INDEX 2
/* Define BAM pipe lock groups for NANDc*/
#define P_LOCK_GROUP_0 0
/* Define BAM pipe lock super groups for NANDc
* Note: This is configured by TZ.
*/
#define P_LOCK_SUPERGROUP_0 0
#define P_LOCK_SUPERGROUP_1 1
#define ONFI_SIGNATURE 0x49464E4F
#define ONFI_CRC_POLYNOMIAL 0x8005
#define ONFI_CRC_INIT_VALUE 0x4F4E
#define ONFI_READ_PARAM_PAGE_ADDR_CYCLES 1
#define ONFI_READ_ID_ADDR_CYCLES 1
#define ONFI_READ_ID_CMD 0x90
#define ONFI_READ_PARAM_PAGE_CMD 0xEC
#define ONFI_READ_ID_ADDR 0x20
#define ONFI_READ_PARAM_PAGE_ADDR 0x00
#define NAND_CFG0_RAW_ONFI_ID 0x88000800
#define NAND_CFG0_RAW_ONFI_PARAM_PAGE 0x88040000
#define NAND_CFG1_RAW_ONFI_ID 0x0005045D
#define NAND_CFG1_RAW_ONFI_PARAM_PAGE 0x0005045D
#define NAND_CFG0 0x290409c0
#define NAND_CFG1 0x08045d5c
#define NAND_ECC_BCH_CFG 0x42040d10
#define NAND_Bad_Block 0x00000175
#define NAND_ECC_BUF_CFG 0x00000203
#define ONFI_READ_ID_BUFFER_SIZE 0x4
#define ONFI_READ_PARAM_PAGE_BUFFER_SIZE 0x200
#define ONFI_PARAM_PAGE_SIZE 0x100
#define NAND_8BIT_DEVICE 0x01
#define NAND_16BIT_DEVICE 0x02
#define NAND_CW_SIZE_4_BIT_ECC 528
#define NAND_CW_SIZE_8_BIT_ECC 532
/* Indicates the data bytes in the user data portion of the code word. */
#define USER_DATA_BYTES_PER_CW 512
/* Indicates the number of bytes covered by BCH ECC logic when
* a codeword is written to a NAND flash device.
* This is also the number of bytes that are part of the image in CW.
* 516 bytes = (512 bytes of user data and 4 bytes of spare data)
*/
#define DATA_BYTES_IN_IMG_PER_CW 516
#define NAND_CW_DIV_RIGHT_SHIFT 9
/* Number of max cw's the driver allows to flash. */
#define QPIC_NAND_MAX_CWS_IN_PAGE 10
/* Reset Values for Status registers */
#define NAND_FLASH_STATUS_RESET 0x00000020
#define NAND_READ_STATUS_RESET 0x000000C0
/* result type */
typedef enum {
NANDC_RESULT_SUCCESS = 0,
NANDC_RESULT_FAILURE = 1,
NANDC_RESULT_TIMEOUT = 2,
NANDC_RESULT_PARAM_INVALID = 3,
NANDC_RESULT_DEV_NOT_SUPPORTED = 4,
NANDC_RESULT_BAD_PAGE = 5,
NANDC_RESULT_BAD_BLOCK = 6,
} nand_result_t;
enum nand_bad_block_value
{
NAND_BAD_BLK_VALUE_NOT_READ,
NAND_BAD_BLK_VALUE_IS_BAD,
NAND_BAD_BLK_VALUE_IS_GOOD,
};
enum nand_cfg_value
{
NAND_CFG_RAW,
NAND_CFG,
};
struct onfi_param_page
{
uint32_t signature;
uint16_t rev;
uint16_t feature_supported;
uint16_t opt_cmd_supported;
uint8_t reserved_1[22];
uint8_t mib[12];
uint8_t device_model[20];
uint8_t manufacturer_id;
uint16_t date_code;
uint8_t reserved_2[13];
uint32_t data_per_pg;
uint16_t spare_per_pg;
uint32_t data_per_partial_pg;
uint16_t spare_per_partial_pg;
uint32_t pgs_per_blk;
uint32_t blks_per_LUN;
uint8_t num_LUN;
uint8_t num_addr_cycles;
uint8_t num_bits_per_cell;
uint16_t bad_blks_max_per_LUN;
uint16_t blk_endurance;
uint8_t guaranteed_vld_blks_at_start;
uint16_t blk_endurance_for_garunteed_vld_blks;
uint8_t num_prg_per_pg;
uint8_t partial_prog_attr;
uint8_t num_bits_ecc_correctability;
uint8_t num_interleaved_addr_bits;
uint8_t interleaved_op_attr;
uint8_t reserved_3[13];
uint8_t io_pin_capcacitance;
uint16_t timing_mode_support;
uint16_t prog_cache_timing_mode_support;
uint16_t max_pg_prog_time_us;
uint16_t max_blk_erase_time_us;
uint16_t max_pr_rd_time_us;
uint16_t min_chg_col_setup_time_us;
uint8_t reserved_4[23];
uint16_t vendor_rev;
uint8_t vendor_specific[88];
uint16_t interity_crc;
}__PACKED;
struct cfg_params
{
uint32_t addr0;
uint32_t addr1;
uint32_t cfg0;
uint32_t cfg1;
uint32_t cmd;
uint32_t ecc_cfg;
uint32_t addr_loc_0;
uint32_t exec;
};
struct onfi_probe_params
{
uint32_t vld;
uint32_t dev_cmd1;
struct cfg_params cfg;
};
/* This stucture is used to create a static list of devices we support.
* This include a subset of values defined in the flash_info struct as
* other values can be derived.
*/
struct flash_id
{
unsigned flash_id;
unsigned mask;
unsigned density;
unsigned widebus;
unsigned pagesize;
unsigned blksize;
unsigned oobsize;
unsigned ecc_8_bits;
};
/* Structure to hold the pipe numbers */
struct qpic_nand_bam_pipes
{
unsigned read_pipe;
unsigned write_pipe;
unsigned cmd_pipe;
uint8_t read_pipe_grp;
uint8_t write_pipe_grp;
uint8_t cmd_pipe_grp;
};
/* Structure to define the initial nand config */
struct qpic_nand_init_config
{
uint32_t nand_base;
uint32_t bam_base;
uint32_t ee;
uint32_t max_desc_len;
struct qpic_nand_bam_pipes pipes;
};
void
qpic_nand_init(struct qpic_nand_init_config *config);
unsigned
flash_block_size(void);
void
qpic_nand_uninit();
#endif
bootable/bootloader/lk/platform/msm_shared/include/qtimer.h
+46
View File
@@ -0,0 +1,46 @@
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/types.h>
#include <platform/timer.h>
#define QTMR_TIMER_CTRL_ENABLE (1 << 0)
#define QTMR_TIMER_CTRL_INT_MASK (1 << 1)
#define QTMR_PHY_CNT_MAX_VALUE 0xFFFFFFFFFFFFFF
void qtimer_set_physical_timer(time_t msecs_interval,
platform_timer_callback tmr_callback, void *tmr_arg);
void qtimer_disable();
uint64_t qtimer_get_phy_timer_cnt();
uint32_t qtimer_current_time();
uint32_t qtimer_get_frequency();
void qtimer_uninit();
void qtimer_init();
uint32_t qtimer_tick_rate();
bootable/bootloader/lk/platform/msm_shared/include/qtimer_mmap_hw.h
+43
View File
@@ -0,0 +1,43 @@
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLATFORM_MSM_SHARED_QTMR_MMAP_H
#define __PLATFORM_MSM_SHARED_QRMR_MMAP_H
#include <platform/iomap.h>
#define QTMR_V1_CNTPCT_LO (0x00000000 + QTMR_BASE)
#define QTMR_V1_CNTPCT_HI (0x00000004 + QTMR_BASE)
#define QTMR_V1_CNTFRQ (0x00000010 + QTMR_BASE)
#define QTMR_V1_CNTP_CVAL_LO (0x00000020 + QTMR_BASE)
#define QTMR_V1_CNTP_CVAL_HI (0x00000024 + QTMR_BASE)
#define QTMR_V1_CNTP_TVAL (0x00000028 + QTMR_BASE)
#define QTMR_V1_CNTP_CTL (0x0000002C + QTMR_BASE)
#endif
bootable/bootloader/lk/platform/msm_shared/include/scm.h
+236
View File
@@ -0,0 +1,236 @@
/* Copyright (c) 2011-2013, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SCM_H__
#define __SCM_H__
/* 8 Byte SSD magic number (LE) */
#define DECRYPT_MAGIC_0 0x73737A74
#define DECRYPT_MAGIC_1 0x676D6964
#define ENCRYPT_MAGIC_0 0x6B647373
#define ENCRYPT_MAGIC_1 0x676D6973
#define SSD_HEADER_MAGIC_SIZE 8
#define SSD_HEADER_XML_SIZE 2048
#define SSD_HEADER_MIN_SIZE 128
#define MULTIPLICATION_FACTOR 2
typedef unsigned int uint32;
typedef struct {
uint32 len;
uint32 buf_offset;
uint32 resp_hdr_offset;
uint32 id;
} scm_command;
typedef struct {
uint32 len;
uint32 buf_offset;
uint32 is_complete;
} scm_response;
typedef struct {
uint32 *img_ptr;
uint32 *img_len_ptr;
} img_req;
typedef struct {
uint32 id;
uint32 spare;
} tz_secure_cfg;
typedef struct {
uint32 md_len;
uint32* md;
} ssd_parse_md_req;
typedef struct {
uint32 status;
uint32 md_ctx_id;
uint32* md_end_ptr;
} ssd_parse_md_rsp;
typedef struct {
uint32 md_ctx_id;
uint32 last_frag;
uint32 frag_len;
uint32 *frag;
} ssd_decrypt_img_frag_req;
typedef struct {
uint32 status;
} ssd_decrypt_img_frag_rsp;
typedef struct{
uint32 feature_id;
} feature_version_req;
typedef struct{
uint32 version;
} feature_version_rsp;
typedef struct{
uint32 *keystore_ptr;
uint32 keystore_len;
} ssd_protect_keystore_req;
typedef struct{
uint32 status;
} ssd_protect_keystore_rsp;
/* Service IDs */
#define TZBSP_SVC_INFO 0x06
#define SCM_SVC_SSD 0x07
#define SVC_MEMORY_PROTECTION 0x0C
/*Service specific command IDs */
#define SSD_DECRYPT_ID 0x01
#define SSD_ENCRYPT_ID 0x02
#define SSD_PROTECT_KEYSTORE_ID 0x05
#define SSD_PARSE_MD_ID 0x06
#define SSD_DECRYPT_IMG_FRAG_ID 0x07
#define SECURE_DEVICE_MDSS 0x01
#define IOMMU_SECURE_CFG 0x02
#define TZ_INFO_GET_FEATURE_ID 0x03
/* SSD parsing status messages from TZ */
#define SSD_PMD_ENCRYPTED 0
#define SSD_PMD_NOT_ENCRYPTED 1
#define SSD_PMD_NO_MD_FOUND 3
#define SSD_PMD_BUSY 4
#define SSD_PMD_BAD_MD_PTR_OR_LEN 5
#define SSD_PMD_PARSING_INCOMPLETE 6
#define SSD_PMD_PARSING_FAILED 7
#define SSD_PMD_SETUP_CIPHER_FAILED 8
/* Keystore status messages */
#define TZBSP_SSD_PKS_SUCCESS 0 /**< Successful return. */
#define TZBSP_SSD_PKS_INVALID_PTR 1 /**< Keystore pointer invalid. */
#define TZBSP_SSD_PKS_INVALID_LEN 2 /**< Keystore length incorrect. */
#define TZBSP_SSD_PKS_UNALIGNED_PTR 3 /**< Keystore pointer not word
aligned. */
#define TZBSP_SSD_PKS_PROTECT_MEM_FAILED 4 /**< Failure when protecting
the keystore memory.*/
#define TZBSP_SSD_PKS_INVALID_NUM_KEYS 5 /**< Unsupported number of
keys passed. If a valid
pointer to non-secure
memory is passed that
isn't a keystore, this is
a likely return code. */
#define TZBSP_SSD_PKS_DECRYPT_FAILED 6 /**< The keystore could not be
decrypted. */
/* Features in TZ */
#define TZBSP_FVER_SSD 5
#define TZBSP_GET_FEATURE_VERSION(major) ((major >> 22)& 0x3FF)
static uint32 smc(uint32 cmd_addr);
int decrypt_scm(uint32_t ** img_ptr, uint32_t * img_len_ptr);
int decrypt_scm_v2(uint32_t ** img_ptr, uint32_t * img_len_ptr);
int encrypt_scm(uint32_t ** img_ptr, uint32_t * img_len_ptr);
int scm_svc_version(uint32 * major, uint32 * minor);
int scm_protect_keystore(uint32_t * img_ptr, uint32_t img_len);
#define SCM_SVC_FUSE 0x08
#define SCM_BLOW_SW_FUSE_ID 0x01
#define SCM_IS_SW_FUSE_BLOWN_ID 0x02
#define HLOS_IMG_TAMPER_FUSE 0
#define SCM_SVC_CE_CHN_SWITCH_ID 0x04
#define SCM_CE_CHN_SWITCH_ID 0x02
#define SCM_SVC_ES 0x10
#define SCM_SAVE_PARTITION_HASH_ID 0x01
enum ap_ce_channel_type {
AP_CE_REGISTER_USE = 0,
AP_CE_ADM_USE = 1
};
/* Apps CE resource. */
#define TZ_RESOURCE_CE_AP 2
uint8_t switch_ce_chn_cmd(enum ap_ce_channel_type channel);
void set_tamper_fuse_cmd();
/**
* struct scm_command - one SCM command buffer
* @len: total available memory for command and response
* @buf_offset: start of command buffer
* @resp_hdr_offset: start of response buffer
* @id: command to be executed
* @buf: buffer returned from scm_get_command_buffer()
*
* An SCM command is layed out in memory as follows:
*
* ------------------- <--- struct scm_command
* | command header |
* ------------------- <--- scm_get_command_buffer()
* | command buffer |
* ------------------- <--- struct scm_response and
* | response header | scm_command_to_response()
* ------------------- <--- scm_get_response_buffer()
* | response buffer |
* -------------------
*
* There can be arbitrary padding between the headers and buffers so
* you should always use the appropriate scm_get_*_buffer() routines
* to access the buffers in a safe manner.
*/
struct scm_command {
uint32_t len;
uint32_t buf_offset;
uint32_t resp_hdr_offset;
uint32_t id;
uint32_t buf[0];
};
/**
* struct scm_response - one SCM response buffer
* @len: total available memory for response
* @buf_offset: start of response data relative to start of scm_response
* @is_complete: indicates if the command has finished processing
*/
struct scm_response {
uint32_t len;
uint32_t buf_offset;
uint32_t is_complete;
};
#endif
bootable/bootloader/lk/platform/msm_shared/include/sdhci.h
+341
View File
@@ -0,0 +1,341 @@
/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLATFORM_SDHCI_H_
#define __PLATFORM_SDHCI_H_
#include <reg.h>
#include <bits.h>
/*
* Capabilities for the host controller
* These values are read from the capabilities
* register in the controller
*/
struct host_caps {
uint32_t base_clk_rate; /* Max clock rate supported */
uint32_t max_blk_len; /* Max block len supported */
uint8_t bus_width_8bit; /* 8 Bit mode supported */
uint8_t adma_support; /* Adma support */
uint8_t voltage; /* Supported voltage */
uint8_t sdr_support; /* Single Data rate */
uint8_t ddr_support; /* Dual Data rate */
uint8_t sdr50_support; /* UHS mode, with 100 MHZ clock */
};
/*
* sdhci host structure, holding information about host
* controller parameters
*/
struct sdhci_host {
uint32_t base; /* Base address for the host */
uint32_t cur_clk_rate; /* Running clock rate */
struct host_caps caps; /* Host capabilities */
};
/*
* Data pointer to be read/written
*/
struct mmc_data {
void *data_ptr; /* Points to stream of data */
uint32_t blk_sz; /* Block size for the data */
uint32_t num_blocks; /* num of blocks, each always of size SDHCI_MMC_BLK_SZ */
};
/*
* mmc command structure as per the spec
*/
struct mmc_command {
uint16_t cmd_index; /* Command index */
uint32_t argument; /* Command argument */
uint8_t data_present; /* Command has data */
uint8_t cmd_type; /* command type */
uint16_t resp_type; /* Response type of the command */
uint32_t resp[4]; /* 128 bit response value */
uint32_t trans_mode; /* Transfer mode, read/write */
uint32_t cmd_retry; /* Retry the command, if card is busy */
struct mmc_data data; /* Data pointer */
};
/*
* Descriptor table for adma
*/
struct desc_entry {
uint16_t tran_att; /* Attribute for transfer data */
uint16_t len; /* Length of data */
void *addr; /* Address of the data */
};
/*
* Command types for sdhci
*/
enum {
SDHCI_CMD_TYPE_NORMAL = 0,
SDHCI_CMD_TYPE_SUSPEND,
SDHCI_CMD_TYPE_RESUME,
SDHCI_CMD_TYPE_ABORT,
} sdhci_cmd_type;
/*
* Response type values for sdhci
*/
enum {
SDHCI_CMD_RESP_NONE = 0,
SDHCI_CMD_RESP_136,
SDHCI_CMD_RESP_48,
SDHCI_CMD_RESP_48_BUSY,
} sdhci_resp_type;
/*
* Helper macros for writing byte, word & long registers
*/
#define REG_READ8(host, a) readb(host->base + a);
#define REG_WRITE8(host, v, a) writeb(v, (host->base + a))
#define REG_READ32(host, a) readl(host->base + a)
#define REG_WRITE32(host, v, a) writel(v, (host->base + a))
#define REG_READ16(host, a) readhw(host->base + a)
#define REG_WRITE16(host, v, a) writehw(v, (host->base + a))
/*
* SDHCI registers, as per the host controller spec v 3.0
*/
#define SDHCI_ARG2_REG (0x000)
#define SDHCI_BLKSZ_REG (0x004)
#define SDHCI_BLK_CNT_REG (0x006)
#define SDHCI_ARGUMENT_REG (0x008)
#define SDHCI_TRANS_MODE_REG (0x00C)
#define SDHCI_CMD_REG (0x00E)
#define SDHCI_RESP_REG (0x010)
#define SDHCI_PRESENT_STATE_REG (0x024)
#define SDHCI_HOST_CTRL1_REG (0x028)
#define SDHCI_PWR_CTRL_REG (0x029)
#define SDHCI_CLK_CTRL_REG (0x02C)
#define SDHCI_TIMEOUT_REG (0x02E)
#define SDHCI_RESET_REG (0x02F)
#define SDHCI_NRML_INT_STS_REG (0x030)
#define SDHCI_ERR_INT_STS_REG (0x032)
#define SDHCI_NRML_INT_STS_EN_REG (0x034)
#define SDHCI_ERR_INT_STS_EN_REG (0x036)
#define SDHCI_NRML_INT_SIG_EN_REG (0x038)
#define SDHCI_ERR_INT_SIG_EN_REG (0x03A)
#define SDHCI_HOST_CTRL2_REG (0x03E)
#define SDHCI_CAPS_REG1 (0x040)
#define SDHCI_CAPS_REG2 (0x044)
#define SDHCI_ADM_ADDR_REG (0x058)
/*
* Helper macros for register writes
*/
#define SDHCI_SOFT_RESET BIT(0)
#define SOFT_RESET_CMD BIT(1)
#define SOFT_RESET_DATA BIT(2)
#define SDHCI_1_8_VOL_SET BIT(3)
/*
* Interrupt related
*/
#define SDHCI_NRML_INT_STS_EN 0x000B
#define SDHCI_ERR_INT_STS_EN 0xFFFF
#define SDHCI_NRML_INT_SIG_EN 0x000B
#define SDHCI_ERR_INT_SIG_EN 0xFFFF
#define SDCC_HC_INT_CARD_REMOVE BIT(7)
#define SDCC_HC_INT_CARD_INSERT BIT(6)
/*
* HC mode enable/disable
*/
#define SDHCI_HC_MODE_EN BIT(0)
#define SDHCI_HC_MODE_DIS (0 << 1)
/*
* Clk control related
*/
#define SDHCI_CLK_MAX_DIV 2046
#define SDHCI_SDCLK_FREQ_SEL 8
#define SDHCI_SDCLK_UP_BIT_SEL 6
#define SDHCI_SDCLK_FREQ_MASK 0xFF
#define SDHC_SDCLK_UP_BIT_MASK 0x300
#define SDHCI_INT_CLK_EN BIT(0)
#define SDHCI_CLK_STABLE_MASK BIT(1)
#define SDHCI_CLK_STABLE BIT(1)
#define SDHCI_CLK_EN BIT(2)
#define SDHCI_CLK_DIS (0 << 2)
#define SDHCI_CLK_RATE_MASK 0x0000FF00
#define SDHCI_CLK_RATE_BIT 8
#define SDHCI_CMD_ACT BIT(0)
#define SDHCI_DAT_ACT BIT(1)
/*
* Bus voltage related macros
*/
#define SDHCI_BUS_VOL_SEL 1
#define SDHCI_BUS_PWR_EN BIT(0)
#define SDHCI_VOL_1_8 5
#define SDHCI_VOL_3_0 6
#define SDHCI_VOL_3_3 7
#define SDHCI_3_3_VOL_MASK 0x01000000
#define SDHCI_3_0_VOL_MASK 0x02000000
#define SDHCI_1_8_VOL_MASK 0x04000000
/*
* Bus width related macros
*/
#define SDHCI_8BIT_WIDTH_MASK 0x00040000
#define SDHCI_BUS_WITDH_1BIT (0)
#define SDHCI_BUS_WITDH_4BIT BIT(1)
#define SDHCI_BUS_WITDH_8BIT BIT(5)
/*
* Adma related macros
*/
#define SDHCI_BLK_LEN_MASK 0x00030000
#define SDHCI_BLK_LEN_BIT 16
#define SDHCI_BLK_ADMA_MASK 0x00080000
#define SDHCI_INT_STS_TRANS_COMPLETE BIT(1)
#define SDHCI_STATE_CMD_DAT_MASK 0x0003
#define SDHCI_INT_STS_CMD_COMPLETE BIT(0)
#define SDHCI_ERR_INT_STAT_MASK 0x8000
#define SDHCI_ADMA_DESC_LINE_SZ 65536
#define SDHCI_ADMA_MAX_TRANS_SZ (65535 * 512)
#define SDHCI_ADMA_TRANS_VALID BIT(0)
#define SDHCI_ADMA_TRANS_END BIT(1)
#define SDHCI_ADMA_TRANS_DATA BIT(5)
#define SDHCI_MMC_BLK_SZ 512
#define SDHCI_MMC_CUR_BLK_CNT_BIT 16
#define SDHCI_MMC_BLK_SZ_BIT 0
#define SDHCI_TRANS_MULTI BIT(5)
#define SDHCI_TRANS_SINGLE (0 << 5)
#define SDHCI_BLK_CNT_EN BIT(1)
#define SDHCI_DMA_EN BIT(0)
#define SDHCI_AUTO_CMD23_EN BIT(3)
#define SDHCI_ADMA_32BIT BIT(4)
/*
* Command related macros
*/
#define SDHCI_CMD_RESP_TYPE_SEL_BIT 0
#define SDHCI_CMD_CRC_CHECK_BIT 3
#define SDHCI_CMD_IDX_CHECK_BIT 4
#define SDHCI_CMD_DATA_PRESENT_BIT 5
#define SDHCI_CMD_CMD_TYPE_BIT 6
#define SDHCI_CMD_CMD_IDX_BIT 8
#define SDHCI_CMD_TIMEOUT_MASK BIT(0)
#define SDHCI_CMD_CRC_MASK BIT(1)
#define SDHCI_CMD_END_BIT_MASK BIT(2)
#define SDHCI_CMD_IDX_MASK BIT(3)
#define SDHCI_DAT_TIMEOUT_MASK BIT(4)
#define SDHCI_DAT_CRC_MASK BIT(5)
#define SDHCI_DAT_END_BIT_MASK BIT(6)
#define SDHCI_CUR_LIM_MASK BIT(7)
#define SDHCI_AUTO_CMD12_MASK BIT(8)
#define SDHCI_ADMA_MASK BIT(9)
#define SDHCI_READ_MODE BIT(4)
#define SDHCI_SWITCH_CMD 6
#define SDHCI_CMD_TIMEOUT 0xE
#define SDHCI_MAX_CMD_RETRY 10000
#define SDHCI_MAX_TRANS_RETRY 100000
#define SDHCI_PREP_CMD(c, f) ((((c) & 0xff) << 8) | ((f) & 0xff))
/*
* command response related
*/
#define SDHCI_RESP_LSHIFT 8
#define SDHCI_RESP_RSHIFT 24
/*
* Power control relatd macros
*/
#define SDHCI_SOFT_RESET_MASK (BIT(0) | BIT(1) | BIT(2))
#define SDCC_HC_PWR_CTRL_INT 0xF
#define SDCC_HC_BUS_ON BIT(0)
#define SDCC_HC_BUS_OFF BIT(1)
#define SDCC_HC_BUS_ON_OFF_SUCC BIT(0)
#define SDCC_HC_IO_SIG_LOW BIT(2)
#define SDCC_HC_IO_SIG_HIGH BIT(3)
#define SDCC_HC_IO_SIG_SUCC BIT(2)
/*
* Command response
*/
#define SDHCI_CMD_RESP_NONE 0
#define SDHCI_CMD_RESP_R1 BIT(0)
#define SDHCI_CMD_RESP_R1B BIT(1)
#define SDHCI_CMD_RESP_R2 BIT(2)
#define SDHCI_CMD_RESP_R3 BIT(3)
#define SDHCI_CMD_RESP_R6 BIT(6)
#define SDHCI_CMD_RESP_R7 BIT(7)
/*
* Clock Divider values
*/
#define SDHCI_CLK_400KHZ 400000
#define SDHCI_CLK_25MHZ 25000000
#define SDHCI_CLK_50MHZ 50000000
#define SDHCI_CLK_100MHZ 100000000
#define SDHCI_CLK_200MHZ 200000000
/* DDR mode related macros */
#define SDHCI_DDR_MODE_EN 0x0004
#define SDHCI_DDR_MODE_MASK BIT(2)
/* HS200/SDR50 mode related macros */
#define SDHCI_SDR50_MODE_MASK BIT(0)
#define SDHCI_SDR50_MODE_EN 0x0002
/*
* APIs and macros exposed for mmc/sd drivers
*/
#define SDHCI_MMC_WRITE 0
#define SDHCI_MMC_READ 1
#define DATA_BUS_WIDTH_1BIT 0
#define DATA_BUS_WIDTH_4BIT 1
#define DATA_BUS_WIDTH_8BIT 2
#define DATA_DDR_BUS_WIDTH_4BIT 5
#define DATA_DDR_BUS_WIDTH_8BIT 6
/* API: to initialize the controller */
void sdhci_init(struct sdhci_host *);
/* API: Send the command & transfer data using adma */
uint32_t sdhci_send_command(struct sdhci_host *, struct mmc_command *);
/* API: Set the bus width for the contoller */
uint8_t sdhci_set_bus_width(struct sdhci_host *, uint16_t);
/* API: Clock supply for the controller */
uint32_t sdhci_clk_supply(struct sdhci_host *, uint32_t);
/* API: Enable DDR mode */
void sdhci_set_ddr_mode(struct sdhci_host *);
/* API: To enable SDR mode */
void sdhci_set_sdr_mode(struct sdhci_host *);
#endif
bootable/bootloader/lk/platform/msm_shared/include/splash.h
+8808
View File
File diff suppressed because it is too large Load Diff
bootable/bootloader/lk/platform/msm_shared/include/splash.h.README
+3
View File
@@ -0,0 +1,3 @@
Splash image credit: http://www.isc.tamu.edu/~lewing/linux/
Permission to use and/or modify this image is granted provided you acknowledge me lewing@isc.tamu.edu and The GIMP if someone asks.
bootable/bootloader/lk/platform/msm_shared/include/spmi.h
+140
View File
@@ -0,0 +1,140 @@
/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SPMI_H
#define __SPMI_H
#define SPMI_MSM8974_MASTER_ID 0
#define SPMI_GENI_REG(x) (SPMI_GENI_BASE + (x))
#define SPMI_GENI_CFG_REG_BASE SPMI_GENI_REG(0x100)
#define SPMI_GENI_CFG_RAM_BASE SPMI_GENI_REG(0x200)
#define SPMI_GENI_CFG_REGn(x) (SPMI_GENI_CFG_REG_BASE + 4 * (x))
#define SPMI_GENI_CFG_RAM_REGn(x) (SPMI_GENI_CFG_RAM_BASE + 4 * (x))
#define SPMI_GENI_CLK_CTRL_REG SPMI_GENI_REG(0x00)
#define SPMI_GENI_OUTPUT_CTRL_REG SPMI_GENI_REG(0x10)
#define SPMI_GENI_FORCE_DEFAULT_REG SPMI_GENI_REG(0x0C)
#define SPMI_MID_REG SPMI_GENI_REG(0xF00)
#define SPMI_CFG_REG SPMI_GENI_REG(0xF04)
#define SPMI_SEC_DISABLE_REG SPMI_GENI_REG(0xF08)
#define SPMI_GENI_IRQ_ENABLE (SPMI_GENI_BASE + 0x24)
#define SPMI_GENI_IRQ_CLEAR (SPMI_GENI_BASE + 0x28)
#define SPMI_GENI_TX_FIFO_BASE (SPMI_GENI_BASE + 0x40)
#define SPMI_GENI_RX_FIFO_BASE (SPMI_GENI_BASE + 0x80)
#define SPMI_GENI_TX_FIFOn(x) (SPMI_GENI_TX_FIFO_BASE + 4 * (x))
#define SPMI_GENI_RX_FIFOn(x) (SPMI_GENI_RX_FIFO_BASE + 4 * (x))
#define PMIC_ARB_CHNLn_CMD0(x) (SPMI_BASE + 0xF800 + (x) * 0x80)
#define PMIC_ARB_CMD_OPCODE_SHIFT 27
#define PMIC_ARB_CMD_PRIORITY_SHIFT 26
#define PMIC_ARB_CMD_SLAVE_ID_SHIFT 20
#define PMIC_ARB_CMD_ADDR_SHIFT 12
#define PMIC_ARB_CMD_ADDR_OFFSET_SHIFT 4
#define PMIC_ARB_CMD_BYTE_CNT_SHIFT 0
#define PMIC_ARB_CHNLn_CONFIG(x) (SPMI_BASE + 0xF804 + (x) * 0x80)
#define PMIC_ARB_CHNLn_STATUS(x) (SPMI_BASE + 0xF808 + (x) * 0x80)
#define PMIC_ARB_CHNLn_WDATA(x, n) (SPMI_BASE + 0xF810 + \
(x) * 0x80 + (n) * 4)
#define PMIC_ARB_CHNLn_RDATA(x,n) (SPMI_BASE + 0xF818 + \
(x) * 0x80 + (n) * 4)
/* PIC Registers */
#define SPMI_PIC_OWNERm_ACC_STATUSn(m, n) (SPMI_PIC_BASE + 32 * (m) + 4 * (n))
#define SPMI_PIC_ACC_ENABLEn(n) (SPMI_PIC_BASE + 0x200 + 4 * (n))
#define SPMI_PIC_IRQ_STATUSn(n) (SPMI_PIC_BASE + 0x600 + 0x4 * (n))
#define SPMI_PIC_IRQ_CLEARn(n) (SPMI_PIC_BASE + 0xA00 + 0x4 * (n))
/* SPMI Commands */
#define SPMI_CMD_EXT_REG_WRTIE_LONG 0x00
#define SPMI_CMD_EXT_REG_READ_LONG 0x01
#define SPMI_CMD_EXT_REG_READ_LONG_DELAYED 0x02
#define SPMI_CMD_TRANSFER_BUS_OWNERSHIP 0x03
/* The commands below are not yet supported */
#define SPMI_CMD_RESET 0x04
#define SPMI_CMD_SLEEP 0x05
#define SPMI_CMD_SHUTDOWN 0x06
#define SPMI_CMD_WAKEUP 0x07
#define SPMI_CMD_EXT_REG_WRITE 0x08
#define SPMI_CMD_EXT_REG_READ 0x09
#define SPMI_CMD_REG_WRITE 0x0A
#define SPMI_CMD_REG_READ 0x0B
#define SPMI_CMD_REG_0_WRITE 0x0C
#define SPMI_CMD_AUTH 0x0D
#define SPMI_CMD_MASTER_WRITE 0x0E
#define SPMI_CMD_MASTER_READ 0x0F
#define SPMI_CMD_DEV_DESC_BLK_MASTER_READ 0x10
#define SPMI_CMD_DEV_DESC_BLK_SLAVE_READ 0x11
enum spmi_geni_cmd_return_value{
SPMI_CMD_DONE,
SMPI_CMD_DENIED,
SPMI_CMD_FAILURE,
SPMI_ILLEGAL_CMD,
SPMI_CMD_OVERRUN = 6,
SPMI_TX_FIFO_RD_ERR,
SPMI_TX_FIFO_WR_ERR,
SPMI_RX_FIFO_RD_ERR,
SPMI_RX_FIFO_WR_ERR
};
enum pmic_arb_chnl_return_values{
PMIC_ARB_CMD_DONE,
PMIC_ARB_CMD_FAILURE,
PMIC_ARB_CMD_DENIED,
PMIC_ARB_CMD_DROPPED,
};
struct pmic_arb_cmd{
uint8_t opcode;
uint8_t priority;
uint8_t slave_id;
uint8_t address;
uint8_t offset;
uint8_t byte_cnt;
};
struct pmic_arb_param{
uint8_t *buffer;
uint8_t size;
};
typedef void (*spmi_callback)();
void spmi_init(uint32_t, uint32_t);
unsigned int pmic_arb_write_cmd(struct pmic_arb_cmd *cmd,
struct pmic_arb_param *param);
unsigned int pmic_arb_read_cmd(struct pmic_arb_cmd *cmd,
struct pmic_arb_param *param);
#endif
bootable/bootloader/lk/platform/msm_shared/include/uart_dm.h
+269
View File
@@ -0,0 +1,269 @@
/* Copyright (c) 2010, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __UART_DM_H__
#define __UART_DM_H__
#include <platform/iomap.h>
#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \
((value << (32 - end_pos))\
>> (32 - (end_pos - start_pos)))
/* UART Parity Mode */
enum MSM_BOOT_UART_DM_PARITY_MODE {
MSM_BOOT_UART_DM_NO_PARITY,
MSM_BOOT_UART_DM_ODD_PARITY,
MSM_BOOT_UART_DM_EVEN_PARITY,
MSM_BOOT_UART_DM_SPACE_PARITY
};
/* UART Stop Bit Length */
enum MSM_BOOT_UART_DM_STOP_BIT_LEN {
MSM_BOOT_UART_DM_SBL_9_16,
MSM_BOOT_UART_DM_SBL_1,
MSM_BOOT_UART_DM_SBL_1_9_16,
MSM_BOOT_UART_DM_SBL_2
};
/* UART Bits per Char */
enum MSM_BOOT_UART_DM_BITS_PER_CHAR {
MSM_BOOT_UART_DM_5_BPS,
MSM_BOOT_UART_DM_6_BPS,
MSM_BOOT_UART_DM_7_BPS,
MSM_BOOT_UART_DM_8_BPS
};
/* 8-N-1 Configuration */
#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \
(MSM_BOOT_UART_DM_SBL_1 << 2) | \
(MSM_BOOT_UART_DM_8_BPS << 4))
/* UART_DM Registers */
/* UART Operational Mode Register */
#define MSM_BOOT_UART_DM_MR1(base) ((base) + 0x00)
#define MSM_BOOT_UART_DM_MR2(base) ((base) + 0x04)
#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8)
#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7)
/* UART Clock Selection Register */
#if PERIPH_BLK_BLSP
#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0)
#else
#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08)
#endif
/* UART DM TX FIFO Registers - 4 */
#if PERIPH_BLK_BLSP
#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x100+(4*(x)))
#else
#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x)))
#endif
/* UART Command Register */
#if PERIPH_BLK_BLSP
#define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8)
#else
#define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10)
#endif
#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0)
#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1)
#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2)
#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3)
/* UART Channel Command */
#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4)
#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4 ) << 11 )
#define MSM_BOOT_UART_DM_CR_CH_CMD(x) (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x)\
| MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x))
#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0)
#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1)
#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2)
#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3)
#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4)
#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5)
#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6)
#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7)
#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8)
#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9)
#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C)
#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D)
#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E)
#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10)
#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11)
#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12)
#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13)
#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14)
/*UART General Command */
#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8)
#define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0)
#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1)
#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2)
#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3)
#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4)
#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5)
#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6)
/* UART Interrupt Mask Register */
#if PERIPH_BLK_BLSP
#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0)
#else
#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14)
#endif
#define MSM_BOOT_UART_DM_TXLEV (1 << 0)
#define MSM_BOOT_UART_DM_RXHUNT (1 << 1)
#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2)
#define MSM_BOOT_UART_DM_RXSTALE (1 << 3)
#define MSM_BOOT_UART_DM_RXLEV (1 << 4)
#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5)
#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6)
#define MSM_BOOT_UART_DM_TX_READY (1 << 7)
#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8)
#define MSM_BOOT_UART_DM_TX_DONE (1 << 9)
#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10)
#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11)
#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12)
#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \
MSM_BOOT_UART_DM_TXLEV | \
MSM_BOOT_UART_DM_RXLEV | \
MSM_BOOT_UART_DM_RXSTALE)
/* UART Interrupt Programming Register */
#define MSM_BOOT_UART_DM_IPR(base) ((base) + 0x18)
#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f
#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */
/* UART Transmit/Receive FIFO Watermark Register */
#define MSM_BOOT_UART_DM_TFWR(base) ((base) + 0x1C)
/* Interrupt is generated when FIFO level is less than or equal to this value */
#define MSM_BOOT_UART_DM_TFW_VALUE 0
#define MSM_BOOT_UART_DM_RFWR(base) ((base) + 0x20)
/*Interrupt generated when no of words in RX FIFO is greater than this value */
#define MSM_BOOT_UART_DM_RFW_VALUE 0
/* UART Hunt Character Register */
#define MSM_BOOT_UART_DM_HCR(base) ((base) + 0x24)
/* Used for RX transfer initialization */
#define MSM_BOOT_UART_DM_DMRX(base) ((base) + 0x34)
/* Default DMRX value - any value bigger than FIFO size would be fine */
#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220
/* Register to enable IRDA function */
#if PERIPH_BLK_BLSP
#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8)
#else
#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38)
#endif
/* UART Data Mover Enable Register */
#define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C)
/* Number of characters for Transmission */
#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base) ((base) + 0x040)
/* UART RX FIFO Base Address */
#define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44)
/* UART Status Register */
#if PERIPH_BLK_BLSP
#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4)
#else
#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008)
#endif
#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0)
#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1)
#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2)
#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3)
#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4)
#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5)
#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6)
#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7)
#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8)
/* UART Receive FIFO Registers - 4 in numbers */
#if PERIPH_BLK_BLSP
#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x)))
#else
#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x)))
#endif
/* UART Masked Interrupt Status Register */
#if PERIPH_BLK_BLSP
#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC)
#else
#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10)
#endif
/* UART Interrupt Status Register */
#if PERIPH_BLK_BLSP
#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4)
#else
#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14)
#endif
/* Number of characters received since the end of last RX transfer */
#if PERIPH_BLK_BLSP
#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC)
#else
#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38)
#endif
/* UART TX FIFO Status Register */
#define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C)
#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6)
#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31)
#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9)
#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13)
/* UART RX FIFO Status Register */
#define MSM_BOOT_UART_DM_RXFS(base) ((base) + 0x50)
#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6)
#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31)
#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9)
#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13)
/* Macros for Common Errors */
#define MSM_BOOT_UART_DM_E_SUCCESS 0
#define MSM_BOOT_UART_DM_E_FAILURE 1
#define MSM_BOOT_UART_DM_E_TIMEOUT 2
#define MSM_BOOT_UART_DM_E_INVAL 3
#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4
#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5
void uart_dm_init(uint8_t id,
uint32_t gsbi_base,
uint32_t uart_dm_base);
#endif /* __UART_DM_H__ */