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338
bootable/bootloader/lk/platform/msm7x27a/acpuclock.c Normal file
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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdint.h>
#include <kernel/thread.h>
#include <platform/iomap.h>
#include <reg.h>
#include <smem.h>
#include <debug.h>
#include <mmc.h>
#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
#define BIT(x) (1 << (x))
#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
#define VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124)
#define PLL2_MODE_ADDR (MSM_CLK_CTL_BASE + 0x338)
#define PLL4_MODE_ADDR (MSM_CLK_CTL_BASE + 0x374)
#define PLL_RESET_N BIT(2)
#define PLL_BYPASSNL BIT(1)
#define PLL_OUTCTRL BIT(0)
#define SRC_SEL_TCX0 0 /* TCXO */
#define SRC_SEL_PLL1 1 /* PLL1: modem_pll */
#define SRC_SEL_PLL2 2 /* PLL2: backup_pll_0 */
#define SRC_SEL_PLL3 3 /* PLL3: backup_pll_1 */
#define SRC_SEL_PLL4 6 /* PLL4: sparrow_pll */
#define DIV_1 0
#define DIV_2 1
#define DIV_3 2
#define DIV_4 3
#define DIV_5 4
#define DIV_6 5
#define DIV_7 6
#define DIV_8 7
#define DIV_9 8
#define DIV_10 9
#define DIV_11 10
#define DIV_12 11
#define DIV_13 12
#define DIV_14 13
#define DIV_15 14
#define DIV_16 15
#define WAIT_CNT 100
#define MIN_AXI_HZ 120000000
#define ACPU_800MHZ 41
#define A11S_CLK_SEL_MASK 0x1 /* bits 2:0 */
/* The stepping frequencies have been choosen to make sure the step
* is <= 256 MHz for both 7x27a and 7x25a targets. The
* table also assumes the ACPU is running at TCXO freq and AHB div is
* set to DIV_1.
*
* To use the tables:
* - Start at location 0/1 depending on clock source sel bit.
* - Set values till end of table skipping every other entry.
* - When you reach the end of the table, you are done scaling.
*/
uint32_t const clk_cntl_reg_val_7627A[] = {
(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_16,
(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_8 << 8),
(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_4,
(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_2 << 8),
/* TODO: Fix it for 800MHz */
#if 0
(WAIT_CNT << 16) | (SRC_SEL_PLL4 << 4) | DIV_1,
#endif
};
/*
* Use PLL4 to run acpu @ 1.2 GHZ
*/
uint32_t const clk_cntl_reg_val_8X25[] = {
(WAIT_CNT << 16) | (SRC_SEL_PLL4 << 4) | DIV_2,
(WAIT_CNT << 16) | (SRC_SEL_PLL4 << 12) | (DIV_1 << 8),
};
uint32_t const clk_cntl_reg_val_7625A[] = {
(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_16,
(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_8 << 8),
(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 4) | DIV_4,
(WAIT_CNT << 16) | (SRC_SEL_PLL2 << 12) | (DIV_2 << 8),
};
/* Using DIV_1 for all cases to avoid worrying about turbo vs. normal
* mode. Able to use DIV_1 for all steps because it's the largest AND
* the final value. */
uint32_t const clk_sel_reg_val[] = {
DIV_1 << 1 | 1, /* Switch to src1 */
DIV_1 << 1 | 0, /* Switch to src0 */
};
/*
* Mask to make sure current selected src frequency doesn't change.
*/
uint32_t const clk_cntl_mask[] = {
0x0000FF00, /* Mask to read src0 */
0x000000FF /* Mask to read src1 */
};
/* enum for SDC CLK IDs */
enum {
SDC1_CLK = 19,
SDC1_PCLK = 20,
SDC2_CLK = 21,
SDC2_PCLK = 22,
SDC3_CLK = 23,
SDC3_PCLK = 24,
SDC4_CLK = 25,
SDC4_PCLK = 26
};
/* Zero'th entry is dummy */
static uint8_t sdc_clk[] = { 0, SDC1_CLK, SDC2_CLK, SDC3_CLK, SDC4_CLK };
static uint8_t sdc_pclk[] = { 0, SDC1_PCLK, SDC2_PCLK, SDC3_PCLK, SDC4_PCLK };
/* VDD_PLEVEL */
unsigned vdd_plevel = 0;
void mdelay(unsigned msecs);
unsigned board_msm_id(void);
unsigned board_msm_version(void);
void pll_enable(void *pll_mode_addr)
{
/* TODO: Need to add spin-lock to avoid race conditions */
uint32_t nVal;
/* Check status */
nVal = readl(pll_mode_addr);
if (nVal & PLL_OUTCTRL)
return;
/* Put the PLL in reset mode */
nVal = 0;
nVal &= ~PLL_RESET_N;
nVal &= ~PLL_BYPASSNL;
nVal &= ~PLL_OUTCTRL;
writel(nVal, pll_mode_addr);
/* Put the PLL in warm-up mode */
nVal |= PLL_RESET_N;
nVal |= PLL_BYPASSNL;
writel(nVal, pll_mode_addr);
/* Wait for the PLL warm-up time */
udelay(50);
/* Put the PLL in active mode */
nVal |= PLL_RESET_N;
nVal |= PLL_BYPASSNL;
nVal |= PLL_OUTCTRL;
writel(nVal, pll_mode_addr);
}
void pll_request(unsigned pll, unsigned enable)
{
int val = 0;
if (!enable) {
/* Disable not supported */
return;
}
switch (pll) {
case 2:
pll_enable(PLL2_MODE_ADDR);
return;
case 4:
pll_enable(PLL4_MODE_ADDR);
return;
default:
return;
};
}
void acpu_clock_init(void)
{
uint32_t i, clk;
uint32_t val;
uint32_t *clk_cntl_reg_val, size;
unsigned msm_id, msm_version;
msm_version = board_msm_version();
if (msm_version == 2)
vdd_plevel = 4;
else
vdd_plevel = 6;
/* Set VDD plevel */
writel((1 << 7) | (vdd_plevel << 3), VDD_SVS_PLEVEL_ADDR);
#if (!ENABLE_NANDWRITE)
thread_sleep(1);
#else
mdelay(1);
#endif
msm_id = board_msm_id();
switch (msm_id) {
case MSM7227A:
case MSM7627A:
case ESM7227A:
clk_cntl_reg_val = clk_cntl_reg_val_7627A;
size = ARRAY_SIZE(clk_cntl_reg_val_7627A);
pll_request(2, 1);
/* TODO: Enable this PLL while switching to 800MHz */
#if 0
pll_request(4, 1);
#endif
break;
case MSM8625:
/* Fix me: Will move to PLL4 later */
clk_cntl_reg_val = clk_cntl_reg_val_7627A;
size = ARRAY_SIZE(clk_cntl_reg_val_7627A);
pll_request(2, 1);
break;
case MSM7225A:
case MSM7625A:
default:
clk_cntl_reg_val = clk_cntl_reg_val_7625A;
size = ARRAY_SIZE(clk_cntl_reg_val_7625A);
pll_request(2, 1);
break;
};
/* Read clock source select bit. */
val = readl(A11S_CLK_SEL_ADDR);
i = val & 1;
/* Jump into table and set every entry. */
for (; i < size; i++) {
val = readl(A11S_CLK_SEL_ADDR);
val |= BIT(1) | BIT(2);
writel(val, A11S_CLK_SEL_ADDR);
val = readl(A11S_CLK_CNTL_ADDR);
/* Make sure not to disturb already used src */
val &= clk_cntl_mask[i % 2];
val += clk_cntl_reg_val[i];
writel(val, A11S_CLK_CNTL_ADDR);
/* Would need a dmb() here but the whole address space is
* strongly ordered, so it should be fine.
*/
val = readl(A11S_CLK_SEL_ADDR);
val &= ~(A11S_CLK_SEL_MASK);
val |= (A11S_CLK_SEL_MASK & clk_sel_reg_val[i % 2]);
writel(val, A11S_CLK_SEL_ADDR);
#if (!ENABLE_NANDWRITE)
thread_sleep(1);
#else
mdelay(1);
#endif
}
}
void hsusb_clock_init(void)
{
/* USB local clock control not enabled; use proc comm */
usb_clock_init();
}
/* Configure MMC clock */
void clock_config_mmc(uint32_t interface, uint32_t freq)
{
uint32_t reg = 0;
if (mmc_clock_set_rate(sdc_clk[interface], freq) < 0) {
dprintf(CRITICAL, "Failure setting clock rate for MCLK - "
"clk_rate: %d\n!", freq);
ASSERT(0);
}
/* enable clock */
if (mmc_clock_enable_disable(sdc_clk[interface], MMC_CLK_ENABLE) < 0) {
dprintf(CRITICAL, "Failure enabling MMC Clock!\n");
ASSERT(0);
}
reg |= MMC_BOOT_MCI_CLK_ENABLE;
reg |= MMC_BOOT_MCI_CLK_ENA_FLOW;
reg |= MMC_BOOT_MCI_CLK_IN_FEEDBACK;
writel(reg, MMC_BOOT_MCI_CLK);
/* Wait for the MMC_BOOT_MCI_CLK write to go through. */
mmc_mclk_reg_wr_delay();
/* Wait 1 ms to provide the free running SD CLK to the card. */
mdelay(1);
}
/* Intialize MMC clock */
void clock_init_mmc(uint32_t interface)
{
if (mmc_clock_enable_disable(sdc_pclk[interface], MMC_CLK_ENABLE) < 0) {
dprintf(CRITICAL, "Failure enabling PCLK!\n");
ASSERT(0);
}
}

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bootable/bootloader/lk/platform/msm7x27a/arch_init.S Normal file
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/*
* Copyright (c) 2009-2011, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Google, Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
.globl SET_SA
SET_SA:
//; routine complete
B _cpu_early_init_complete
.ltorg
.globl __cpu_early_init
__cpu_early_init:
//; Zero out r0 for use throughout this code. All other GPRs
//; (r1-r3) are set throughout this code to help establish
//; a consistent startup state for any code that follows.
//; Users should add code at the end of this routine to establish
//; their own stack address (r13), add translation page tables, enable
//; the caches, etc.
MOV r0, #0x0
//; Remove hardcoded cache settings. appsbl_handler.s calls Set_SA
//; API to dynamically configure cache for slow/nominal/fast parts
//; Initialize ASID to zero
MCR p15, 0, r0, c13, c0, 1 //; WCP15_CONTEXTIDR r0
//; ICIALL to invalidate entire I-Cache
MCR p15, 0, r0, c7, c5, 0 //; ICIALLU
//; Initialize ADFSR to zero
MCR p15, 0, r0, c5, c1, 0 //; ADFSR r0
//; Ensure the MCR's above have completed their operation before continuing
DSB
ISB
//;-------------------------------------------------------------------
//; There are a number of registers that must be set prior to enabling
//; the MMU. The DCAR is one of these registers. We are setting
//; it to zero (no access) to easily detect improper setup in subsequent
//; code sequences
//;-------------------------------------------------------------------
//; Setup DACR (Domain Access Control Register) to zero
MCR p15, 0, r0, c3, c0, 0 //; WCP15_DACR r0
//;Make sure TLBLKCR is complete before continuing
ISB
//; Invalidate the UTLB
MCR p15, 0, r0, c8, c7, 0 //; UTLBIALL
//; Make sure UTLB request has been presented to macro before continuing
ISB
SYSI2:
//; Enable Z bit to enable branch prediction (default is off)
MRC p15, 0, r2, c1, c0, 0 //; RCP15_SCTLR r2
ORR r2, r2, #0x00000800
MCR p15, 0, r2, c1, c0, 0 //; WCP15_SCTLR r2
//; Make sure Link stack is initialized with branch and links to sequential addresses
//; This aids in creating a predictable startup environment
BL SEQ1
SEQ1: BL SEQ2
SEQ2: BL SEQ3
SEQ3: BL SEQ4
SEQ4: BL SEQ5
SEQ5: BL SEQ6
SEQ6: BL SEQ7
SEQ7: BL SEQ8
SEQ8:
ISB
//; Initialize the Watchpoint Control Registers to zero (optional)
//;;; MCR p14, 0, r0, c0, c0, 7 ; WCP14_DBGWCR0 r0
//;;; MCR p14, 0, r0, c0, c1, 7 ; WCP14_DBGWCR1 r0
//;----------------------------------------------------------------------
//; The saved Program Status Registers (SPSRs) should be setup
//; prior to any automatic mode switches. The following
//; code sets these registers up to a known state. Users will need to
//; customize these settings to meet their needs.
//;----------------------------------------------------------------------
MOV r2, #0x1f
MOV r1, #0xd7 //;ABT mode
msr cpsr_c, r1 //;ABT mode
msr spsr_cxfs, r2 //;clear the spsr
MOV r1, #0xdb //;UND mode
msr cpsr_c, r1 //;UND mode
msr spsr_cxfs, r2 //;clear the spsr
MOV r1, #0xd1 //;FIQ mode
msr cpsr_c, r1 //;FIQ mode
msr spsr_cxfs, r2 //;clear the spsr
MOV r1, #0xd2 //;IRQ mode
msr cpsr_c, r1 //;IRQ mode
msr spsr_cxfs, r2 //;clear the spsr
MOV r1, #0xd6 //;Monitor mode
msr cpsr_c, r1 //;Monitor mode
msr spsr_cxfs, r2 //;clear the spsr
MOV r1, #0xd3 //;SVC mode
msr cpsr_c, r1 //;SVC mode
msr spsr_cxfs, r2 //;clear the spsr
//;----------------------------------------------------------------------
//; Enabling Error reporting is something users may want to do at
//; some other point in time. We have chosen some default settings
//; that should be reviewed. Most of these registers come up in an
//; unpredictable state after reset.
//;----------------------------------------------------------------------
//;Start of error and control setting
//; Set ACTLR (reset unpredictable)
//; Set AVIVT control, error reporting, etc.
//; MOV r3, #0x07
//; Enable I and D cache parity
//;ACTLR[2:0] = 3'h7 - enable parity error reporting from L2/I$/D$)
//;ACTLR[5:4] = 2'h3 - enable parity
//;ACTLR[19:18] =2'h3 - always generate and check parity(when MMU disabled).
//;Value to be written #0xC0037
// MOVW r3, #0x0037
//; .word 0xe3003037 // hardcoded MOVW instruction due to lack of compiler support
// MOVT r3, #0x000C
//; .word 0xe340300c // hardcoded MOVW instruction due to lack of compiler support
//; MCR p15, 0, r3, c1, c0, 1 //; WCP15_ACTLR r3
//;End of error and control setting
/*
#ifdef APPSBL_ETM_ENABLE
;----------------------------------------------------------------------
; Optionally Enable the ETM (Embedded Trace Macro) which is used for debug
;----------------------------------------------------------------------
; enable ETM clock if disabled
MRC p15, 7, r1, c15, c0, 5 ; RCP15_CPMR r1
ORR r1, r1, #0x00000008
MCR p15, 7, r1, c15, c0, 5 ; WCP15_CPMR r1
ISB
; set trigger event to counter1 being zero
MOV r3, #0x00000040
MCR p14, 1, r3, c0, c2, 0 ; WCP14_ETMTRIGGER r3
; clear ETMSR
MOV r2, #0x00000000
MCR p14, 1, r2, c0, c4, 0 ; WCP14_ETMSR r2
; clear trace enable single address comparator usage
MCR p14, 1, r2, c0, c7, 0 ; WCP14_ETMTECR2 r2
; set trace enable to always
MOV r2, #0x0000006F
MCR p14, 1, r2, c0, c8, 0 ; WCP14_ETMTEEVR r2
; clear trace enable address range comparator usage and exclude nothing
MOV r2, #0x01000000
MCR p14, 1, r2, c0, c9, 0 ; WCP14_ETMTECR1 r2
; set view data to always
MOV r2, #0x0000006F
MCR p14, 1, r2, c0, c12, 0 ; WCP14_ETMVDEVR r2
; clear view data single address comparator usage
MOV r2, #0x00000000
MCR p14, 1, r2, c0, c13, 0 ; WCP14_ETMVDCR1 r2
; clear view data address range comparator usage and exclude nothing
MOV r2, #0x00010000
MCR p14, 1, r2, c0, c15, 0 ; WCP14_ETMVDCR3 r2
; set counter1 to 194
MOV r2, #0x000000C2
MCR p14, 1, r2, c0, c0, 5 ; WCP14_ETMCNTRLDVR1 r2
; set counter1 to never reload
MOV r2, #0x0000406F
MCR p14, 1, r2, c0, c8, 5 ; WCP14_ETMCNTRLDEVR1 r2
; set counter1 to decrement every cycle
MOV r2, #0x0000006F
MCR p14, 1, r2, c0, c4, 5 ; WCP14_ETMCNTENR1 r2
; Set trace synchronization frequency 1024 bytes
MOV r2, #0x00000400
MCR p14, 1, r2, c0, c8, 7 ; WCP14_ETMSYNCFR r2
; Program etm control register
; - Set the CPU to ETM clock ratio to 1:1
; - Set the ETM to perform data address tracing
MOV r2, #0x00002008
MCR p14, 1, r2, c0, c0, 0 ; WCP14_ETMCR r2
ISB
#endif *//* APPSBL_ETM_ENABLE */
/*
#ifdef APPSBL_VFP_ENABLE
;----------------------------------------------------------------------
; Perform the following operations if you intend to make use of
; the VFP/Neon unit. Note that the FMXR instruction requires a CPU ID
; indicating the VFP unit is present (i.e.Cortex-A8). .
; Some tools will require full double precision floating point support
; which will become available in Scorpion pass 2
;----------------------------------------------------------------------
; allow full access to CP 10 and 11 space for VFP/NEON use
MRC p15, 0, r1, c1, c0, 2 ; Read CP Access Control Register
ORR r1, r1, #0x00F00000 ; enable full access for p10,11
MCR p15, 0, r1, c1, c0, 2 ; Write CPACR
;make sure the CPACR is complete before continuing
ISB
; Enable VFP itself (certain OSes may want to dynamically set/clear
; the enable bit based on the application being executed
MOV r1, #0x40000000
FMXR FPEXC, r1
#endif *//* APPSBL_VFP_ENABLE */
/* we have no stack, so just tail-call into the SET_SA routine... */
B SET_SA
.ltorg

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bootable/bootloader/lk/platform/msm7x27a/gpio.c Normal file
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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <debug.h>
#include <reg.h>
#include <platform/iomap.h>
#include <dev/gpio.h>
#define GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
/* output value */
#define GPIO_OUT_0 GPIO1_REG(0x00) /* gpio 15-0 */
#define GPIO_OUT_1 GPIO2_REG(0x00) /* gpio 42-16 */
#define GPIO_OUT_2 GPIO1_REG(0x04) /* gpio 67-43 */
#define GPIO_OUT_3 GPIO1_REG(0x08) /* gpio 94-68 */
#define GPIO_OUT_4 GPIO1_REG(0x0C) /* gpio 106-95 */
#define GPIO_OUT_5 GPIO1_REG(0x50) /* gpio 132-107 */
/* same pin map as above, output enable */
#define GPIO_OE_0 GPIO1_REG(0x10)
#define GPIO_OE_1 GPIO2_REG(0x08)
#define GPIO_OE_2 GPIO1_REG(0x14)
#define GPIO_OE_3 GPIO1_REG(0x18)
#define GPIO_OE_4 GPIO1_REG(0x1C)
#define GPIO_OE_5 GPIO1_REG(0x54)
/* same pin map as above, input read */
#define GPIO_IN_0 GPIO1_REG(0x34)
#define GPIO_IN_1 GPIO2_REG(0x20)
#define GPIO_IN_2 GPIO1_REG(0x38)
#define GPIO_IN_3 GPIO1_REG(0x3C)
#define GPIO_IN_4 GPIO1_REG(0x40)
#define GPIO_IN_5 GPIO1_REG(0x44)
/* same pin map as above, 1=edge 0=level interrup */
#define GPIO_INT_EDGE_0 GPIO1_REG(0x60)
#define GPIO_INT_EDGE_1 GPIO2_REG(0x50)
#define GPIO_INT_EDGE_2 GPIO1_REG(0x64)
#define GPIO_INT_EDGE_3 GPIO1_REG(0x68)
#define GPIO_INT_EDGE_4 GPIO1_REG(0x6C)
#define GPIO_INT_EDGE_5 GPIO1_REG(0xC0)
/* same pin map as above, 1=positive 0=negative */
#define GPIO_INT_POS_0 GPIO1_REG(0x70)
#define GPIO_INT_POS_1 GPIO2_REG(0x58)
#define GPIO_INT_POS_2 GPIO1_REG(0x74)
#define GPIO_INT_POS_3 GPIO1_REG(0x78)
#define GPIO_INT_POS_4 GPIO1_REG(0x7C)
#define GPIO_INT_POS_5 GPIO1_REG(0xBC)
/* same pin map as above, interrupt enable */
#define GPIO_INT_EN_0 GPIO1_REG(0x80)
#define GPIO_INT_EN_1 GPIO2_REG(0x60)
#define GPIO_INT_EN_2 GPIO1_REG(0x84)
#define GPIO_INT_EN_3 GPIO1_REG(0x88)
#define GPIO_INT_EN_4 GPIO1_REG(0x8C)
#define GPIO_INT_EN_5 GPIO1_REG(0xB8)
/* same pin map as above, write 1 to clear interrupt */
#define GPIO_INT_CLEAR_0 GPIO1_REG(0x90)
#define GPIO_INT_CLEAR_1 GPIO2_REG(0x68)
#define GPIO_INT_CLEAR_2 GPIO1_REG(0x94)
#define GPIO_INT_CLEAR_3 GPIO1_REG(0x98)
#define GPIO_INT_CLEAR_4 GPIO1_REG(0x9C)
#define GPIO_INT_CLEAR_5 GPIO1_REG(0xB4)
/* same pin map as above, 1=interrupt pending */
#define GPIO_INT_STATUS_0 GPIO1_REG(0xA0)
#define GPIO_INT_STATUS_1 GPIO2_REG(0x70)
#define GPIO_INT_STATUS_2 GPIO1_REG(0xA4)
#define GPIO_INT_STATUS_3 GPIO1_REG(0xA8)
#define GPIO_INT_STATUS_4 GPIO1_REG(0xAC)
#define GPIO_INT_STATUS_5 GPIO1_REG(0xB0)
typedef struct gpioregs gpioregs;
struct gpioregs {
unsigned out;
unsigned in;
unsigned int_status;
unsigned int_clear;
unsigned int_en;
unsigned int_edge;
unsigned int_pos;
unsigned oe;
};
static gpioregs GPIO_REGS[] = {
{
.out = GPIO_OUT_0,
.in = GPIO_IN_0,
.int_status = GPIO_INT_STATUS_0,
.int_clear = GPIO_INT_CLEAR_0,
.int_en = GPIO_INT_EN_0,
.int_edge = GPIO_INT_EDGE_0,
.int_pos = GPIO_INT_POS_0,
.oe = GPIO_OE_0,
},
{
.out = GPIO_OUT_1,
.in = GPIO_IN_1,
.int_status = GPIO_INT_STATUS_1,
.int_clear = GPIO_INT_CLEAR_1,
.int_en = GPIO_INT_EN_1,
.int_edge = GPIO_INT_EDGE_1,
.int_pos = GPIO_INT_POS_1,
.oe = GPIO_OE_1,
},
{
.out = GPIO_OUT_2,
.in = GPIO_IN_2,
.int_status = GPIO_INT_STATUS_2,
.int_clear = GPIO_INT_CLEAR_2,
.int_en = GPIO_INT_EN_2,
.int_edge = GPIO_INT_EDGE_2,
.int_pos = GPIO_INT_POS_2,
.oe = GPIO_OE_2,
},
{
.out = GPIO_OUT_3,
.in = GPIO_IN_3,
.int_status = GPIO_INT_STATUS_3,
.int_clear = GPIO_INT_CLEAR_3,
.int_en = GPIO_INT_EN_3,
.int_edge = GPIO_INT_EDGE_3,
.int_pos = GPIO_INT_POS_3,
.oe = GPIO_OE_3,
},
{
.out = GPIO_OUT_4,
.in = GPIO_IN_4,
.int_status = GPIO_INT_STATUS_4,
.int_clear = GPIO_INT_CLEAR_4,
.int_en = GPIO_INT_EN_4,
.int_edge = GPIO_INT_EDGE_4,
.int_pos = GPIO_INT_POS_4,
.oe = GPIO_OE_4,
},
{
.out = GPIO_OUT_5,
.in = GPIO_IN_5,
.int_status = GPIO_INT_STATUS_5,
.int_clear = GPIO_INT_CLEAR_5,
.int_en = GPIO_INT_EN_5,
.int_edge = GPIO_INT_EDGE_5,
.int_pos = GPIO_INT_POS_5,
.oe = GPIO_OE_5,
},
};
static gpioregs *find_gpio(unsigned n, unsigned *bit)
{
if (n > 132)
return 0;
if (n > 106) {
*bit = 1 << (n - 107);
return GPIO_REGS + 5;
}
if (n > 94) {
*bit = 1 << (n - 95);
return GPIO_REGS + 4;
}
if (n > 67) {
*bit = 1 << (n - 68);
return GPIO_REGS + 3;
}
if (n > 42) {
*bit = 1 << (n - 43);
return GPIO_REGS + 2;
}
if (n > 15) {
*bit = 1 << (n - 16);
return GPIO_REGS + 1;
}
*bit = 1 << n;
return GPIO_REGS + 0;
}
int gpio_config(unsigned n, unsigned flags)
{
gpioregs *r;
unsigned b;
unsigned v;
if ((r = find_gpio(n, &b)) == 0)
return -1;
v = readl(r->oe);
if (flags & GPIO_OUTPUT) {
writel(v | b, r->oe);
} else {
writel(v & (~b), r->oe);
}
return 0;
}
void gpio_set(unsigned n, unsigned on)
{
gpioregs *r;
unsigned b;
unsigned v;
if ((r = find_gpio(n, &b)) == 0)
return;
v = readl(r->out);
if (on) {
writel(v | b, r->out);
} else {
writel(v & (~b), r->out);
}
}
int gpio_get(unsigned n)
{
gpioregs *r;
unsigned b;
if ((r = find_gpio(n, &b)) == 0)
return 0;
return (readl(r->in) & b) ? 1 : 0;
}

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/*
* * Copyright (c) 2011, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLATFORM_MSM7627A_CLOCK_H
#define __PLATFORM_MSM7627A_CLOCK_H
#endif

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/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLATFORM_MSM7X27A_GPIO_H
#define __PLATFORM_MSM7X27A_GPIO_H
/* GPIO TLMM: Direction */
#ifndef GPIO_INPUT
#define GPIO_INPUT 0
#endif
#ifndef GPIO_OUTPUT
#define GPIO_OUTPUT 1
#endif
/* GPIO TLMM: Pullup/Pulldown */
#define GPIO_NO_PULL 0
#define GPIO_PULL_DOWN 1
#define GPIO_KEEPER 2
#define GPIO_PULL_UP 3
/* GPIO TLMM: Drive Strength */
#define GPIO_2MA 0
#define GPIO_4MA 1
#define GPIO_6MA 2
#define GPIO_8MA 3
#define GPIO_10MA 4
#define GPIO_12MA 5
#define GPIO_14MA 6
#define GPIO_16MA 7
/* GPIO TLMM: Status */
#define GPIO_ENABLE 0
#define GPIO_DISABLE 1
#define GPIO_CFG(gpio, func, dir, pull, drvstr)\
((((gpio) & 0x3ff) << 4) | \
((func) & 0xf) | \
(((dir) & 0x1) << 14) | \
(((pull) & 0x3) << 15) | \
(((drvstr) & 0xf) << 17))
#endif

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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Google, Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _PLATFORM_MSM7627A_IOMAP_H_
#define _PLATFORM_MSM7627A_IOMAP_H_
#define MSM_GPIO1_BASE 0xA9200000
#define MSM_GPIO2_BASE 0xA9300000
#define MSM_UART1_BASE 0xA9A00000
#define MSM_UART2_BASE 0xA9B00000
#define MSM_UART3_BASE 0xA9C00000
#define MSM_VIC_BASE 0xC0000000
#define MSM_GPT_BASE 0xC0100000
#define GPT_REG(off) (MSM_GPT_BASE + (off))
#define GPT_MATCH_VAL GPT_REG(0x0000)
#define GPT_COUNT_VAL GPT_REG(0x0004)
#define GPT_ENABLE GPT_REG(0x0008)
#define GPT_CLEAR GPT_REG(0x000C)
#define DGT_MATCH_VAL GPT_REG(0x0010)
#define DGT_COUNT_VAL GPT_REG(0x0014)
#define DGT_ENABLE GPT_REG(0x0018)
#define DGT_CLEAR GPT_REG(0x001C)
#define SPSS_TIMER_STATUS GPT_REG(0x0034)
#define MSM_CSR_BASE 0xC0100000
#define MSM_CLK_CTL_BASE 0xA8600000
#define MSM_SHARED_BASE 0x00100000
#define MSM_SDC1_BASE 0xA0400000
#define MSM_SDC3_BASE 0xA0600000
#define MIPI_DSI_BASE (0xA1100000)
#define DSI_PHY_SW_RESET (0xA1100128)
#define REG_DSI(off) (MIPI_DSI_BASE + (off))
#define MDP_BASE (0xAA200000)
#define REG_MDP(off) (MDP_BASE + (off))
#define DSIPHY_REGULATOR_BASE (0x2CC)
#define DSIPHY_TIMING_BASE (0x260)
#define DSIPHY_CTRL_BASE (0x290)
#define DSIPHY_PLL_BASE (0x200)
#define DSIPHY_STRENGTH_BASE (0x2A0)
/* Range 0 - 4 */
#define DSIPHY_REGULATOR_CTRL(x) REG_DSI(DSIPHY_REGULATOR_BASE + (x) * 4)
/* Range 0 - 11 */
#define DSIPHY_TIMING_CTRL(x) REG_DSI(DSIPHY_TIMING_BASE + (x) * 4)
/* Range 0 - 3 */
#define DSIPHY_CTRL(x) REG_DSI(DSIPHY_CTRL_BASE + (x) * 4)
/* Range 0 - 2 */
#define DSIPHY_STRENGTH_CTRL(x) REG_DSI(DSIPHY_STRENGTH_BASE + (x) * 4)
/* Range 0 - 19 */
#define DSIPHY_PLL_CTRL(x) REG_DSI(DSIPHY_PLL_BASE + (x) * 4)
#define MDP_DMA_P_CONFIG (0xAA290000)
#define MDP_DMA_P_OUT_XY (0xAA290010)
#define MDP_DMA_P_SIZE (0xAA290004)
#define MDP_DMA_P_BUF_ADDR (0xAA290008)
#define MDP_DMA_P_BUF_Y_STRIDE (0xAA29000C)
#define MDP_DSI_VIDEO_EN (0xAA2F0000)
#define MDP_DSI_VIDEO_HSYNC_CTL (0xAA2F0004)
#define MDP_DSI_VIDEO_VSYNC_PERIOD (0xAA2F0008)
#define MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH (0xAA2F000C)
#define MDP_DSI_VIDEO_DISPLAY_HCTL (0xAA2F0010)
#define MDP_DSI_VIDEO_DISPLAY_V_START (0xAA2F0014)
#define MDP_DSI_VIDEO_DISPLAY_V_END (0xAA2F0018)
#define MDP_DSI_VIDEO_BORDER_CLR (0xAA2F0028)
#define MDP_DSI_VIDEO_HSYNC_SKEW (0xAA2F0030)
#define MDP_DSI_VIDEO_CTL_POLARITY (0xAA2F0038)
#define MDP_DSI_VIDEO_TEST_CTL (0xAA2F0034)
#define MDP_DMA_P_START REG_MDP(0x00044)
#define MDP_DMA_S_START REG_MDP(0x00048)
#define MDP_DISP_INTF_SEL REG_MDP(0x00038)
#define MDP_MAX_RD_PENDING_CMD_CONFIG REG_MDP(0x0004C)
#define MDP_INTR_ENABLE REG_MDP(0x00020)
#define MDP_INTR_CLEAR REG_MDP(0x00028)
#define MDP_DSI_CMD_MODE_ID_MAP REG_MDP(0xF1000)
#define MDP_DSI_CMD_MODE_TRIGGER_EN REG_MDP(0XF1004)
#define MDP_TEST_MODE_CLK REG_MDP(0xF0000)
#define MDP_INTR_STATUS REG_MDP(0x00054)
#define MSM_CRYPTO_BASE (0xA0C00000)
#define MSM_GIC_DIST_BASE (0xC0000000)
#define MSM_GIC_CPU_BASE (0xC0002000)
#define LCDC_BASE (0x000E0000)
#endif

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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Google, Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _PLATFORM_MSM7K_IRQS_H_
#define _PLATFORM_MSM7K_IRQS_H_
extern int debug_timer;
extern int gpt_timer;
extern int usb_hs_int;
#define GIC_PPI_START 16
#define INT_A9_M2A_0 0
#define INT_A9_M2A_1 1
#define INT_A9_M2A_2 2
#define INT_A9_M2A_3 3
#define INT_A9_M2A_4 4
#define INT_A9_M2A_5 5
#define INT_A9_M2A_6 6
#define INT_GP_TIMER_EXP gpt_timer
#define INT_DEBUG_TIMER_EXP debug_timer
#define INT_UART1 9
#define INT_UART2 10
#define INT_UART3 11
#define INT_UART1_RX 12
#define INT_UART2_RX 13
#define INT_UART3_RX 14
#define INT_USB_OTG 15
#define INT_MDDI_PRI 16
#define INT_MDDI_EXT 17
#define INT_MDDI_CLIENT 18
#define INT_MDP 19
#define INT_GRAPHICS 20
#define INT_ADM_AARM 21
#define INT_ADSP_A11 22
#define INT_ADSP_A9_A11 23
#define INT_SDC1_0 24
#define INT_SDC1_1 25
#define INT_SDC2_0 26
#define INT_SDC2_1 27
#define INT_KEYSENSE 28
#define INT_TCHSCRN_SSBI 29
#define INT_TCHSCRN1 30
#define INT_TCHSCRN2 31
#define INT_GPIO_GROUP1 (32 + 0)
#define INT_GPIO_GROUP2 (32 + 1)
#define INT_PWB_I2C (32 + 2)
#define INT_NAND_WR_ER_DONE (32 + 3)
#define INT_NAND_OP_DONE (32 + 4)
#define INT_SOFTRESET (32 + 5)
#define INT_PBUS_ARM11 (32 + 6)
#define INT_AXI_MPU_SMI (32 + 7)
#define INT_AXI_MPU_EBI1 (32 + 8)
#define INT_AD_HSSD (32 + 9)
#define INT_ARM11_PM (32 + 10)
#define INT_ARM11_DMA (32 + 11)
#define INT_TSIF_IRQ (32 + 12)
#define INT_UART1DM_IRQ (32 + 13)
#define INT_UART1DM_RX (32 + 14)
#define INT_USB_HS_VIC (32 + 15)
#define INT_USB_HS_GIC (32 + 32 + 15)
#define INT_USB_HS usb_hs_int
#define INT_SDC3_0 (32 + 16)
#define INT_SDC3_1 (32 + 17)
#define INT_SDC4_0 (32 + 18)
#define INT_SDC4_1 (32 + 19)
#define INT_UART2DM_RX (32 + 20)
#define INT_UART2DM_IRQ (32 + 21)
#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31))
#define NR_IRQS NR_IRQS_QGIC
#define NR_IRQS_VIC 54
#define NR_IRQS_QGIC 261
#endif

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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Copyright (c) 2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Google, Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <debug.h>
#include <arch/arm.h>
#include <reg.h>
#include <kernel/thread.h>
#include <platform/interrupts.h>
#include <platform/irqs.h>
#include <platform/iomap.h>
#define VIC_REG(off) (MSM_VIC_BASE + (off))
#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
#define VIC_INT_EN0 VIC_REG(0x0010)
#define VIC_INT_EN1 VIC_REG(0x0014)
#define VIC_INT_ENCLEAR0 VIC_REG(0x0020)
#define VIC_INT_ENCLEAR1 VIC_REG(0x0024)
#define VIC_INT_ENSET0 VIC_REG(0x0030)
#define VIC_INT_ENSET1 VIC_REG(0x0034)
#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
#define VIC_NO_PEND_VAL VIC_REG(0x0060)
#define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */
#define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */
#define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */
#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
#define VIC_IRQ_STATUS1 VIC_REG(0x0084)
#define VIC_FIQ_STATUS0 VIC_REG(0x0090)
#define VIC_FIQ_STATUS1 VIC_REG(0x0094)
#define VIC_RAW_STATUS0 VIC_REG(0x00A0)
#define VIC_RAW_STATUS1 VIC_REG(0x00A4)
#define VIC_INT_CLEAR0 VIC_REG(0x00B0)
#define VIC_INT_CLEAR1 VIC_REG(0x00B4)
#define VIC_SOFTINT0 VIC_REG(0x00C0)
#define VIC_SOFTINT1 VIC_REG(0x00C4)
#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
#define VIC_IRQ_VEC_WR VIC_REG(0x00D8)
#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E0)
#define VIC_IRQ_IN_STACK VIC_REG(0x00E4)
#define VIC_TEST_BUS_SEL VIC_REG(0x00E8)
struct ihandler {
int_handler func;
void *arg;
};
static struct ihandler handler[NR_IRQS_VIC];
void platform_init_interrupts(void)
{
writel(0xffffffff, VIC_INT_CLEAR0);
writel(0xffffffff, VIC_INT_CLEAR1);
writel(0, VIC_INT_SELECT0);
writel(0, VIC_INT_SELECT1);
writel(0xffffffff, VIC_INT_TYPE0);
writel(0xffffffff, VIC_INT_TYPE1);
writel(0, VIC_CONFIG);
writel(1, VIC_INT_MASTEREN);
}
enum handler_return vic_platform_irq(struct arm_iframe *frame)
{
unsigned num;
enum handler_return ret;
num = readl(VIC_IRQ_VEC_RD);
num = readl(VIC_IRQ_VEC_PEND_RD);
if (num > NR_IRQS_VIC)
return 0;
writel(1 << (num & 31), (num > 31) ? VIC_INT_CLEAR1 : VIC_INT_CLEAR0);
ret = handler[num].func(handler[num].arg);
writel(0, VIC_IRQ_VEC_WR);
return ret;
}
void vic_platform_fiq(struct arm_iframe *frame)
{
PANIC_UNIMPLEMENTED;
}
status_t vic_mask_interrupt(unsigned int vector)
{
unsigned reg = (vector > 31) ? VIC_INT_ENCLEAR1 : VIC_INT_ENCLEAR0;
unsigned bit = 1 << (vector & 31);
writel(bit, reg);
return 0;
}
status_t vic_unmask_interrupt(unsigned int vector)
{
unsigned reg = (vector > 31) ? VIC_INT_ENSET1 : VIC_INT_ENSET0;
unsigned bit = 1 << (vector & 31);
writel(bit, reg);
return 0;
}
void vic_register_int_handler(unsigned int vector, int_handler func, void *arg)
{
if (vector >= NR_IRQS_VIC)
return;
enter_critical_section();
handler[vector].func = func;
handler[vector].arg = arg;
exit_critical_section();
}

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/* Copyright 2007, Google Inc. */
#include <debug.h>
#include <dev/gpio.h>
#include <kernel/thread.h>
#include <mddi.h>
#define MDDI_CLIENT_CORE_BASE 0x108000
#define LCD_CONTROL_BLOCK_BASE 0x110000
#define SPI_BLOCK_BASE 0x120000
#define I2C_BLOCK_BASE 0x130000
#define PWM_BLOCK_BASE 0x140000
#define GPIO_BLOCK_BASE 0x150000
#define SYSTEM_BLOCK1_BASE 0x160000
#define SYSTEM_BLOCK2_BASE 0x170000
#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)
#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)
#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)
#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)
#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)
#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)
#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)
#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)
#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)
#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)
#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)
#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)
#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)
#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)
#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)
#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)
#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
#define START (LCD_CONTROL_BLOCK_BASE|0x08)
#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)
#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)
#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)
#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)
#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)
#define PXL (LCD_CONTROL_BLOCK_BASE|0x30)
#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
#define HSW (LCD_CONTROL_BLOCK_BASE|0x38)
#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)
#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)
#define VSW (LCD_CONTROL_BLOCK_BASE|0x48)
#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)
#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)
#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)
#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)
#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)
#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)
#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)
#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)
#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)
#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)
#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)
#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)
#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)
#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)
#define MONI (LCD_CONTROL_BLOCK_BASE|0xB0)
#define Current (LCD_CONTROL_BLOCK_BASE|0xC0)
#define LCD (LCD_CONTROL_BLOCK_BASE|0xC4)
#define COMMAND (LCD_CONTROL_BLOCK_BASE|0xC8)
#define SSICTL (SPI_BLOCK_BASE|0x00)
#define SSITIME (SPI_BLOCK_BASE|0x04)
#define SSITX (SPI_BLOCK_BASE|0x08)
#define SSIRX (SPI_BLOCK_BASE|0x0C)
#define SSIINTC (SPI_BLOCK_BASE|0x10)
#define SSIINTS (SPI_BLOCK_BASE|0x14)
#define SSIDBG1 (SPI_BLOCK_BASE|0x18)
#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
#define SSIID (SPI_BLOCK_BASE|0x20)
#define I2CSETUP (I2C_BLOCK_BASE|0x00)
#define I2CCTRL (I2C_BLOCK_BASE|0x04)
#define TIMER0LOAD (PWM_BLOCK_BASE|0x00)
#define TIMER0VALUE (PWM_BLOCK_BASE|0x04)
#define TIMER0CONTROL (PWM_BLOCK_BASE|0x08)
#define TIMER0INTCLR (PWM_BLOCK_BASE|0x0C)
#define TIMER0RIS (PWM_BLOCK_BASE|0x10)
#define TIMER0MIS (PWM_BLOCK_BASE|0x14)
#define TIMER0BGLOAD (PWM_BLOCK_BASE|0x18)
#define PWM0OFF (PWM_BLOCK_BASE|0x1C)
#define TIMER1LOAD (PWM_BLOCK_BASE|0x20)
#define TIMER1VALUE (PWM_BLOCK_BASE|0x24)
#define TIMER1CONTROL (PWM_BLOCK_BASE|0x28)
#define TIMER1INTCLR (PWM_BLOCK_BASE|0x2C)
#define TIMER1RIS (PWM_BLOCK_BASE|0x30)
#define TIMER1MIS (PWM_BLOCK_BASE|0x34)
#define TIMER1BGLOAD (PWM_BLOCK_BASE|0x38)
#define PWM1OFF (PWM_BLOCK_BASE|0x3C)
#define TIMERITCR (PWM_BLOCK_BASE|0x60)
#define TIMERITOP (PWM_BLOCK_BASE|0x64)
#define PWMCR (PWM_BLOCK_BASE|0x68)
#define PWMID (PWM_BLOCK_BASE|0x6C)
#define PWMMON (PWM_BLOCK_BASE|0x70)
#define GPIODATA (GPIO_BLOCK_BASE|0x00)
#define GPIODIR (GPIO_BLOCK_BASE|0x04)
#define GPIOIS (GPIO_BLOCK_BASE|0x08)
#define GPIOIBE (GPIO_BLOCK_BASE|0x0C)
#define GPIOIEV (GPIO_BLOCK_BASE|0x10)
#define GPIOIE (GPIO_BLOCK_BASE|0x14)
#define GPIORIS (GPIO_BLOCK_BASE|0x18)
#define GPIOMIS (GPIO_BLOCK_BASE|0x1C)
#define GPIOIC (GPIO_BLOCK_BASE|0x20)
#define GPIOOMS (GPIO_BLOCK_BASE|0x24)
#define GPIOPC (GPIO_BLOCK_BASE|0x28)
#define GPIOID (GPIO_BLOCK_BASE|0x30)
#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
struct init_table {
unsigned int reg;
unsigned int val;
};
static struct init_table toshiba_480x640_init_table[] = {
{DPSET0, 0x4BEC0066}, // # MDC.DPSET0 # Setup DPLL parameters
{DPSET1, 0x00000113}, // # MDC.DPSET1
{DPSUS, 0x00000000}, // # MDC.DPSUS # Set DPLL oscillation enable
{DPRUN, 0x00000001}, // # MDC.DPRUN # Release reset signal for DPLL
{0, 14}, // wait_ms(14);
{SYSCKENA, 0x00000001}, // # MDC.SYSCKENA # Enable system clock output
{CLKENB, 0x000000EF}, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK)
{GPIO_BLOCK_BASE, 0x03FF0000}, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0
{GPIODIR, 0x0000024D}, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output)
{SYSTEM_BLOCK2_BASE, 0x00000173}, // # SYS.GPIOSEL # GPIO port multiplexing control
{GPIOPC, 0x03C300C0}, // # GPI .GPIOPC # GPIO2,3 PD cut
{SYSTEM_BLOCK1_BASE, 0x00000000}, // # SYS.WKREQ # Wake-up request event is VSYNC alignment
{GPIOIS, 0x00000000}, // # GPI .GPIOIS # Set interrupt sense of GPIO
{GPIOIEV, 0x00000001}, // # GPI .GPIOIEV # Set interrupt event of GPIO
{GPIOIC, 0x000003FF}, // # GPI .GPIOIC # GPIO interrupt clear
{GPIO_BLOCK_BASE, 0x00060006}, // # GPI .GPIODATA # Release LCDD reset
{GPIO_BLOCK_BASE, 0x00080008}, // # GPI .GPIODATA # eDRAM VD supply
{GPIO_BLOCK_BASE, 0x02000200}, // # GPI .GPIODATA # TEST LED ON
{DRAMPWR, 0x00000001}, // # SYS.DRAMPWR # eDRAM power up
{TIMER0CONTROL, 0x00000060}, // # PWM.Timer0Control # PWM0 output stop
{PWM_BLOCK_BASE, 0x00001388}, // # PWM.Timer0Load # PWM0 10kHz , Duty 99 (BackLight OFF)
//{PWM0OFF, 0x00000001 }, // # PWM.PWM0OFF
#if 0
{PWM0OFF, 0x00001387}, // SURF 100% backlight
{PWM0OFF, 0x00000000}, // FFA 100% backlight
#endif
{PWM0OFF, 0x000009C3}, // 50% BL
{TIMER1CONTROL, 0x00000060}, // # PWM.Timer1Control # PWM1 output stop
{TIMER1LOAD, 0x00001388}, // # PWM.Timer1Load # PWM1 10kHz , Duty 99 (BackLight OFF)
//{PWM1OFF, 0x00000001 }, // # PWM.PWM1OFF
{PWM1OFF, 0x00001387},
{TIMER0CONTROL, 0x000000E0}, // # PWM.Timer0Control # PWM0 output start
{TIMER1CONTROL, 0x000000E0}, // # PWM.Timer1Control # PWM1 output start
{PWMCR, 0x00000003}, // # PWM.PWMCR # PWM output enable
{0, 1}, // wait_ms(1);
{SPI_BLOCK_BASE, 0x00000799}, // # SPI .SSICTL # SPI operation mode setting
{SSITIME, 0x00000100}, // # SPI .SSITIME # SPI serial interface timing setting
{SPI_BLOCK_BASE, 0x0000079b}, // # SPI .SSICTL # Set SPI active mode
{SSITX, 0x00000000}, // # SPI.SSITX # Release from Deep Stanby mode
{0, 1}, // wait_ms(1);
{SSITX, 0x00000000}, // # SPI.SSITX
{0, 1}, // wait_ms(1);
{SSITX, 0x00000000}, // # SPI.SSITX
{0, 1}, // wait_ms(1);
{SSITX, 0x000800BA}, // # SPI.SSITX *NOTE 1 # Command setting of SPI block
{SSITX, 0x00000111}, // # Display mode setup(1) : Normaly Black
{SSITX, 0x00080036}, // # Command setting of SPI block
{SSITX, 0x00000100}, // # Memory access control
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800BB}, // # Command setting of SPI block
{SSITX, 0x00000100}, // # Display mode setup(2)
{SSITX, 0x0008003A}, // # Command setting of SPI block
{SSITX, 0x00000160}, // # RGB Interface data format
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800BF}, // # Command setting of SPI block
{SSITX, 0x00000100}, // # Drivnig method
{SSITX, 0x000800B1}, // # Command setting of SPI block
{SSITX, 0x0000015D}, // # Booster operation setup
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800B2}, // # Command setting of SPI block
{SSITX, 0x00000133}, // # Booster mode setup
{SSITX, 0x000800B3}, // # Command setting of SPI block
{SSITX, 0x00000122}, // # Booster frequencies setup
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800B4}, // # Command setting of SPI block
{SSITX, 0x00000102}, // # OP-amp capability/System clock freq. division setup
{SSITX, 0x000800B5}, // # Command setting of SPI block
{SSITX, 0x0000011F}, // # VCS Voltage adjustment (1C->1F for Rev 2)
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800B6}, // # Command setting of SPI block
{SSITX, 0x00000128}, // # VCOM Voltage adjustment
{SSITX, 0x000800B7}, // # Command setting of SPI block
{SSITX, 0x00000103}, // # Configure an external display signal
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800B9}, // # Command setting of SPI block
{SSITX, 0x00000120}, // # DCCK/DCEV timing setup
{SSITX, 0x000800BD}, // # Command setting of SPI block
{SSITX, 0x00000102}, // # ASW signal control
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800BE}, // # Command setting of SPI block
{SSITX, 0x00000100}, // # Dummy display (white/black) count setup for QUAD Data operation
{SSITX, 0x000800C0}, // # Command setting of SPI block
{SSITX, 0x00000111}, // # wait_ms(-out FR count setup (A)
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800C1}, // # Command setting of SPI block
{SSITX, 0x00000111}, // # wait_ms(-out FR count setup (B)
{SSITX, 0x000800C2}, // # Command setting of SPI block
{SSITX, 0x00000111}, // # wait_ms(-out FR count setup (C)
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800C3}, // # Command setting of SPI block
{SSITX, 0x0008010A}, // # wait_ms(-in line clock count setup (D)
{SSITX, 0x0000010A}, //
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800C4}, // # Command setting of SPI block
{SSITX, 0x00080160}, // # Seep-in line clock count setup (E)
{SSITX, 0x00000160}, //
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800C5}, // # Command setting of SPI block
{SSITX, 0x00080160}, // # wait_ms(-in line clock count setup (F)
{SSITX, 0x00000160}, //
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800C6}, // # Command setting of SPI block
{SSITX, 0x00080160}, // # wait_ms(-in line clock setup (G)
{SSITX, 0x00000160}, //
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800C7}, // # Command setting of SPI block
{SSITX, 0x00080133}, // # Gamma 1 fine tuning (1)
{SSITX, 0x00000143}, //
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800C8}, // # Command setting of SPI block
{SSITX, 0x00000144}, // # Gamma 1 fine tuning (2)
{SSITX, 0x000800C9}, // # Command setting of SPI block
{SSITX, 0x00000133}, // # Gamma 1 inclination adjustment
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800CA}, // # Command setting of SPI block
{SSITX, 0x00000100}, // # Gamma 1 blue offset adjustment
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800EC}, // # Command setting of SPI block
{SSITX, 0x00080102}, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]
{SSITX, 0x00000118}, //
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800CF}, // # Command setting of SPI block
{SSITX, 0x00000101}, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800D0}, // # Command setting of SPI block
{SSITX, 0x00080110}, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]
{SSITX, 0x00000104}, //
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800D1}, // # Command setting of SPI block
{SSITX, 0x00000101}, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800D2}, // # Command setting of SPI block
{SSITX, 0x00080100}, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]
{SSITX, 0x0000013A}, //
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800D3}, // # Command setting of SPI block
{SSITX, 0x00080100}, // # OEV timing control [PCLK Sync. Table1 for VGA]
{SSITX, 0x0000013A}, //
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800D4}, // # Command setting of SPI block
{SSITX, 0x00080124}, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]
{SSITX, 0x0000016E}, //
{0, 1}, // wait_ms(1); // # Wait SPI fifo empty
{SSITX, 0x000800D5}, // # Command setting of SPI block
{SSITX, 0x00000124}, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800ED}, // # Command setting of SPI block
{SSITX, 0x00080101}, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]
{SSITX, 0x0000010A}, //
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800D6}, // # Command setting of SPI block
{SSITX, 0x00000101}, // # Blanking period control (1) [PCLK Sync. Table2 for QVGA]
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800D7}, // # Command setting of SPI block
{SSITX, 0x00080110}, // # Blanking period control (2) [PCLK Sync. Table2 for QVGA]
{SSITX, 0x0000010A}, //
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800D8}, // # Command setting of SPI block
{SSITX, 0x00000101}, // # CKV timing control on/off [PCLK Sync. Table2 for QVGA]
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800D9}, // # Command setting of SPI block
{SSITX, 0x00080100}, // # CKV1,2 timing control [PCLK Sync. Table2 for QVGA]
{SSITX, 0x00000114}, //
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800DE}, // # Command setting of SPI block
{SSITX, 0x00080100}, // # OEV timing control [PCLK Sync. Table2 for QVGA]
{SSITX, 0x00000114}, //
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800DF}, // # Command setting of SPI block
{SSITX, 0x00080112}, // # ASW timing control (1) [PCLK Sync. Table2 for QVGA]
{SSITX, 0x0000013F}, //
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800E0}, // # Command setting of SPI block
{SSITX, 0x0000010B}, // # ASW timing control (2) [PCLK Sync. Table2 for QVGA]
{SSITX, 0x000800E2}, // # Command setting of SPI block
{SSITX, 0x00000101}, // # Built-in oscillator frequency division setup [Frequency division ratio : 2 (60Hq)
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800E3}, // # Command setting of SPI block
{SSITX, 0x00000136}, // # Built-in oscillator clock count setup
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800E4}, // # Command setting of SPI block
{SSITX, 0x00080100}, // # CKV timing control for using build-in osc
{SSITX, 0x00000103}, //
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800E5}, // # Command setting of SPI block
{SSITX, 0x00080102}, // # OEV timing control for using build-in osc
{SSITX, 0x00000104}, //
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800E6}, // # Command setting of SPI block
{SSITX, 0x00000103}, // # DCEV timing control for using build-in osc
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800E7}, // # Command setting of SPI block
{SSITX, 0x00080104}, // # ASW timing setup for using build-in osc(1)
{SSITX, 0x0000010A}, //
{0, 2}, // wait_ms(2); // # Wait SPI fifo empty
{SSITX, 0x000800E8}, // # Command setting of SPI block
{SSITX, 0x00000104}, // # ASW timing setup for using build-in osc(2)
{CLKENB, 0x000001EF}, // # SYS.CLKENB # DCLK enable
{START, 0x00000000}, // # LCD.START # LCDC wait_ms( mode
{WRSTB, 0x0000003F}, // # LCD.WRSTB # write_client_reg( strobe
{RDSTB, 0x00000432}, // # LCD.RDSTB # Read strobe
{PORT_ENB, 0x00000002}, // # LCD.PORT_ENB # Asynchronous port enable
{VSYNIF, 0x00000000}, // # LCD.VSYNCIF # VSYNC I/F mode set
{ASY_DATA, 0x80000000}, // # LCD.ASY_DATx # Index setting of SUB LCDD
{ASY_DATB, 0x00000001}, // # Oscillator start
{ASY_CMDSET, 0x00000005}, // # LCD.ASY_CMDSET # Direct command transfer enable
{ASY_CMDSET, 0x00000004}, // # LCD.ASY_CMDSET # Direct command transfer disable
{0, 10}, // wait_ms(10);
{ASY_DATA, 0x80000000}, // # LCD.ASY_DATx # DUMMY write_client_reg(<28>@*NOTE2
{ASY_DATB, 0x80000000}, //
{ASY_DATC, 0x80000000}, //
{ASY_DATD, 0x80000000}, //
{ASY_CMDSET, 0x00000009}, // # LCD.ASY_CMDSET
{ASY_CMDSET, 0x00000008}, // # LCD.ASY_CMDSET
{ASY_DATA, 0x80000007}, // # LCD.ASY_DATx # Index setting of SUB LCDD
{ASY_DATB, 0x00004005}, // # LCD driver control
{ASY_CMDSET, 0x00000005}, // # LCD.ASY_CMDSET # Direct command transfer enable
{ASY_CMDSET, 0x00000004}, // # LCD.ASY_CMDSET # Direct command transfer disable
{0, 20}, // wait_ms(20);
{ASY_DATA, 0x80000059}, // # LCD.ASY_DATx # Index setting of SUB LCDD
{ASY_DATB, 0x00000000}, // # LTPS I/F control
{ASY_CMDSET, 0x00000005}, // # LCD.ASY_CMDSET # Direct command transfer enable
{ASY_CMDSET, 0x00000004}, // # LCD.ASY_CMDSET # Direct command transfer disable
{VSYNIF, 0x00000001}, // # LCD.VSYNCIF # VSYNC I/F mode OFF
{PORT_ENB, 0x00000001}, // # LCD.PORT_ENB # SYNC I/F output select
/******************************/
{VSYNIF, 0x00000001}, // VSYNC I/F mode OFF
{PORT_ENB, 0x00000001}, // SYNC I/F mode ON
{BITMAP1, 0x01E000F0}, // MDC.BITMAP2 ); // Setup of PITCH size to Frame buffer1
{BITMAP2, 0x01E000F0}, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2
{BITMAP3, 0x01E000F0}, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3
{BITMAP4, 0x00DC00B0}, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4
{CLKENB, 0x000001EF}, // SYS.CLKENB ); // DCLK supply
{PORT_ENB, 0x00000001}, // LCD.PORT_ENB ); // Synchronous port enable
{PORT, 0x00000004}, // LCD.PORT ); // Polarity of DE is set to high active
{PXL, 0x00000002}, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output)
{MPLFBUF, 0x00000000}, // LCD.MPLFBUF ); // Select the reading buffer
{HCYCLE, 0x0000010b}, // LCD.HCYCLE ); // Setup to VGA size
{HSW, 0x00000003}, // LCD.HSW
{HDE_START, 0x00000007}, // LCD.HDE_START
{HDE_SIZE, 0x000000EF}, // LCD.HDE_SIZE
{VCYCLE, 0x00000285}, // LCD.VCYCLE
{VSW, 0x00000001}, // LCD.VSW
{VDE_START, 0x00000003}, // LCD.VDE_START
{VDE_SIZE, 0x0000027F}, // LCD.VDE_SIZE
{START, 0x00000001}, // LCD.START ); // LCDC - Pixel data transfer start
{0, 10}, // wait_ms( 10 );
{SSITX, 0x000800BC}, // SPI.SSITX ); // Command setting of SPI block
{SSITX, 0x00000180}, // Display data setup
{SSITX, 0x0008003B}, // Command setting of SPI block
{SSITX, 0x00000100}, // Quad Data configuration - VGA
{0, 1}, // wait_ms( 1 ); // Wait SPI fifo empty
{SSITX, 0x000800B0}, // Command setting of SPI block
{SSITX, 0x00000116}, // Power supply ON/OFF control
{0, 1}, // wait_ms( 1 ); // Wait SPI fifo empty
{SSITX, 0x000800B8}, // Command setting of SPI block
{SSITX, 0x000801FF}, // Output control
{SSITX, 0x000001F5},
{0, 1}, // wait_ms( 1); // Wait SPI fifo empty
{SSITX, 0x00000011}, // wait_ms(-out (Command only)
{SSITX, 0x00000029}, // Display on (Command only)
{SYSTEM_BLOCK1_BASE, 0x00000002}, // # wakeREQ -> GPIO
{0, 0}
};
static void _panel_init(struct init_table *init_table)
{
unsigned n;
dprintf(INFO, "panel_init()\n");
n = 0;
while (init_table[n].reg != 0 || init_table[n].val != 0) {
if (init_table[n].reg != 0)
mddi_remote_write(init_table[n].val, init_table[n].reg);
else
mdelay(init_table[n].val);
n++;
}
dprintf(INFO, "panel_init() done\n");
}
void panel_init(struct mddi_client_caps *client_caps)
{
switch (client_caps->manufacturer_name) {
case 0xd263: // Toshiba
dprintf(INFO, "Found Toshiba panel\n");
_panel_init(toshiba_480x640_init_table);
break;
case 0x4474: //??
if (client_caps->product_code == 0xc065)
dprintf(INFO, "Found WVGA panel\n");
break;
}
}
void panel_poweron(void)
{
gpio_set(88, 0);
gpio_config(88, GPIO_OUTPUT);
udelay(10);
gpio_set(88, 1);
mdelay(10);
//mdelay(1000); // uncomment for second stage boot
}
void panel_backlight(int on)
{
}

127
bootable/bootloader/lk/platform/msm7x27a/platform.c Executable file
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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Google, Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <reg.h>
#include <debug.h>
#include <kernel/thread.h>
#include <platform/debug.h>
#include <platform/iomap.h>
#include <platform/irqs.h>
#include <mddi.h>
#include <dev/fbcon.h>
#include <dev/gpio.h>
#include <smem.h>
static struct fbcon_config *fb_config;
static uint32_t ticks_per_sec = 0;
void platform_init_interrupts(void);
void platform_init_timer();
void uart3_clock_init(void);
void uart_init(void);
void acpu_clock_init(void);
void mddi_clock_init(unsigned num, unsigned rate);
unsigned board_msm_id(void);
static int target_uses_qgic;
int debug_timer = 0, gpt_timer = 0, usb_hs_int = 0;
void platform_early_init(void)
{
#if WITH_DEBUG_UART
uart1_clock_init();
uart_init();
#endif
if(machine_is_8x25()) {
qgic_init();
target_uses_qgic = 1;
debug_timer = (GIC_PPI_START + 2);
gpt_timer = (GIC_PPI_START + 3);
usb_hs_int = INT_USB_HS_GIC;
} else {
platform_init_interrupts();
debug_timer = 8;
gpt_timer = 7;
usb_hs_int = INT_USB_HS_VIC;
}
platform_init_timer();
}
void platform_init(void)
{
dprintf(INFO, "platform_init()\n");
acpu_clock_init();
}
void platform_uninit(void)
{
#if DISPLAY_SPLASH_SCREEN
display_shutdown();
#endif
platform_uninit_timer();
}
/* Initialize DGT timer */
void platform_init_timer(void)
{
/* disable timer */
writel(0, DGT_ENABLE);
ticks_per_sec = 19200000; /* Uses TCXO (19.2 MHz) */
}
/* Returns timer ticks per sec */
uint32_t platform_tick_rate(void)
{
return ticks_per_sec;
}
bool machine_is_7x25a(void)
{
if ((board_msm_id() == MSM7225A) || (board_msm_id() == MSM7625A))
return 1;
else
return 0;
}
int target_supports_qgic()
{
return target_uses_qgic;
}

27
bootable/bootloader/lk/platform/msm7x27a/rules.mk Normal file
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LOCAL_DIR := $(GET_LOCAL_DIR)
ARCH := arm
# Cann't use cortex-a5 as its not supported by gcc 4.4.0
ARM_CPU := cortex-a8
CPU := generic
DEFINES += ARM_CPU_CORE_A5
MMC_SLOT := 3
DEFINES += WITH_CPU_EARLY_INIT=1 MMC_SLOT=$(MMC_SLOT)
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
MODULES += dev/fbcon
OBJS += \
$(LOCAL_DIR)/arch_init.o \
$(LOCAL_DIR)/platform.o \
$(LOCAL_DIR)/interrupts.o \
$(LOCAL_DIR)/gpio.o \
$(LOCAL_DIR)/acpuclock.o
LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
include platform/msm_shared/rules.mk