M7350v1_en_gpl

bootable/bootloader/lk/platform/mdm9x25/acpuclock.c

@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *   * Neither the name of Linux Foundation nor
+ *     the names of its contributors may be used to endorse or promote
+ *     products derived from this software without specific prior written
+ *     permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <err.h>
+#include <assert.h>
+#include <debug.h>
+#include <reg.h>
+#include <clock.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+#include <platform/timer.h>
+
+void hsusb_clock_init(void)
+{
+	int ret;
+	struct clk *iclk;
+	struct clk *cclk;
+
+	iclk = clk_get("usb_iface_clk");
+	cclk = clk_get("usb_core_clk");
+
+	ASSERT(iclk);
+	ASSERT(cclk);
+
+	/* Disable interface and core clk */
+	clk_disable(iclk);
+	clk_disable(cclk);
+
+	/* Start the block reset for usb */
+	writel(1, USB_HS_BCR);
+
+	/* Take usb block out of reset */
+	writel(0, USB_HS_BCR);
+
+	ret = clk_enable(iclk);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	ret = clk_set_rate(cclk, 75000000);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set_rate of usb_core_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	ret = clk_enable(cclk);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to enable usb_core_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+}
+
+void clock_config_uart_dm(uint8_t id)
+{
+	int ret;
+	char clk_name[64];
+
+    ret = clk_get_set_enable("uart_iface_clk", 0, 1);
+    if (ret)
+	{
+		dprintf(CRITICAL, "failed to set uart_iface_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	snprintf(clk_name, 64, "uart%u_core_clk", id);
+
+    ret = clk_get_set_enable(clk_name, 7372800, 1);
+	if (ret)
+	{
+		dprintf(CRITICAL, "failed to set uart%u_core_clk ret = %d\n", id, ret);
+		ASSERT(0);
+	}
+}
+

bootable/bootloader/lk/platform/mdm9x25/gpio.c

@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *   * Neither the name of Linux Foundation nor
+ *     the names of its contributors may be used to endorse or promote
+ *     products derived from this software without specific prior written
+ *     permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <reg.h>
+#include <debug.h>
+#include <platform/iomap.h>
+#include <platform/gpio.h>
+
+void gpio_tlmm_config(uint32_t gpio,
+					  uint8_t  func,
+					  uint8_t  dir,
+					  uint8_t  pull,
+					  uint8_t  drvstr,
+					  uint32_t enable)
+{
+	uint32_t val = 0;
+
+	val |= pull;
+	val |= func << 2;
+	val |= drvstr << 6;
+	val |= enable << 9;
+
+	writel(val, GPIO_CONFIG_ADDR(gpio));
+
+	return;
+}
+
+void gpio_set(uint32_t gpio, uint32_t dir)
+{
+	writel(dir, GPIO_IN_OUT_ADDR(gpio));
+
+	return;
+}
+
+uint32_t gpio_get_state(uint32_t gpio)
+{
+	return readl(GPIO_IN_OUT_ADDR(gpio));
+}
+
+void gpio_config_uart_dm(uint8_t id)
+{
+	if (id == 3)
+	{
+		/* configure rx gpio. */
+		gpio_tlmm_config(9, 1, GPIO_INPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
+
+		/* configure tx gpio. */
+		gpio_tlmm_config(8, 1, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
+	}
+	else
+	{
+		dprintf(CRITICAL, "GPIO config for UART id = %d not supported.\n", id);
+		ASSERT(0);
+	}
+}
+

bootable/bootloader/lk/platform/mdm9x25/include/platform/clock.h

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *   * Neither the name of Linux Foundation nor
+ *     the names of its contributors may be used to endorse or promote
+ *     products derived from this software without specific prior written
+ *     permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_MDM9625_CLOCK_H
+#define __PLATFORM_MDM9625_CLOCK_H
+
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+
+void hsusb_clock_init(void);
+void clock_config_uart_dm(uint8_t id);
+
+#endif

bootable/bootloader/lk/platform/mdm9x25/include/platform/gpio.h

@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *   * Neither the name of Linux Foundation nor
+ *     the names of its contributors may be used to endorse or promote
+ *     products derived from this software without specific prior written
+ *     permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_MDM9625_GPIO_H
+#define __PLATFORM_MDM9625_GPIO_H
+
+/* GPIO TLMM: Direction */
+#define GPIO_INPUT      0
+#define GPIO_OUTPUT     1
+
+/* GPIO TLMM: Pullup/Pulldown */
+#define GPIO_NO_PULL    0
+#define GPIO_PULL_DOWN  1
+#define GPIO_KEEPER     2
+#define GPIO_PULL_UP    3
+
+/* GPIO TLMM: Drive Strength */
+#define GPIO_2MA        0
+#define GPIO_4MA        1
+#define GPIO_6MA        2
+#define GPIO_8MA        3
+#define GPIO_10MA       4
+#define GPIO_12MA       5
+#define GPIO_14MA       6
+#define GPIO_16MA       7
+
+/* GPIO TLMM: Status */
+#define GPIO_ENABLE     0
+#define GPIO_DISABLE    1
+
+void gpio_tlmm_config(uint32_t gpio,
+					  uint8_t  func,
+					  uint8_t  dir,
+					  uint8_t  pull,
+					  uint8_t  drvstr,
+					  uint32_t enable);
+uint32_t gpio_get_state(uint32_t gpio);
+void gpio_set(uint32_t gpio, uint32_t dir);
+void gpio_config_uart_dm(uint8_t id);
+
+#endif

bootable/bootloader/lk/platform/mdm9x25/include/platform/iomap.h

@@ -0,0 +1,127 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PLATFORM_MDM9625_IOMAP_H_
+#define _PLATFORM_MDM9625_IOMAP_H_
+
+#define MSM_IOMAP_BASE            0xF9000000
+#define MSM_IOMAP_END             0xFEFFFFFF
+
+#define MSM_SHARED_BASE           0x00000000
+
+/*SDRAM start address */
+#define SDRAM_START_ADDR          0x00000000
+
+#define MSM_SHARED_IMEM_BASE      0xFC42A800
+#define RESTART_REASON_ADDR       (MSM_SHARED_IMEM_BASE + 0x65C)
+
+#define MSM_SHARED_IMEM_BASE_V2   0xFE807800
+#define RESTART_REASON_ADDR_V2    (MSM_SHARED_IMEM_BASE_V2 + 0x65C)
+
+#define ELAN_A5SS_BASE            0xF9000000
+
+/* Peripheral subsystem */
+#define PERIPH_SS_BASE            0xF9800000
+#define PERIPH_SS_QPIC_BASE       0xF9AC4000
+
+#define CLK_CTL_BASE              0xFC400000 /* GCC base */
+
+/* MPM2_MPM */
+#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL    0xFC4A3000
+#define MPM2_MPM_PS_HOLD                     0xFC4AB000
+
+#define SPMI_BASE                 0xFC4C0000
+#define SPMI_GENI_BASE            (SPMI_BASE + 0xA000)
+#define SPMI_PIC_BASE             (SPMI_BASE + 0xB000)
+#define TLMM_BASE_ADDR            0xFD500000
+
+/* QGIC2 */
+#define MSM_GIC_DIST_BASE         (ELAN_A5SS_BASE + 0x0000)
+#define MSM_GIC_CPU_BASE          (ELAN_A5SS_BASE + 0x2000)
+
+/* QTMR */
+#define APCS_F0_QTMR_V1_BASE      (ELAN_A5SS_BASE + 0x21000)
+#define QTMR_BASE                  APCS_F0_QTMR_V1_BASE
+
+/* GPIO */
+#define GPIO_CONFIG_ADDR(x)       (TLMM_BASE_ADDR + 0x10000 + 0x1000 + (x)*0x10)
+#define GPIO_IN_OUT_ADDR(x)       (TLMM_BASE_ADDR + 0x10000 + 0x1004 + (x)*0x10)
+
+/* USB */
+#define MSM_USB_BASE              (PERIPH_SS_BASE + 0x00255000)
+
+/* UART */
+#define MSM_UART2_BASE             0xF991F000
+
+/* NAND */
+#define MSM_NAND_BASE              0xF9AF0000
+/* NAND BAM */
+#define MSM_NAND_BAM_BASE          0xF9AC4000
+
+/************ CLOCKS ***********/
+
+/* GPLL */
+#define GPLL0_STATUS                         (CLK_CTL_BASE + 0x001C)
+#define APCS_GPLL_ENA_VOTE                   (CLK_CTL_BASE + 0x1480)
+
+/* UART */
+
+#define BLSP1_AHB_CBCR                       (CLK_CTL_BASE + 0x5C4)
+
+#define BLSP1_UART1_APPS_CBCR                (CLK_CTL_BASE + 0x684)
+#define BLSP1_UART1_APPS_CMD_RCGR            (CLK_CTL_BASE + 0x68C)
+#define BLSP1_UART1_APPS_CFG_RCGR            (CLK_CTL_BASE + 0x690)
+#define BLSP1_UART1_APPS_M                   (CLK_CTL_BASE + 0x694)
+#define BLSP1_UART1_APPS_N                   (CLK_CTL_BASE + 0x698)
+#define BLSP1_UART1_APPS_D                   (CLK_CTL_BASE + 0x69C)
+
+#define BLSP1_UART3_APPS_CBCR                (CLK_CTL_BASE + 0x784)
+#define BLSP1_UART3_APPS_CMD_RCGR            (CLK_CTL_BASE + 0x78C)
+#define BLSP1_UART3_APPS_CFG_RCGR            (CLK_CTL_BASE + 0x790)
+#define BLSP1_UART3_APPS_M                   (CLK_CTL_BASE + 0x794)
+#define BLSP1_UART3_APPS_N                   (CLK_CTL_BASE + 0x798)
+#define BLSP1_UART3_APPS_D                   (CLK_CTL_BASE + 0x79C)
+
+#define BLSP1_UART2_APPS_CBCR                (CLK_CTL_BASE + 0x704)
+#define BLSP1_UART2_APPS_CMD_RCGR            (CLK_CTL_BASE + 0x70C)
+#define BLSP1_UART2_APPS_CFG_RCGR            (CLK_CTL_BASE + 0x710)
+#define BLSP1_UART2_APPS_M                   (CLK_CTL_BASE + 0x714)
+#define BLSP1_UART2_APPS_N                   (CLK_CTL_BASE + 0x718)
+#define BLSP1_UART2_APPS_D                   (CLK_CTL_BASE + 0x71C)
+
+#define APCS_CLOCK_BRANCH_ENA_VOTE           (CLK_CTL_BASE + 0x1484)
+
+/* USB */
+#define USB_HS_BCR                           (CLK_CTL_BASE + 0x480)
+#define USB_HS_SYSTEM_CBCR                   (CLK_CTL_BASE + 0x484)
+#define USB_HS_AHB_CBCR                      (CLK_CTL_BASE + 0x488)
+#define GCC_USB_HS_INACTIVITY_TIMERS_CBCR    (CLK_CTL_BASE + 0x48C)
+#define USB_HS_SYSTEM_CMD_RCGR               (CLK_CTL_BASE + 0x490)
+#define USB_HS_SYSTEM_CFG_RCGR               (CLK_CTL_BASE + 0x494)
+
+#endif

bootable/bootloader/lk/platform/mdm9x25/include/platform/irqs.h

@@ -0,0 +1,59 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of The Linux Foundation nor
+ *       the names of its contributors may be used to endorse or promote
+ *       products derived from this software without specific prior written
+ *       permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __IRQS_9625_H
+#define __IRQS_9625_H
+
+/* TBD: The numbers need to be reviewed */
+
+/* 0-15:  STI/SGI (software triggered/generated interrupts)
+ * 16-31: PPI (private peripheral interrupts)
+ * 32+:   SPI (shared peripheral interrupts)
+ */
+
+#define GIC_PPI_START                          16
+#define GIC_SPI_START                          32
+
+#define INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP      (GIC_SPI_START + 7)
+
+#define USB1_HS_BAM_IRQ                        (GIC_SPI_START + 135)
+#define USB1_HS_IRQ                            (GIC_SPI_START + 134)
+
+/* Retrofit universal macro names */
+#define INT_USB_HS                             USB1_HS_IRQ
+
+#define EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ         (GIC_SPI_START + 190)
+
+#define NR_MSM_IRQS                            256
+#define NR_GPIO_IRQS                           173
+#define NR_BOARD_IRQS                          0
+
+#define NR_IRQS                                (NR_MSM_IRQS + NR_GPIO_IRQS + \
+                                               NR_BOARD_IRQS)
+
+#endif /* __IRQS_9625_H */

bootable/bootloader/lk/platform/mdm9x25/mdm9x25-clock.c

@@ -0,0 +1,291 @@
+/*
+ * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *   * Neither the name of Linux Foundation nor
+ *     the names of its contributors may be used to endorse or promote
+ *     products derived from this software without specific prior written
+ *     permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <reg.h>
+#include <err.h>
+#include <clock.h>
+#include <clock_pll.h>
+#include <clock_lib2.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+
+
+/* Mux source select values */
+#define cxo_source_val    0
+#define gpll0_source_val  1
+
+struct clk_freq_tbl rcg_dummy_freq = F_END;
+
+
+/* Clock Operations */
+static struct clk_ops clk_ops_branch =
+{
+	.enable     = clock_lib2_branch_clk_enable,
+	.disable    = clock_lib2_branch_clk_disable,
+	.set_rate   = clock_lib2_branch_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg_mnd =
+{
+	.enable     = clock_lib2_rcg_enable,
+	.set_rate   = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg =
+{
+	.enable     = clock_lib2_rcg_enable,
+	.set_rate   = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_cxo =
+{
+	.enable     = cxo_clk_enable,
+	.disable    = cxo_clk_disable,
+};
+
+static struct clk_ops clk_ops_pll_vote =
+{
+	.enable     = pll_vote_clk_enable,
+	.disable    = pll_vote_clk_disable,
+	.auto_off   = pll_vote_clk_disable,
+	.is_enabled = pll_vote_clk_is_enabled,
+};
+
+static struct clk_ops clk_ops_vote =
+{
+	.enable     = clock_lib2_vote_clk_enable,
+	.disable    = clock_lib2_vote_clk_disable,
+};
+
+/* Clock Sources */
+static struct fixed_clk cxo_clk_src =
+{
+	.c = {
+		.rate     = 19200000,
+		.dbg_name = "cxo_clk_src",
+		.ops      = &clk_ops_cxo,
+	},
+};
+
+static struct pll_vote_clk gpll0_clk_src =
+{
+	.en_reg       = (void *) APCS_GPLL_ENA_VOTE,
+	.en_mask      = BIT(0),
+	.status_reg   = (void *) GPLL0_STATUS,
+	.status_mask  = BIT(17),
+	.parent       = &cxo_clk_src.c,
+
+	.c = {
+		.rate     = 600000000,
+		.dbg_name = "gpll0_clk_src",
+		.ops      = &clk_ops_pll_vote,
+	},
+};
+
+/* UART Clocks */
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+	.cbcr_reg = BLSP1_AHB_CBCR,
+	.vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask = BIT(17),
+
+	.c = {
+		.dbg_name = "gcc_blsp1_ahb_clk",
+		.ops = &clk_ops_vote,
+	},
+};
+
+static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] =
+{
+	F( 3686400,  gpll0,    1,  96,  15625),
+	F( 7372800,  gpll0,    1, 192,  15625),
+	F(14745600,  gpll0,    1, 384,  15625),
+	F(16000000,  gpll0,    5,   2,     15),
+	F(19200000,    cxo,    1,   0,      0),
+	F(24000000,  gpll0,    5,   1,      5),
+	F(32000000,  gpll0,    1,   4,     75),
+	F(40000000,  gpll0,   15,   0,      0),
+	F(46400000,  gpll0,    1,  29,    375),
+	F(48000000,  gpll0, 12.5,   0,      0),
+	F(51200000,  gpll0,    1,  32,    375),
+	F(56000000,  gpll0,    1,   7,     75),
+	F(58982400,  gpll0,    1, 1536, 15625),
+	F(60000000,  gpll0,   10,   0,      0),
+	F_END
+};
+
+static struct rcg_clk blsp1_uart1_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP1_UART1_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP1_UART1_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP1_UART1_APPS_M,
+	.n_reg        = (uint32_t *) BLSP1_UART1_APPS_N,
+	.d_reg        = (uint32_t *) BLSP1_UART1_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp1_uart1_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct rcg_clk blsp1_uart2_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP1_UART2_APPS_M,
+	.n_reg        = (uint32_t *) BLSP1_UART2_APPS_N,
+	.d_reg        = (uint32_t *) BLSP1_UART2_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp1_uart2_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct rcg_clk blsp1_uart3_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP1_UART3_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP1_UART3_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP1_UART3_APPS_M,
+	.n_reg        = (uint32_t *) BLSP1_UART3_APPS_N,
+	.d_reg        = (uint32_t *) BLSP1_UART3_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp1_uart3_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_blsp1_uart1_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP1_UART1_APPS_CBCR,
+	.parent       = &blsp1_uart1_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp1_uart1_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk gcc_blsp1_uart2_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP1_UART2_APPS_CBCR,
+	.parent       = &blsp1_uart2_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp1_uart2_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk gcc_blsp1_uart3_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP1_UART3_APPS_CBCR,
+	.parent       = &blsp1_uart3_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp1_uart3_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+/* USB Clocks */
+static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
+{
+	F(75000000,  gpll0,   8,   0,   0),
+	F_END
+};
+
+static struct rcg_clk usb_hs_system_clk_src =
+{
+	.cmd_reg      = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR,
+
+	.set_rate     = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl     = ftbl_gcc_usb_hs_system_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "usb_hs_system_clk",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct branch_clk gcc_usb_hs_system_clk =
+{
+	.cbcr_reg     = (uint32_t *) USB_HS_SYSTEM_CBCR,
+	.parent       = &usb_hs_system_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_usb_hs_system_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk gcc_usb_hs_ahb_clk =
+{
+	.cbcr_reg     = (uint32_t *) USB_HS_AHB_CBCR,
+	.has_sibling  = 1,
+
+	.c = {
+		.dbg_name = "gcc_usb_hs_ahb_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+/* Clock lookup table */
+static struct clk_lookup mdm_9625_clocks[] =
+{
+	CLK_LOOKUP("uart_iface_clk", gcc_blsp1_ahb_clk.c),
+	CLK_LOOKUP("uart1_core_clk", gcc_blsp1_uart1_apps_clk.c),
+	CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
+	CLK_LOOKUP("uart3_core_clk", gcc_blsp1_uart3_apps_clk.c),
+
+	CLK_LOOKUP("usb_iface_clk",  gcc_usb_hs_ahb_clk.c),
+	CLK_LOOKUP("usb_core_clk",   gcc_usb_hs_system_clk.c),
+
+};
+
+
+void platform_clock_init(void)
+{
+	clk_init(mdm_9625_clocks, ARRAY_SIZE(mdm_9625_clocks));
+}

bootable/bootloader/lk/platform/mdm9x25/platform.c

@@ -0,0 +1,254 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <platform.h>
+#include <qgic.h>
+#include <qtimer.h>
+#include <board.h>
+#include <qpic_nand.h>
+#include <mmu.h>
+#include <arch/arm/mmu.h>
+#include <platform/iomap.h>
+#include <target.h>
+#include <smem.h>
+#include <reg.h>
+#include <board.h>
+#include <boot_stats.h>
+
+extern struct smem_ram_ptable* target_smem_ram_ptable_init();
+
+#define MB                                  (1024*1024)
+
+#define MSM_IOMAP_SIZE                      ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
+
+/* LK memory - Strongly ordered, executable */
+#define LK_MEMORY                             (MMU_MEMORY_TYPE_NORMAL | \
+                                              MMU_MEMORY_AP_READ_WRITE)
+/* Scratch memory - Strongly ordered, non-executable */
+#define SCRATCH_MEMORY                        (MMU_MEMORY_TYPE_NORMAL | \
+                                              MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+/* Peripherals - shared device */
+#define IOMAP_MEMORY                          (MMU_MEMORY_TYPE_DEVICE_SHARED | \
+                                              MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+#define SCRATCH_REGION1_VIRT_START            SCRATCH_REGION1
+#define SCRATCH_REGION2_VIRT_START            (SCRATCH_REGION1_VIRT_START + \
+                                              (SCRATCH_REGION1_SIZE))
+
+#define SDRAM_BANK0_LAST_FIXED_ADDR           (SCRATCH_REGION2 + SCRATCH_REGION2_SIZE)
+
+/* Map all the accesssible memory according to the following rules:
+ * 1. Map 1MB from MSM_SHARED_BASE with 1 -1 mapping.
+ * 2. Map MEMBASE - MEMSIZE with 1 -1 mapping.
+ * 3. Map all the scratch regions immediately after Appsbl memory.
+ *     Virtual addresses start right after Appsbl Virtual address.
+ * 4. Map all the IOMAP space with 1 - 1 mapping.
+ * 5. Map all the rest of the SDRAM/ IMEM regions as 1 -1.
+ */
+mmu_section_t mmu_section_table[] = {
+/*   Physical addr,         Virtual addr,               Size (in MB),              Flags   */
+	{MSM_SHARED_BASE,       MSM_SHARED_BASE,            1,                         SCRATCH_MEMORY},
+	{MEMBASE,               MEMBASE,                    MEMSIZE / MB,              LK_MEMORY},
+	{SCRATCH_REGION1,       SCRATCH_REGION1_VIRT_START, SCRATCH_REGION1_SIZE / MB, SCRATCH_MEMORY},
+	{SCRATCH_REGION2,       SCRATCH_REGION2_VIRT_START, SCRATCH_REGION2_SIZE / MB, SCRATCH_MEMORY},
+	{MSM_IOMAP_BASE,        MSM_IOMAP_BASE,             MSM_IOMAP_SIZE,            IOMAP_MEMORY},
+};
+
+/* Boot timestamps */
+#define BS_INFO_OFFSET     (0x6B0)
+#define BS_INFO_ADDR_V1    (MSM_SHARED_IMEM_BASE    + BS_INFO_OFFSET)
+#define BS_INFO_ADDR_V2    (MSM_SHARED_IMEM_BASE_V2 + BS_INFO_OFFSET)
+
+void platform_early_init(void)
+{
+	/* Initialize board identifier data */
+	board_init();
+
+	/* Initialize clock driver */
+	platform_clock_init();
+
+	/* Initialize interrupt controller */
+	qgic_init();
+
+	/* timer */
+	qtimer_init();
+}
+
+void platform_init(void)
+{
+	dprintf(INFO, "platform_init()\n");
+}
+
+static uint32_t platform_get_sclk_count(void)
+{
+	return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
+}
+
+static uint32_t kernel_load_start;
+void bs_set_timestamp(enum bs_entry bs_id)
+{
+	void *bs_imem;
+	uint32_t soc_ver = board_soc_version();
+
+	if (bs_id >= BS_MAX) {
+		dprintf(CRITICAL, "bad bs id: %u, max: %u\n", bs_id, BS_MAX);
+		ASSERT(0);
+	}
+
+	if (bs_id == BS_KERNEL_LOAD_START) {
+		kernel_load_start = platform_get_sclk_count();
+		return;
+	}
+
+	if (soc_ver < BOARD_SOC_VERSION2)
+		bs_imem = (void *)BS_INFO_ADDR_V1;
+	else
+		bs_imem = (void *)BS_INFO_ADDR_V2;
+
+	if(bs_id == BS_KERNEL_LOAD_DONE)
+		writel(platform_get_sclk_count() - kernel_load_start,
+			   bs_imem + (sizeof(uint32_t) * BS_KERNEL_LOAD_TIME));
+	else
+		writel(platform_get_sclk_count(),
+			   bs_imem + (sizeof(uint32_t) * bs_id));
+}
+
+void platform_uninit(void)
+{
+	qtimer_uninit();
+	qpic_nand_uninit();
+}
+
+void platform_init_mmu_mappings(void)
+{
+	struct smem_ram_ptable *ram_ptable;
+	uint32_t i;
+	uint32_t sections;
+	uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+	uint32_t last_fixed_addr = SDRAM_BANK0_LAST_FIXED_ADDR;
+
+	ram_ptable = target_smem_ram_ptable_init();
+
+	/* Configure the MMU page entries for SDRAM and IMEM memory read
+	   from the smem ram table*/
+	for(i = 0; i < ram_ptable->len; i++)
+	{
+		if((ram_ptable->parts[i].category == IMEM) || (ram_ptable->parts[i].category == SDRAM))
+		{
+			/* First bank info is added according to the static table - mmu_section_table. */
+			if((ram_ptable->parts[i].start <= last_fixed_addr) &&
+			   ((ram_ptable->parts[i].start + ram_ptable->parts[i].size) >= last_fixed_addr))
+					continue;
+
+			/* Check to ensure that start address is 1MB aligned */
+			ASSERT((ram_ptable->parts[i].start & 0xFFFFF) == 0);
+
+			sections = (ram_ptable->parts[i].size) / MB;
+
+			while(sections--)
+			{
+				arm_mmu_map_section(ram_ptable->parts[i].start + sections * MB,
+									ram_ptable->parts[i].start + sections * MB,
+									SCRATCH_MEMORY);
+			}
+		}
+    }
+
+	/* Configure the MMU page entries for memory read from the
+	   mmu_section_table */
+	for (i = 0; i < table_size; i++)
+	{
+		sections = mmu_section_table[i].num_of_sections;
+
+		while (sections--)
+		{
+			arm_mmu_map_section(mmu_section_table[i].paddress + sections * MB,
+								mmu_section_table[i].vaddress + sections * MB,
+								mmu_section_table[i].flags);
+		}
+	}
+}
+
+addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr)
+{
+	uint32_t paddr;
+	uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+	uint32_t limit;
+
+	for (uint32_t i = 0; i < table_size; i++)
+	{
+		limit = (mmu_section_table[i].num_of_sections * MB) - 0x1;
+
+		if (virt_addr >= mmu_section_table[i].vaddress &&
+			virt_addr <= (mmu_section_table[i].vaddress + limit))
+		{
+				paddr = mmu_section_table[i].paddress + (virt_addr - mmu_section_table[i].vaddress);
+				return paddr;
+		}
+	}
+	/* No special mapping found.
+	 * Assume 1-1 mapping.
+	 */
+	 paddr = virt_addr;
+
+	return paddr;
+}
+
+addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr)
+{
+	uint32_t vaddr;
+	uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+	uint32_t limit;
+
+	for (uint32_t i = 0; i < table_size; i++)
+	{
+		limit = (mmu_section_table[i].num_of_sections * MB) - 0x1;
+
+		if (phys_addr >= mmu_section_table[i].paddress &&
+			phys_addr <= (mmu_section_table[i].paddress + limit))
+		{
+				vaddr = mmu_section_table[i].vaddress + (phys_addr - mmu_section_table[i].paddress);
+				return vaddr;
+		}
+	}
+
+	/* No special mapping found.
+	 * Assume 1-1 mapping.
+	 */
+	 vaddr = phys_addr;
+
+	return vaddr;
+}
+
+/* Do not use default identitiy mappings. */
+int platform_use_identity_mmu_mappings(void)
+{
+	return 0;
+}
+

bootable/bootloader/lk/platform/mdm9x25/rules.mk

@@ -0,0 +1,21 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+ARCH    := arm
+# Cann't use cortex-a5 as its not supported by gcc 4.4.0
+ARM_CPU := cortex-a8
+CPU     := generic
+
+DEFINES += ARM_CPU_CORE_A5
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
+
+OBJS += \
+	$(LOCAL_DIR)/platform.o \
+	$(LOCAL_DIR)/gpio.o \
+	$(LOCAL_DIR)/acpuclock.o \
+	$(LOCAL_DIR)/mdm9x25-clock.o
+
+LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
+
+include platform/msm_shared/rules.mk
+