M7350v1_en_gpl

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2024-09-09 08:52:07 +00:00
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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
* Copyright (c) 2009-2011, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <reg.h>
#include <stdint.h>
#include <debug.h>
#include <gsbi.h>
#include <platform/iomap.h>
#include <platform/clock.h>
/* Set rate and enable the clock */
void clock_config(uint32_t ns, uint32_t md, uint32_t ns_addr, uint32_t md_addr)
{
unsigned int val = 0;
/* Activate the reset for the M/N Counter */
val = 1 << 7;
writel(val, ns_addr);
/* Write the MD value into the MD register */
if (md_addr != 0x0)
writel(md, md_addr);
/* Write the ns value, and active reset for M/N Counter, again */
val = 1 << 7;
val |= ns;
writel(val, ns_addr);
/* De-activate the reset for M/N Counter */
val = 1 << 7;
val = ~val;
val = val & readl(ns_addr);
writel(val, ns_addr);
/* Enable the Clock Root */
val = 1 << 11;
val = val | readl(ns_addr);
writel(val, ns_addr);
/* Enable the Clock Branch */
val = 1 << 9;
val = val | readl(ns_addr);
writel(val, ns_addr);
/* Enable the M/N Counter */
val = 1 << 8;
val = val | readl(ns_addr);
writel(val, ns_addr);
}
void pll8_enable(void)
{
unsigned int curr_value = 0;
/* Vote for PLL8 to be enabled */
curr_value = readl(MSM_BOOT_PLL_ENABLE_SC0);
curr_value |= (1 << 8);
writel(curr_value, MSM_BOOT_PLL_ENABLE_SC0);
/* Proceed only after PLL is enabled */
while (!(readl(MSM_BOOT_PLL8_STATUS) & (1<<16)));
}
void acpu_clock_init(void)
{
/* ADM3: enable cc_adm0_clk */
writel( (1 << SC0_U_BRANCH_ENA_VOTE_ADM0) |
(1 << SC0_U_BRANCH_ENA_VOTE_ADM0_PBUS), SC0_U_BRANCH_ENA_VOTE);
}
void hsusb_clock_init(void)
{
uint32_t reg;
pll8_enable();
/* Setup USB HS1 System clock - 60 Mhz */
//TODO: Remove this when verify that this is already configured
if (!(readl(USB_HS1_SYSTEM_CLK_NS))){
clock_config(USB_XCVR_CLK_NS,
USB_XCVR_CLK_MD,
USB_HS1_SYSTEM_CLK_NS,
USB_HS1_SYSTEM_CLK_MD);
}
/* Setup USB HS1 XCVR clock - 60 Mhz */
clock_config(USB_XCVR_CLK_NS,
USB_XCVR_CLK_MD,
USB_HS1_XCVR_FS_CLK_NS,
USB_HS1_XCVR_FS_CLK_MD);
/* HS-USB: enable cc_usb_hs1_hs_clk */
reg = readl(USB_HS1_HCLK_CTL);
reg |= 0x1 << 4;
writel( reg, USB_HS1_HCLK_CTL);
}
/* Configure UART clock - based on the gsbi id */
void clock_config_uart_dm(uint8_t id)
{
/* Enable gsbi_uart_clk */
clock_config(UART_DM_CLK_NS_115200,
UART_DM_CLK_MD_115200,
GSBIn_UART_APPS_NS(id),
GSBIn_UART_APPS_MD(id));
/* Enable gsbi_pclk */
writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id));
}

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/* Copyright (c) 2011, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <debug.h>
#include <reg.h>
#include <platform/iomap.h>
#include <platform/gpio.h>
#include <gsbi.h>
void gpio_tlmm_config(uint32_t gpio, uint8_t func,
uint8_t dir, uint8_t pull,
uint8_t drvstr, uint32_t enable)
{
unsigned int val = 0;
val |= pull;
val |= func << 2;
val |= drvstr << 6;
val |= enable << 9;
unsigned int *addr = (unsigned int *)GPIO_CONFIG_ADDR(gpio);
writel(val, addr);
return;
}
void gpio_set(uint32_t gpio, uint32_t dir)
{
unsigned int *addr = (unsigned int *)GPIO_IN_OUT_ADDR(gpio);
writel(dir, addr);
return;
}
/* Configure gpio for uart - based on gsbi id */
void gpio_config_uart_dm(uint8_t id)
{
switch (id)
{
case GSBI_ID_4:
/* Enable GSBI4 through gpio */
/* configure rx gpio -- gsbi4(2) */
gpio_tlmm_config(14, 1, GPIO_INPUT, GPIO_NO_PULL,
GPIO_8MA, GPIO_DISABLE);
/* configure tx gpio -- gsbi4(3) */
gpio_tlmm_config(15, 1, GPIO_OUTPUT, GPIO_NO_PULL,
GPIO_8MA, GPIO_DISABLE);
break;
default:
ASSERT(0);
}
}

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/*
* * Copyright (c) 2011, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLATFORM_MDM9615_CLOCK_H
#define __PLATFORM_MDM9615_CLOCK_H
/* NS/MD value for USB XCVR */
#define USB_XCVR_CLK_NS 0x00E400C3
#define USB_XCVR_CLK_MD 0x000500DF
/* NS/MD value for UART */
/* Target is 1.8 MHz with cxo source */
#define UART_DM_CLK_NS_115200 0xFFEC0040
#define UART_DM_CLK_MD_115200 0x0002FFEA
#define UART_DM_CLK_RX_TX_BIT_RATE 0xFF
#define SC0_U_BRANCH_ENA_VOTE 0x903080
#define SC0_U_BRANCH_ENA_VOTE_ADM0 2
#define SC0_U_BRANCH_ENA_VOTE_ADM0_PBUS 3
void hsusb_clock_init(void);
void clock_config_uart_dm(uint8_t id);
#endif

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/* Copyright (c) 2011, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLATFORM_MDM9615_GPIO_H
#define __PLATFORM_MDM9615_GPIO_H
/* GPIO TLMM: Direction */
#define GPIO_INPUT 0
#define GPIO_OUTPUT 1
/* GPIO TLMM: Pullup/Pulldown */
#define GPIO_NO_PULL 0
#define GPIO_PULL_DOWN 1
#define GPIO_KEEPER 2
#define GPIO_PULL_UP 3
/* GPIO TLMM: Drive Strength */
#define GPIO_2MA 0
#define GPIO_4MA 1
#define GPIO_6MA 2
#define GPIO_8MA 3
#define GPIO_10MA 4
#define GPIO_12MA 5
#define GPIO_14MA 6
#define GPIO_16MA 7
/* GPIO TLMM: Status */
#define GPIO_ENABLE 0
#define GPIO_DISABLE 1
void gpio_config_uart_dm(uint8_t id);
#endif

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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Copyright (c) 2011, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Google, Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _PLATFORM_MDM9615_IOMAP_H_
#define _PLATFORM_MDM9615_IOMAP_H_
#define GSBI_BASE(id) ((id) <= 7 ? (0x16000000 + (((id)-1) << 20)) : \
(0x1A000000 + (((id)-8) << 20)))
#define GSBI_UART_DM_BASE(id) (GSBI_BASE(id) + 0x40000)
#define TLMM_BASE_ADDR 0x00800000
#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10)
#define MSM_PSHOLD_CTL_SU (TLMM_BASE_ADDR + 0x820)
#define MSM_SHARED_IMEM_BASE 0x2B000000
#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
/* QGIC2 */
#define MSM_GIC_DIST_BASE 0x02000000
#define MSM_GIC_CPU_BASE 0x02002000
#define APCS_GLBSECURE_BASE 0x02010000
#define APCS_GLB_REG(x) (APCS_GLBSECURE_BASE + (x))
#define APCS_GLB_QGIC_CFG APCS_GLB_REG(0x38)
#define MSM_TMR_BASE 0x0200A000
#define TMR_REG(off) (MSM_TMR_BASE + (off))
#define MSM_GPT_BASE TMR_REG(0x4)
#define GPT_REG(off) (MSM_GPT_BASE + (off))
#define GPT_MATCH_VAL GPT_REG(0x0000)
#define GPT_COUNT_VAL GPT_REG(0x0004)
#define GPT_ENABLE GPT_REG(0x0008)
#define GPT_CLEAR GPT_REG(0x000C)
#define DGT_MATCH_VAL TMR_REG(0x0024)
#define DGT_COUNT_VAL TMR_REG(0x0028)
#define DGT_ENABLE TMR_REG(0x002C)
#define DGT_CLEAR TMR_REG(0x0030)
/* TMR_STS - status of SCSS timers */
#define SPSS_TIMER_STATUS TMR_REG(0x0088)
#define MSM_USB_BASE 0x12500000
#define CLK_CTL_BASE 0x00900000
#define USB_HS1_HCLK_CTL (CLK_CTL_BASE + 0x2900)
#define USB_HS1_XCVR_FS_CLK_MD (CLK_CTL_BASE + 0x2908)
#define USB_HS1_XCVR_FS_CLK_NS (CLK_CTL_BASE + 0x290C)
#define USB_HS1_SYSTEM_CLK_NS (CLK_CTL_BASE + 0x36A4)
#define USB_HS1_SYSTEM_CLK_MD (CLK_CTL_BASE + 0x36A0)
#define GSBIn_HCLK_CTL(n) (CLK_CTL_BASE + 0x29C0 + (32 * ((n) - 1)))
#define GSBIn_UART_APPS_MD(n) (CLK_CTL_BASE + 0x29D0 + (32 * ((n) - 1)))
#define GSBIn_UART_APPS_NS(n) (CLK_CTL_BASE + 0x29D4 + (32 * ((n) - 1)))
#define MSM_BOOT_PLL8_STATUS (CLK_CTL_BASE + 0x3158)
#define MSM_BOOT_PLL_ENABLE_SC0 (CLK_CTL_BASE + 0x34C0)
#define MSM_SHARED_BASE 0x40000000
#endif

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/* Copyright (c) 2009-2011, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of The Linux Foundation nor
* the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __IRQS_9615_H
#define __IRQS_9615_H
/* MSM ACPU Interrupt Numbers */
/* 0-15: STI/SGI (software triggered/generated interrupts)
* 16-31: PPI (private peripheral interrupts)
* 32+: SPI (shared peripheral interrupts)
*/
#define GIC_PPI_START 16
#define GIC_SPI_START 32
#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1)
#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94)
#define USB1_HS_IRQ (GIC_SPI_START + 100)
#define USB2_IRQ (GIC_SPI_START + 141)
#define USB1_IRQ (GIC_SPI_START + 142)
#define GSBI_QUP_IRQ(id) ((id) <= 8 ? (GIC_SPI_START + 145 + 2*((id))) : \
(GIC_SPI_START + 187 + 2*((id)-8)))
/* Retrofit universal macro names */
#define INT_USB_HS USB1_HS_IRQ
#define NR_MSM_IRQS 256
#define NR_GPIO_IRQS 173
#define NR_BOARD_IRQS 0
#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
#endif /* __IRQS_9615_H */

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/*
* Copyright (c) 2008, Google Inc.
* All rights reserved.
*
* Copyright (c) 2009-2011, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Google, Inc. nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <reg.h>
#include <debug.h>
#include <kernel/thread.h>
#include <platform/debug.h>
#include <platform/iomap.h>
#include <smem.h>
#include <qgic.h>
static uint32_t ticks_per_sec = 0;
extern void platform_uninit_timer(void);
void platform_init_timer();
void platform_early_init(void)
{
uint8_t cfg_bid = 0x1;
uint8_t cfg_pid = 0x1;
uint8_t gsbi_id = target_uart_gsbi();
uart_dm_init(gsbi_id, GSBI_BASE(gsbi_id), GSBI_UART_DM_BASE(gsbi_id));
/* Timers - QGIC Config */
writel((cfg_bid << 7 | cfg_pid << 10), APCS_GLB_QGIC_CFG);
qgic_init();
platform_init_timer();
}
void platform_init(void)
{
dprintf(INFO, "platform_init()\n");
acpu_clock_init();
}
void platform_uninit(void)
{
platform_uninit_timer();
}
/* Initialize DGT timer */
void platform_init_timer(void)
{
/* disable timer */
writel(0, DGT_ENABLE);
ticks_per_sec = 19200000; /* Uses CXO (19.2 MHz) */
}
/* Returns timer ticks per sec */
uint32_t platform_tick_rate(void)
{
return ticks_per_sec;
}

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LOCAL_DIR := $(GET_LOCAL_DIR)
ARCH := arm
# Cann't use cortex-a5 as its not supported by gcc 4.4.0
ARM_CPU := cortex-a8
CPU := generic
DEFINES += ARM_CPU_CORE_A5
INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
OBJS += \
$(LOCAL_DIR)/platform.o \
$(LOCAL_DIR)/acpuclock.o \
$(LOCAL_DIR)/gpio.o \
LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
include platform/msm_shared/rules.mk