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107
bootable/bootloader/lk/dev/pmic/pm8x41/include/pm8x41.h Normal file
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/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _PM8x41_H_
#define _PM8x41_H_
#include <sys/types.h>
#define PM_GPIO_DIR_OUT 0x01
#define PM_GPIO_DIR_IN 0x00
#define PM_GPIO_DIR_BOTH 0x02
#define PM_GPIO_PULL_UP_30 0
#define PM_GPIO_PULL_UP_1_5 1
#define PM_GPIO_PULL_UP_31_5 2
/* 1.5uA + 30uA boost */
#define PM_GPIO_PULL_UP_1_5_30 3
#define PM_GPIO_PULL_RESV_1 4
#define PM_GPIO_PULL_RESV_2 5
#define PM_GPIO_OUT_CMOS 0x00
#define PM_GPIO_OUT_DRAIN_NMOS 0x01
#define PM_GPIO_OUT_DRAIN_PMOS 0x02
#define PM_GPIO_OUT_DRIVE_LOW 0x01
#define PM_GPIO_OUT_DRIVE_MED 0x02
#define PM_GPIO_OUT_DRIVE_HIGH 0x03
#define PM_GPIO_FUNC_LOW 0x00
#define PM_GPIO_FUNC_HIGH 0x01
#define PM_GPIO_MODE_MASK 0x70
#define PM_GPIO_OUTPUT_MASK 0x0F
#define PON_PSHOLD_WARM_RESET 0x1
#define PON_PSHOLD_SHUTDOWN 0x4
#define PMIC_VERSION_V2 1
/*Target power on reasons*/
#define DC_CHG 8
#define USB_CHG 16
#define PON1 32
#define CBLPWR_N 64
#define KPDPWR_N 128
struct pm8x41_gpio {
int direction;
int output_buffer;
int output_value;
int pull;
int vin_sel;
int out_strength;
int function;
int inv_int_pol;
int disable_pin;
};
int pm8x41_gpio_get(uint8_t gpio, uint8_t *status);
int pm8x41_gpio_set(uint8_t gpio, uint8_t value);
int pm8x41_gpio_config(uint8_t gpio, struct pm8x41_gpio *config);
void pm8x41_set_boot_done();
uint32_t pm8x41_resin_status();
uint32_t pm8x41_resin_bark_workaround_status();
void pm8x41_reset_configure(uint8_t);
void pm8x41_v2_reset_configure(uint8_t);
int pm8x41_ldo_set_voltage(const char *, uint32_t);
int pm8x41_ldo_control(const char *, uint8_t);
uint8_t pm8x41_get_pmic_rev();
uint8_t pm8x41_get_pon_reason();
struct pm8x41_ldo {
const char *name;
uint8_t type;
uint32_t base;
uint32_t range_reg;
uint32_t step_reg;
uint32_t enable_reg;
};
#endif

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bootable/bootloader/lk/dev/pmic/pm8x41/include/pm8x41_adc.h Normal file
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/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _PM8X41_ADC_H_
#define _PM8X41_ADC_H_
#include <bits.h>
#include <stdint.h>
struct adc_conf {
uint32_t base;
uint8_t mode;
uint16_t chan;
uint8_t adc_param;
uint8_t hw_set_time;
uint8_t fast_avg;
uint8_t calib_type;
};
#define CHAN_INIT(_base, _chan, _mode, _adc_param, _hw_set_time, _fast_avg, _calib_type) \
{\
.base = _base, \
.chan = _chan, \
.mode = _mode, \
.adc_param = _adc_param, \
.hw_set_time = _hw_set_time, \
.fast_avg = _fast_avg, \
.calib_type = _calib_type, \
}
/* ADC1 Apps base */
#define VADC_USR1_BASE 0x3100
/* ADC mode control */
#define VADC_MODE_CTRL 0x40
#define VADC_MODE_NORMAL 0x0
#define VADC_MODE_BIT_NORMAL 3
/* ADC channel control */
#define VADC_CHAN_SEL 0x48
/* ADC dig param setup */
#define VADC_DIG_ADC_PARAM 0x50
#define VADC_DECIM_RATIO_VAL 0x1
#define VADC_DECIM_RATIO_SEL 2
#define VADC_CLK_SEL 1
/* ADC HE settle time */
#define VADC_HW_SETTLE_TIME 0x51
#define VADC_HW_SET_TIME_SEL 7
#define HW_SET_DELAY_100US 0x1
/* Request VADC conversion */
#define VADC_CONV_REQ 0x52
#define VADC_CON_REQ_BIT BIT(7)
/* ADC fast avg setup */
#define VADC_FAST_AVG 0x5A
#define VADC_FAST_AVG_EN 0x5B
#define FAST_AVG_SAMP_1 0x0
/* VADC status */
#define VADC_STATUS 0x08
#define VADC_STATUS_EOC 0x1
#define VADC_STATUS_MASK 0x3
/* VADC Enable */
#define VADC_EN_CTL 0x46
#define VADC_CTL_EN_BIT BIT(7)
/* VADC result */
#define VADC_REG_DATA_MSB 0x61
#define VADC_REG_DATA_LSB 0x60
/* Channel IDs */
#define VADC_BAT_VOL_CHAN_ID 6
#define VREF_625_CHAN_ID 9
#define VREF_125_CHAN_ID 10
#define GND_REF_CHAN_ID 14
#define VDD_VADC_CHAN_ID 15
#define VADC_BAT_CHAN_ID 49
/* Calibration type */
#define CALIB_ABS 0
#define CALIB_RATIO 1
/* VADC result range */
#define VADC_MIN_VAL 0x6000
#define VADC_MAX_VAL 0xA800
/* Data points needed for calibration */
/* Absolute calibration */
#define VREF_625_MV 625000
#define OFFSET_GAIN_DNOM 3
#define OFFSET_GAIN_NUME 1
/* Ratiometric calibration */
#define VREF_18_V 1800000
/* Current value for USB & BAT */
#define USB_CUR_100UA 100000
#define USB_CUR_150UA 150000
#define IUSB_MAX_REG 0x1344
#define BAT_CUR_100UA 100000
#define BAT_CUR_STEP 50000
#define IBAT_MAX_REG 0x1044
#define IUSB_MIN_UA 100000
#define IBAT_MIN_UA 100000
#define IBAT_MAX_UA 3250000
#define IUSB_MAX_UA 2500000
/* Macros for setting VDD max & charge control */
#define CHGR_VDD_MAX 0x1040
#define VDD_MIN_UA 3240000
#define VDD_MAX_UA 5790000
#define VDD_VOL_STEP 10000
/* Macros for charge control */
#define CHGR_CHG_CTRL 0x1049
#define CHGR_ENABLE 1
#define CHGR_EN_BIT 7
#define CHGR_DISABLE 0x0
/* Macros for boot done */
#define MISC_BOOT_DONE 0x1642
#define BOOT_DONE 1
#define BOOT_DONE_BIT 7
/* Function declations */
uint32_t pm8x41_adc_channel_read(uint16_t ch_num);
int pm8x41_iusb_max_config(uint32_t current);
int pm8x41_ibat_max_config(uint32_t current);
/* API: To set VDD max */
int pm8x41_chgr_vdd_max_config(uint32_t voltage);
/* API: To enable charging */
int pm8x41_chgr_ctl_enable(uint8_t enable);
/* API: Get battery voltage*/
uint32_t pm8x41_get_batt_voltage();
/* API: Get Voltage based State of Charge */
uint32_t pm8x41_get_voltage_based_soc(uint32_t cutoff_vol, uint32_t vdd_max);
#endif /* _PM8X41_ADC_H_ */

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bootable/bootloader/lk/dev/pmic/pm8x41/include/pm8x41_hw.h Normal file
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/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _PM8x41_HW_H_
#define _PM8x41_HW_H_
/* SMBB Registers */
#define SMBB_MISC_BOOT_DONE 0x1642
/* SMBB bit values */
#define BOOT_DONE_BIT 7
#define REVID_REVISION4 0x103
/* GPIO Registers */
#define GPIO_PERIPHERAL_BASE 0xC000
/* Peripheral base address for GPIO_X */
#define GPIO_N_PERIPHERAL_BASE(x) (GPIO_PERIPHERAL_BASE + ((x) - 1) * 0x100)
/* Register offsets within GPIO */
#define GPIO_STATUS 0x08
#define GPIO_MODE_CTL 0x40
#define GPIO_DIG_VIN_CTL 0x41
#define GPIO_DIG_PULL_CTL 0x42
#define GPIO_DIG_OUT_CTL 0x45
#define GPIO_EN_CTL 0x46
/* GPIO bit values */
#define PERPH_EN_BIT 7
#define GPIO_STATUS_VAL_BIT 0
/* PON Peripheral registers */
#define PON_PON_REASON1 0x808
#define PON_INT_RT_STS 0x810
#define PON_INT_SET_TYPE 0x811
#define PON_INT_POLARITY_HIGH 0x812
#define PON_INT_POLARITY_LOW 0x813
#define PON_INT_LATCHED_CLR 0x814
#define PON_INT_EN_SET 0x815
#define PON_INT_LATCHED_STS 0x818
#define PON_INT_PENDING_STS 0x819
#define PON_RESIN_N_RESET_S1_TIMER 0x844 /* bits 0:3 : S1_TIMER */
#define PON_RESIN_N_RESET_S2_TIMER 0x845 /* bits 0:2 : S2_TIMER */
#define PON_RESIN_N_RESET_S2_CTL 0x846 /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE */
#define PON_PS_HOLD_RESET_CTL 0x85A /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE */
#define PON_PS_HOLD_RESET_CTL2 0x85B
/* PON Peripheral register bit values */
#define RESIN_ON_INT_BIT 1
#define RESIN_BARK_INT_BIT 4
#define S2_RESET_EN_BIT 7
#define S2_RESET_TYPE_WARM 0x1
#define PON_RESIN_N_RESET_S2_TIMER_MAX_VALUE 0x7
void pm8x41_reg_write(uint32_t addr, uint8_t val);
uint8_t pm8x41_reg_read(uint32_t addr);
/* SPMI Macros */
#define REG_READ(_a) pm8x41_reg_read(_a)
#define REG_WRITE(_a, _v) pm8x41_reg_write(_a, _v)
#define REG_OFFSET(_addr) ((_addr) & 0xFF)
#define PERIPH_ID(_addr) (((_addr) & 0xFF00) >> 8)
#define SLAVE_ID(_addr) ((_addr) >> 16)
/* LDO voltage ranges */
#define NLDO_UV_MIN 375000
#define NLDO_UV_MAX 1537500
#define NLDO_UV_STEP 12500
#define NLDO_UV_VMIN_LOW 750000
#define PLDO_UV_VMIN_LOW 750000
#define PLDO_UV_VMIN_MID 1500000
#define PLDO_UV_VMIN_HIGH 1750000
#define PLDO_UV_MIN 1537500
#define PDLO_UV_MID 3075000
#define PLDO_UV_MAX 4900000
#define PLDO_UV_STEP_LOW 12500
#define PLDO_UV_STEP_MID 25000
#define PLDO_UV_STEP_HIGH 50000
#define LDO_RANGE_SEL_BIT 0
#define LDO_VSET_SEL_BIT 0
#define LDO_VREG_ENABLE_BIT 7
#define LDO_NORMAL_PWR_BIT 7
#define LDO_RANGE_CTRL 0x40
#define LDO_STEP_CTRL 0x41
#define LDO_POWER_MODE 0x45
#define LDO_EN_CTL_REG 0x46
#define PLDO_TYPE 0
#define NLDO_TYPE 1
#define LDO(_name, _type, _base, _range, _step, _enable) \
{ \
.name = _name, \
.type = _type, \
.base = _base, \
.range_reg = _range, \
.step_reg = _step, \
.enable_reg = _enable, \
}
#endif

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bootable/bootloader/lk/dev/pmic/pm8x41/include/pm8x41_wled.h Normal file
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/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <bits.h>
#include <debug.h>
#include <reg.h>
#define PM_WLED_BASE 0x1D800
#define PM_WLED_CTNL_REG(n) (PM_WLED_BASE + n)
#define PM_WLED_LED1_BRIGHTNESS_LSB PM_WLED_CTNL_REG(0x40)
#define PM_WLED_LED1_BRIGHTNESS_MSB PM_WLED_CTNL_REG(0x41)
#define PM_WLED_LED2_BRIGHTNESS_LSB PM_WLED_CTNL_REG(0x42)
#define PM_WLED_LED2_BRIGHTNESS_MSB PM_WLED_CTNL_REG(0x43)
#define PM_WLED_LED3_BRIGHTNESS_LSB PM_WLED_CTNL_REG(0x44)
#define PM_WLED_LED3_BRIGHTNESS_MSB PM_WLED_CTNL_REG(0x45)
#define PM_WLED_ENABLE PM_WLED_CTNL_REG(0x46)
#define PM_WLED_ILED_SYNC_BIT PM_WLED_CTNL_REG(0x47)
#define PM_WLED_MODULATION_SCHEME PM_WLED_CTNL_REG(0x4A)
#define PM_WLED_MAX_DUTY_CYCLE PM_WLED_CTNL_REG(0x4B)
#define PM_WLED_CURRENT_SINK PM_WLED_CTNL_REG(0x4F)
#define PM_WLED_LED1_SINK_MASK BIT(7)
#define PM_WLED_LED2_SINK_MASK BIT(6)
#define PM_WLED_LED3_SINK_MASK BIT(5)
#define PM_WLED_LED1_ILED_SYNC_MASK BIT(2)
#define PM_WLED_LED2_ILED_SYNC_MASK BIT(1)
#define PM_WLED_LED3_ILED_SYNC_MASK BIT(0)
#define PM_WLED_ENABLE_MODULE_MASK BIT(7)
struct pm8x41_wled_data{
uint8_t mod_scheme;
uint16_t led1_brightness;
uint16_t led2_brightness;
uint16_t led3_brightness;
uint8_t max_duty_cycle;
};
void pm8x41_wled_config(struct pm8x41_wled_data *wled_ctrl);
void pm8x41_wled_iled_sync_control(uint8_t enable);
void pm8x41_wled_sink_control(uint8_t enable);
void pm8x41_wled_enable(uint8_t enable);

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bootable/bootloader/lk/dev/pmic/pm8x41/pm8x41.c Normal file
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/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <bits.h>
#include <debug.h>
#include <reg.h>
#include <spmi.h>
#include <string.h>
#include <pm8x41_hw.h>
#include <pm8x41.h>
#include <platform/timer.h>
struct pm8x41_ldo ldo_data[] = {
LDO("LDO2", NLDO_TYPE, 0x14100, LDO_RANGE_CTRL, LDO_STEP_CTRL, LDO_EN_CTL_REG),
LDO("LDO12", PLDO_TYPE, 0x14B00, LDO_RANGE_CTRL, LDO_STEP_CTRL, LDO_EN_CTL_REG),
LDO("LDO22", PLDO_TYPE, 0x15500, LDO_RANGE_CTRL, LDO_STEP_CTRL, LDO_EN_CTL_REG),
};
/* SPMI helper functions */
uint8_t pm8x41_reg_read(uint32_t addr)
{
uint8_t val = 0;
struct pmic_arb_cmd cmd;
struct pmic_arb_param param;
cmd.address = PERIPH_ID(addr);
cmd.offset = REG_OFFSET(addr);
cmd.slave_id = SLAVE_ID(addr);
cmd.priority = 0;
param.buffer = &val;
param.size = 1;
pmic_arb_read_cmd(&cmd, &param);
return val;
}
void pm8x41_reg_write(uint32_t addr, uint8_t val)
{
struct pmic_arb_cmd cmd;
struct pmic_arb_param param;
cmd.address = PERIPH_ID(addr);
cmd.offset = REG_OFFSET(addr);
cmd.slave_id = SLAVE_ID(addr);
cmd.priority = 0;
param.buffer = &val;
param.size = 1;
pmic_arb_write_cmd(&cmd, &param);
}
/* Exported functions */
/* Set the boot done flag */
void pm8x41_set_boot_done()
{
uint8_t val;
val = REG_READ(SMBB_MISC_BOOT_DONE);
val |= BIT(BOOT_DONE_BIT);
REG_WRITE(SMBB_MISC_BOOT_DONE, val);
}
/* Configure GPIO */
int pm8x41_gpio_config(uint8_t gpio, struct pm8x41_gpio *config)
{
uint8_t val;
uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio);
/* Disable the GPIO */
val = REG_READ(gpio_base + GPIO_EN_CTL);
val &= ~BIT(PERPH_EN_BIT);
REG_WRITE(gpio_base + GPIO_EN_CTL, val);
/* Select the mode */
val = config->function | (config->direction << 4);
REG_WRITE(gpio_base + GPIO_MODE_CTL, val);
/* Set the right pull */
val = config->pull;
REG_WRITE(gpio_base + GPIO_DIG_PULL_CTL, val);
/* Select the VIN */
val = config->vin_sel;
REG_WRITE(gpio_base + GPIO_DIG_VIN_CTL, val);
if (config->direction == PM_GPIO_DIR_OUT) {
/* Set the right dig out control */
val = config->out_strength | (config->output_buffer << 4);
REG_WRITE(gpio_base + GPIO_DIG_OUT_CTL, val);
}
/* Enable the GPIO */
val = REG_READ(gpio_base + GPIO_EN_CTL);
val |= BIT(PERPH_EN_BIT);
REG_WRITE(gpio_base + GPIO_EN_CTL, val);
return 0;
}
/* Reads the status of requested gpio */
int pm8x41_gpio_get(uint8_t gpio, uint8_t *status)
{
uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio);
*status = REG_READ(gpio_base + GPIO_STATUS);
/* Return the value of the GPIO pin */
*status &= BIT(GPIO_STATUS_VAL_BIT);
dprintf(SPEW, "GPIO %d status is %d\n", gpio, *status);
return 0;
}
/* Write the output value of the requested gpio */
int pm8x41_gpio_set(uint8_t gpio, uint8_t value)
{
uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio);
uint8_t val;
/* Set the output value of the gpio */
val = REG_READ(gpio_base + GPIO_MODE_CTL);
val = (val & ~PM_GPIO_OUTPUT_MASK) | value;
REG_WRITE(gpio_base + GPIO_MODE_CTL, val);
return 0;
}
/* Prepare PON RESIN S2 reset (bite) */
void pm8x41_resin_s2_reset_enable()
{
uint8_t val;
/* disable s2 reset */
REG_WRITE(PON_RESIN_N_RESET_S2_CTL, 0x0);
/* Delay needed for disable to kick in. */
udelay(300);
/* configure s1 timer to 0 */
REG_WRITE(PON_RESIN_N_RESET_S1_TIMER, 0x0);
/* configure s2 timer to 2s */
REG_WRITE(PON_RESIN_N_RESET_S2_TIMER, PON_RESIN_N_RESET_S2_TIMER_MAX_VALUE);
/* configure reset type */
REG_WRITE(PON_RESIN_N_RESET_S2_CTL, S2_RESET_TYPE_WARM);
val = REG_READ(PON_RESIN_N_RESET_S2_CTL);
/* enable s2 reset */
val |= BIT(S2_RESET_EN_BIT);
REG_WRITE(PON_RESIN_N_RESET_S2_CTL, val);
}
/* Disable PON RESIN S2 reset. (bite)*/
void pm8x41_resin_s2_reset_disable()
{
/* disable s2 reset */
REG_WRITE(PON_RESIN_N_RESET_S2_CTL, 0x0);
/* Delay needed for disable to kick in. */
udelay(300);
}
/* Resin irq status for faulty pmic*/
uint32_t pm8x41_resin_bark_workaround_status()
{
uint8_t rt_sts = 0;
/* Enable S2 reset so we can detect the volume down key press */
pm8x41_resin_s2_reset_enable();
/* Delay before interrupt triggering.
* See PON_DEBOUNCE_CTL reg.
*/
mdelay(100);
rt_sts = REG_READ(PON_INT_RT_STS);
/* Must disable S2 reset otherwise PMIC will reset if key
* is held longer than S2 timer.
*/
pm8x41_resin_s2_reset_disable();
return (rt_sts & BIT(RESIN_BARK_INT_BIT));
}
/* Resin pin status */
uint32_t pm8x41_resin_status()
{
uint8_t rt_sts = 0;
rt_sts = REG_READ(PON_INT_RT_STS);
return (rt_sts & BIT(RESIN_ON_INT_BIT));
}
void pm8x41_v2_reset_configure(uint8_t reset_type)
{
uint8_t val;
/* disable PS_HOLD_RESET */
REG_WRITE(PON_PS_HOLD_RESET_CTL, 0x0);
/* Delay needed for disable to kick in. */
udelay(300);
/* configure reset type */
REG_WRITE(PON_PS_HOLD_RESET_CTL, reset_type);
val = REG_READ(PON_PS_HOLD_RESET_CTL);
/* enable PS_HOLD_RESET */
val |= BIT(S2_RESET_EN_BIT);
REG_WRITE(PON_PS_HOLD_RESET_CTL, val);
}
void pm8x41_reset_configure(uint8_t reset_type)
{
/* disable PS_HOLD_RESET */
REG_WRITE(PON_PS_HOLD_RESET_CTL2, 0x0);
/* Delay needed for disable to kick in. */
udelay(300);
/* configure reset type */
REG_WRITE(PON_PS_HOLD_RESET_CTL, reset_type);
/* enable PS_HOLD_RESET */
REG_WRITE(PON_PS_HOLD_RESET_CTL2, BIT(S2_RESET_EN_BIT));
}
static struct pm8x41_ldo *ldo_get(const char *ldo_name)
{
uint8_t i;
struct pm8x41_ldo *ldo = NULL;
for (i = 0; i < ARRAY_SIZE(ldo_data); i++) {
ldo = &ldo_data[i];
if (!strncmp(ldo->name, ldo_name, strlen(ldo_name)))
break;
}
return ldo;
}
/*
* LDO set voltage, takes ldo name & voltage in UV as input
*/
int pm8x41_ldo_set_voltage(const char *name, uint32_t voltage)
{
uint32_t range = 0;
uint32_t step = 0;
uint32_t mult = 0;
uint32_t val = 0;
uint32_t vmin = 0;
struct pm8x41_ldo *ldo;
ldo = ldo_get(name);
if (!ldo) {
dprintf(CRITICAL, "LDO requsted is not supported: %s\n", name);
return 1;
}
/* Program Normal power mode */
val = 0x0;
val = (1 << LDO_NORMAL_PWR_BIT);
REG_WRITE((ldo->base + LDO_POWER_MODE), val);
/*
* Select range, step & vmin based on input voltage & type of LDO
* LDO can operate in low, mid, high power mode
*/
if (ldo->type == PLDO_TYPE) {
if (voltage < PLDO_UV_MIN) {
range = 2;
step = PLDO_UV_STEP_LOW;
vmin = PLDO_UV_VMIN_LOW;
} else if (voltage < PDLO_UV_MID) {
range = 3;
step = PLDO_UV_STEP_MID;
vmin = PLDO_UV_VMIN_MID;
} else {
range = 4;
step = PLDO_UV_STEP_HIGH;
vmin = PLDO_UV_VMIN_HIGH;
}
} else {
range = 2;
step = NLDO_UV_STEP;
vmin = NLDO_UV_VMIN_LOW;
}
mult = (voltage - vmin) / step;
/* Set Range in voltage ctrl register */
val = 0x0;
val = range << LDO_RANGE_SEL_BIT;
REG_WRITE((ldo->base + ldo->range_reg), val);
/* Set multiplier in voltage ctrl register */
val = 0x0;
val = mult << LDO_VSET_SEL_BIT;
REG_WRITE((ldo->base + ldo->step_reg), val);
return 0;
}
/*
* Enable or Disable LDO
*/
int pm8x41_ldo_control(const char *name, uint8_t enable)
{
uint32_t val = 0;
struct pm8x41_ldo *ldo;
ldo = ldo_get(name);
if (!ldo) {
dprintf(CRITICAL, "Requested LDO is not supported : %s\n", name);
return 1;
}
/* Enable LDO */
if (enable)
val = (1 << LDO_VREG_ENABLE_BIT);
else
val = (0 << LDO_VREG_ENABLE_BIT);
REG_WRITE((ldo->base + ldo->enable_reg), val);
return 0;
}
uint8_t pm8x41_get_pmic_rev()
{
return REG_READ(REVID_REVISION4);
}
uint8_t pm8x41_get_pon_reason()
{
return REG_READ(PON_PON_REASON1);
}

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bootable/bootloader/lk/dev/pmic/pm8x41/pm8x41_adc.c Normal file
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/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation, Inc. nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <bits.h>
#include <debug.h>
#include <reg.h>
#include <spmi.h>
#include <platform/timer.h>
#include <pm8x41_adc.h>
#include <pm8x41_hw.h>
/*
* This is the predefined adc configuration values for the supported
* channels
*/
static struct adc_conf adc_data[] = {
CHAN_INIT(VADC_USR1_BASE, VADC_BAT_CHAN_ID, VADC_MODE_NORMAL, VADC_DECIM_RATIO_VAL, HW_SET_DELAY_100US, FAST_AVG_SAMP_1, CALIB_RATIO),
CHAN_INIT(VADC_USR1_BASE, VADC_BAT_VOL_CHAN_ID, VADC_MODE_NORMAL, VADC_DECIM_RATIO_VAL, HW_SET_DELAY_100US, FAST_AVG_SAMP_1, CALIB_ABS),
};
static struct adc_conf* get_channel_prop(uint16_t ch_num)
{
struct adc_conf *chan_data = NULL;
uint8_t i;
for(i = 0; i < ARRAY_SIZE(adc_data) ; i++) {
chan_data = &adc_data[i];
if (chan_data->chan == ch_num)
break;
}
return chan_data;
}
static void adc_limit_result_range(uint16_t *result)
{
if (*result < VADC_MIN_VAL)
*result = VADC_MIN_VAL;
else if(*result > VADC_MAX_VAL)
*result = VADC_MAX_VAL;
}
static void adc_read_conv_result(struct adc_conf *adc, uint16_t *result)
{
uint8_t val = 0;
/* Read the MSB part */
val = REG_READ(adc->base + VADC_REG_DATA_MSB);
*result = val;
/* Read the LSB part */
val = REG_READ(adc->base + VADC_REG_DATA_LSB);
*result = ((*result) << 8) | val;
adc_limit_result_range(result);
}
static void adc_enable(struct adc_conf *adc, uint8_t enable)
{
if (enable)
REG_WRITE((adc->base + VADC_EN_CTL), VADC_CTL_EN_BIT);
else
REG_WRITE((adc->base + VADC_EN_CTL), (uint8_t) (~VADC_CTL_EN_BIT));
}
static void adc_measure(struct adc_conf *adc, uint16_t *result)
{
uint8_t status;
/* Request conversion */
REG_WRITE((adc->base + VADC_CONV_REQ), VADC_CON_REQ_BIT);
/* Poll for the conversion to complete */
do {
status = REG_READ(adc->base + VADC_STATUS);
status &= VADC_STATUS_MASK;
if (status == VADC_STATUS_EOC) {
dprintf(SPEW, "ADC conversion is complete\n");
break;
}
/* Wait for sometime before polling for the status again */
udelay(10);
} while(1);
/* Now read the conversion result */
adc_read_conv_result(adc, result);
}
/*
* This function configures adc & requests for conversion
*/
static uint16_t adc_configure(struct adc_conf *adc)
{
uint8_t mode;
uint8_t adc_p;
uint16_t result;
/* Mode Selection */
mode = (adc->mode << VADC_MODE_BIT_NORMAL);
REG_WRITE((adc->base + VADC_MODE_CTRL), mode);
/* Select Channel */
REG_WRITE((adc->base + VADC_CHAN_SEL), adc->chan);
/* ADC digital param setup */
adc_p = (adc->adc_param << VADC_DECIM_RATIO_SEL);
REG_WRITE((adc->base + VADC_DIG_ADC_PARAM), adc_p);
/* hardware settling time */
REG_WRITE((adc->base + VADC_HW_SETTLE_TIME), adc->hw_set_time);
/* For normal mode set the fast avg */
REG_WRITE((adc->base + VADC_FAST_AVG), adc->fast_avg);
/* Enable Vadc */
adc_enable(adc, true);
/* Measure the result */
adc_measure(adc, &result);
/* Disable vadc */
adc_enable(adc, false);
return result;
}
static uint32_t vadc_calibrate(uint16_t result, uint8_t calib_type)
{
struct adc_conf calib;
uint16_t calib1;
uint16_t calib2;
uint32_t calib_result = 0;
uint32_t mul;
if(calib_type == CALIB_ABS) {
/*
* Measure the calib data for 1.25 V ref
*/
calib.base = VADC_USR1_BASE;
calib.chan = VREF_125_CHAN_ID;
calib.mode = VADC_MODE_NORMAL;
calib.adc_param = VADC_DECIM_RATIO_VAL;
calib.hw_set_time = 0x0;
calib.fast_avg = 0x0;
calib1 = adc_configure(&calib);
/*
* Measure the calib data for 0.625 V ref
*/
calib.base = VADC_USR1_BASE;
calib.chan = VREF_625_CHAN_ID;
calib.mode = VADC_MODE_NORMAL;
calib.adc_param = VADC_DECIM_RATIO_VAL;
calib.hw_set_time = 0x0;
calib.fast_avg = 0x0;
calib2 = adc_configure(&calib);
mul = VREF_625_MV / (calib1 - calib2);
calib_result = (result - calib2) * mul;
calib_result += VREF_625_MV;
calib_result *= OFFSET_GAIN_DNOM;
calib_result /= OFFSET_GAIN_NUME;
} else if(calib_type == CALIB_RATIO) {
/*
* Measure the calib data for VDD_ADC ref
*/
calib.base = VADC_USR1_BASE;
calib.chan = VDD_VADC_CHAN_ID;
calib.mode = VADC_MODE_NORMAL;
calib.adc_param = VADC_DECIM_RATIO_VAL;
calib.hw_set_time = 0;
calib.fast_avg = 0;
calib1 = adc_configure(&calib);
/*
* Measure the calib data for ADC_GND
*/
calib.base = VADC_USR1_BASE;
calib.chan = GND_REF_CHAN_ID;
calib.mode = VADC_MODE_NORMAL;
calib.adc_param = VADC_DECIM_RATIO_VAL;
calib.hw_set_time = 0;
calib.fast_avg = 0;
calib2 = adc_configure(&calib);
mul = VREF_18_V / (calib1 - calib2);
calib_result = (result - calib2) * mul;
}
return calib_result;
}
/*
* This API takes channel number as input
* & returns the calibrated voltage as output
* The calibrated result is the voltage in uVs
*/
uint32_t pm8x41_adc_channel_read(uint16_t ch_num)
{
struct adc_conf *adc;
uint16_t result;
uint32_t calib_result;
adc = get_channel_prop(ch_num);
if (!adc) {
dprintf(CRITICAL, "Error: requested channel is not supported: %u\n", ch_num);
return 0;
}
result = adc_configure(adc);
calib_result = vadc_calibrate(result, adc->calib_type);
dprintf(SPEW, "Result: Raw %u\tCalibrated:%llu\n", result, calib_result);
return calib_result;
}
/*
* This function configures the maximum
* current for USB in uA
*/
int pm8x41_iusb_max_config(uint32_t current)
{
uint32_t mul;
if(current < IUSB_MIN_UA || current > IUSB_MAX_UA) {
dprintf(CRITICAL, "Error: Current value for USB are not in permissible range\n");
return -1;
}
if (current == USB_CUR_100UA)
mul = 0x0;
else if (current == USB_CUR_150UA)
mul = 0x1;
else
mul = current / USB_CUR_100UA;
REG_WRITE(IUSB_MAX_REG, mul);
return 0;
}
/*
* This function configures the maximum
* current for battery in uA
*/
int pm8x41_ibat_max_config(uint32_t current)
{
uint32_t mul;
if(current < IBAT_MIN_UA || current > IBAT_MAX_UA) {
dprintf(CRITICAL, "Error: Current value for BAT are not in permissible range\n");
return -1;
}
mul = (current - BAT_CUR_100UA) / BAT_CUR_STEP;
REG_WRITE(IBAT_MAX_REG, mul);
return 0;
}
/*
* API: pm8x41_chgr_vdd_max_config
* Configure the VDD max to i/p value
*/
int pm8x41_chgr_vdd_max_config(uint32_t vol)
{
uint8_t mul;
/* Check for permissible range of i/p */
if (vol < VDD_MIN_UA || vol > VDD_MAX_UA)
{
dprintf(CRITICAL, "Error: Voltage values are not in permissible range\n");
return -1;
}
/* Calculate the multiplier */
mul = (vol - VDD_MIN_UA) / VDD_VOL_STEP;
/* Write to VDD_MAX register */
REG_WRITE(CHGR_VDD_MAX, mul);
return 0;
}
/*
* API: pm8x41_chgr_ctl_enable
* Enable FSM-controlled autonomous charging
*/
int pm8x41_chgr_ctl_enable(uint8_t enable)
{
/* If charging has to be enabled?
* 1. Enable charging in charge control
* 2. Enable boot done to enable charging
*/
if (enable)
{
REG_WRITE(CHGR_CHG_CTRL, (CHGR_ENABLE << CHGR_EN_BIT));
REG_WRITE(MISC_BOOT_DONE, (BOOT_DONE << BOOT_DONE_BIT));
}
else
REG_WRITE(CHGR_CHG_CTRL, CHGR_DISABLE);
return 0;
}
/*
* API: pm8x41_get_batt_voltage
* Get calibrated battery voltage from VADC, in UV
*/
uint32_t pm8x41_get_batt_voltage()
{
uint32_t voltage;
voltage = pm8x41_adc_channel_read(VADC_BAT_VOL_CHAN_ID);
if(!voltage)
{
dprintf(CRITICAL, "Error getting battery Voltage\n");
return 0;
}
return voltage;
}
/*
* API: pm8x41_get_voltage_based_soc
* Get voltage based State Of Charge, this takes vdd max & battery cutoff
* voltage as i/p in uV
*/
uint32_t pm8x41_get_voltage_based_soc(uint32_t cutoff_vol, uint32_t vdd_max)
{
uint32_t vol_soc;
uint32_t batt_vol;
batt_vol = pm8x41_get_batt_voltage();
if(!batt_vol)
{
dprintf(CRITICAL, "Error: Getting battery voltage based Soc\n");
return 0;
}
if (cutoff_vol >= vdd_max)
{
dprintf(CRITICAL, "Cutoff is greater than VDD max, Voltage based soc can't be calculated\n");
return 0;
}
vol_soc = ((batt_vol - cutoff_vol) * 100) / (vdd_max - cutoff_vol);
return vol_soc;
}

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bootable/bootloader/lk/dev/pmic/pm8x41/pm8x41_wled.c Normal file
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/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* * Neither the name of The Linux Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <bits.h>
#include <reg.h>
#include <pm8x41_hw.h>
#include <pm8x41_wled.h>
void pm8x41_wled_config(struct pm8x41_wled_data *wled_ctrl) {
if (!wled_ctrl) {
dprintf(CRITICAL, "Error: Invalid WLED data.\n");
return;
}
REG_WRITE(PM_WLED_MODULATION_SCHEME, wled_ctrl->mod_scheme);
REG_WRITE(PM_WLED_LED1_BRIGHTNESS_LSB, (wled_ctrl->led1_brightness & 0xFF));
REG_WRITE(PM_WLED_LED1_BRIGHTNESS_MSB, ((wled_ctrl->led1_brightness >> 8) & 0xFF));
REG_WRITE(PM_WLED_LED2_BRIGHTNESS_LSB, (wled_ctrl->led2_brightness & 0xFF));
REG_WRITE(PM_WLED_LED2_BRIGHTNESS_MSB, ((wled_ctrl->led2_brightness >> 8) & 0xFF));
REG_WRITE(PM_WLED_LED3_BRIGHTNESS_LSB, (wled_ctrl->led3_brightness & 0xFF));
REG_WRITE(PM_WLED_LED3_BRIGHTNESS_MSB, ((wled_ctrl->led3_brightness >> 8) & 0xFF));
REG_WRITE(PM_WLED_MAX_DUTY_CYCLE, wled_ctrl->max_duty_cycle);
dprintf(SPEW, "WLED Configuration Success.\n");
}
void pm8x41_wled_sink_control(uint8_t enable) {
uint8_t value = 0x0;
if (enable) {
value = PM_WLED_LED1_SINK_MASK |
PM_WLED_LED2_SINK_MASK |
PM_WLED_LED3_SINK_MASK;
}
REG_WRITE(PM_WLED_CURRENT_SINK, value);
dprintf(SPEW, "WLED Sink Success\n");
}
void pm8x41_wled_iled_sync_control(uint8_t enable) {
uint8_t value = 0x0;
if (enable) {
value = PM_WLED_LED1_ILED_SYNC_MASK |
PM_WLED_LED1_ILED_SYNC_MASK |
PM_WLED_LED1_ILED_SYNC_MASK;
}
REG_WRITE(PM_WLED_ILED_SYNC_BIT, value);
dprintf(SPEW, "WLED ILED Sync Success\n");
}
void pm8x41_wled_enable(uint8_t enable) {
uint8_t value = 0x0;
if (enable)
value = PM_WLED_ENABLE_MODULE_MASK;
REG_WRITE(PM_WLED_ENABLE, value);
dprintf(SPEW, "WLED Enable Success\n");
}

8
bootable/bootloader/lk/dev/pmic/pm8x41/rules.mk Normal file
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LOCAL_DIR := $(GET_LOCAL_DIR)
INCLUDES += -I$(LOCAL_DIR)/include
OBJS += \
$(LOCAL_DIR)/pm8x41.o \
$(LOCAL_DIR)/pm8x41_adc.o \
$(LOCAL_DIR)/pm8x41_wled.o